1 /***************************************************************************
2 * Copyright (C) 2008 by Spencer Oliver *
3 * spen@spen-soft.co.uk *
4 * *
5 * Copyright (C) 2008 by David T.L. Wong *
6 * *
7 * This program is free software; you can redistribute it and/or modify *
8 * it under the terms of the GNU General Public License as published by *
9 * the Free Software Foundation; either version 2 of the License, or *
10 * (at your option) any later version. *
11 * *
12 * This program is distributed in the hope that it will be useful, *
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of *
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
15 * GNU General Public License for more details. *
16 * *
17 * You should have received a copy of the GNU General Public License *
18 * along with this program. If not, see <http://www.gnu.org/licenses/>. *
19 ***************************************************************************/
20
21 #ifndef OPENOCD_TARGET_MIPS_EJTAG_H
22 #define OPENOCD_TARGET_MIPS_EJTAG_H
23
24 #include <jtag/jtag.h>
25
26 /* tap instructions */
27 #define EJTAG_INST_IDCODE 0x01
28 #define EJTAG_INST_IMPCODE 0x03
29 #define EJTAG_INST_ADDRESS 0x08
30 #define EJTAG_INST_DATA 0x09
31 #define EJTAG_INST_CONTROL 0x0A
32 #define EJTAG_INST_ALL 0x0B
33 #define EJTAG_INST_EJTAGBOOT 0x0C
34 #define EJTAG_INST_NORMALBOOT 0x0D
35 #define EJTAG_INST_FASTDATA 0x0E
36 #define EJTAG_INST_TCBCONTROLA 0x10
37 #define EJTAG_INST_TCBCONTROLB 0x11
38 #define EJTAG_INST_TCBDATA 0x12
39 #define EJTAG_INST_TCBCONTROLC 0x13
40 #define EJTAG_INST_PCSAMPLE 0x14
41 #define EJTAG_INST_TCBCONTROLD 0x15
42 #define EJTAG_INST_TCBCONTROLE 0x16
43 #define EJTAG_INST_FDC 0x17
44 #define EJTAG_INST_BYPASS 0xFF
45
46 /* microchip PIC32MX specific instructions */
47 #define MTAP_SW_MTAP 0x04
48 #define MTAP_SW_ETAP 0x05
49 #define MTAP_COMMAND 0x07
50
51 /* microchip specific cmds */
52 #define MCHP_ASERT_RST 0xd1
53 #define MCHP_DE_ASSERT_RST 0xd0
54 #define MCHP_ERASE 0xfc
55 #define MCHP_STATUS 0x00
56
57 /* ejtag control register bits ECR */
58 #define EJTAG_CTRL_TOF (1 << 1)
59 #define EJTAG_CTRL_TIF (1 << 2)
60 #define EJTAG_CTRL_BRKST (1 << 3)
61 #define EJTAG_CTRL_DLOCK (1 << 5)
62 #define EJTAG_CTRL_DRWN (1 << 9)
63 #define EJTAG_CTRL_DERR (1 << 10)
64 #define EJTAG_CTRL_DSTRT (1 << 11)
65 #define EJTAG_CTRL_JTAGBRK (1 << 12)
66 #define EJTAG_CTRL_DBGISA (1 << 13)
67 #define EJTAG_CTRL_SETDEV (1 << 14)
68 #define EJTAG_CTRL_PROBEN (1 << 15)
69 #define EJTAG_CTRL_PRRST (1 << 16)
70 #define EJTAG_CTRL_DMAACC (1 << 17)
71 #define EJTAG_CTRL_PRACC (1 << 18)
72 #define EJTAG_CTRL_PRNW (1 << 19)
73 #define EJTAG_CTRL_PERRST (1 << 20)
74 #define EJTAG_CTRL_SYNC (1 << 23)
75 #define EJTAG_CTRL_DNM (1 << 28)
76 #define EJTAG_CTRL_ROCC (1 << 31)
77
78 /* Debug Register (CP0 Register 23, Select 0) */
79
80 #define EJTAG_DEBUG_DSS (1 << 0)
81 #define EJTAG_DEBUG_DBP (1 << 1)
82 #define EJTAG_DEBUG_DDBL (1 << 2)
83 #define EJTAG_DEBUG_DDBS (1 << 3)
84 #define EJTAG_DEBUG_DIB (1 << 4)
85 #define EJTAG_DEBUG_DINT (1 << 5)
86 #define EJTAG_DEBUG_OFFLINE (1 << 7)
87 #define EJTAG_DEBUG_SST (1 << 8)
88 #define EJTAG_DEBUG_NOSST (1 << 9)
89 #define EJTAG_DEBUG_DDBLIMPR (1 << 18)
90 #define EJTAG_DEBUG_DDBSIMPR (1 << 19)
91 #define EJTAG_DEBUG_IEXI (1 << 20)
92 #define EJTAG_DEBUG_DBUSEP (1 << 21)
93 #define EJTAG_DEBUG_CACHEEP (1 << 22)
94 #define EJTAG_DEBUG_MCHECKP (1 << 23)
95 #define EJTAG_DEBUG_IBUSEP (1 << 24)
96 #define EJTAG_DEBUG_COUNTDM (1 << 25)
97 #define EJTAG_DEBUG_HALT (1 << 26)
98 #define EJTAG_DEBUG_DOZE (1 << 27)
99 #define EJTAG_DEBUG_LSNM (1 << 28)
100 #define EJTAG_DEBUG_NODCR (1 << 29)
101 #define EJTAG_DEBUG_DM (1 << 30)
102 #define EJTAG_DEBUG_DBD (1 << 31)
103
104 /* implementation MIPS register bits.
105 * Bits marked with V20 or v2.0 mean that, this registers supported only
106 * by EJTAG v2.0. Bits marked with Lexra or BMIPS are different from the
107 * official EJATG.
108 * NOTE: Lexra or BMIPS use EJTAG v2.0 */
109
110 #define EJTAG_IMP_HAS(x) (ejtag_info->impcode & (x))
111 /* v2.0(Lexra) 29 - 1’b1 - Lexra Internal Trace Buffer implemented. This bit
112 * overlaps with version bit of MIPS EJTAG specification. */
113 #define EJTAG_V26_IMP_R3K (1 << 28)
114 /* v2.0 - 24:25 - 2’b00- No profiling support */
115 #define EJTAG_V26_IMP_DINT (1 << 24)
116 #define EJTAG_V20_IMP_SDBBP (1 << 23) /* 1’b1 - sdbbp is Special2 Opcode */
117 #define EJTAG_IMP_ASID8 (1 << 22)
118 #define EJTAG_IMP_ASID6 (1 << 21)
119 #define EJTAG_V20_IMP_COMPLEX_BREAK (1 << 20) /* Complex Breaks supported*/
120 #define EJTAG_V20_IMP_EADDR_NO32BIT (1 << 19) /* EJTAG_ADDR > 32 bits wide */
121 #define EJTAG_V20_IMP_DCACHE_COH (1 << 18) /* DCache does keep DMA coherent */
122 #define EJTAG_V20_IMP_ICACHE_COH (1 << 17) /* DCache does keep DMA coherent */
123 #define EJTAG_IMP_MIPS16 (1 << 16)
124 #define EJTAG_IMP_NODMA (1 << 14)
125 /* v2.0 - 11:13 external PC trace. Trace PC Width. */
126 /* v2.0 - 8:10 external PC trace. PCST Width and DCLK Division Factor */
127 #define EJTAG_V20_IMP_NOPB (1 << 7) /* no processor breaks */
128 #define EJTAG_V20_IMP_NODB (1 << 6) /* no data breaks */
129 #define EJTAG_V20_IMP_NOIB (1 << 5) /* no instruction breaks implemented */
130 /* v2.0 - 1:4 Number of Break Channels. */
131 #define EJTAG_V20_IMP_BCHANNELS_MASK 0xf
132 #define EJTAG_V20_IMP_BCHANNELS_SHIFT 1
133 #define EJTAG_IMP_MIPS64 (1 << 0)
134
135 /* Debug Control Register DCR */
136 #define EJTAG_DCR 0xFF300000
137 #define EJTAG_DCR_ENM (1 << 29)
138 #define EJTAG_DCR_DB (1 << 17)
139 #define EJTAG_DCR_IB (1 << 16)
140 #define EJTAG_DCR_INTE (1 << 4)
141 #define EJTAG_DCR_MP (1 << 2)
142
143 /* breakpoint support */
144 /* EJTAG_V20_* was tested on Broadcom BCM7401
145 * and may or will differ with other hardware. For example EZ4021-FC. */
146 #define EJTAG_V20_IBS 0xFF300004
147 #define EJTAG_V20_IBA0 0xFF300100
148 #define EJTAG_V20_IBC_OFFS 0x4 /* IBC Offset */
149 #define EJTAG_V20_IBM_OFFS 0x8
150 #define EJTAG_V20_IBAn_STEP 0x10 /* Offset for next channel */
151 #define EJTAG_V20_DBS 0xFF300008
152 #define EJTAG_V20_DBA0 0xFF300200
153 #define EJTAG_V20_DBC_OFFS 0x4
154 #define EJTAG_V20_DBM_OFFS 0x8
155 #define EJTAG_V20_DBV_OFFS 0xc
156 #define EJTAG_V20_DBAn_STEP 0x10
157
158 #define EJTAG_V25_IBS 0xFF301000
159 #define EJTAG_V25_IBA0 0xFF301100
160 #define EJTAG_V25_IBM_OFFS 0x8
161 #define EJTAG_V25_IBASID_OFFS 0x10
162 #define EJTAG_V25_IBC_OFFS 0x18
163 #define EJTAG_V25_IBAn_STEP 0x100
164 #define EJTAG_V25_DBS 0xFF302000
165 #define EJTAG_V25_DBA0 0xFF302100
166 #define EJTAG_V25_DBM_OFFS 0x8
167 #define EJTAG_V25_DBASID_OFFS 0x10
168 #define EJTAG_V25_DBC_OFFS 0x18
169 #define EJTAG_V25_DBV_OFFS 0x20
170 #define EJTAG_V25_DBAn_STEP 0x100
171
172 #define EJTAG_DBCn_NOSB (1 << 13)
173 #define EJTAG_DBCn_NOLB (1 << 12)
174 #define EJTAG_DBCn_BLM_MASK 0xff
175 #define EJTAG_DBCn_BLM_SHIFT 4
176 #define EJTAG_DBCn_BE (1 << 0)
177
178 #define EJTAG_VERSION_20 0
179 #define EJTAG_VERSION_25 1
180 #define EJTAG_VERSION_26 2
181 #define EJTAG_VERSION_31 3
182 #define EJTAG_VERSION_41 4
183 #define EJTAG_VERSION_51 5
184
185 /*
186 * Additional defines for MIPS64 EJTAG
187 */
188 #define EJTAG64_DCR 0xFFFFFFFFFF300000ull
189 #define EJTAG64_DCR_ENM (1llu << 29)
190 #define EJTAG64_DCR_DB (1llu << 17)
191 #define EJTAG64_DCR_IB (1llu << 16)
192 #define EJTAG64_DCR_INTE (1llu << 4)
193 #define EJTAG64_DCR_MP (1llu << 2)
194 #define EJTAG64_V25_DBA0 0xFFFFFFFFFF302100ull
195 #define EJTAG64_V25_DBS 0xFFFFFFFFFF302000ull
196 #define EJTAG64_V25_IBA0 0xFFFFFFFFFF301100ull
197 #define EJTAG64_V25_IBS 0xFFFFFFFFFF301000ull
198
199 struct mips_ejtag {
200 struct jtag_tap *tap;
201 uint32_t impcode;
202 uint32_t idcode;
203 uint32_t ejtag_ctrl;
204 int fast_access_save;
205 uint32_t config_regs; /* number of config registers read */
206 uint32_t config[4]; /* cp0 config to config3 */
207
208 uint32_t reg8;
209 uint32_t reg9;
210 unsigned scan_delay;
211 int mode;
212 uint32_t pa_ctrl;
213 uint32_t pa_addr;
214 unsigned int ejtag_version;
215 uint32_t isa;
216 uint32_t endianness;
217
218 /* Memory-Mapped Registers. This addresses are not same on different
219 * EJTAG versions. */
220 uint32_t debug_caps;
221 uint32_t ejtag_ibs_addr; /* Instruction Address Break Status */
222 uint32_t ejtag_iba0_addr; /* IAB channel 0 */
223 uint32_t ejtag_ibc_offs; /* IAB Control offset */
224 uint32_t ejtag_ibm_offs; /* IAB Mask offset */
225 uint32_t ejtag_ibasid_offs; /* IAB ASID (4Kc) */
226
227 uint32_t ejtag_dbs_addr; /* Data Address Break Status Register */
228 uint32_t ejtag_dba0_addr; /* DAB channel 0 */
229 uint32_t ejtag_dbc_offs; /* DAB Control offset */
230 uint32_t ejtag_dbm_offs; /* DAB Mask offset */
231 uint32_t ejtag_dbv_offs; /* DAB Value offset */
232 uint32_t ejtag_dbasid_offs; /* DAB ASID (4Kc) */
233
234 uint32_t ejtag_iba_step_size;
235 uint32_t ejtag_dba_step_size; /* size of step till next *DBAn register. */
236 };
237
238 void mips_ejtag_set_instr(struct mips_ejtag *ejtag_info, uint32_t new_instr);
239 int mips_ejtag_enter_debug(struct mips_ejtag *ejtag_info);
240 int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
241 int mips64_ejtag_exit_debug(struct mips_ejtag *ejtag_info);
242 int mips_ejtag_get_idcode(struct mips_ejtag *ejtag_info);
243 void mips_ejtag_add_scan_96(struct mips_ejtag *ejtag_info,
244 uint32_t ctrl, uint32_t data, uint8_t *in_scan_buf);
245 int mips_ejtag_drscan_64(struct mips_ejtag *ejtag_info, uint64_t *data);
246 void mips_ejtag_drscan_32_out(struct mips_ejtag *ejtag_info, uint32_t data);
247 int mips_ejtag_drscan_32(struct mips_ejtag *ejtag_info, uint32_t *data);
248 void mips_ejtag_drscan_8_out(struct mips_ejtag *ejtag_info, uint8_t data);
249 int mips_ejtag_drscan_8(struct mips_ejtag *ejtag_info, uint8_t *data);
250 int mips_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, int write_t, uint32_t *data);
251 int mips64_ejtag_fastdata_scan(struct mips_ejtag *ejtag_info, bool write_t, uint64_t *data);
252
253 int mips_ejtag_init(struct mips_ejtag *ejtag_info);
254 int mips_ejtag_config_step(struct mips_ejtag *ejtag_info, int enable_step);
255 int mips64_ejtag_config_step(struct mips_ejtag *ejtag_info, bool enable_step);
256
mips_le_to_h_u32(jtag_callback_data_t arg)257 static inline void mips_le_to_h_u32(jtag_callback_data_t arg)
258 {
259 uint8_t *in = (uint8_t *)arg;
260 *((uint32_t *)arg) = le_to_h_u32(in);
261 }
262
mips_le_to_h_u64(jtag_callback_data_t arg)263 static inline void mips_le_to_h_u64(jtag_callback_data_t arg)
264 {
265 uint8_t *in = (uint8_t *)arg;
266 *((uint64_t *)arg) = le_to_h_u64(in);
267 }
268
269 #endif /* OPENOCD_TARGET_MIPS_EJTAG_H */
270