xref: /dragonfly/sys/dev/netif/emx/if_emx.h (revision 74dc3754)
1 /*
2  * Copyright (c) 2001-2008, Intel Corporation
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  *  1. Redistributions of source code must retain the above copyright notice,
9  *     this list of conditions and the following disclaimer.
10  *
11  *  2. Redistributions in binary form must reproduce the above copyright
12  *     notice, this list of conditions and the following disclaimer in the
13  *     documentation and/or other materials provided with the distribution.
14  *
15  *  3. Neither the name of the Intel Corporation nor the names of its
16  *     contributors may be used to endorse or promote products derived from
17  *     this software without specific prior written permission.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #ifndef _IF_EMX_H_
33 #define _IF_EMX_H_
34 
35 /* Tunables */
36 
37 /*
38  * EMX_TXD: Maximum number of Transmit Descriptors
39  * Valid Range: 256-4096 for others
40  * Default Value: 512
41  *   This value is the number of transmit descriptors allocated by the driver.
42  *   Increasing this value allows the driver to queue more transmits. Each
43  *   descriptor is 16 bytes.
44  *   Since TDLEN should be multiple of 128bytes, the number of transmit
45  *   desscriptors should meet the following condition.
46  *      (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
47  */
48 #define EMX_MIN_TXD			256
49 #define EMX_MAX_TXD			4096
50 #define EMX_DEFAULT_TXD			512
51 
52 /*
53  * EMX_RXD - Maximum number of receive Descriptors
54  * Valid Range: 256-4096 for others
55  * Default Value: 512
56  *   This value is the number of receive descriptors allocated by the driver.
57  *   Increasing this value allows the driver to buffer more incoming packets.
58  *   Each descriptor is 16 bytes.  A receive buffer is also allocated for each
59  *   descriptor. The maximum MTU size is 16110.
60  *   Since TDLEN should be multiple of 128bytes, the number of transmit
61  *   desscriptors should meet the following condition.
62  *      (num_tx_desc * sizeof(struct e1000_tx_desc)) % 128 == 0
63  */
64 #define EMX_MIN_RXD			256
65 #define EMX_MAX_RXD			4096
66 #define EMX_DEFAULT_RXD			512
67 
68 /*
69  * Receive Interrupt Delay Timer (Packet Timer)
70  *
71  * NOTE:
72  * RDTR and RADV are deprecated; use ITR instead.  They are only used to
73  * workaround hardware bug on certain 82573 based NICs.
74  */
75 #define EMX_RDTR_82573			32
76 
77 /*
78  * Receive Interrupt Absolute Delay Timer (Not valid for 82542/82543/82544)
79  *
80  * NOTE:
81  * RDTR and RADV are deprecated; use ITR instead.  They are only used to
82  * workaround hardware bug on certain 82573 based NICs.
83  */
84 #define EMX_RADV_82573			64
85 
86 /*
87  * This parameter controls the duration of transmit watchdog timer.
88  */
89 #define EMX_TX_TIMEOUT			5
90 
91 /* One for TX csum offloading desc, the other 2 are reserved */
92 #define EMX_TX_RESERVED			3
93 
94 /* Large enough for 64K TSO segment */
95 #define EMX_TX_SPARE			33
96 
97 #define EMX_TX_OACTIVE_MAX		64
98 
99 /* Interrupt throttle rate */
100 #define EMX_DEFAULT_ITR			6000
101 
102 /* Number of segments sent before writing to TX related registers */
103 #define EMX_DEFAULT_TXWREG		8
104 
105 /*
106  * This parameter controls whether or not autonegotation is enabled.
107  *              0 - Disable autonegotiation
108  *              1 - Enable  autonegotiation
109  */
110 #define EMX_DO_AUTO_NEG			1
111 
112 /* Tunables -- End */
113 
114 #define EMX_AUTONEG_ADV_DEFAULT		(ADVERTISE_10_HALF | \
115 					 ADVERTISE_10_FULL | \
116 					 ADVERTISE_100_HALF | \
117 					 ADVERTISE_100_FULL | \
118 					 ADVERTISE_1000_FULL)
119 
120 #define EMX_AUTO_ALL_MODES		0
121 
122 /* PHY master/slave setting */
123 #define EMX_MASTER_SLAVE		e1000_ms_hw_default
124 
125 /*
126  * Micellaneous constants
127  */
128 #define EMX_VENDOR_ID			0x8086
129 
130 #define EMX_BAR_MEM			PCIR_BAR(0)
131 #define EMX_BAR_FLASH			PCIR_BAR(1)
132 
133 #define EMX_JUMBO_PBA			0x00000028
134 #define EMX_DEFAULT_PBA			0x00000030
135 #define EMX_SMARTSPEED_DOWNSHIFT	3
136 #define EMX_SMARTSPEED_MAX		15
137 #define EMX_MAX_INTR			10
138 
139 #define EMX_MCAST_ADDR_MAX		128
140 #define EMX_FC_PAUSE_TIME		1000
141 #define EMX_EEPROM_APME			0x400;
142 
143 #define EMX_PCICFG_DESC_RING_STATUS	0xe4
144 #define EMX_FLUSH_DESC_REQUIRED		0x100
145 
146 /*
147  * TDBA/RDBA should be aligned on 16 byte boundary. But TDLEN/RDLEN should be
148  * multiple of 128 bytes. So we align TDBA/RDBA on 128 byte boundary. This will
149  * also optimize cache line size effect. H/W supports up to cache line size 128.
150  */
151 #define EMX_DBA_ALIGN			128
152 
153 /*
154  * Speed mode bit in TARC0.
155  * 82571EB/82572EI only, used to improve small packet transmit performance.
156  */
157 #define EMX_TARC_SPEED_MODE		(1 << 21)
158 
159 #define EMX_TARC_COMPENSATION_MODE	(1 << 7) /* Compensation Mode */
160 
161 #define EMX_TARC_MQ_FIX			(1 << 23) | \
162 					(1 << 24) | \
163 					(1 << 25) /* Handle errata in MQ mode */
164 #define EMX_TARC_ERRATA 		(1 << 26) /* 82574 errata */
165 
166 /*
167  * Multiple TX queues arbitration count mask in TARC0/TARC1.
168  */
169 #define EMX_TARC_COUNT_MASK		0x7f
170 
171 #define EMX_MAX_SCATTER			64
172 #define EMX_TSO_SIZE			(IP_MAXPACKET + \
173 					 sizeof(struct ether_vlan_header))
174 #define EMX_MAX_SEGSIZE			PAGE_SIZE
175 #define EMX_MSIX_MASK			0x01F00000 /* For 82574 use */
176 
177 #define EMX_CSUM_FEATURES		(CSUM_IP | CSUM_TCP | CSUM_UDP)
178 
179 /*
180  * 82574 has a nonstandard address for EIAC
181  * and since its only used in MSIX, and in
182  * the em driver only 82574 uses MSIX we can
183  * solve it just using this define.
184  */
185 #define EMX_EIAC			0x000DC
186 
187 #define EMX_NRSSRK			10
188 #define EMX_RSSRK_SIZE			4
189 #define EMX_RSSRK_VAL(key, i)		(key[(i) * EMX_RSSRK_SIZE] | \
190 					 key[(i) * EMX_RSSRK_SIZE + 1] << 8 | \
191 					 key[(i) * EMX_RSSRK_SIZE + 2] << 16 | \
192 					 key[(i) * EMX_RSSRK_SIZE + 3] << 24)
193 
194 #define EMX_NRETA			32
195 #define EMX_RETA_SIZE			4
196 #define EMX_RETA_RINGIDX_SHIFT		7
197 
198 #define EMX_RDRTABLE_SIZE		(EMX_NRETA * EMX_RETA_SIZE)
199 
200 #define EMX_NRX_RING			2
201 #define EMX_NTX_RING			2
202 #define EMX_NSERIALIZE			5
203 
204 typedef union e1000_rx_desc_extended	emx_rxdesc_t;
205 
206 #define rxd_bufaddr	read.buffer_addr	/* 64bits */
207 #define rxd_length	wb.upper.length		/* 16bits */
208 #define rxd_vlan	wb.upper.vlan		/* 16bits */
209 #define rxd_staterr	wb.upper.status_error	/* 32bits */
210 #define rxd_mrq		wb.lower.mrq		/* 32bits */
211 #define rxd_rss		wb.lower.hi_dword.rss	/* 32bits */
212 
213 #define EMX_RXDMRQ_RSSTYPE_MASK	0xf
214 #define EMX_RXDMRQ_NO_HASH	0
215 #define EMX_RXDMRQ_IPV4_TCP	1
216 #define EMX_RXDMRQ_IPV4		2
217 #define EMX_RXDMRQ_IPV6_TCP	3
218 #define EMX_RXDMRQ_IPV6		5
219 
220 struct emx_softc;
221 
222 struct emx_rxdata {
223 	struct lwkt_serialize	rx_serialize;
224 	struct emx_softc	*sc;
225 	int			idx;
226 
227 	/*
228 	 * Receive definitions
229 	 *
230 	 * we have an array of num_rx_desc rx_desc (handled by the
231 	 * controller), and paired with an array of rx_buffers
232 	 * (at rx_buffer_area).
233 	 * The next pair to check on receive is at offset next_rx_desc_to_check
234 	 */
235 	emx_rxdesc_t		*rx_desc;
236 	uint32_t		next_rx_desc_to_check;
237 	int			num_rx_desc;
238 	struct emx_rxbuf	*rx_buf;
239 	bus_dma_tag_t		rxtag;
240 	bus_dmamap_t		rx_sparemap;
241 
242 	/*
243 	 * First/last mbuf pointers, for
244 	 * collecting multisegment RX packets.
245 	 */
246 	struct mbuf		*fmp;
247 	struct mbuf		*lmp;
248 
249 	/* RX statistics */
250 	unsigned long		rx_pkts;
251 
252 	bus_dma_tag_t		rx_desc_dtag;
253 	bus_dmamap_t		rx_desc_dmap;
254 	bus_addr_t		rx_desc_paddr;
255 } __cachealign;
256 
257 struct emx_txdata {
258 	struct lwkt_serialize	tx_serialize;
259 	struct emx_softc	*sc;
260 	struct ifaltq_subque	*ifsq;
261 	int			idx;
262 	int16_t			tx_running;
263 #define EMX_TX_RUNNING		100
264 #define EMX_TX_RUNNING_DEC	25
265 	uint16_t		tx_flags;
266 #define EMX_TXFLAG_TSO_PULLEX	0x1
267 #define EMX_TXFLAG_ENABLED	0x2
268 #define EMX_TXFLAG_FORCECTX	0x4
269 
270 	/*
271 	 * Transmit definitions
272 	 *
273 	 * We have an array of num_tx_desc descriptors (handled
274 	 * by the controller) paired with an array of tx_buffers
275 	 * (at tx_buffer_area).
276 	 * The index of the next available descriptor is next_avail_tx_desc.
277 	 * The number of remaining tx_desc is num_tx_desc_avail.
278 	 */
279 	struct e1000_tx_desc	*tx_desc_base;
280 	struct emx_txbuf	*tx_buf;
281 	uint32_t		next_avail_tx_desc;
282 	uint32_t		next_tx_to_clean;
283 	int			num_tx_desc_avail;
284 	int			num_tx_desc;
285 	bus_dma_tag_t		txtag;		/* dma tag for tx */
286 	int			spare_tx_desc;
287 	int			oact_tx_desc;
288 	int			tx_nmbuf;
289 
290 	/* Saved csum offloading context information */
291 	int			csum_flags;
292 	int			csum_lhlen;
293 	int			csum_iphlen;
294 
295 	int			csum_thlen;	/* TSO */
296 	int			csum_mss;	/* TSO */
297 	int			csum_pktlen;	/* TSO */
298 
299 	uint32_t		csum_txd_upper;
300 	uint32_t		csum_txd_lower;
301 
302 	int			tx_wreg_nsegs;
303 
304 	/*
305 	 * Variables used to reduce TX interrupt rate and
306 	 * number of device's TX ring write requests.
307 	 *
308 	 * tx_nsegs:
309 	 * Number of TX descriptors setup so far.
310 	 *
311 	 * tx_int_nsegs:
312 	 * Once tx_nsegs > tx_int_nsegs, RS bit will be set
313 	 * in the last TX descriptor of the packet, and
314 	 * tx_nsegs will be reset to 0.  So TX interrupt and
315 	 * TX ring write request should be generated roughly
316 	 * every tx_int_nsegs TX descriptors.
317 	 *
318 	 * tx_dd[]:
319 	 * Index of the TX descriptors which have RS bit set,
320 	 * i.e. DD bit will be set on this TX descriptor after
321 	 * the data of the TX descriptor are transfered to
322 	 * hardware's internal packet buffer.  Only the TX
323 	 * descriptors listed in tx_dd[] will be checked upon
324 	 * TX interrupt.  This array is used as circular ring.
325 	 *
326 	 * tx_dd_tail, tx_dd_head:
327 	 * Tail and head index of valid elements in tx_dd[].
328 	 * tx_dd_tail == tx_dd_head means there is no valid
329 	 * elements in tx_dd[].  tx_dd_tail points to the position
330 	 * which is one beyond the last valid element in tx_dd[].
331 	 * tx_dd_head points to the first valid element in
332 	 * tx_dd[].
333 	 */
334 	int			tx_intr_nsegs;
335 	int			tx_nsegs;
336 	int			tx_dd_tail;
337 	int			tx_dd_head;
338 #define EMX_TXDD_MAX	64
339 #define EMX_TXDD_SAFE	48 /* 48 <= val < EMX_TXDD_MAX */
340 	int			tx_dd[EMX_TXDD_MAX];
341 
342 	struct ifsubq_watchdog	tx_watchdog;
343 	struct callout		tx_gc_timer;
344 
345 	/* TX statistics */
346 	unsigned long		tx_pkts;
347 	unsigned long		tso_segments;
348 	unsigned long		tso_ctx_reused;
349 	unsigned long		tx_gc;
350 
351 	bus_dma_tag_t		tx_desc_dtag;
352 	bus_dmamap_t		tx_desc_dmap;
353 	bus_addr_t		tx_desc_paddr;
354 } __cachealign;
355 
356 struct emx_softc {
357 	struct arpcom		arpcom;
358 	struct e1000_hw		hw;
359 	int			flags;
360 #define EMX_FLAG_SHARED_INTR	0x0001
361 #define EMX_FLAG_HAS_MGMT	0x0004
362 #define EMX_FLAG_HAS_AMT	0x0008
363 #define EMX_FLAG_HW_CTRL	0x0010
364 
365 	/* DragonFly operating-system-specific structures. */
366 	struct e1000_osdep	osdep;
367 	device_t		dev;
368 
369 	bus_dma_tag_t		parent_dtag;
370 
371 	struct resource		*memory;
372 	int			memory_rid;
373 
374 	struct resource		*flash;
375 	int			flash_rid;
376 
377 	struct resource		*intr_res;
378 	void			*intr_tag;
379 	int			intr_rid;
380 	int			intr_type;
381 
382 	struct ifmedia		media;
383 	struct callout		timer;
384 	int			if_flags;
385 
386 	/* WOL register value */
387 	int			wol;
388 
389 	/* Multicast array memory */
390 	uint8_t			*mta;
391 
392 	/* Info about the board itself */
393 	uint8_t			link_active;
394 	uint16_t		link_speed;
395 	uint16_t		link_duplex;
396 	uint32_t		smartspeed;
397 	int			int_throttle_ceil;
398 
399 	struct lwkt_serialize	main_serialize;
400 	struct lwkt_serialize	*serializes[EMX_NSERIALIZE];
401 
402 	int			tx_ring_cnt;
403 	int			tx_ring_inuse;
404 	struct emx_txdata	tx_data[EMX_NTX_RING];
405 
406 	int			rss_debug;
407 	int			rx_ring_cnt;
408 	struct emx_rxdata	rx_data[EMX_NRX_RING];
409 
410 	int			ifm_flowctrl;
411 
412 	/* Misc stats maintained by the driver */
413 	unsigned long		rx_overruns;
414 
415 	struct e1000_hw_stats	stats;
416 
417 	struct if_ringmap	*rx_rmap;
418 	struct if_ringmap	*tx_rmap;
419 	int			rdr_table[EMX_RDRTABLE_SIZE];
420 };
421 
422 struct emx_txbuf {
423 	struct mbuf	*m_head;
424 	bus_dmamap_t	map;
425 };
426 
427 struct emx_rxbuf {
428 	struct mbuf	*m_head;
429 	bus_dmamap_t	map;
430 	bus_addr_t	paddr;
431 };
432 
433 #define EMX_IS_OACTIVE(tdata) \
434 	((tdata)->num_tx_desc_avail <= (tdata)->oact_tx_desc)
435 
436 #define EMX_INC_TXDD_IDX(idx) \
437 do { \
438 	if (++(idx) == EMX_TXDD_MAX) \
439 		(idx) = 0; \
440 } while (0)
441 
442 #endif /* !_IF_EMX_H_ */
443