1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (c) 2015-2023 Amazon.com, Inc. or its affiliates.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 *
11 * * Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * * Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
16 * distribution.
17 * * Neither the name of copyright holder nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 */
33
34 #ifndef _ENA_ADMIN_H_
35 #define _ENA_ADMIN_H_
36
37 #define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32
38 #define ENA_ADMIN_EXTRA_PROPERTIES_COUNT 32
39
40 #define ENA_ADMIN_RSS_KEY_PARTS 10
41
42 #define ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK 0x3F
43 #define ENA_ADMIN_CUSTOMER_METRICS_MIN_SUPPORT_MASK 0x1F
44
45 /* customer metrics - in correlation with
46 * ENA_ADMIN_CUSTOMER_METRICS_SUPPORT_MASK
47 */
48 enum ena_admin_customer_metrics_id {
49 ENA_ADMIN_BW_IN_ALLOWANCE_EXCEEDED = 0,
50 ENA_ADMIN_BW_OUT_ALLOWANCE_EXCEEDED = 1,
51 ENA_ADMIN_PPS_ALLOWANCE_EXCEEDED = 2,
52 ENA_ADMIN_CONNTRACK_ALLOWANCE_EXCEEDED = 3,
53 ENA_ADMIN_LINKLOCAL_ALLOWANCE_EXCEEDED = 4,
54 ENA_ADMIN_CONNTRACK_ALLOWANCE_AVAILABLE = 5,
55 };
56
57 enum ena_admin_aq_opcode {
58 ENA_ADMIN_CREATE_SQ = 1,
59 ENA_ADMIN_DESTROY_SQ = 2,
60 ENA_ADMIN_CREATE_CQ = 3,
61 ENA_ADMIN_DESTROY_CQ = 4,
62 ENA_ADMIN_GET_FEATURE = 8,
63 ENA_ADMIN_SET_FEATURE = 9,
64 ENA_ADMIN_GET_STATS = 11,
65 };
66
67 enum ena_admin_aq_completion_status {
68 ENA_ADMIN_SUCCESS = 0,
69 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1,
70 ENA_ADMIN_BAD_OPCODE = 2,
71 ENA_ADMIN_UNSUPPORTED_OPCODE = 3,
72 ENA_ADMIN_MALFORMED_REQUEST = 4,
73 /* Additional status is provided in ACQ entry extended_status */
74 ENA_ADMIN_ILLEGAL_PARAMETER = 5,
75 ENA_ADMIN_UNKNOWN_ERROR = 6,
76 ENA_ADMIN_RESOURCE_BUSY = 7,
77 };
78
79 /* subcommands for the set/get feature admin commands */
80 enum ena_admin_aq_feature_id {
81 ENA_ADMIN_DEVICE_ATTRIBUTES = 1,
82 ENA_ADMIN_MAX_QUEUES_NUM = 2,
83 ENA_ADMIN_HW_HINTS = 3,
84 ENA_ADMIN_LLQ = 4,
85 ENA_ADMIN_EXTRA_PROPERTIES_STRINGS = 5,
86 ENA_ADMIN_EXTRA_PROPERTIES_FLAGS = 6,
87 ENA_ADMIN_MAX_QUEUES_EXT = 7,
88 ENA_ADMIN_RSS_HASH_FUNCTION = 10,
89 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11,
90 ENA_ADMIN_RSS_INDIRECTION_TABLE_CONFIG = 12,
91 ENA_ADMIN_MTU = 14,
92 ENA_ADMIN_RSS_HASH_INPUT = 18,
93 ENA_ADMIN_INTERRUPT_MODERATION = 20,
94 ENA_ADMIN_AENQ_CONFIG = 26,
95 ENA_ADMIN_LINK_CONFIG = 27,
96 ENA_ADMIN_HOST_ATTR_CONFIG = 28,
97 ENA_ADMIN_PHC_CONFIG = 29,
98 ENA_ADMIN_FEATURES_OPCODE_NUM = 32,
99 };
100
101 /* feature version for the set/get ENA_ADMIN_LLQ feature admin commands */
102 enum ena_admin_llq_feature_version {
103 /* legacy base version in older drivers */
104 ENA_ADMIN_LLQ_FEATURE_VERSION_0_LEGACY = 0,
105 /* support entry_size recommendation by device */
106 ENA_ADMIN_LLQ_FEATURE_VERSION_1 = 1,
107 };
108
109 /* device capabilities */
110 enum ena_admin_aq_caps_id {
111 ENA_ADMIN_ENI_STATS = 0,
112 /* ENA SRD customer metrics */
113 ENA_ADMIN_ENA_SRD_INFO = 1,
114 ENA_ADMIN_CUSTOMER_METRICS = 2,
115 ENA_ADMIN_EXTENDED_RESET_REASONS = 3,
116 ENA_ADMIN_CDESC_MBZ = 4,
117 };
118
119 enum ena_admin_placement_policy_type {
120 /* descriptors and headers are in host memory */
121 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1,
122 /* descriptors and headers are in device memory (a.k.a Low Latency
123 * Queue)
124 */
125 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3,
126 };
127
128 enum ena_admin_link_types {
129 ENA_ADMIN_LINK_SPEED_1G = 0x1,
130 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2,
131 ENA_ADMIN_LINK_SPEED_5G = 0x4,
132 ENA_ADMIN_LINK_SPEED_10G = 0x8,
133 ENA_ADMIN_LINK_SPEED_25G = 0x10,
134 ENA_ADMIN_LINK_SPEED_40G = 0x20,
135 ENA_ADMIN_LINK_SPEED_50G = 0x40,
136 ENA_ADMIN_LINK_SPEED_100G = 0x80,
137 ENA_ADMIN_LINK_SPEED_200G = 0x100,
138 ENA_ADMIN_LINK_SPEED_400G = 0x200,
139 };
140
141 enum ena_admin_completion_policy_type {
142 /* completion queue entry for each sq descriptor */
143 ENA_ADMIN_COMPLETION_POLICY_DESC = 0,
144 /* completion queue entry upon request in sq descriptor */
145 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1,
146 /* current queue head pointer is updated in OS memory upon sq
147 * descriptor request
148 */
149 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2,
150 /* current queue head pointer is updated in OS memory for each sq
151 * descriptor
152 */
153 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3,
154 };
155
156 /* basic stats return ena_admin_basic_stats while extanded stats return a
157 * buffer (string format) with additional statistics per queue and per
158 * device id
159 */
160 enum ena_admin_get_stats_type {
161 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0,
162 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1,
163 /* extra HW stats for specific network interface */
164 ENA_ADMIN_GET_STATS_TYPE_ENI = 2,
165 /* extra HW stats for ENA SRD */
166 ENA_ADMIN_GET_STATS_TYPE_ENA_SRD = 3,
167 ENA_ADMIN_GET_STATS_TYPE_CUSTOMER_METRICS = 4,
168
169 };
170
171 enum ena_admin_get_stats_scope {
172 ENA_ADMIN_SPECIFIC_QUEUE = 0,
173 ENA_ADMIN_ETH_TRAFFIC = 1,
174 };
175
176 enum ena_admin_phc_feature_version {
177 /* Readless with error_bound */
178 ENA_ADMIN_PHC_FEATURE_VERSION_0 = 0,
179 };
180
181 enum ena_admin_phc_error_flags {
182 ENA_ADMIN_PHC_ERROR_FLAG_TIMESTAMP = BIT(0),
183 ENA_ADMIN_PHC_ERROR_FLAG_ERROR_BOUND = BIT(1),
184 };
185
186 /* ENA SRD configuration for ENI */
187 enum ena_admin_ena_srd_flags {
188 /* Feature enabled */
189 ENA_ADMIN_ENA_SRD_ENABLED = BIT(0),
190 /* UDP support enabled */
191 ENA_ADMIN_ENA_SRD_UDP_ENABLED = BIT(1),
192 /* Bypass Rx UDP ordering */
193 ENA_ADMIN_ENA_SRD_UDP_ORDERING_BYPASS_ENABLED = BIT(2),
194 };
195
196 struct ena_admin_aq_common_desc {
197 /* 11:0 : command_id
198 * 15:12 : reserved12
199 */
200 uint16_t command_id;
201
202 /* as appears in ena_admin_aq_opcode */
203 uint8_t opcode;
204
205 /* 0 : phase
206 * 1 : ctrl_data - control buffer address valid
207 * 2 : ctrl_data_indirect - control buffer address
208 * points to list of pages with addresses of control
209 * buffers
210 * 7:3 : reserved3
211 */
212 uint8_t flags;
213 };
214
215 /* used in ena_admin_aq_entry. Can point directly to control data, or to a
216 * page list chunk. Used also at the end of indirect mode page list chunks,
217 * for chaining.
218 */
219 struct ena_admin_ctrl_buff_info {
220 uint32_t length;
221
222 struct ena_common_mem_addr address;
223 };
224
225 struct ena_admin_sq {
226 uint16_t sq_idx;
227
228 /* 4:0 : reserved
229 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
230 */
231 uint8_t sq_identity;
232
233 uint8_t reserved1;
234 };
235
236 struct ena_admin_aq_entry {
237 struct ena_admin_aq_common_desc aq_common_descriptor;
238
239 union {
240 uint32_t inline_data_w1[3];
241
242 struct ena_admin_ctrl_buff_info control_buffer;
243 } u;
244
245 uint32_t inline_data_w4[12];
246 };
247
248 struct ena_admin_acq_common_desc {
249 /* command identifier to associate it with the aq descriptor
250 * 11:0 : command_id
251 * 15:12 : reserved12
252 */
253 uint16_t command;
254
255 uint8_t status;
256
257 /* 0 : phase
258 * 7:1 : reserved1
259 */
260 uint8_t flags;
261
262 uint16_t extended_status;
263
264 /* indicates to the driver which AQ entry has been consumed by the
265 * device and could be reused
266 */
267 uint16_t sq_head_indx;
268 };
269
270 struct ena_admin_acq_entry {
271 struct ena_admin_acq_common_desc acq_common_descriptor;
272
273 uint32_t response_specific_data[14];
274 };
275
276 struct ena_admin_aq_create_sq_cmd {
277 struct ena_admin_aq_common_desc aq_common_descriptor;
278
279 /* 4:0 : reserved0_w1
280 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
281 */
282 uint8_t sq_identity;
283
284 uint8_t reserved8_w1;
285
286 /* 3:0 : placement_policy - Describing where the SQ
287 * descriptor ring and the SQ packet headers reside:
288 * 0x1 - descriptors and headers are in OS memory,
289 * 0x3 - descriptors and headers in device memory
290 * (a.k.a Low Latency Queue)
291 * 6:4 : completion_policy - Describing what policy
292 * to use for generation completion entry (cqe) in
293 * the CQ associated with this SQ: 0x0 - cqe for each
294 * sq descriptor, 0x1 - cqe upon request in sq
295 * descriptor, 0x2 - current queue head pointer is
296 * updated in OS memory upon sq descriptor request
297 * 0x3 - current queue head pointer is updated in OS
298 * memory for each sq descriptor
299 * 7 : reserved15_w1
300 */
301 uint8_t sq_caps_2;
302
303 /* 0 : is_physically_contiguous - Described if the
304 * queue ring memory is allocated in physical
305 * contiguous pages or split.
306 * 7:1 : reserved17_w1
307 */
308 uint8_t sq_caps_3;
309
310 /* associated completion queue id. This CQ must be created prior to SQ
311 * creation
312 */
313 uint16_t cq_idx;
314
315 /* submission queue depth in entries */
316 uint16_t sq_depth;
317
318 /* SQ physical base address in OS memory. This field should not be
319 * used for Low Latency queues. Has to be page aligned.
320 */
321 struct ena_common_mem_addr sq_ba;
322
323 /* specifies queue head writeback location in OS memory. Valid if
324 * completion_policy is set to completion_policy_head_on_demand or
325 * completion_policy_head. Has to be cache aligned
326 */
327 struct ena_common_mem_addr sq_head_writeback;
328
329 uint32_t reserved0_w7;
330
331 uint32_t reserved0_w8;
332 };
333
334 enum ena_admin_sq_direction {
335 ENA_ADMIN_SQ_DIRECTION_TX = 1,
336 ENA_ADMIN_SQ_DIRECTION_RX = 2,
337 };
338
339 struct ena_admin_acq_create_sq_resp_desc {
340 struct ena_admin_acq_common_desc acq_common_desc;
341
342 uint16_t sq_idx;
343
344 uint16_t reserved;
345
346 /* queue doorbell address as an offset to PCIe MMIO REG BAR */
347 uint32_t sq_doorbell_offset;
348
349 /* low latency queue ring base address as an offset to PCIe MMIO
350 * LLQ_MEM BAR
351 */
352 uint32_t llq_descriptors_offset;
353
354 /* low latency queue headers' memory as an offset to PCIe MMIO
355 * LLQ_MEM BAR
356 */
357 uint32_t llq_headers_offset;
358 };
359
360 struct ena_admin_aq_destroy_sq_cmd {
361 struct ena_admin_aq_common_desc aq_common_descriptor;
362
363 struct ena_admin_sq sq;
364 };
365
366 struct ena_admin_acq_destroy_sq_resp_desc {
367 struct ena_admin_acq_common_desc acq_common_desc;
368 };
369
370 struct ena_admin_aq_create_cq_cmd {
371 struct ena_admin_aq_common_desc aq_common_descriptor;
372
373 /* 4:0 : reserved5
374 * 5 : interrupt_mode_enabled - if set, cq operates
375 * in interrupt mode, otherwise - polling
376 * 7:6 : reserved6
377 */
378 uint8_t cq_caps_1;
379
380 /* 4:0 : cq_entry_size_words - size of CQ entry in
381 * 32-bit words, valid values: 4, 8.
382 * 7:5 : reserved7
383 */
384 uint8_t cq_caps_2;
385
386 /* completion queue depth in # of entries. must be power of 2 */
387 uint16_t cq_depth;
388
389 /* msix vector assigned to this cq */
390 uint32_t msix_vector;
391
392 /* cq physical base address in OS memory. CQ must be physically
393 * contiguous
394 */
395 struct ena_common_mem_addr cq_ba;
396 };
397
398 struct ena_admin_acq_create_cq_resp_desc {
399 struct ena_admin_acq_common_desc acq_common_desc;
400
401 uint16_t cq_idx;
402
403 /* actual cq depth in number of entries */
404 uint16_t cq_actual_depth;
405
406 uint32_t numa_node_register_offset;
407
408 uint32_t cq_head_db_register_offset;
409
410 uint32_t cq_interrupt_unmask_register_offset;
411 };
412
413 struct ena_admin_aq_destroy_cq_cmd {
414 struct ena_admin_aq_common_desc aq_common_descriptor;
415
416 uint16_t cq_idx;
417
418 uint16_t reserved1;
419 };
420
421 struct ena_admin_acq_destroy_cq_resp_desc {
422 struct ena_admin_acq_common_desc acq_common_desc;
423 };
424
425 /* ENA AQ Get Statistics command. Extended statistics are placed in control
426 * buffer pointed by AQ entry
427 */
428 struct ena_admin_aq_get_stats_cmd {
429 struct ena_admin_aq_common_desc aq_common_descriptor;
430
431 union {
432 /* command specific inline data */
433 uint32_t inline_data_w1[3];
434
435 struct ena_admin_ctrl_buff_info control_buffer;
436 } u;
437
438 /* stats type as defined in enum ena_admin_get_stats_type */
439 uint8_t type;
440
441 /* stats scope defined in enum ena_admin_get_stats_scope */
442 uint8_t scope;
443
444 uint16_t reserved3;
445
446 /* queue id. used when scope is specific_queue */
447 uint16_t queue_idx;
448
449 /* device id, value 0xFFFF means mine. only privileged device can get
450 * stats of other device
451 */
452 uint16_t device_id;
453
454 /* a bitmap representing the requested metric values */
455 uint64_t requested_metrics;
456 };
457
458 /* Basic Statistics Command. */
459 struct ena_admin_basic_stats {
460 uint32_t tx_bytes_low;
461
462 uint32_t tx_bytes_high;
463
464 uint32_t tx_pkts_low;
465
466 uint32_t tx_pkts_high;
467
468 uint32_t rx_bytes_low;
469
470 uint32_t rx_bytes_high;
471
472 uint32_t rx_pkts_low;
473
474 uint32_t rx_pkts_high;
475
476 uint32_t rx_drops_low;
477
478 uint32_t rx_drops_high;
479
480 uint32_t tx_drops_low;
481
482 uint32_t tx_drops_high;
483
484 uint32_t rx_overruns_low;
485
486 uint32_t rx_overruns_high;
487 };
488
489 /* ENI Statistics Command. */
490 struct ena_admin_eni_stats {
491 /* The number of packets shaped due to inbound aggregate BW
492 * allowance being exceeded
493 */
494 uint64_t bw_in_allowance_exceeded;
495
496 /* The number of packets shaped due to outbound aggregate BW
497 * allowance being exceeded
498 */
499 uint64_t bw_out_allowance_exceeded;
500
501 /* The number of packets shaped due to PPS allowance being exceeded */
502 uint64_t pps_allowance_exceeded;
503
504 /* The number of packets shaped due to connection tracking
505 * allowance being exceeded and leading to failure in establishment
506 * of new connections
507 */
508 uint64_t conntrack_allowance_exceeded;
509
510 /* The number of packets shaped due to linklocal packet rate
511 * allowance being exceeded
512 */
513 uint64_t linklocal_allowance_exceeded;
514 };
515
516 struct ena_admin_ena_srd_stats {
517 /* Number of packets transmitted over ENA SRD */
518 uint64_t ena_srd_tx_pkts;
519
520 /* Number of packets transmitted or could have been
521 * transmitted over ENA SRD
522 */
523 uint64_t ena_srd_eligible_tx_pkts;
524
525 /* Number of packets received over ENA SRD */
526 uint64_t ena_srd_rx_pkts;
527
528 /* Percentage of the ENA SRD resources that is in use */
529 uint64_t ena_srd_resource_utilization;
530 };
531
532 /* ENA SRD Statistics Command */
533 struct ena_admin_ena_srd_info {
534 /* ENA SRD configuration bitmap. See ena_admin_ena_srd_flags for
535 * details
536 */
537 uint64_t flags;
538
539 struct ena_admin_ena_srd_stats ena_srd_stats;
540 };
541
542 /* Customer Metrics Command. */
543 struct ena_admin_customer_metrics {
544 /* A bitmap representing the reported customer metrics according to
545 * the order they are reported
546 */
547 uint64_t reported_metrics;
548 };
549
550 struct ena_admin_acq_get_stats_resp {
551 struct ena_admin_acq_common_desc acq_common_desc;
552
553 union {
554 uint64_t raw[7];
555
556 struct ena_admin_basic_stats basic_stats;
557
558 struct ena_admin_eni_stats eni_stats;
559
560 struct ena_admin_ena_srd_info ena_srd_info;
561
562 struct ena_admin_customer_metrics customer_metrics;
563 } u;
564 };
565
566 struct ena_admin_get_set_feature_common_desc {
567 /* 1:0 : select - 0x1 - current value; 0x3 - default
568 * value
569 * 7:3 : reserved3
570 */
571 uint8_t flags;
572
573 /* as appears in ena_admin_aq_feature_id */
574 uint8_t feature_id;
575
576 /* The driver specifies the max feature version it supports and the
577 * device responds with the currently supported feature version. The
578 * field is zero based
579 */
580 uint8_t feature_version;
581
582 uint8_t reserved8;
583 };
584
585 struct ena_admin_device_attr_feature_desc {
586 uint32_t impl_id;
587
588 uint32_t device_version;
589
590 /* bitmap of ena_admin_aq_feature_id, which represents supported
591 * subcommands for the set/get feature admin commands.
592 */
593 uint32_t supported_features;
594
595 /* bitmap of ena_admin_aq_caps_id, which represents device
596 * capabilities.
597 */
598 uint32_t capabilities;
599
600 /* Indicates how many bits are used physical address access. */
601 uint32_t phys_addr_width;
602
603 /* Indicates how many bits are used virtual address access. */
604 uint32_t virt_addr_width;
605
606 /* unicast MAC address (in Network byte order) */
607 uint8_t mac_addr[6];
608
609 uint8_t reserved7[2];
610
611 uint32_t max_mtu;
612 };
613
614 enum ena_admin_llq_header_location {
615 /* header is in descriptor list */
616 ENA_ADMIN_INLINE_HEADER = 1,
617 /* header in a separate ring, implies 16B descriptor list entry */
618 ENA_ADMIN_HEADER_RING = 2,
619 };
620
621 enum ena_admin_llq_ring_entry_size {
622 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1,
623 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2,
624 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4,
625 };
626
627 enum ena_admin_llq_num_descs_before_header {
628 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0,
629 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1,
630 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2,
631 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4,
632 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8,
633 };
634
635 /* packet descriptor list entry always starts with one or more descriptors,
636 * followed by a header. The rest of the descriptors are located in the
637 * beginning of the subsequent entry. Stride refers to how the rest of the
638 * descriptors are placed. This field is relevant only for inline header
639 * mode
640 */
641 enum ena_admin_llq_stride_ctrl {
642 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1,
643 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2,
644 };
645
646 enum ena_admin_accel_mode_feat {
647 ENA_ADMIN_DISABLE_META_CACHING = 0,
648 ENA_ADMIN_LIMIT_TX_BURST = 1,
649 };
650
651 struct ena_admin_accel_mode_get {
652 /* bit field of enum ena_admin_accel_mode_feat */
653 uint16_t supported_flags;
654
655 /* maximum burst size between two doorbells. The size is in bytes */
656 uint16_t max_tx_burst_size;
657 };
658
659 struct ena_admin_accel_mode_set {
660 /* bit field of enum ena_admin_accel_mode_feat */
661 uint16_t enabled_flags;
662
663 uint16_t reserved;
664 };
665
666 struct ena_admin_accel_mode_req {
667 union {
668 uint32_t raw[2];
669
670 struct ena_admin_accel_mode_get get;
671
672 struct ena_admin_accel_mode_set set;
673 } u;
674 };
675
676 struct ena_admin_feature_llq_desc {
677 uint32_t max_llq_num;
678
679 uint32_t max_llq_depth;
680
681 /* specify the header locations the device supports. bitfield of enum
682 * ena_admin_llq_header_location.
683 */
684 uint16_t header_location_ctrl_supported;
685
686 /* the header location the driver selected to use. */
687 uint16_t header_location_ctrl_enabled;
688
689 /* if inline header is specified - this is the size of descriptor list
690 * entry. If header in a separate ring is specified - this is the size
691 * of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size.
692 * specify the entry sizes the device supports
693 */
694 uint16_t entry_size_ctrl_supported;
695
696 /* the entry size the driver selected to use. */
697 uint16_t entry_size_ctrl_enabled;
698
699 /* valid only if inline header is specified. First entry associated with
700 * the packet includes descriptors and header. Rest of the entries
701 * occupied by descriptors. This parameter defines the max number of
702 * descriptors precedding the header in the first entry. The field is
703 * bitfield of enum ena_admin_llq_num_descs_before_header and specify
704 * the values the device supports
705 */
706 uint16_t desc_num_before_header_supported;
707
708 /* the desire field the driver selected to use */
709 uint16_t desc_num_before_header_enabled;
710
711 /* valid only if inline was chosen. bitfield of enum
712 * ena_admin_llq_stride_ctrl
713 */
714 uint16_t descriptors_stride_ctrl_supported;
715
716 /* the stride control the driver selected to use */
717 uint16_t descriptors_stride_ctrl_enabled;
718
719 /* feature version of device resp to either GET/SET commands. */
720 uint8_t feature_version;
721
722 /* llq entry size recommended by the device,
723 * values correlated to enum ena_admin_llq_ring_entry_size.
724 * used only for GET command.
725 */
726 uint8_t entry_size_recommended;
727
728 /* max depth of wide llq, or 0 for N/A */
729 uint16_t max_wide_llq_depth;
730
731 /* accelerated low latency queues requirement. driver needs to
732 * support those requirements in order to use accelerated llq
733 */
734 struct ena_admin_accel_mode_req accel_mode;
735 };
736
737 struct ena_admin_queue_ext_feature_fields {
738 uint32_t max_tx_sq_num;
739
740 uint32_t max_tx_cq_num;
741
742 uint32_t max_rx_sq_num;
743
744 uint32_t max_rx_cq_num;
745
746 uint32_t max_tx_sq_depth;
747
748 uint32_t max_tx_cq_depth;
749
750 uint32_t max_rx_sq_depth;
751
752 uint32_t max_rx_cq_depth;
753
754 uint32_t max_tx_header_size;
755
756 /* Maximum Descriptors number, including meta descriptor, allowed for a
757 * single Tx packet
758 */
759 uint16_t max_per_packet_tx_descs;
760
761 /* Maximum Descriptors number allowed for a single Rx packet */
762 uint16_t max_per_packet_rx_descs;
763 };
764
765 struct ena_admin_queue_feature_desc {
766 uint32_t max_sq_num;
767
768 uint32_t max_sq_depth;
769
770 uint32_t max_cq_num;
771
772 uint32_t max_cq_depth;
773
774 uint32_t max_legacy_llq_num;
775
776 uint32_t max_legacy_llq_depth;
777
778 uint32_t max_header_size;
779
780 /* Maximum Descriptors number, including meta descriptor, allowed for a
781 * single Tx packet
782 */
783 uint16_t max_packet_tx_descs;
784
785 /* Maximum Descriptors number allowed for a single Rx packet */
786 uint16_t max_packet_rx_descs;
787 };
788
789 struct ena_admin_set_feature_mtu_desc {
790 /* exclude L2 */
791 uint32_t mtu;
792 };
793
794 struct ena_admin_get_extra_properties_strings_desc {
795 uint32_t count;
796 };
797
798 struct ena_admin_get_extra_properties_flags_desc {
799 uint32_t flags;
800 };
801
802 struct ena_admin_set_feature_host_attr_desc {
803 /* host OS info base address in OS memory. host info is 4KB of
804 * physically contiguous
805 */
806 struct ena_common_mem_addr os_info_ba;
807
808 /* host debug area base address in OS memory. debug area must be
809 * physically contiguous
810 */
811 struct ena_common_mem_addr debug_ba;
812
813 /* debug area size */
814 uint32_t debug_area_size;
815 };
816
817 struct ena_admin_feature_intr_moder_desc {
818 /* interrupt delay granularity in usec */
819 uint16_t intr_delay_resolution;
820
821 uint16_t reserved;
822 };
823
824 struct ena_admin_get_feature_link_desc {
825 /* Link speed in Mb */
826 uint32_t speed;
827
828 /* bit field of enum ena_admin_link types */
829 uint32_t supported;
830
831 /* 0 : autoneg
832 * 1 : duplex - Full Duplex
833 * 31:2 : reserved2
834 */
835 uint32_t flags;
836 };
837
838 struct ena_admin_feature_aenq_desc {
839 /* bitmask for AENQ groups the device can report */
840 uint32_t supported_groups;
841
842 /* bitmask for AENQ groups to report */
843 uint32_t enabled_groups;
844 };
845
846 struct ena_admin_feature_offload_desc {
847 /* 0 : TX_L3_csum_ipv4
848 * 1 : TX_L4_ipv4_csum_part - The checksum field
849 * should be initialized with pseudo header checksum
850 * 2 : TX_L4_ipv4_csum_full
851 * 3 : TX_L4_ipv6_csum_part - The checksum field
852 * should be initialized with pseudo header checksum
853 * 4 : TX_L4_ipv6_csum_full
854 * 5 : tso_ipv4
855 * 6 : tso_ipv6
856 * 7 : tso_ecn
857 */
858 uint32_t tx;
859
860 /* Receive side supported stateless offload
861 * 0 : RX_L3_csum_ipv4 - IPv4 checksum
862 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
863 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
864 * 3 : RX_hash - Hash calculation
865 */
866 uint32_t rx_supported;
867
868 uint32_t rx_enabled;
869 };
870
871 enum ena_admin_hash_functions {
872 ENA_ADMIN_TOEPLITZ = 1,
873 ENA_ADMIN_CRC32 = 2,
874 };
875
876 struct ena_admin_feature_rss_flow_hash_control {
877 uint32_t key_parts;
878
879 uint32_t reserved;
880
881 uint32_t key[ENA_ADMIN_RSS_KEY_PARTS];
882 };
883
884 struct ena_admin_feature_rss_flow_hash_function {
885 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */
886 uint32_t supported_func;
887
888 /* 7:0 : selected_func - bitmask of
889 * ena_admin_hash_functions
890 */
891 uint32_t selected_func;
892
893 /* initial value */
894 uint32_t init_val;
895 };
896
897 /* RSS flow hash protocols */
898 enum ena_admin_flow_hash_proto {
899 ENA_ADMIN_RSS_TCP4 = 0,
900 ENA_ADMIN_RSS_UDP4 = 1,
901 ENA_ADMIN_RSS_TCP6 = 2,
902 ENA_ADMIN_RSS_UDP6 = 3,
903 ENA_ADMIN_RSS_IP4 = 4,
904 ENA_ADMIN_RSS_IP6 = 5,
905 ENA_ADMIN_RSS_IP4_FRAG = 6,
906 ENA_ADMIN_RSS_NOT_IP = 7,
907 /* TCPv6 with extension header */
908 ENA_ADMIN_RSS_TCP6_EX = 8,
909 /* IPv6 with extension header */
910 ENA_ADMIN_RSS_IP6_EX = 9,
911 ENA_ADMIN_RSS_PROTO_NUM = 16,
912 };
913
914 /* RSS flow hash fields */
915 enum ena_admin_flow_hash_fields {
916 /* Ethernet Dest Addr */
917 ENA_ADMIN_RSS_L2_DA = BIT(0),
918 /* Ethernet Src Addr */
919 ENA_ADMIN_RSS_L2_SA = BIT(1),
920 /* ipv4/6 Dest Addr */
921 ENA_ADMIN_RSS_L3_DA = BIT(2),
922 /* ipv4/6 Src Addr */
923 ENA_ADMIN_RSS_L3_SA = BIT(3),
924 /* tcp/udp Dest Port */
925 ENA_ADMIN_RSS_L4_DP = BIT(4),
926 /* tcp/udp Src Port */
927 ENA_ADMIN_RSS_L4_SP = BIT(5),
928 };
929
930 struct ena_admin_proto_input {
931 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */
932 uint16_t fields;
933
934 uint16_t reserved2;
935 };
936
937 struct ena_admin_feature_rss_hash_control {
938 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM];
939
940 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM];
941
942 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM];
943
944 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM];
945 };
946
947 struct ena_admin_feature_rss_flow_hash_input {
948 /* supported hash input sorting
949 * 1 : L3_sort - support swap L3 addresses if DA is
950 * smaller than SA
951 * 2 : L4_sort - support swap L4 ports if DP smaller
952 * SP
953 */
954 uint16_t supported_input_sort;
955
956 /* enabled hash input sorting
957 * 1 : enable_L3_sort - enable swap L3 addresses if
958 * DA smaller than SA
959 * 2 : enable_L4_sort - enable swap L4 ports if DP
960 * smaller than SP
961 */
962 uint16_t enabled_input_sort;
963 };
964
965 struct ena_admin_host_info {
966 /* Host OS type defined as ENA_ADMIN_OS_* */
967 uint32_t os_type;
968
969 /* os distribution string format */
970 uint8_t os_dist_str[128];
971
972 /* OS distribution numeric format */
973 uint32_t os_dist;
974
975 /* kernel version string format */
976 uint8_t kernel_ver_str[32];
977
978 /* Kernel version numeric format */
979 uint32_t kernel_ver;
980
981 /* 7:0 : major
982 * 15:8 : minor
983 * 23:16 : sub_minor
984 * 31:24 : module_type
985 */
986 uint32_t driver_version;
987
988 /* features bitmap */
989 uint32_t supported_network_features[2];
990
991 /* ENA spec version of driver */
992 uint16_t ena_spec_version;
993
994 /* ENA device's Bus, Device and Function
995 * 2:0 : function
996 * 7:3 : device
997 * 15:8 : bus
998 */
999 uint16_t bdf;
1000
1001 /* Number of CPUs */
1002 uint16_t num_cpus;
1003
1004 uint16_t reserved;
1005
1006 /* 0 : reserved
1007 * 1 : rx_offset
1008 * 2 : interrupt_moderation
1009 * 3 : rx_buf_mirroring
1010 * 4 : rss_configurable_function_key
1011 * 5 : reserved
1012 * 6 : rx_page_reuse
1013 * 7 : tx_ipv6_csum_offload
1014 * 8 : phc
1015 * 31:9 : reserved
1016 */
1017 uint32_t driver_supported_features;
1018 };
1019
1020 struct ena_admin_rss_ind_table_entry {
1021 uint16_t cq_idx;
1022
1023 uint16_t reserved;
1024 };
1025
1026 struct ena_admin_feature_rss_ind_table {
1027 /* min supported table size (2^min_size) */
1028 uint16_t min_size;
1029
1030 /* max supported table size (2^max_size) */
1031 uint16_t max_size;
1032
1033 /* table size (2^size) */
1034 uint16_t size;
1035
1036 /* 0 : one_entry_update - The ENA device supports
1037 * setting a single RSS table entry
1038 */
1039 uint8_t flags;
1040
1041 uint8_t reserved;
1042
1043 /* index of the inline entry. 0xFFFFFFFF means invalid */
1044 uint32_t inline_index;
1045
1046 /* used for updating single entry, ignored when setting the entire
1047 * table through the control buffer.
1048 */
1049 struct ena_admin_rss_ind_table_entry inline_entry;
1050 };
1051
1052 /* When hint value is 0, driver should use it's own predefined value */
1053 struct ena_admin_ena_hw_hints {
1054 /* value in ms */
1055 uint16_t mmio_read_timeout;
1056
1057 /* value in ms */
1058 uint16_t driver_watchdog_timeout;
1059
1060 /* Per packet tx completion timeout. value in ms */
1061 uint16_t missing_tx_completion_timeout;
1062
1063 uint16_t missed_tx_completion_count_threshold_to_reset;
1064
1065 /* value in ms */
1066 uint16_t admin_completion_tx_timeout;
1067
1068 uint16_t netdev_wd_timeout;
1069
1070 uint16_t max_tx_sgl_size;
1071
1072 uint16_t max_rx_sgl_size;
1073
1074 uint16_t reserved[8];
1075 };
1076
1077 struct ena_admin_get_feat_cmd {
1078 struct ena_admin_aq_common_desc aq_common_descriptor;
1079
1080 struct ena_admin_ctrl_buff_info control_buffer;
1081
1082 struct ena_admin_get_set_feature_common_desc feat_common;
1083
1084 uint32_t raw[11];
1085 };
1086
1087 struct ena_admin_queue_ext_feature_desc {
1088 /* version */
1089 uint8_t version;
1090
1091 uint8_t reserved1[3];
1092
1093 union {
1094 struct ena_admin_queue_ext_feature_fields max_queue_ext;
1095
1096 uint32_t raw[10];
1097 };
1098 };
1099
1100 struct ena_admin_feature_phc_desc {
1101 /* PHC version as defined in enum ena_admin_phc_feature_version,
1102 * used only for GET command as max supported PHC version by the device.
1103 */
1104 uint8_t version;
1105
1106 /* Reserved - MBZ */
1107 uint8_t reserved1[3];
1108
1109 /* PHC doorbell address as an offset to PCIe MMIO REG BAR,
1110 * used only for GET command.
1111 */
1112 uint32_t doorbell_offset;
1113
1114 /* Max time for valid PHC retrieval, passing this threshold will
1115 * fail the get-time request and block PHC requests for
1116 * block_timeout_usec, used only for GET command.
1117 */
1118 uint32_t expire_timeout_usec;
1119
1120 /* PHC requests block period, blocking starts if PHC request expired
1121 * in order to prevent floods on busy device,
1122 * used only for GET command.
1123 */
1124 uint32_t block_timeout_usec;
1125
1126 /* Shared PHC physical address (ena_admin_phc_resp),
1127 * used only for SET command.
1128 */
1129 struct ena_common_mem_addr output_address;
1130
1131 /* Shared PHC Size (ena_admin_phc_resp),
1132 * used only for SET command.
1133 */
1134 uint32_t output_length;
1135 };
1136
1137 struct ena_admin_get_feat_resp {
1138 struct ena_admin_acq_common_desc acq_common_desc;
1139
1140 union {
1141 uint32_t raw[14];
1142
1143 struct ena_admin_device_attr_feature_desc dev_attr;
1144
1145 struct ena_admin_feature_llq_desc llq;
1146
1147 struct ena_admin_queue_feature_desc max_queue;
1148
1149 struct ena_admin_queue_ext_feature_desc max_queue_ext;
1150
1151 struct ena_admin_feature_aenq_desc aenq;
1152
1153 struct ena_admin_get_feature_link_desc link;
1154
1155 struct ena_admin_feature_offload_desc offload;
1156
1157 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
1158
1159 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
1160
1161 struct ena_admin_feature_rss_ind_table ind_table;
1162
1163 struct ena_admin_feature_intr_moder_desc intr_moderation;
1164
1165 struct ena_admin_ena_hw_hints hw_hints;
1166
1167 struct ena_admin_feature_phc_desc phc;
1168
1169 struct ena_admin_get_extra_properties_strings_desc extra_properties_strings;
1170
1171 struct ena_admin_get_extra_properties_flags_desc extra_properties_flags;
1172 } u;
1173 };
1174
1175 struct ena_admin_set_feat_cmd {
1176 struct ena_admin_aq_common_desc aq_common_descriptor;
1177
1178 struct ena_admin_ctrl_buff_info control_buffer;
1179
1180 struct ena_admin_get_set_feature_common_desc feat_common;
1181
1182 union {
1183 uint32_t raw[11];
1184
1185 /* mtu size */
1186 struct ena_admin_set_feature_mtu_desc mtu;
1187
1188 /* host attributes */
1189 struct ena_admin_set_feature_host_attr_desc host_attr;
1190
1191 /* AENQ configuration */
1192 struct ena_admin_feature_aenq_desc aenq;
1193
1194 /* rss flow hash function */
1195 struct ena_admin_feature_rss_flow_hash_function flow_hash_func;
1196
1197 /* rss flow hash input */
1198 struct ena_admin_feature_rss_flow_hash_input flow_hash_input;
1199
1200 /* rss indirection table */
1201 struct ena_admin_feature_rss_ind_table ind_table;
1202
1203 /* LLQ configuration */
1204 struct ena_admin_feature_llq_desc llq;
1205
1206 /* PHC configuration */
1207 struct ena_admin_feature_phc_desc phc;
1208 } u;
1209 };
1210
1211 struct ena_admin_set_feat_resp {
1212 struct ena_admin_acq_common_desc acq_common_desc;
1213
1214 union {
1215 uint32_t raw[14];
1216 } u;
1217 };
1218
1219 struct ena_admin_aenq_common_desc {
1220 uint16_t group;
1221
1222 uint16_t syndrome;
1223
1224 /* 0 : phase
1225 * 7:1 : reserved - MBZ
1226 */
1227 uint8_t flags;
1228
1229 uint8_t reserved1[3];
1230
1231 uint32_t timestamp_low;
1232
1233 uint32_t timestamp_high;
1234 };
1235
1236 /* asynchronous event notification groups */
1237 enum ena_admin_aenq_group {
1238 ENA_ADMIN_LINK_CHANGE = 0,
1239 ENA_ADMIN_FATAL_ERROR = 1,
1240 ENA_ADMIN_WARNING = 2,
1241 ENA_ADMIN_NOTIFICATION = 3,
1242 ENA_ADMIN_KEEP_ALIVE = 4,
1243 ENA_ADMIN_REFRESH_CAPABILITIES = 5,
1244 ENA_ADMIN_CONF_NOTIFICATIONS = 6,
1245 ENA_ADMIN_DEVICE_REQUEST_RESET = 7,
1246 ENA_ADMIN_AENQ_GROUPS_NUM = 8,
1247 };
1248
1249 enum ena_admin_aenq_notification_syndrome {
1250 ENA_ADMIN_UPDATE_HINTS = 2,
1251 };
1252
1253 struct ena_admin_aenq_entry {
1254 struct ena_admin_aenq_common_desc aenq_common_desc;
1255
1256 /* command specific inline data */
1257 uint32_t inline_data_w4[12];
1258 };
1259
1260 struct ena_admin_aenq_link_change_desc {
1261 struct ena_admin_aenq_common_desc aenq_common_desc;
1262
1263 /* 0 : link_status */
1264 uint32_t flags;
1265 };
1266
1267 struct ena_admin_aenq_keep_alive_desc {
1268 struct ena_admin_aenq_common_desc aenq_common_desc;
1269
1270 uint32_t rx_drops_low;
1271
1272 uint32_t rx_drops_high;
1273
1274 uint32_t tx_drops_low;
1275
1276 uint32_t tx_drops_high;
1277
1278 uint32_t rx_overruns_low;
1279
1280 uint32_t rx_overruns_high;
1281 };
1282
1283 struct ena_admin_aenq_conf_notifications_desc {
1284 struct ena_admin_aenq_common_desc aenq_common_desc;
1285
1286 uint64_t notifications_bitmap;
1287
1288 uint64_t reserved;
1289 };
1290
1291 struct ena_admin_ena_mmio_req_read_less_resp {
1292 uint16_t req_id;
1293
1294 uint16_t reg_off;
1295
1296 /* value is valid when poll is cleared */
1297 uint32_t reg_val;
1298 };
1299
1300 struct ena_admin_phc_resp {
1301 /* Request Id, received from DB register */
1302 uint16_t req_id;
1303
1304 uint8_t reserved1[6];
1305
1306 /* PHC timestamp (nsec) */
1307 uint64_t timestamp;
1308
1309 uint8_t reserved2[8];
1310
1311 /* Timestamp error limit (nsec) */
1312 uint32_t error_bound;
1313
1314 /* Bit field of enum ena_admin_phc_error_flags */
1315 uint32_t error_flags;
1316
1317 uint8_t reserved3[32];
1318 };
1319
1320 /* aq_common_desc */
1321 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1322 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0)
1323 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1
1324 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1)
1325 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2
1326 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2)
1327
1328 /* sq */
1329 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5
1330 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5)
1331
1332 /* acq_common_desc */
1333 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0)
1334 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0)
1335
1336 /* aq_create_sq_cmd */
1337 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5
1338 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5)
1339 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0)
1340 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4
1341 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4)
1342 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0)
1343
1344 /* aq_create_cq_cmd */
1345 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5
1346 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5)
1347 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0)
1348
1349 /* get_set_feature_common_desc */
1350 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0)
1351
1352 /* get_feature_link_desc */
1353 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0)
1354 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1
1355 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1)
1356
1357 /* feature_offload_desc */
1358 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0)
1359 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1
1360 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1)
1361 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2
1362 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2)
1363 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3
1364 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3)
1365 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4
1366 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4)
1367 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5
1368 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5)
1369 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6
1370 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6)
1371 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7
1372 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7)
1373 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0)
1374 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1
1375 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1)
1376 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2
1377 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2)
1378 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3
1379 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3)
1380
1381 /* feature_rss_flow_hash_function */
1382 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0)
1383 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0)
1384
1385 /* feature_rss_flow_hash_input */
1386 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1
1387 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1)
1388 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2
1389 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2)
1390 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1
1391 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1)
1392 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2
1393 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2)
1394
1395 /* host_info */
1396 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0)
1397 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8
1398 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8)
1399 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16
1400 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16)
1401 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24
1402 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24)
1403 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0)
1404 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3
1405 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3)
1406 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8
1407 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8)
1408 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1
1409 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1)
1410 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2
1411 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2)
1412 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT 3
1413 #define ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK BIT(3)
1414 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT 4
1415 #define ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK BIT(4)
1416 #define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT 6
1417 #define ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK BIT(6)
1418 #define ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_SHIFT 7
1419 #define ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_MASK BIT(7)
1420 #define ENA_ADMIN_HOST_INFO_PHC_SHIFT 8
1421 #define ENA_ADMIN_HOST_INFO_PHC_MASK BIT(8)
1422
1423 /* feature_rss_ind_table */
1424 #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0)
1425
1426 /* aenq_common_desc */
1427 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0)
1428
1429 /* aenq_link_change_desc */
1430 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0)
1431
1432 #if !defined(DEFS_LINUX_MAINLINE)
get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc * p)1433 static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p)
1434 {
1435 return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1436 }
1437
set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc * p,uint16_t val)1438 static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val)
1439 {
1440 p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK;
1441 }
1442
get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc * p)1443 static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p)
1444 {
1445 return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1446 }
1447
set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc * p,uint8_t val)1448 static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val)
1449 {
1450 p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK;
1451 }
1452
get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc * p)1453 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p)
1454 {
1455 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT;
1456 }
1457
set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc * p,uint8_t val)1458 static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val)
1459 {
1460 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK;
1461 }
1462
get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc * p)1463 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p)
1464 {
1465 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT;
1466 }
1467
set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc * p,uint8_t val)1468 static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val)
1469 {
1470 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK;
1471 }
1472
get_ena_admin_sq_sq_direction(const struct ena_admin_sq * p)1473 static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p)
1474 {
1475 return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT;
1476 }
1477
set_ena_admin_sq_sq_direction(struct ena_admin_sq * p,uint8_t val)1478 static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val)
1479 {
1480 p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK;
1481 }
1482
get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc * p)1483 static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p)
1484 {
1485 return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1486 }
1487
set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc * p,uint16_t val)1488 static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val)
1489 {
1490 p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK;
1491 }
1492
get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc * p)1493 static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p)
1494 {
1495 return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1496 }
1497
set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc * p,uint8_t val)1498 static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val)
1499 {
1500 p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK;
1501 }
1502
get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd * p)1503 static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p)
1504 {
1505 return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT;
1506 }
1507
set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd * p,uint8_t val)1508 static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1509 {
1510 p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK;
1511 }
1512
get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd * p)1513 static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p)
1514 {
1515 return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1516 }
1517
set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd * p,uint8_t val)1518 static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1519 {
1520 p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK;
1521 }
1522
get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd * p)1523 static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p)
1524 {
1525 return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT;
1526 }
1527
set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd * p,uint8_t val)1528 static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1529 {
1530 p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK;
1531 }
1532
get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd * p)1533 static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p)
1534 {
1535 return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1536 }
1537
set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd * p,uint8_t val)1538 static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val)
1539 {
1540 p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK;
1541 }
1542
get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd * p)1543 static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p)
1544 {
1545 return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT;
1546 }
1547
set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd * p,uint8_t val)1548 static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1549 {
1550 p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK;
1551 }
1552
get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd * p)1553 static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p)
1554 {
1555 return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1556 }
1557
set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd * p,uint8_t val)1558 static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val)
1559 {
1560 p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK;
1561 }
1562
get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc * p)1563 static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p)
1564 {
1565 return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1566 }
1567
set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc * p,uint8_t val)1568 static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val)
1569 {
1570 p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK;
1571 }
1572
get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc * p)1573 static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p)
1574 {
1575 return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1576 }
1577
set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc * p,uint32_t val)1578 static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1579 {
1580 p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK;
1581 }
1582
get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc * p)1583 static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p)
1584 {
1585 return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT;
1586 }
1587
set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc * p,uint32_t val)1588 static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val)
1589 {
1590 p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK;
1591 }
1592
get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc * p)1593 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1594 {
1595 return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1596 }
1597
set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc * p,uint32_t val)1598 static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1599 {
1600 p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK;
1601 }
1602
get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc * p)1603 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p)
1604 {
1605 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT;
1606 }
1607
set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc * p,uint32_t val)1608 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1609 {
1610 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK;
1611 }
1612
get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc * p)1613 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p)
1614 {
1615 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT;
1616 }
1617
set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc * p,uint32_t val)1618 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1619 {
1620 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK;
1621 }
1622
get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc * p)1623 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p)
1624 {
1625 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT;
1626 }
1627
set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc * p,uint32_t val)1628 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val)
1629 {
1630 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK;
1631 }
1632
get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc * p)1633 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p)
1634 {
1635 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT;
1636 }
1637
set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc * p,uint32_t val)1638 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val)
1639 {
1640 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK;
1641 }
1642
get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc * p)1643 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p)
1644 {
1645 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT;
1646 }
1647
set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc * p,uint32_t val)1648 static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1649 {
1650 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK;
1651 }
1652
get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc * p)1653 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p)
1654 {
1655 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT;
1656 }
1657
set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc * p,uint32_t val)1658 static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val)
1659 {
1660 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK;
1661 }
1662
get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc * p)1663 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p)
1664 {
1665 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT;
1666 }
1667
set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc * p,uint32_t val)1668 static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val)
1669 {
1670 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK;
1671 }
1672
get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc * p)1673 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p)
1674 {
1675 return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1676 }
1677
set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc * p,uint32_t val)1678 static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val)
1679 {
1680 p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK;
1681 }
1682
get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc * p)1683 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p)
1684 {
1685 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT;
1686 }
1687
set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc * p,uint32_t val)1688 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1689 {
1690 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK;
1691 }
1692
get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc * p)1693 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p)
1694 {
1695 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT;
1696 }
1697
set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc * p,uint32_t val)1698 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val)
1699 {
1700 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK;
1701 }
1702
get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc * p)1703 static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p)
1704 {
1705 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT;
1706 }
1707
set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc * p,uint32_t val)1708 static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val)
1709 {
1710 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK;
1711 }
1712
get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function * p)1713 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p)
1714 {
1715 return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1716 }
1717
set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function * p,uint32_t val)1718 static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1719 {
1720 p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK;
1721 }
1722
get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function * p)1723 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p)
1724 {
1725 return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1726 }
1727
set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function * p,uint32_t val)1728 static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val)
1729 {
1730 p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK;
1731 }
1732
get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input * p)1733 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1734 {
1735 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT;
1736 }
1737
set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input * p,uint16_t val)1738 static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1739 {
1740 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK;
1741 }
1742
get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input * p)1743 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1744 {
1745 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT;
1746 }
1747
set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input * p,uint16_t val)1748 static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1749 {
1750 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK;
1751 }
1752
get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input * p)1753 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1754 {
1755 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT;
1756 }
1757
set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input * p,uint16_t val)1758 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1759 {
1760 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK;
1761 }
1762
get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input * p)1763 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p)
1764 {
1765 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT;
1766 }
1767
set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input * p,uint16_t val)1768 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val)
1769 {
1770 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK;
1771 }
1772
get_ena_admin_host_info_major(const struct ena_admin_host_info * p)1773 static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p)
1774 {
1775 return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1776 }
1777
set_ena_admin_host_info_major(struct ena_admin_host_info * p,uint32_t val)1778 static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val)
1779 {
1780 p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK;
1781 }
1782
get_ena_admin_host_info_minor(const struct ena_admin_host_info * p)1783 static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p)
1784 {
1785 return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT;
1786 }
1787
set_ena_admin_host_info_minor(struct ena_admin_host_info * p,uint32_t val)1788 static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val)
1789 {
1790 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK;
1791 }
1792
get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info * p)1793 static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p)
1794 {
1795 return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT;
1796 }
1797
set_ena_admin_host_info_sub_minor(struct ena_admin_host_info * p,uint32_t val)1798 static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val)
1799 {
1800 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK;
1801 }
1802
get_ena_admin_host_info_module_type(const struct ena_admin_host_info * p)1803 static inline uint32_t get_ena_admin_host_info_module_type(const struct ena_admin_host_info *p)
1804 {
1805 return (p->driver_version & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK) >> ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT;
1806 }
1807
set_ena_admin_host_info_module_type(struct ena_admin_host_info * p,uint32_t val)1808 static inline void set_ena_admin_host_info_module_type(struct ena_admin_host_info *p, uint32_t val)
1809 {
1810 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT) & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK;
1811 }
1812
get_ena_admin_host_info_function(const struct ena_admin_host_info * p)1813 static inline uint16_t get_ena_admin_host_info_function(const struct ena_admin_host_info *p)
1814 {
1815 return p->bdf & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1816 }
1817
set_ena_admin_host_info_function(struct ena_admin_host_info * p,uint16_t val)1818 static inline void set_ena_admin_host_info_function(struct ena_admin_host_info *p, uint16_t val)
1819 {
1820 p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK;
1821 }
1822
get_ena_admin_host_info_device(const struct ena_admin_host_info * p)1823 static inline uint16_t get_ena_admin_host_info_device(const struct ena_admin_host_info *p)
1824 {
1825 return (p->bdf & ENA_ADMIN_HOST_INFO_DEVICE_MASK) >> ENA_ADMIN_HOST_INFO_DEVICE_SHIFT;
1826 }
1827
set_ena_admin_host_info_device(struct ena_admin_host_info * p,uint16_t val)1828 static inline void set_ena_admin_host_info_device(struct ena_admin_host_info *p, uint16_t val)
1829 {
1830 p->bdf |= (val << ENA_ADMIN_HOST_INFO_DEVICE_SHIFT) & ENA_ADMIN_HOST_INFO_DEVICE_MASK;
1831 }
1832
get_ena_admin_host_info_bus(const struct ena_admin_host_info * p)1833 static inline uint16_t get_ena_admin_host_info_bus(const struct ena_admin_host_info *p)
1834 {
1835 return (p->bdf & ENA_ADMIN_HOST_INFO_BUS_MASK) >> ENA_ADMIN_HOST_INFO_BUS_SHIFT;
1836 }
1837
set_ena_admin_host_info_bus(struct ena_admin_host_info * p,uint16_t val)1838 static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, uint16_t val)
1839 {
1840 p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK;
1841 }
1842
get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info * p)1843 static inline uint32_t get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info *p)
1844 {
1845 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK) >> ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT;
1846 }
1847
set_ena_admin_host_info_rx_offset(struct ena_admin_host_info * p,uint32_t val)1848 static inline void set_ena_admin_host_info_rx_offset(struct ena_admin_host_info *p, uint32_t val)
1849 {
1850 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT) & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK;
1851 }
1852
get_ena_admin_host_info_interrupt_moderation(const struct ena_admin_host_info * p)1853 static inline uint32_t get_ena_admin_host_info_interrupt_moderation(const struct ena_admin_host_info *p)
1854 {
1855 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK) >> ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT;
1856 }
1857
set_ena_admin_host_info_interrupt_moderation(struct ena_admin_host_info * p,uint32_t val)1858 static inline void set_ena_admin_host_info_interrupt_moderation(struct ena_admin_host_info *p, uint32_t val)
1859 {
1860 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT) & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK;
1861 }
1862
get_ena_admin_host_info_rx_buf_mirroring(const struct ena_admin_host_info * p)1863 static inline uint32_t get_ena_admin_host_info_rx_buf_mirroring(const struct ena_admin_host_info *p)
1864 {
1865 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK) >> ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT;
1866 }
1867
set_ena_admin_host_info_rx_buf_mirroring(struct ena_admin_host_info * p,uint32_t val)1868 static inline void set_ena_admin_host_info_rx_buf_mirroring(struct ena_admin_host_info *p, uint32_t val)
1869 {
1870 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_SHIFT) & ENA_ADMIN_HOST_INFO_RX_BUF_MIRRORING_MASK;
1871 }
1872
get_ena_admin_host_info_rss_configurable_function_key(const struct ena_admin_host_info * p)1873 static inline uint32_t get_ena_admin_host_info_rss_configurable_function_key(const struct ena_admin_host_info *p)
1874 {
1875 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK) >> ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT;
1876 }
1877
set_ena_admin_host_info_rss_configurable_function_key(struct ena_admin_host_info * p,uint32_t val)1878 static inline void set_ena_admin_host_info_rss_configurable_function_key(struct ena_admin_host_info *p, uint32_t val)
1879 {
1880 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_SHIFT) & ENA_ADMIN_HOST_INFO_RSS_CONFIGURABLE_FUNCTION_KEY_MASK;
1881 }
1882
get_ena_admin_host_info_rx_page_reuse(const struct ena_admin_host_info * p)1883 static inline uint32_t get_ena_admin_host_info_rx_page_reuse(const struct ena_admin_host_info *p)
1884 {
1885 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK) >> ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT;
1886 }
1887
set_ena_admin_host_info_rx_page_reuse(struct ena_admin_host_info * p,uint32_t val)1888 static inline void set_ena_admin_host_info_rx_page_reuse(struct ena_admin_host_info *p, uint32_t val)
1889 {
1890 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_SHIFT) & ENA_ADMIN_HOST_INFO_RX_PAGE_REUSE_MASK;
1891 }
1892
get_ena_admin_host_info_tx_ipv6_csum_offload(const struct ena_admin_host_info * p)1893 static inline uint32_t get_ena_admin_host_info_tx_ipv6_csum_offload(const struct ena_admin_host_info *p)
1894 {
1895 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_MASK) >> ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_SHIFT;
1896 }
1897
set_ena_admin_host_info_tx_ipv6_csum_offload(struct ena_admin_host_info * p,uint32_t val)1898 static inline void set_ena_admin_host_info_tx_ipv6_csum_offload(struct ena_admin_host_info *p, uint32_t val)
1899 {
1900 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_SHIFT) & ENA_ADMIN_HOST_INFO_TX_IPV6_CSUM_OFFLOAD_MASK;
1901 }
1902
get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table * p)1903 static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p)
1904 {
1905 return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1906 }
1907
set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table * p,uint8_t val)1908 static inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table *p, uint8_t val)
1909 {
1910 p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK;
1911 }
1912
get_ena_admin_host_info_phc(const struct ena_admin_host_info * p)1913 static inline uint32_t get_ena_admin_host_info_phc(const struct ena_admin_host_info *p)
1914 {
1915 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_PHC_MASK) >> ENA_ADMIN_HOST_INFO_PHC_SHIFT;
1916 }
1917
set_ena_admin_host_info_phc(struct ena_admin_host_info * p,uint32_t val)1918 static inline void set_ena_admin_host_info_phc(struct ena_admin_host_info *p, uint32_t val)
1919 {
1920 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_PHC_SHIFT) & ENA_ADMIN_HOST_INFO_PHC_MASK;
1921 }
1922
get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc * p)1923 static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p)
1924 {
1925 return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1926 }
1927
set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc * p,uint8_t val)1928 static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val)
1929 {
1930 p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK;
1931 }
1932
get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc * p)1933 static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p)
1934 {
1935 return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1936 }
1937
set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc * p,uint32_t val)1938 static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val)
1939 {
1940 p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK;
1941 }
1942
1943 #endif /* !defined(DEFS_LINUX_MAINLINE) */
1944 #endif /* _ENA_ADMIN_H_ */
1945