1 /* 2 * Copyright (c) 1982, 1986 Regents of the University of California. 3 * All rights reserved. 4 * 5 * %sccs.include.redist.c% 6 * 7 * @(#)if_enreg.h 7.3 (Berkeley) 06/28/90 8 */ 9 10 /* 11 * Xerox experimental ethernet registers. 12 * 13 * N.B.: status register and device address are read/write, 14 * device address is read-only, rest are WRITE ONLY! 15 */ 16 struct endevice { 17 short en_owc; /* output word count (10 bits) */ 18 short en_oba; /* output buffer address */ 19 short en_ostat; /* output control and status */ 20 short en_odelay; /* output start delay, 25usec units */ 21 short en_iwc; /* input word count */ 22 short en_iba; /* input buffer address */ 23 short en_istat; /* input csr */ 24 short en_addr; /* ~device address (low 8 bits) */ 25 }; 26 27 /* 28 * Control and status bits. 29 */ 30 #define EN_IERROR 0x8000 /* CRC error, buf ovflo or overrun */ 31 #define EN_OERROR 0x8000 /* collision or output underrun */ 32 #define EN_OPDONE 0x0080 /* previous operation completed */ 33 #define EN_IEN 0x0040 /* enable interrupt when DONE */ 34 #define EN_PROMISCUOUS 0x0002 /* promiscuous, input any packet */ 35 #define EN_GO 0x0001 /* start op bit */ 36 37 #define EN_BITS "\10\20ERR\10OPDONE\7IEN\2PROM\1GO" 38 39 #define spl_enet() spl5() 40