1 /* vax_defs.h: VAX architecture definitions file 2 3 Copyright (c) 1998-2011, Robert M Supnik 4 5 Permission is hereby granted, free of charge, to any person obtaining a 6 copy of this software and associated documentation files (the "Software"), 7 to deal in the Software without restriction, including without limitation 8 the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 and/or sell copies of the Software, and to permit persons to whom the 10 Software is furnished to do so, subject to the following conditions: 11 12 The above copyright notice and this permission notice shall be included in 13 all copies or substantial portions of the Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 22 Except as contained in this notice, the name of Robert M Supnik shall not be 23 used in advertising or otherwise to promote the sale, use or other dealings 24 in this Software without prior written authorization from Robert M Supnik. 25 26 The author gratefully acknowledges the help of Stephen Shirron, Antonio 27 Carlini, and Kevin Peterson in providing specifications for the Qbus VAX's 28 29 05-Nov-11 RMS Added PSL_IPL17 definition 30 09-May-06 RMS Added system PTE ACV error code 31 03-May-06 RMS Added EDITPC get/put cc's macros 32 03-Nov-05 RMS Added 780 stop codes 33 22-Jul-05 RMS Fixed warning from Solaris C (from Doug Gwyn) 34 02-Sep-04 RMS Added octa specifier definitions 35 30-Aug-04 RMS Added octa, h_floating instruction definitions 36 24-Aug-04 RMS Added compatibility mode definitions 37 18-Apr-04 RMS Added octa, fp, string definitions 38 19-May-03 RMS Revised for new conditional compilation scheme 39 14-Jul-02 RMS Added infinite loop message 40 30-Apr-02 RMS Added CLR_TRAPS macro 41 */ 42 43 #ifndef _VAX_DEFS_H 44 #define _VAX_DEFS_H 0 45 46 #ifndef VM_VAX 47 #define VM_VAX 0 48 #endif 49 50 #include "sim_defs.h" 51 #include <setjmp.h> 52 53 /* Stops and aborts */ 54 55 #define STOP_HALT 1 /* halt */ 56 #define STOP_IBKPT 2 /* breakpoint */ 57 #define STOP_CHMFI 3 /* chg mode IS */ 58 #define STOP_ILLVEC 4 /* illegal vector */ 59 #define STOP_INIE 5 /* exc in intexc */ 60 #define STOP_PPTE 6 /* proc pte in Px */ 61 #define STOP_UIPL 7 /* undefined IPL */ 62 #define STOP_RQ 8 /* fatal RQ err */ 63 #define STOP_LOOP 9 /* infinite loop */ 64 #define STOP_SANITY 10 /* sanity timer exp */ 65 #define STOP_SWDN 11 /* software done (780) */ 66 #define STOP_BOOT 12 /* reboot (780) */ 67 #define STOP_UNKNOWN 13 /* unknown reason */ 68 #define STOP_UNKABO 14 /* unknown abort */ 69 #define ABORT_INTR -1 /* interrupt */ 70 #define ABORT_MCHK (-SCB_MCHK) /* machine check */ 71 #define ABORT_RESIN (-SCB_RESIN) /* rsvd instruction */ 72 #define ABORT_RESAD (-SCB_RESAD) /* rsvd addr mode */ 73 #define ABORT_RESOP (-SCB_RESOP) /* rsvd operand */ 74 #define ABORT_CMODE (-SCB_CMODE) /* comp mode fault */ 75 #define ABORT_ARITH (-SCB_ARITH) /* arithmetic trap */ 76 #define ABORT_ACV (-SCB_ACV) /* access violation */ 77 #define ABORT_TNV (-SCB_TNV) /* transl not vaid */ 78 #define ABORT(x) longjmp (save_env, (x)) /* abort */ 79 #define RSVD_INST_FAULT ABORT (ABORT_RESIN) 80 #define RSVD_ADDR_FAULT ABORT (ABORT_RESAD) 81 #define RSVD_OPND_FAULT ABORT (ABORT_RESOP) 82 #define FLT_OVFL_FAULT p1 = FLT_OVRFLO, ABORT (ABORT_ARITH) 83 #define FLT_DZRO_FAULT p1 = FLT_DIVZRO, ABORT (ABORT_ARITH) 84 #define FLT_UNFL_FAULT p1 = FLT_UNDFLO, ABORT (ABORT_ARITH) 85 #define CMODE_FAULT(cd) p1 = (cd), ABORT (ABORT_CMODE) 86 #define MACH_CHECK(cd) p1 = (cd), ABORT (ABORT_MCHK) 87 88 /* Recovery queue */ 89 90 #define RQ_RN 0xF /* register */ 91 #define RQ_V_LNT 4 /* length */ 92 #define RQ_M_LNT 0x7 /* 0,1,2,3,4 */ 93 #define RQ_DIR 0x800 /* 0 = -, 1 = + */ 94 #define RQ_REC(d,r) (((d) << RQ_V_LNT) | (r)) 95 #define RQ_GETRN(x) ((x) & RQ_RN) 96 #define RQ_GETLNT(x) (((x) >> RQ_V_LNT) & RQ_M_LNT) 97 98 /* Address space */ 99 100 #define VAMASK 0xFFFFFFFF /* virt addr mask */ 101 #define PAWIDTH 30 /* phys addr width */ 102 #define PASIZE (1 << PAWIDTH) /* phys addr size */ 103 #define PAMASK (PASIZE - 1) /* phys addr mask */ 104 #define IOPAGE (1 << (PAWIDTH - 1)) /* start of I/O page */ 105 106 /* Architectural constants */ 107 108 #define BMASK 0x000000FF /* byte */ 109 #define BSIGN 0x00000080 110 #define WMASK 0x0000FFFF /* word */ 111 #define WSIGN 0x00008000 112 #define LMASK 0xFFFFFFFF /* longword */ 113 #define LSIGN 0x80000000 114 #define FPSIGN 0x00008000 /* floating point */ 115 #define L_BYTE 1 /* bytes per */ 116 #define L_WORD 2 /* data type */ 117 #define L_LONG 4 118 #define L_QUAD 8 119 #define L_OCTA 16 120 #define NUM_INST 512 /* one byte+two byte */ 121 #define MAX_SPEC 6 /* max spec/instr */ 122 123 /* Floating point formats */ 124 125 #define FD_V_EXP 7 /* f/d exponent */ 126 #define FD_M_EXP 0xFF 127 #define FD_BIAS 0x80 /* f/d bias */ 128 #define FD_EXP (FD_M_EXP << FD_V_EXP) 129 #define FD_HB (1 << FD_V_EXP) /* f/d hidden bit */ 130 #define FD_GUARD (15 - FD_V_EXP) /* # guard bits */ 131 #define FD_GETEXP(x) (((x) >> FD_V_EXP) & FD_M_EXP) 132 133 #define G_V_EXP 4 /* g exponent */ 134 #define G_M_EXP 0x7FF 135 #define G_BIAS 0x400 /* g bias */ 136 #define G_EXP (G_M_EXP << G_V_EXP) 137 #define G_HB (1 << G_V_EXP) /* g hidden bit */ 138 #define G_GUARD (15 - G_V_EXP) /* # guard bits */ 139 #define G_GETEXP(x) (((x) >> G_V_EXP) & G_M_EXP) 140 141 #define H_V_EXP 0 /* h exponent */ 142 #define H_M_EXP 0x7FFF 143 #define H_BIAS 0x4000 /* h bias */ 144 #define H_EXP (H_M_EXP << H_V_EXP) 145 #define H_HB (1 << H_V_EXP) /* h hidden bit */ 146 #define H_GUARD (15 - H_V_EXP) /* # guard bits */ 147 #define H_GETEXP(x) (((x) >> H_V_EXP) & H_M_EXP) 148 149 /* Memory management modes */ 150 151 #define KERN 0 152 #define EXEC 1 153 #define SUPV 2 154 #define USER 3 155 156 /* Register and stack aliases */ 157 158 #define nAP 12 159 #define nFP 13 160 #define nSP 14 161 #define nPC 15 162 #define AP R[nAP] 163 #define FP R[nFP] 164 #define SP R[nSP] 165 #define PC R[nPC] 166 #define RGMASK 0xF 167 #define KSP STK[KERN] 168 #define ESP STK[EXEC] 169 #define SSP STK[SUPV] 170 #define USP STK[USER] 171 #define IS STK[4] 172 173 /* PSL, PSW, and condition codes */ 174 175 #define PSL_V_CM 31 /* compatibility mode */ 176 #define PSL_CM (1u << PSL_V_CM) 177 #define PSL_V_TP 30 /* trace pending */ 178 #define PSL_TP (1 << PSL_V_TP) 179 #define PSL_V_FPD 27 /* first part done */ 180 #define PSL_FPD (1 << PSL_V_FPD) 181 #define PSL_V_IS 26 /* interrupt stack */ 182 #define PSL_IS (1 << PSL_V_IS) 183 #define PSL_V_CUR 24 /* current mode */ 184 #define PSL_V_PRV 22 /* previous mode */ 185 #define PSL_M_MODE 0x3 /* mode mask */ 186 #define PSL_CUR (PSL_M_MODE << PSL_V_CUR) 187 #define PSL_PRV (PSL_M_MODE << PSL_V_PRV) 188 #define PSL_V_IPL 16 /* int priority lvl */ 189 #define PSL_M_IPL 0x1F 190 #define PSL_IPL (PSL_M_IPL << PSL_V_IPL) 191 #define PSL_IPL1 (0x01 << PSL_V_IPL) 192 #define PSL_IPL17 (0x17 << PSL_V_IPL) 193 #define PSL_IPL1F (0x1F << PSL_V_IPL) 194 #define PSL_MBZ (0x30200000 | PSW_MBZ) /* must be zero */ 195 #define PSW_MBZ 0xFF00 /* must be zero */ 196 #define PSW_DV 0x80 /* dec ovflo enable */ 197 #define PSW_FU 0x40 /* flt undflo enable */ 198 #define PSW_IV 0x20 /* int ovflo enable */ 199 #define PSW_T 0x10 /* trace enable */ 200 #define CC_N 0x08 /* negative */ 201 #define CC_Z 0x04 /* zero */ 202 #define CC_V 0x02 /* overflow */ 203 #define CC_C 0x01 /* carry */ 204 #define CC_MASK (CC_N | CC_Z | CC_V | CC_C) 205 #define PSL_GETCUR(x) (((x) >> PSL_V_CUR) & PSL_M_MODE) 206 #define PSL_GETPRV(x) (((x) >> PSL_V_PRV) & PSL_M_MODE) 207 #define PSL_GETIPL(x) (((x) >> PSL_V_IPL) & PSL_M_IPL) 208 209 /* Software interrupt summary register */ 210 211 #define SISR_MASK 0xFFFE 212 #define SISR_2 (1 << 2) 213 214 /* AST register */ 215 216 #define AST_MASK 7 217 #define AST_MAX 4 218 219 /* Virtual address */ 220 221 #define VA_N_OFF 9 /* offset size */ 222 #define VA_PAGSIZE (1u << VA_N_OFF) /* page size */ 223 #define VA_M_OFF ((1u << VA_N_OFF) - 1) /* offset mask */ 224 #define VA_V_VPN VA_N_OFF /* vpn start */ 225 #define VA_N_VPN (31 - VA_N_OFF) /* vpn size */ 226 #define VA_M_VPN ((1u << VA_N_VPN) - 1) /* vpn mask */ 227 #define VA_S0 (1u << 31) /* S0 space */ 228 #define VA_P1 (1u << 30) /* P1 space */ 229 #define VA_N_TBI 12 /* TB index size */ 230 #define VA_TBSIZE (1u << VA_N_TBI) /* TB size */ 231 #define VA_M_TBI ((1u << VA_N_TBI) - 1) /* TB index mask */ 232 #define VA_GETOFF(x) ((x) & VA_M_OFF) 233 #define VA_GETVPN(x) (((x) >> VA_V_VPN) & VA_M_VPN) 234 #define VA_GETTBI(x) ((x) & VA_M_TBI) 235 236 /* PTE */ 237 238 #define PTE_V_V 31 /* valid */ 239 #define PTE_V (1u << PTE_V_V) 240 #define PTE_V_ACC 27 /* access */ 241 #define PTE_M_ACC 0xF 242 #define PTE_ACC (PTE_M_ACC << PTE_V_ACC) 243 #define PTE_V_M 26 /* modified */ 244 #define PTE_M (1u << PTE_V_M) 245 #define PTE_GETACC(x) (((x) >> PTE_V_ACC) & PTE_M_ACC) 246 247 /* TLB entry */ 248 249 #define TLB_V_RACC 0 /* rd acc field */ 250 #define TLB_V_WACC 4 /* wr acc field */ 251 #define TLB_M_ACC 0xF 252 #define TLB_RACC (TLB_M_ACC << TLB_V_RACC) 253 #define TLB_WACC (TLB_M_ACC << TLB_V_WACC) 254 #define TLB_V_M 8 /* m bit */ 255 #define TLB_M (1u << TLB_V_M) 256 #define TLB_N_PFN (PAWIDTH - VA_N_OFF) /* ppfn size */ 257 #define TLB_M_PFN ((1u << TLB_N_PFN) - 1) /* ppfn mask */ 258 #define TLB_PFN (TLB_M_PFN << VA_V_VPN) 259 260 /* Traps and interrupt requests */ 261 262 #define TIR_V_IRQL 0 /* int request lvl */ 263 #define TIR_V_TRAP 5 /* trap requests */ 264 #define TIR_M_TRAP 07 265 #define TIR_TRAP (TIR_M_TRAP << TIR_V_TRAP) 266 #define TRAP_INTOV (1 << TIR_V_TRAP) /* integer overflow */ 267 #define TRAP_DIVZRO (2 << TIR_V_TRAP) /* divide by zero */ 268 #define TRAP_FLTOVF (3 << TIR_V_TRAP) /* flt overflow */ 269 #define TRAP_FLTDIV (4 << TIR_V_TRAP) /* flt/dec div by zero */ 270 #define TRAP_FLTUND (5 << TIR_V_TRAP) /* flt underflow */ 271 #define TRAP_DECOVF (6 << TIR_V_TRAP) /* decimal overflow */ 272 #define TRAP_SUBSCR (7 << TIR_V_TRAP) /* subscript range */ 273 #define SET_TRAP(x) trpirq = (trpirq & PSL_M_IPL) | (x) 274 #define CLR_TRAPS trpirq = trpirq & ~TIR_TRAP 275 #define SET_IRQL trpirq = (trpirq & TIR_TRAP) | eval_int () 276 #define GET_TRAP(x) (((x) >> TIR_V_TRAP) & TIR_M_TRAP) 277 #define GET_IRQL(x) (((x) >> TIR_V_IRQL) & PSL_M_IPL) 278 279 /* Floating point fault parameters */ 280 281 #define FLT_OVRFLO 0x8 /* flt overflow */ 282 #define FLT_DIVZRO 0x9 /* flt div by zero */ 283 #define FLT_UNDFLO 0xA /* flt underflow */ 284 285 /* Compatability mode fault parameters */ 286 287 #define CMODE_RSVI 0x0 /* reserved instr */ 288 #define CMODE_BPT 0x1 /* BPT */ 289 #define CMODE_IOT 0x2 /* IOT */ 290 #define CMODE_EMT 0x3 /* EMT */ 291 #define CMODE_TRAP 0x4 /* TRAP */ 292 #define CMODE_ILLI 0x5 /* illegal instr */ 293 #define CMODE_ODD 0x6 /* odd address */ 294 295 /* EDITPC suboperators */ 296 297 #define EO_END 0x00 /* end */ 298 #define EO_END_FLOAT 0x01 /* end float */ 299 #define EO_CLR_SIGNIF 0x02 /* clear signif */ 300 #define EO_SET_SIGNIF 0x03 /* set signif */ 301 #define EO_STORE_SIGN 0x04 /* store sign */ 302 #define EO_LOAD_FILL 0x40 /* load fill */ 303 #define EO_LOAD_SIGN 0x41 /* load sign */ 304 #define EO_LOAD_PLUS 0x42 /* load sign if + */ 305 #define EO_LOAD_MINUS 0x43 /* load sign if - */ 306 #define EO_INSERT 0x44 /* insert */ 307 #define EO_BLANK_ZERO 0x45 /* blank zero */ 308 #define EO_REPL_SIGN 0x46 /* replace sign */ 309 #define EO_ADJUST_LNT 0x47 /* adjust length */ 310 #define EO_FILL 0x80 /* fill */ 311 #define EO_MOVE 0x90 /* move */ 312 #define EO_FLOAT 0xA0 /* float */ 313 #define EO_RPT_MASK 0x0F /* rpt mask */ 314 #define EO_RPT_FLAG 0x80 /* rpt flag */ 315 316 /* EDITPC R2 packup parameters */ 317 318 #define ED_V_CC 16 /* condition codes */ 319 #define ED_M_CC 0xFF 320 #define ED_CC (ED_M_CC << ED_V_CC) 321 #define ED_V_SIGN 8 /* sign */ 322 #define ED_M_SIGN 0xFF 323 #define ED_SIGN (ED_M_SIGN << ED_V_SIGN) 324 #define ED_V_FILL 0 /* fill */ 325 #define ED_M_FILL 0xFF 326 #define ED_FILL (ED_M_FILL << ED_V_FILL) 327 #define ED_GETCC(x) (((x) >> ED_V_CC) & CC_MASK) 328 #define ED_GETSIGN(x) (((x) >> ED_V_SIGN) & ED_M_SIGN) 329 #define ED_GETFILL(x) (((x) >> ED_V_FILL) & ED_M_FILL) 330 #define ED_PUTCC(r,x) (((r) & ~ED_CC) | (((x) << ED_V_CC) & ED_CC)) 331 #define ED_PUTSIGN(r,x) (((r) & ~ED_SIGN) | (((x) << ED_V_SIGN) & ED_SIGN)) 332 #define ED_PUTFILL(r,x) (((r) & ~ED_FILL) | (((x) << ED_V_FILL) & ED_FILL)) 333 334 /* SCB offsets */ 335 336 #define SCB_MCHK 0x04 /* machine chk */ 337 #define SCB_KSNV 0x08 /* ker stk invalid */ 338 #define SCB_PWRFL 0x0C /* power fail */ 339 #define SCB_RESIN 0x10 /* rsvd/priv instr */ 340 #define SCB_XFC 0x14 /* XFC instr */ 341 #define SCB_RESOP 0x18 /* rsvd operand */ 342 #define SCB_RESAD 0x1C /* rsvd addr mode */ 343 #define SCB_ACV 0x20 /* ACV */ 344 #define SCB_TNV 0x24 /* TNV */ 345 #define SCB_TP 0x28 /* trace pending */ 346 #define SCB_BPT 0x2C /* BPT instr */ 347 #define SCB_CMODE 0x30 /* comp mode fault */ 348 #define SCB_ARITH 0x34 /* arith fault */ 349 #define SCB_CHMK 0x40 /* CHMK */ 350 #define SCB_CHME 0x44 /* CHME */ 351 #define SCB_CHMS 0x48 /* CHMS */ 352 #define SCB_CHMU 0x4C /* CHMU */ 353 #define SCB_CRDERR 0x54 /* CRD err intr */ 354 #define SCB_MEMERR 0x60 /* mem err intr */ 355 #define SCB_IPLSOFT 0x80 /* software intr */ 356 #define SCB_INTTIM 0xC0 /* timer intr */ 357 #define SCB_EMULATE 0xC8 /* emulation */ 358 #define SCB_EMULFPD 0xCC /* emulation, FPD */ 359 #define SCB_CSI 0xF0 /* constor input */ 360 #define SCB_CSO 0xF4 /* constor output */ 361 #define SCB_TTI 0xF8 /* console input */ 362 #define SCB_TTO 0xFC /* console output */ 363 #define SCB_INTR 0x100 /* hardware intr */ 364 365 #define IPL_HLTPIN 0x1F /* halt pin IPL */ 366 #define IPL_MEMERR 0x1D /* mem err IPL */ 367 #define IPL_CRDERR 0x1A /* CRD err IPL */ 368 369 /* Interrupt and exception types */ 370 371 #define IE_SVE -1 /* severe exception */ 372 #define IE_EXC 0 /* normal exception */ 373 #define IE_INT 1 /* interrupt */ 374 375 /* Decode ROM: opcode entry */ 376 377 #define DR_F 0x80 /* FPD ok flag */ 378 #define DR_NSPMASK 0x07 /* #specifiers */ 379 #define DR_V_USPMASK 4 380 #define DR_M_USPMASK 0x70 /* #spec, sym_ */ 381 #define DR_GETNSP(x) ((x) & DR_NSPMASK) 382 #define DR_GETUSP(x) (((x) >> DR_V_USPMASK) & DR_M_USPMASK) 383 384 /* Decode ROM: specifier entry */ 385 386 #define DR_ACMASK 0x300 /* type */ 387 #define DR_SPFLAG 0x008 /* special decode */ 388 #define DR_LNMASK 0x007 /* length mask */ 389 #define DR_LNT(x) (1 << (x & DR_LNMASK)) /* disp to lnt */ 390 391 /* Decode ROM: length */ 392 393 #define DR_BYTE 0x000 /* byte */ 394 #define DR_WORD 0x001 /* word */ 395 #define DR_LONG 0x002 /* long */ 396 #define DR_QUAD 0x003 /* quad */ 397 #define DR_OCTA 0x004 /* octa */ 398 399 /* Decode ROM: operand type */ 400 401 #define SH0 0x000 /* short literal */ 402 #define SH1 0x010 403 #define SH2 0x020 404 #define SH3 0x030 405 #define IDX 0x040 /* indexed */ 406 #define GRN 0x050 /* register */ 407 #define RGD 0x060 /* register def */ 408 #define ADC 0x070 /* autodecrement */ 409 #define AIN 0x080 /* autoincrement */ 410 #define AID 0x090 /* autoinc def */ 411 #define BDP 0x0A0 /* byte disp */ 412 #define BDD 0x0B0 /* byte disp def */ 413 #define WDP 0x0C0 /* word disp */ 414 #define WDD 0x0D0 /* word disp def */ 415 #define LDP 0x0E0 /* long disp */ 416 #define LDD 0x0F0 /* long disp def */ 417 418 /* Decode ROM: access type */ 419 420 #define DR_R 0x000 /* read */ 421 #define DR_M 0x100 /* modify */ 422 #define DR_A 0x200 /* address */ 423 #define DR_W 0x300 /* write */ 424 425 /* Decode ROM: access type and length */ 426 427 #define RB (DR_R|DR_BYTE) 428 #define RW (DR_R|DR_WORD) 429 #define RL (DR_R|DR_LONG) 430 #define RQ (DR_R|DR_QUAD) 431 #define RO (DR_R|DR_OCTA) 432 #define MB (DR_M|DR_BYTE) 433 #define MW (DR_M|DR_WORD) 434 #define ML (DR_M|DR_LONG) 435 #define MQ (DR_M|DR_QUAD) 436 #define MO (DR_M|DR_OCTA) 437 #define AB (DR_A|DR_BYTE) 438 #define AW (DR_A|DR_WORD) 439 #define AL (DR_A|DR_LONG) 440 #define AQ (DR_A|DR_QUAD) 441 #define AO (DR_A|DR_OCTA) 442 #define WB (DR_W|DR_BYTE) 443 #define WW (DR_W|DR_WORD) 444 #define WL (DR_W|DR_LONG) 445 #define WQ (DR_W|DR_QUAD) 446 #define WO (DR_W|DR_OCTA) 447 448 /* Special dispatches. 449 450 vb = variable bit field, treated as wb except for register 451 rf = f_floating, treated as rl except for short literal 452 rd = d_floating, treated as rq except for short literal 453 rg = g_floating, treated as rq except for short literal 454 rh = h_floating, treated as ro except for short literal 455 bb = branch byte displacement 456 bw = branch word displacement 457 458 Length field must be correct 459 */ 460 461 #define VB (DR_SPFLAG|WB) /* .vb */ 462 #define RF (DR_SPFLAG|RL) /* .rf */ 463 #define RD (DR_SPFLAG|RQ) /* .rd */ 464 #define RG (DR_SPFLAG|MQ) /* .rg */ 465 #define RH (DR_SPFLAG|RO) /* .rh */ 466 #define BB (DR_SPFLAG|WB|6) /* byte branch */ 467 #define BW (DR_SPFLAG|WB|7) /* word branch */ 468 469 /* Probe results and memory management fault codes */ 470 471 #define PR_ACV 0 /* ACV */ 472 #define PR_LNV 1 /* length viol */ 473 #define PR_PACV 2 /* pte ACV (780) */ 474 #define PR_PLNV 3 /* pte len viol */ 475 #define PR_TNV 4 /* TNV */ 476 /* #define PR_TB 5 /* impossible */ 477 #define PR_PTNV 6 /* pte TNV */ 478 #define PR_OK 7 /* ok */ 479 #define MM_PARAM(w,p) (((w)? 4: 0) | ((p) & 3)) /* fault param */ 480 481 /* Memory management errors */ 482 483 #define MM_WRITE 4 /* write */ 484 #define MM_EMASK 3 /* against probe */ 485 486 /* Privileged registers */ 487 488 #define MT_KSP 0 489 #define MT_ESP 1 490 #define MT_SSP 2 491 #define MT_USP 3 492 #define MT_IS 4 493 #define MT_P0BR 8 494 #define MT_P0LR 9 495 #define MT_P1BR 10 496 #define MT_P1LR 11 497 #define MT_SBR 12 498 #define MT_SLR 13 499 #define MT_PCBB 16 500 #define MT_SCBB 17 501 #define MT_IPL 18 502 #define MT_ASTLVL 19 503 #define MT_SIRR 20 504 #define MT_SISR 21 505 #define MT_ICCS 24 506 #define MT_NICR 25 507 #define MT_ICR 26 508 #define MT_TODR 27 509 #define MT_CSRS 28 510 #define MT_CSRD 29 511 #define MT_CSTS 30 512 #define MT_CSTD 31 513 #define MT_RXCS 32 514 #define MT_RXDB 33 515 #define MT_TXCS 34 516 #define MT_TXDB 35 517 #define MT_MAPEN 56 518 #define MT_TBIA 57 519 #define MT_TBIS 58 520 #define MT_PME 61 521 #define MT_SID 62 522 #define MT_TBCHK 63 523 524 #define BR_MASK 0xFFFFFFFC 525 #define LR_MASK 0x003FFFFF 526 527 /* Opcodes */ 528 529 enum opcodes { 530 HALT, NOP, REI, BPT, RET, RSB, LDPCTX, SVPCTX, 531 CVTPS, CVTSP, INDEX, CRC, PROBER, PROBEW, INSQUE, REMQUE, 532 BSBB, BRB, BNEQ, BEQL, BGTR, BLEQ, JSB, JMP, 533 BGEQ, BLSS, BGTRU, BLEQU, BVC, BVS, BGEQU, BLSSU, 534 ADDP4, ADDP6, SUBP4, SUBP6, CVTPT, MULP, CVTTP, DIVP, 535 MOVC3, CMPC3, SCANC, SPANC, MOVC5, CMPC5, MOVTC, MOVTUC, 536 BSBW, BRW, CVTWL, CVTWB, MOVP, CMPP3, CVTPL, CMPP4, 537 EDITPC, MATCHC, LOCC, SKPC, MOVZWL, ACBW, MOVAW, PUSHAW, 538 ADDF2, ADDF3, SUBF2, SUBF3, MULF2, MULF3, DIVF2, DIVF3, 539 CVTFB, CVTFW, CVTFL, CVTRFL, CVTBF, CVTWF, CVTLF, ACBF, 540 MOVF, CMPF, MNEGF, TSTF, EMODF, POLYF, CVTFD, 541 ADAWI = 0x58, INSQHI = 0x5C, INSQTI, REMQHI, REMQTI, 542 ADDD2, ADDD3, SUBD2, SUBD3, MULD2, MULD3, DIVD2, DIVD3, 543 CVTDB, CVTDW, CVTDL, CVTRDL, CVTBD, CVTWD, CVTLD, ACBD, 544 MOVD, CMPD, MNEGD, TSTD, EMODD, POLYD, CVTDF, 545 ASHL = 0x78, ASHQ, EMUL, EDIV, CLRQ, MOVQ, MOVAQ, PUSHAQ, 546 ADDB2, ADDB3, SUBB2, SUBB3, MULB2, MULB3, DIVB2, DIVB3, 547 BISB2, BISB3, BICB2, BICB3, XORB2, XORB3, MNEGB, CASEB, 548 MOVB, CMPB, MCOMB, BITB, CLRB, TSTB, INCB, DECB, 549 CVTBL, CVTBW, MOVZBL, MOVZBW, ROTL, ACBB, MOVAB, PUSHAB, 550 ADDW2, ADDW3, SUBW2, SUBW3, MULW2, MULW3, DIVW2, DIVW3, 551 BISW2, BISW3, BICW2, BICW3, XORW2, XORW3, MNEGW, CASEW, 552 MOVW, CMPW, MCOMW, BITW, CLRW, TSTW, INCW, DECW, 553 BISPSW, BICPSW, POPR, PUSHR, CHMK, CHME, CHMS, CHMU, 554 ADDL2, ADDL3, SUBL2, SUBL3, MULL2, MULL3, DIVL2, DIVL3, 555 BISL2, BISL3, BICL2, BICL3, XORL2, XORL3, MNEGL, CASEL, 556 MOVL, CMPL, MCOML, BITL, CLRL, TSTL, INCL, DECL, 557 ADWC, SBWC, MTPR, MFPR, MOVPSL, PUSHL, MOVAL, PUSHAL, 558 BBS, BBC, BBSS, BBCS, BBSC, BBCC, BBSSI, BBCCI, 559 BLBS, BLBC, FFS, FFC, CMPV, CMPZV, EXTV, EXTZV, 560 INSV, ACBL, AOBLSS, AOBLEQ, SOBGEQ, SOBGTR, CVTLB, CVTLW, 561 ASHP, CVTLP, CALLG, CALLS, XFC, CVTDH = 0x132, CVTGF = 0x133, 562 ADDG2 = 0x140, ADDG3, SUBG2, SUBG3, MULG2, MULG3, DIVG2, DIVG3, 563 CVTGB, CVTGW, CVTGL, CVTRGL, CVTBG, CVTWG, CVTLG, ACBG, 564 MOVG, CMPG, MNEGG, TSTG, EMODG, POLYG, CVTGH, 565 ADDH2 = 0x160, ADDH3, SUBH2, SUBH3, MULH2, MULH3, DIVH2, DIVH3, 566 CVTHB, CVTHW, CVTHL, CVTRHL, CVTBH, CVTWH, CVTLH, ACBH, 567 MOVH, CMPH, MNEGH, TSTH, EMODH, POLYH, CVTHG, 568 CLRO = 0x17C, MOVO, MOVAO, PUSHAO, 569 CVTFH = 0x198, CVTFG = 0x199, 570 CVTHF = 0x1F6, CVTHD = 0x1F7 }; 571 572 /* Repeated operations */ 573 574 #define SXTB(x) (((x) & BSIGN)? ((x) | ~BMASK): ((x) & BMASK)) 575 #define SXTW(x) (((x) & WSIGN)? ((x) | ~WMASK): ((x) & WMASK)) 576 #define SXTBW(x) (((x) & BSIGN)? ((x) | (WMASK - BMASK)): ((x) & BMASK)) 577 #define SXTL(x) (((x) & LSIGN)? ((x) | ~LMASK): ((x) & LMASK)) 578 #define INTOV if (PSL & PSW_IV) SET_TRAP (TRAP_INTOV) 579 #define V_INTOV cc = cc | CC_V; INTOV 580 #define NEG(x) ((~(x) + 1) & LMASK) 581 582 /* Istream access */ 583 584 #define PCQ_SIZE 64 /* must be 2**n */ 585 #define PCQ_MASK (PCQ_SIZE - 1) 586 #define PCQ_ENTRY pcq[pcq_p = (pcq_p - 1) & PCQ_MASK] = fault_PC 587 #define GET_ISTR(d,l) d = get_istr (l, acc) 588 #define BRANCHB(d) PCQ_ENTRY, PC = PC + SXTB (d), FLUSH_ISTR 589 #define BRANCHW(d) PCQ_ENTRY, PC = PC + SXTW (d), FLUSH_ISTR 590 #define JUMP(d) PCQ_ENTRY, PC = (d), FLUSH_ISTR 591 #define CMODE_JUMP(d) PCQ_ENTRY, PC = (d) 592 #define SETPC(d) PC = (d), FLUSH_ISTR 593 #define FLUSH_ISTR ibcnt = 0, ppc = -1 594 595 /* Character string instructions */ 596 597 #define STR_V_DPC 24 /* delta PC */ 598 #define STR_M_DPC 0xFF 599 #define STR_V_CHR 16 /* char argument */ 600 #define STR_M_CHR 0xFF 601 #define STR_LNMASK 0xFFFF /* string length */ 602 #define STR_GETDPC(x) (((x) >> STR_V_DPC) & STR_M_DPC) 603 #define STR_GETCHR(x) (((x) >> STR_V_CHR) & STR_M_CHR) 604 #define STR_PACK(m,x) ((((PC - fault_PC) & STR_M_DPC) << STR_V_DPC) | \ 605 (((m) & STR_M_CHR) << STR_V_CHR) | ((x) & STR_LNMASK)) 606 607 /* Read and write */ 608 609 #define RA (acc) 610 #define WA ((acc) << TLB_V_WACC) 611 #define ACC_MASK(x) (1 << (x)) 612 #define TLB_ACCR(x) (ACC_MASK (x) << TLB_V_RACC) 613 #define TLB_ACCW(x) (ACC_MASK (x) << TLB_V_WACC) 614 #define REF_V 0 615 #define REF_P 1 616 617 /* Condition code macros */ 618 619 #define CC_ZZ1P cc = CC_Z | (cc & CC_C) 620 621 #define CC_IIZZ_B(r) \ 622 if ((r) & BSIGN) cc = CC_N; \ 623 else if ((r) == 0) cc = CC_Z; \ 624 else cc = 0 625 #define CC_IIZZ_W(r) \ 626 if ((r) & WSIGN) cc = CC_N; \ 627 else if ((r) == 0) cc = CC_Z; \ 628 else cc = 0 629 #define CC_IIZZ_L(r) \ 630 if ((r) & LSIGN) cc = CC_N; \ 631 else if ((r) == 0) cc = CC_Z; \ 632 else cc = 0 633 #define CC_IIZZ_Q(rl,rh) \ 634 if ((rh) & LSIGN) cc = CC_N; \ 635 else if (((rl) | (rh)) == 0) cc = CC_Z; \ 636 else cc = 0 637 #define CC_IIZZ_FP CC_IIZZ_W 638 639 #define CC_IIZP_B(r) \ 640 if ((r) & BSIGN) cc = CC_N | (cc & CC_C); \ 641 else if ((r) == 0) cc = CC_Z | (cc & CC_C); \ 642 else cc = cc & CC_C 643 #define CC_IIZP_W(r) \ 644 if ((r) & WSIGN) cc = CC_N | (cc & CC_C); \ 645 else if ((r) == 0) cc = CC_Z | (cc & CC_C); \ 646 else cc = cc & CC_C 647 #define CC_IIZP_L(r) \ 648 if ((r) & LSIGN) cc = CC_N | (cc & CC_C); \ 649 else if ((r) == 0) cc = CC_Z | (cc & CC_C); \ 650 else cc = cc & CC_C 651 #define CC_IIZP_Q(rl,rh) \ 652 if ((rh) & LSIGN) cc = CC_N | (cc & CC_C); \ 653 else if (((rl) | (rh)) == 0) cc = CC_Z | (cc & CC_C); \ 654 else cc = cc & CC_C 655 #define CC_IIZP_O(rl,rm2,rm1,rh) \ 656 if ((rh) & LSIGN) cc = CC_N | (cc & CC_C); \ 657 else if (((rl) | (rm2) | (rm1) | (rh)) == 0) cc = CC_Z | (cc & CC_C); \ 658 else cc = cc & CC_C 659 #define CC_IIZP_FP CC_IIZP_W 660 661 #define V_ADD_B(r,s1,s2) \ 662 if (((~(s1) ^ (s2)) & ((s1) ^ (r))) & BSIGN) { V_INTOV; } 663 #define V_ADD_W(r,s1,s2) \ 664 if (((~(s1) ^ (s2)) & ((s1) ^ (r))) & WSIGN) { V_INTOV; } 665 #define V_ADD_L(r,s1,s2) \ 666 if (((~(s1) ^ (s2)) & ((s1) ^ (r))) & LSIGN) { V_INTOV; } 667 #define C_ADD(r,s1,s2) \ 668 if (((uint32) r) < ((uint32) s2)) cc = cc | CC_C 669 670 #define CC_ADD_B(r,s1,s2) \ 671 CC_IIZZ_B (r); \ 672 V_ADD_B (r, s1, s2); \ 673 C_ADD (r, s1, s2) 674 #define CC_ADD_W(r,s1,s2) \ 675 CC_IIZZ_W (r); \ 676 V_ADD_W (r, s1, s2); \ 677 C_ADD (r, s1, s2) 678 #define CC_ADD_L(r,s1,s2) \ 679 CC_IIZZ_L (r); \ 680 V_ADD_L (r, s1, s2); \ 681 C_ADD (r, s1, s2) 682 683 #define V_SUB_B(r,s1,s2) \ 684 if ((((s1) ^ (s2)) & (~(s1) ^ (r))) & BSIGN) { V_INTOV; } 685 #define V_SUB_W(r,s1,s2) \ 686 if ((((s1) ^ (s2)) & (~(s1) ^ (r))) & WSIGN) { V_INTOV; } 687 #define V_SUB_L(r,s1,s2) \ 688 if ((((s1) ^ (s2)) & (~(s1) ^ (r))) & LSIGN) { V_INTOV; } 689 #define C_SUB(r,s1,s2) \ 690 if (((uint32) s2) < ((uint32) s1)) cc = cc | CC_C 691 692 #define CC_SUB_B(r,s1,s2) \ 693 CC_IIZZ_B (r); \ 694 V_SUB_B (r, s1, s2); \ 695 C_SUB (r, s1, s2) 696 #define CC_SUB_W(r,s1,s2) \ 697 CC_IIZZ_W (r); \ 698 V_SUB_W (r, s1, s2); \ 699 C_SUB (r, s1, s2) 700 #define CC_SUB_L(r,s1,s2) \ 701 CC_IIZZ_L (r); \ 702 V_SUB_L (r, s1, s2); \ 703 C_SUB (r, s1, s2) 704 705 #define CC_CMP_B(s1,s2) \ 706 if (SXTB (s1) < SXTB (s2)) cc = CC_N; \ 707 else if ((s1) == (s2)) cc = CC_Z; \ 708 else cc = 0; \ 709 if (((uint32) s1) < ((uint32) s2)) cc = cc | CC_C 710 #define CC_CMP_W(s1,s2) \ 711 if (SXTW (s1) < SXTW (s2)) cc = CC_N; \ 712 else if ((s1) == (s2)) cc = CC_Z; \ 713 else cc = 0; \ 714 if (((uint32) s1) < ((uint32) s2)) cc = cc | CC_C 715 #define CC_CMP_L(s1,s2) \ 716 if ((s1) < (s2)) cc = CC_N; \ 717 else if ((s1) == (s2)) cc = CC_Z; \ 718 else cc = 0; \ 719 if (((uint32) s1) < ((uint32) s2)) cc = cc | CC_C 720 721 /* Model dependent definitions */ 722 723 #if defined (VAX_780) 724 #include "vax780_defs.h" 725 #else 726 #include "vaxmod_defs.h" 727 #endif 728 729 #endif /* _VAX_DEFS_H */ 730