1 /* $NetBSD: imxepitreg.h,v 1.2 2012/04/17 09:12:08 bsh Exp $ */ 2 /* 3 * Copyright (c) 2009, 2010, 2012 Genetec corp. All rights reserved. 4 * Written by Hashimoto Kenichi for Genetec corp. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORP. ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORP. 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 #ifndef _ARM_IMX_IMXEPITREG_H 28 #define _ARM_IMX_IMXEPITREG_H 29 30 #define EPIT_EPITCR 0x0000 31 #define EPITCR_EN __BIT(0) 32 #define EPITCR_ENMOD __BIT(1) 33 #define EPITCR_OCIEN __BIT(2) 34 #define EPITCR_RLD __BIT(3) 35 #define EPITCR_PRESCALER __BITS(4,15) 36 #define EPITCR_SWR __BIT(16) 37 #define EPITCR_IOVW __BIT(17) 38 #define EPITCR_DBGEN __BIT(18) 39 #define EPITCR_WAITEN __BIT(19) 40 #define EPITCR_DOZEN __BIT(20) /* not in iMX51 */ 41 #define EPITCR_STOPEN __BIT(21) 42 #define EPITCR_OM __BITS(22,23) 43 #define EPITCR_CLKSRC_SHIFT 24 44 #define EPITCR_CLKSRC_MASK __BITS(25, EPITCR_CLKSRC_SHIFT) 45 #define EPITCR_CLKSRC_IPG (1 << EPITCR_CLKSRC_SHIFT) 46 #define EPITCR_CLKSRC_IPGHIGH (2 << EPITCR_CLKSRC_SHIFT) 47 #define EPITCR_CLKSRC_IPG32K (3 << EPITCR_CLKSRC_SHIFT) 48 #define EPITCR_CLKSRC_HIGH (2 << EPITCR_CLKSRC_SHIFT) 49 50 #define EPIT_EPITSR 0x0004 51 #define EPIT_EPITLR 0x0008 52 #define EPIT_EPITCMPR 0x000c 53 #define EPIT_EPITCNT 0x0010 54 55 #endif /* _ARM_IMX_IMXEPITREG_H */ 56