xref: /freebsd/sys/dev/sfxge/common/efx_regs_ef10.h (revision 95ee2897)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2007-2016 Solarflare Communications Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions are met:
9  *
10  * 1. Redistributions of source code must retain the above copyright notice,
11  *    this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright notice,
13  *    this list of conditions and the following disclaimer in the documentation
14  *    and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
18  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
20  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
21  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
22  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
23  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
25  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  *
28  * The views and conclusions contained in the software and documentation are
29  * those of the authors and should not be interpreted as representing official
30  * policies, either expressed or implied, of the FreeBSD Project.
31  */
32 
33 #ifndef	_SYS_EFX_EF10_REGS_H
34 #define	_SYS_EFX_EF10_REGS_H
35 
36 #ifdef	__cplusplus
37 extern "C" {
38 #endif
39 
40 /**************************************************************************
41  * NOTE: the line below marks the start of the autogenerated section
42  * EF10 registers and descriptors
43  *
44  **************************************************************************
45  */
46 
47 /*
48  * BIU_HW_REV_ID_REG(32bit):
49  *
50  */
51 
52 #define	ER_DZ_BIU_HW_REV_ID_REG_OFST 0x00000000
53 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
54 #define	ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face
55 
56 #define	ERF_DZ_HW_REV_ID_LBN 0
57 #define	ERF_DZ_HW_REV_ID_WIDTH 32
58 
59 /*
60  * BIU_MC_SFT_STATUS_REG(32bit):
61  *
62  */
63 
64 #define	ER_DZ_BIU_MC_SFT_STATUS_REG_OFST 0x00000010
65 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
66 #define	ER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4
67 #define	ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8
68 #define	ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face
69 
70 #define	ERF_DZ_MC_SFT_STATUS_LBN 0
71 #define	ERF_DZ_MC_SFT_STATUS_WIDTH 32
72 
73 /*
74  * BIU_INT_ISR_REG(32bit):
75  *
76  */
77 
78 #define	ER_DZ_BIU_INT_ISR_REG_OFST 0x00000090
79 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
80 #define	ER_DZ_BIU_INT_ISR_REG_RESET 0x0
81 
82 #define	ERF_DZ_ISR_REG_LBN 0
83 #define	ERF_DZ_ISR_REG_WIDTH 32
84 
85 /*
86  * MC_DB_LWRD_REG(32bit):
87  *
88  */
89 
90 #define	ER_DZ_MC_DB_LWRD_REG_OFST 0x00000200
91 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
92 #define	ER_DZ_MC_DB_LWRD_REG_RESET 0x0
93 
94 #define	ERF_DZ_MC_DOORBELL_L_LBN 0
95 #define	ERF_DZ_MC_DOORBELL_L_WIDTH 32
96 
97 /*
98  * MC_DB_HWRD_REG(32bit):
99  *
100  */
101 
102 #define	ER_DZ_MC_DB_HWRD_REG_OFST 0x00000204
103 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
104 #define	ER_DZ_MC_DB_HWRD_REG_RESET 0x0
105 
106 #define	ERF_DZ_MC_DOORBELL_H_LBN 0
107 #define	ERF_DZ_MC_DOORBELL_H_WIDTH 32
108 
109 /*
110  * EVQ_RPTR_REG(32bit):
111  *
112  */
113 
114 #define	ER_DZ_EVQ_RPTR_REG_OFST 0x00000400
115 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
116 #define	ER_DZ_EVQ_RPTR_REG_STEP 8192
117 #define	ER_DZ_EVQ_RPTR_REG_ROWS 2048
118 #define	ER_DZ_EVQ_RPTR_REG_RESET 0x0
119 
120 #define	ERF_DZ_EVQ_RPTR_VLD_LBN 15
121 #define	ERF_DZ_EVQ_RPTR_VLD_WIDTH 1
122 #define	ERF_DZ_EVQ_RPTR_LBN 0
123 #define	ERF_DZ_EVQ_RPTR_WIDTH 15
124 
125 /*
126  * EVQ_RPTR_REG_64K(32bit):
127  *
128  */
129 
130 #define	ER_FZ_EVQ_RPTR_REG_64K_OFST 0x00000400
131 /* medford2a0=pf_dbell_bar */
132 #define	ER_FZ_EVQ_RPTR_REG_64K_STEP 65536
133 #define	ER_FZ_EVQ_RPTR_REG_64K_ROWS 2048
134 #define	ER_FZ_EVQ_RPTR_REG_64K_RESET 0x0
135 
136 #define	ERF_FZ_EVQ_RPTR_VLD_LBN 15
137 #define	ERF_FZ_EVQ_RPTR_VLD_WIDTH 1
138 #define	ERF_FZ_EVQ_RPTR_LBN 0
139 #define	ERF_FZ_EVQ_RPTR_WIDTH 15
140 
141 /*
142  * EVQ_RPTR_REG_16K(32bit):
143  *
144  */
145 
146 #define	ER_FZ_EVQ_RPTR_REG_16K_OFST 0x00000400
147 /* medford2a0=pf_dbell_bar */
148 #define	ER_FZ_EVQ_RPTR_REG_16K_STEP 16384
149 #define	ER_FZ_EVQ_RPTR_REG_16K_ROWS 2048
150 #define	ER_FZ_EVQ_RPTR_REG_16K_RESET 0x0
151 
152 /* defined as ERF_FZ_EVQ_RPTR_VLD_LBN 15; */
153 /* defined as ERF_FZ_EVQ_RPTR_VLD_WIDTH 1 */
154 /* defined as ERF_FZ_EVQ_RPTR_LBN 0; */
155 /* defined as ERF_FZ_EVQ_RPTR_WIDTH 15 */
156 
157 /*
158  * EVQ_TMR_REG_64K(32bit):
159  *
160  */
161 
162 #define	ER_FZ_EVQ_TMR_REG_64K_OFST 0x00000420
163 /* medford2a0=pf_dbell_bar */
164 #define	ER_FZ_EVQ_TMR_REG_64K_STEP 65536
165 #define	ER_FZ_EVQ_TMR_REG_64K_ROWS 2048
166 #define	ER_FZ_EVQ_TMR_REG_64K_RESET 0x0
167 
168 #define	ERF_FZ_TC_TMR_REL_VAL_LBN 16
169 #define	ERF_FZ_TC_TMR_REL_VAL_WIDTH 14
170 #define	ERF_FZ_TC_TIMER_MODE_LBN 14
171 #define	ERF_FZ_TC_TIMER_MODE_WIDTH 2
172 #define	ERF_FZ_TC_TIMER_VAL_LBN 0
173 #define	ERF_FZ_TC_TIMER_VAL_WIDTH 14
174 
175 /*
176  * EVQ_TMR_REG_16K(32bit):
177  *
178  */
179 
180 #define	ER_FZ_EVQ_TMR_REG_16K_OFST 0x00000420
181 /* medford2a0=pf_dbell_bar */
182 #define	ER_FZ_EVQ_TMR_REG_16K_STEP 16384
183 #define	ER_FZ_EVQ_TMR_REG_16K_ROWS 2048
184 #define	ER_FZ_EVQ_TMR_REG_16K_RESET 0x0
185 
186 /* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */
187 /* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */
188 /* defined as ERF_FZ_TC_TIMER_MODE_LBN 14; */
189 /* defined as ERF_FZ_TC_TIMER_MODE_WIDTH 2 */
190 /* defined as ERF_FZ_TC_TIMER_VAL_LBN 0; */
191 /* defined as ERF_FZ_TC_TIMER_VAL_WIDTH 14 */
192 
193 /*
194  * EVQ_TMR_REG(32bit):
195  *
196  */
197 
198 #define	ER_DZ_EVQ_TMR_REG_OFST 0x00000420
199 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
200 #define	ER_DZ_EVQ_TMR_REG_STEP 8192
201 #define	ER_DZ_EVQ_TMR_REG_ROWS 2048
202 #define	ER_DZ_EVQ_TMR_REG_RESET 0x0
203 
204 /* defined as ERF_FZ_TC_TMR_REL_VAL_LBN 16; */
205 /* defined as ERF_FZ_TC_TMR_REL_VAL_WIDTH 14 */
206 #define	ERF_DZ_TC_TIMER_MODE_LBN 14
207 #define	ERF_DZ_TC_TIMER_MODE_WIDTH 2
208 #define	ERF_DZ_TC_TIMER_VAL_LBN 0
209 #define	ERF_DZ_TC_TIMER_VAL_WIDTH 14
210 
211 /*
212  * RX_DESC_UPD_REG_16K(32bit):
213  *
214  */
215 
216 #define	ER_FZ_RX_DESC_UPD_REG_16K_OFST 0x00000830
217 /* medford2a0=pf_dbell_bar */
218 #define	ER_FZ_RX_DESC_UPD_REG_16K_STEP 16384
219 #define	ER_FZ_RX_DESC_UPD_REG_16K_ROWS 2048
220 #define	ER_FZ_RX_DESC_UPD_REG_16K_RESET 0x0
221 
222 #define	ERF_FZ_RX_DESC_WPTR_LBN 0
223 #define	ERF_FZ_RX_DESC_WPTR_WIDTH 12
224 
225 /*
226  * RX_DESC_UPD_REG(32bit):
227  *
228  */
229 
230 #define	ER_DZ_RX_DESC_UPD_REG_OFST 0x00000830
231 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
232 #define	ER_DZ_RX_DESC_UPD_REG_STEP 8192
233 #define	ER_DZ_RX_DESC_UPD_REG_ROWS 2048
234 #define	ER_DZ_RX_DESC_UPD_REG_RESET 0x0
235 
236 #define	ERF_DZ_RX_DESC_WPTR_LBN 0
237 #define	ERF_DZ_RX_DESC_WPTR_WIDTH 12
238 
239 /*
240  * RX_DESC_UPD_REG_64K(32bit):
241  *
242  */
243 
244 #define	ER_FZ_RX_DESC_UPD_REG_64K_OFST 0x00000830
245 /* medford2a0=pf_dbell_bar */
246 #define	ER_FZ_RX_DESC_UPD_REG_64K_STEP 65536
247 #define	ER_FZ_RX_DESC_UPD_REG_64K_ROWS 2048
248 #define	ER_FZ_RX_DESC_UPD_REG_64K_RESET 0x0
249 
250 /* defined as ERF_FZ_RX_DESC_WPTR_LBN 0; */
251 /* defined as ERF_FZ_RX_DESC_WPTR_WIDTH 12 */
252 
253 /*
254  * TX_DESC_UPD_REG_64K(96bit):
255  *
256  */
257 
258 #define	ER_FZ_TX_DESC_UPD_REG_64K_OFST 0x00000a10
259 /* medford2a0=pf_dbell_bar */
260 #define	ER_FZ_TX_DESC_UPD_REG_64K_STEP 65536
261 #define	ER_FZ_TX_DESC_UPD_REG_64K_ROWS 2048
262 #define	ER_FZ_TX_DESC_UPD_REG_64K_RESET 0x0
263 
264 #define	ERF_FZ_RSVD_LBN 76
265 #define	ERF_FZ_RSVD_WIDTH 20
266 #define	ERF_FZ_TX_DESC_WPTR_LBN 64
267 #define	ERF_FZ_TX_DESC_WPTR_WIDTH 12
268 #define	ERF_FZ_TX_DESC_HWORD_LBN 32
269 #define	ERF_FZ_TX_DESC_HWORD_WIDTH 32
270 #define	ERF_FZ_TX_DESC_LWORD_LBN 0
271 #define	ERF_FZ_TX_DESC_LWORD_WIDTH 32
272 
273 /*
274  * TX_DESC_UPD_REG_16K(96bit):
275  *
276  */
277 
278 #define	ER_FZ_TX_DESC_UPD_REG_16K_OFST 0x00000a10
279 /* medford2a0=pf_dbell_bar */
280 #define	ER_FZ_TX_DESC_UPD_REG_16K_STEP 16384
281 #define	ER_FZ_TX_DESC_UPD_REG_16K_ROWS 2048
282 #define	ER_FZ_TX_DESC_UPD_REG_16K_RESET 0x0
283 
284 /* defined as ERF_FZ_RSVD_LBN 76; */
285 /* defined as ERF_FZ_RSVD_WIDTH 20 */
286 /* defined as ERF_FZ_TX_DESC_WPTR_LBN 64; */
287 /* defined as ERF_FZ_TX_DESC_WPTR_WIDTH 12 */
288 /* defined as ERF_FZ_TX_DESC_HWORD_LBN 32; */
289 /* defined as ERF_FZ_TX_DESC_HWORD_WIDTH 32 */
290 /* defined as ERF_FZ_TX_DESC_LWORD_LBN 0; */
291 /* defined as ERF_FZ_TX_DESC_LWORD_WIDTH 32 */
292 
293 /*
294  * TX_DESC_UPD_REG(96bit):
295  *
296  */
297 
298 #define	ER_DZ_TX_DESC_UPD_REG_OFST 0x00000a10
299 /* hunta0,medforda0,medford2a0=pf_dbell_bar */
300 #define	ER_DZ_TX_DESC_UPD_REG_STEP 8192
301 #define	ER_DZ_TX_DESC_UPD_REG_ROWS 2048
302 #define	ER_DZ_TX_DESC_UPD_REG_RESET 0x0
303 
304 #define	ERF_DZ_RSVD_LBN 76
305 #define	ERF_DZ_RSVD_WIDTH 20
306 #define	ERF_DZ_TX_DESC_WPTR_LBN 64
307 #define	ERF_DZ_TX_DESC_WPTR_WIDTH 12
308 #define	ERF_DZ_TX_DESC_HWORD_LBN 32
309 #define	ERF_DZ_TX_DESC_HWORD_WIDTH 32
310 #define	ERF_DZ_TX_DESC_LWORD_LBN 0
311 #define	ERF_DZ_TX_DESC_LWORD_WIDTH 32
312 
313 /* ES_DRIVER_EV */
314 #define	ESF_DZ_DRV_CODE_LBN 60
315 #define	ESF_DZ_DRV_CODE_WIDTH 4
316 #define	ESF_DZ_DRV_SUB_CODE_LBN 56
317 #define	ESF_DZ_DRV_SUB_CODE_WIDTH 4
318 #define	ESE_DZ_DRV_TIMER_EV 3
319 #define	ESE_DZ_DRV_START_UP_EV 2
320 #define	ESE_DZ_DRV_WAKE_UP_EV 1
321 #define	ESF_DZ_DRV_SUB_DATA_DW0_LBN 0
322 #define	ESF_DZ_DRV_SUB_DATA_DW0_WIDTH 32
323 #define	ESF_DZ_DRV_SUB_DATA_DW1_LBN 32
324 #define	ESF_DZ_DRV_SUB_DATA_DW1_WIDTH 24
325 #define	ESF_DZ_DRV_SUB_DATA_LBN 0
326 #define	ESF_DZ_DRV_SUB_DATA_WIDTH 56
327 #define	ESF_DZ_DRV_EVQ_ID_LBN 0
328 #define	ESF_DZ_DRV_EVQ_ID_WIDTH 14
329 #define	ESF_DZ_DRV_TMR_ID_LBN 0
330 #define	ESF_DZ_DRV_TMR_ID_WIDTH 14
331 
332 /* ES_EVENT_ENTRY */
333 #define	ESF_DZ_EV_CODE_LBN 60
334 #define	ESF_DZ_EV_CODE_WIDTH 4
335 #define	ESE_DZ_EV_CODE_MCDI_EV 12
336 #define	ESE_DZ_EV_CODE_DRIVER_EV 5
337 #define	ESE_DZ_EV_CODE_TX_EV 2
338 #define	ESE_DZ_EV_CODE_RX_EV 0
339 #define	ESE_DZ_OTHER other
340 #define	ESF_DZ_EV_DATA_DW0_LBN 0
341 #define	ESF_DZ_EV_DATA_DW0_WIDTH 32
342 #define	ESF_DZ_EV_DATA_DW1_LBN 32
343 #define	ESF_DZ_EV_DATA_DW1_WIDTH 28
344 #define	ESF_DZ_EV_DATA_LBN 0
345 #define	ESF_DZ_EV_DATA_WIDTH 60
346 
347 /* ES_MC_EVENT */
348 #define	ESF_DZ_MC_CODE_LBN 60
349 #define	ESF_DZ_MC_CODE_WIDTH 4
350 #define	ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59
351 #define	ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1
352 #define	ESF_DZ_MC_DROP_EVENT_LBN 58
353 #define	ESF_DZ_MC_DROP_EVENT_WIDTH 1
354 #define	ESF_DZ_MC_SOFT_DW0_LBN 0
355 #define	ESF_DZ_MC_SOFT_DW0_WIDTH 32
356 #define	ESF_DZ_MC_SOFT_DW1_LBN 32
357 #define	ESF_DZ_MC_SOFT_DW1_WIDTH 26
358 #define	ESF_DZ_MC_SOFT_LBN 0
359 #define	ESF_DZ_MC_SOFT_WIDTH 58
360 
361 /* ES_RX_EVENT */
362 #define	ESF_DZ_RX_CODE_LBN 60
363 #define	ESF_DZ_RX_CODE_WIDTH 4
364 #define	ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59
365 #define	ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1
366 #define	ESF_DZ_RX_DROP_EVENT_LBN 58
367 #define	ESF_DZ_RX_DROP_EVENT_WIDTH 1
368 #define	ESF_DD_RX_EV_RSVD2_LBN 54
369 #define	ESF_DD_RX_EV_RSVD2_WIDTH 4
370 #define	ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_LBN 57
371 #define	ESF_EZ_RX_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1
372 #define	ESF_EZ_RX_IP_INNER_CHKSUM_ERR_LBN 56
373 #define	ESF_EZ_RX_IP_INNER_CHKSUM_ERR_WIDTH 1
374 #define	ESF_EZ_RX_EV_RSVD2_LBN 54
375 #define	ESF_EZ_RX_EV_RSVD2_WIDTH 2
376 #define	ESF_DZ_RX_EV_SOFT2_LBN 52
377 #define	ESF_DZ_RX_EV_SOFT2_WIDTH 2
378 #define	ESF_DZ_RX_DSC_PTR_LBITS_LBN 48
379 #define	ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4
380 #define	ESF_DE_RX_L4_CLASS_LBN 45
381 #define	ESF_DE_RX_L4_CLASS_WIDTH 3
382 #define	ESE_DE_L4_CLASS_RSVD7 7
383 #define	ESE_DE_L4_CLASS_RSVD6 6
384 #define	ESE_DE_L4_CLASS_RSVD5 5
385 #define	ESE_DE_L4_CLASS_RSVD4 4
386 #define	ESE_DE_L4_CLASS_RSVD3 3
387 #define	ESE_DE_L4_CLASS_UDP 2
388 #define	ESE_DE_L4_CLASS_TCP 1
389 #define	ESE_DE_L4_CLASS_UNKNOWN 0
390 #define	ESF_FZ_RX_FASTPD_INDCTR_LBN 47
391 #define	ESF_FZ_RX_FASTPD_INDCTR_WIDTH 1
392 #define	ESF_FZ_RX_L4_CLASS_LBN 45
393 #define	ESF_FZ_RX_L4_CLASS_WIDTH 2
394 #define	ESE_FZ_L4_CLASS_RSVD3 3
395 #define	ESE_FZ_L4_CLASS_UDP 2
396 #define	ESE_FZ_L4_CLASS_TCP 1
397 #define	ESE_FZ_L4_CLASS_UNKNOWN 0
398 #define	ESF_DZ_RX_L3_CLASS_LBN 42
399 #define	ESF_DZ_RX_L3_CLASS_WIDTH 3
400 #define	ESE_DZ_L3_CLASS_RSVD7 7
401 #define	ESE_DZ_L3_CLASS_IP6_FRAG 6
402 #define	ESE_DZ_L3_CLASS_ARP 5
403 #define	ESE_DZ_L3_CLASS_IP4_FRAG 4
404 #define	ESE_DZ_L3_CLASS_FCOE 3
405 #define	ESE_DZ_L3_CLASS_IP6 2
406 #define	ESE_DZ_L3_CLASS_IP4 1
407 #define	ESE_DZ_L3_CLASS_UNKNOWN 0
408 #define	ESF_DZ_RX_ETH_TAG_CLASS_LBN 39
409 #define	ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3
410 #define	ESE_DZ_ETH_TAG_CLASS_RSVD7 7
411 #define	ESE_DZ_ETH_TAG_CLASS_RSVD6 6
412 #define	ESE_DZ_ETH_TAG_CLASS_RSVD5 5
413 #define	ESE_DZ_ETH_TAG_CLASS_RSVD4 4
414 #define	ESE_DZ_ETH_TAG_CLASS_RSVD3 3
415 #define	ESE_DZ_ETH_TAG_CLASS_VLAN2 2
416 #define	ESE_DZ_ETH_TAG_CLASS_VLAN1 1
417 #define	ESE_DZ_ETH_TAG_CLASS_NONE 0
418 #define	ESF_DZ_RX_ETH_BASE_CLASS_LBN 36
419 #define	ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3
420 #define	ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2
421 #define	ESE_DZ_ETH_BASE_CLASS_LLC 1
422 #define	ESE_DZ_ETH_BASE_CLASS_ETH2 0
423 #define	ESF_DZ_RX_MAC_CLASS_LBN 35
424 #define	ESF_DZ_RX_MAC_CLASS_WIDTH 1
425 #define	ESE_DZ_MAC_CLASS_MCAST 1
426 #define	ESE_DZ_MAC_CLASS_UCAST 0
427 #define	ESF_DD_RX_EV_SOFT1_LBN 32
428 #define	ESF_DD_RX_EV_SOFT1_WIDTH 3
429 #define	ESF_EZ_RX_EV_SOFT1_LBN 34
430 #define	ESF_EZ_RX_EV_SOFT1_WIDTH 1
431 #define	ESF_EZ_RX_ENCAP_HDR_LBN 32
432 #define	ESF_EZ_RX_ENCAP_HDR_WIDTH 2
433 #define	ESE_EZ_ENCAP_HDR_GRE 2
434 #define	ESE_EZ_ENCAP_HDR_VXLAN 1
435 #define	ESE_EZ_ENCAP_HDR_NONE 0
436 #define	ESF_DD_RX_EV_RSVD1_LBN 30
437 #define	ESF_DD_RX_EV_RSVD1_WIDTH 2
438 #define	ESF_EZ_RX_EV_RSVD1_LBN 31
439 #define	ESF_EZ_RX_EV_RSVD1_WIDTH 1
440 #define	ESF_EZ_RX_ABORT_LBN 30
441 #define	ESF_EZ_RX_ABORT_WIDTH 1
442 #define	ESF_DZ_RX_ECC_ERR_LBN 29
443 #define	ESF_DZ_RX_ECC_ERR_WIDTH 1
444 #define	ESF_DZ_RX_TRUNC_ERR_LBN 29
445 #define	ESF_DZ_RX_TRUNC_ERR_WIDTH 1
446 #define	ESF_DZ_RX_CRC1_ERR_LBN 28
447 #define	ESF_DZ_RX_CRC1_ERR_WIDTH 1
448 #define	ESF_DZ_RX_CRC0_ERR_LBN 27
449 #define	ESF_DZ_RX_CRC0_ERR_WIDTH 1
450 #define	ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26
451 #define	ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1
452 #define	ESF_DZ_RX_IPCKSUM_ERR_LBN 25
453 #define	ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1
454 #define	ESF_DZ_RX_ECRC_ERR_LBN 24
455 #define	ESF_DZ_RX_ECRC_ERR_WIDTH 1
456 #define	ESF_DZ_RX_QLABEL_LBN 16
457 #define	ESF_DZ_RX_QLABEL_WIDTH 5
458 #define	ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15
459 #define	ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1
460 #define	ESF_DZ_RX_CONT_LBN 14
461 #define	ESF_DZ_RX_CONT_WIDTH 1
462 #define	ESF_DZ_RX_BYTES_LBN 0
463 #define	ESF_DZ_RX_BYTES_WIDTH 14
464 
465 /* ES_RX_KER_DESC */
466 #define	ESF_DZ_RX_KER_RESERVED_LBN 62
467 #define	ESF_DZ_RX_KER_RESERVED_WIDTH 2
468 #define	ESF_DZ_RX_KER_BYTE_CNT_LBN 48
469 #define	ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14
470 #define	ESF_DZ_RX_KER_BUF_ADDR_DW0_LBN 0
471 #define	ESF_DZ_RX_KER_BUF_ADDR_DW0_WIDTH 32
472 #define	ESF_DZ_RX_KER_BUF_ADDR_DW1_LBN 32
473 #define	ESF_DZ_RX_KER_BUF_ADDR_DW1_WIDTH 16
474 #define	ESF_DZ_RX_KER_BUF_ADDR_LBN 0
475 #define	ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48
476 
477 /* ES_TX_CSUM_TSTAMP_DESC */
478 #define	ESF_DZ_TX_DESC_IS_OPT_LBN 63
479 #define	ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
480 #define	ESF_DZ_TX_OPTION_TYPE_LBN 60
481 #define	ESF_DZ_TX_OPTION_TYPE_WIDTH 3
482 #define	ESE_DZ_TX_OPTION_DESC_TSO 7
483 #define	ESE_DZ_TX_OPTION_DESC_VLAN 6
484 #define	ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
485 #define	ESF_DZ_TX_OPTION_TS_AT_TXDP_LBN 8
486 #define	ESF_DZ_TX_OPTION_TS_AT_TXDP_WIDTH 1
487 #define	ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_LBN 7
488 #define	ESF_DZ_TX_OPTION_INNER_UDP_TCP_CSUM_WIDTH 1
489 #define	ESF_DZ_TX_OPTION_INNER_IP_CSUM_LBN 6
490 #define	ESF_DZ_TX_OPTION_INNER_IP_CSUM_WIDTH 1
491 #define	ESF_DZ_TX_TIMESTAMP_LBN 5
492 #define	ESF_DZ_TX_TIMESTAMP_WIDTH 1
493 #define	ESF_DZ_TX_OPTION_CRC_MODE_LBN 2
494 #define	ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3
495 #define	ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5
496 #define	ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4
497 #define	ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3
498 #define	ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2
499 #define	ESE_DZ_TX_OPTION_CRC_FCOE 1
500 #define	ESE_DZ_TX_OPTION_CRC_OFF 0
501 #define	ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1
502 #define	ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1
503 #define	ESF_DZ_TX_OPTION_IP_CSUM_LBN 0
504 #define	ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1
505 
506 /* ES_TX_EVENT */
507 #define	ESF_DZ_TX_CODE_LBN 60
508 #define	ESF_DZ_TX_CODE_WIDTH 4
509 #define	ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59
510 #define	ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1
511 #define	ESF_DZ_TX_DROP_EVENT_LBN 58
512 #define	ESF_DZ_TX_DROP_EVENT_WIDTH 1
513 #define	ESF_DD_TX_EV_RSVD_LBN 48
514 #define	ESF_DD_TX_EV_RSVD_WIDTH 10
515 #define	ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_LBN 57
516 #define	ESF_EZ_TCP_UDP_INNER_CHKSUM_ERR_WIDTH 1
517 #define	ESF_EZ_IP_INNER_CHKSUM_ERR_LBN 56
518 #define	ESF_EZ_IP_INNER_CHKSUM_ERR_WIDTH 1
519 #define	ESF_EZ_TX_EV_RSVD_LBN 48
520 #define	ESF_EZ_TX_EV_RSVD_WIDTH 8
521 #define	ESF_DZ_TX_SOFT2_LBN 32
522 #define	ESF_DZ_TX_SOFT2_WIDTH 16
523 #define	ESF_DD_TX_SOFT1_LBN 24
524 #define	ESF_DD_TX_SOFT1_WIDTH 8
525 #define	ESF_EZ_TX_CAN_MERGE_LBN 31
526 #define	ESF_EZ_TX_CAN_MERGE_WIDTH 1
527 #define	ESF_EZ_TX_SOFT1_LBN 24
528 #define	ESF_EZ_TX_SOFT1_WIDTH 7
529 #define	ESF_DZ_TX_QLABEL_LBN 16
530 #define	ESF_DZ_TX_QLABEL_WIDTH 5
531 #define	ESF_DZ_TX_DESCR_INDX_LBN 0
532 #define	ESF_DZ_TX_DESCR_INDX_WIDTH 16
533 
534 /* ES_TX_KER_DESC */
535 #define	ESF_DZ_TX_KER_TYPE_LBN 63
536 #define	ESF_DZ_TX_KER_TYPE_WIDTH 1
537 #define	ESF_DZ_TX_KER_CONT_LBN 62
538 #define	ESF_DZ_TX_KER_CONT_WIDTH 1
539 #define	ESF_DZ_TX_KER_BYTE_CNT_LBN 48
540 #define	ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14
541 #define	ESF_DZ_TX_KER_BUF_ADDR_DW0_LBN 0
542 #define	ESF_DZ_TX_KER_BUF_ADDR_DW0_WIDTH 32
543 #define	ESF_DZ_TX_KER_BUF_ADDR_DW1_LBN 32
544 #define	ESF_DZ_TX_KER_BUF_ADDR_DW1_WIDTH 16
545 #define	ESF_DZ_TX_KER_BUF_ADDR_LBN 0
546 #define	ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48
547 
548 /* ES_TX_PIO_DESC */
549 #define	ESF_DZ_TX_PIO_TYPE_LBN 63
550 #define	ESF_DZ_TX_PIO_TYPE_WIDTH 1
551 #define	ESF_DZ_TX_PIO_OPT_LBN 60
552 #define	ESF_DZ_TX_PIO_OPT_WIDTH 3
553 #define	ESF_DZ_TX_PIO_CONT_LBN 59
554 #define	ESF_DZ_TX_PIO_CONT_WIDTH 1
555 #define	ESF_DZ_TX_PIO_BYTE_CNT_LBN 32
556 #define	ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12
557 #define	ESF_DZ_TX_PIO_BUF_ADDR_LBN 0
558 #define	ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12
559 
560 /* ES_TX_TSO_DESC */
561 #define	ESF_DZ_TX_DESC_IS_OPT_LBN 63
562 #define	ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
563 #define	ESF_DZ_TX_OPTION_TYPE_LBN 60
564 #define	ESF_DZ_TX_OPTION_TYPE_WIDTH 3
565 #define	ESE_DZ_TX_OPTION_DESC_TSO 7
566 #define	ESE_DZ_TX_OPTION_DESC_VLAN 6
567 #define	ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
568 #define	ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56
569 #define	ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4
570 #define	ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3
571 #define	ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2
572 #define	ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1
573 #define	ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
574 #define	ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48
575 #define	ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8
576 #define	ESF_DZ_TX_TSO_IP_ID_LBN 32
577 #define	ESF_DZ_TX_TSO_IP_ID_WIDTH 16
578 #define	ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
579 #define	ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
580 
581 /* ES_TX_TSO_V2_DESC_A */
582 #define	ESF_DZ_TX_DESC_IS_OPT_LBN 63
583 #define	ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
584 #define	ESF_DZ_TX_OPTION_TYPE_LBN 60
585 #define	ESF_DZ_TX_OPTION_TYPE_WIDTH 3
586 #define	ESE_DZ_TX_OPTION_DESC_TSO 7
587 #define	ESE_DZ_TX_OPTION_DESC_VLAN 6
588 #define	ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
589 #define	ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56
590 #define	ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4
591 #define	ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3
592 #define	ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2
593 #define	ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1
594 #define	ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
595 #define	ESF_DZ_TX_TSO_IP_ID_LBN 32
596 #define	ESF_DZ_TX_TSO_IP_ID_WIDTH 16
597 #define	ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0
598 #define	ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32
599 
600 /* ES_TX_TSO_V2_DESC_B */
601 #define	ESF_DZ_TX_DESC_IS_OPT_LBN 63
602 #define	ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
603 #define	ESF_DZ_TX_OPTION_TYPE_LBN 60
604 #define	ESF_DZ_TX_OPTION_TYPE_WIDTH 3
605 #define	ESE_DZ_TX_OPTION_DESC_TSO 7
606 #define	ESE_DZ_TX_OPTION_DESC_VLAN 6
607 #define	ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
608 #define	ESF_DZ_TX_TSO_OPTION_TYPE_LBN 56
609 #define	ESF_DZ_TX_TSO_OPTION_TYPE_WIDTH 4
610 #define	ESE_DZ_TX_TSO_OPTION_DESC_FATSO2B 3
611 #define	ESE_DZ_TX_TSO_OPTION_DESC_FATSO2A 2
612 #define	ESE_DZ_TX_TSO_OPTION_DESC_ENCAP 1
613 #define	ESE_DZ_TX_TSO_OPTION_DESC_NORMAL 0
614 #define	ESF_DZ_TX_TSO_TCP_MSS_LBN 32
615 #define	ESF_DZ_TX_TSO_TCP_MSS_WIDTH 16
616 #define	ESF_DZ_TX_TSO_OUTER_IPID_LBN 0
617 #define	ESF_DZ_TX_TSO_OUTER_IPID_WIDTH 16
618 
619 /* ES_TX_VLAN_DESC */
620 #define	ESF_DZ_TX_DESC_IS_OPT_LBN 63
621 #define	ESF_DZ_TX_DESC_IS_OPT_WIDTH 1
622 #define	ESF_DZ_TX_OPTION_TYPE_LBN 60
623 #define	ESF_DZ_TX_OPTION_TYPE_WIDTH 3
624 #define	ESE_DZ_TX_OPTION_DESC_TSO 7
625 #define	ESE_DZ_TX_OPTION_DESC_VLAN 6
626 #define	ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0
627 #define	ESF_DZ_TX_VLAN_OP_LBN 32
628 #define	ESF_DZ_TX_VLAN_OP_WIDTH 2
629 #define	ESF_DZ_TX_VLAN_TAG2_LBN 16
630 #define	ESF_DZ_TX_VLAN_TAG2_WIDTH 16
631 #define	ESF_DZ_TX_VLAN_TAG1_LBN 0
632 #define	ESF_DZ_TX_VLAN_TAG1_WIDTH 16
633 
634 /*************************************************************************
635  * NOTE: the comment line above marks the end of the autogenerated section
636  */
637 
638 /*
639  * The workaround for bug 35388 requires multiplexing writes through
640  * the ERF_DZ_TX_DESC_WPTR address.
641  * TX_DESC_UPD: 0ppppppppppp               (bit 11 lost)
642  * EVQ_RPTR:    1000hhhhhhhh, 1001llllllll (split into high and low bits)
643  * EVQ_TMR:     11mmvvvvvvvv               (bits 8:13 of value lost)
644  */
645 #define	ER_DD_EVQ_INDIRECT_OFST (ER_DZ_TX_DESC_UPD_REG_OFST + 2 * 4)
646 #define	ER_DD_EVQ_INDIRECT_STEP ER_DZ_TX_DESC_UPD_REG_STEP
647 #define	ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8
648 #define	ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4
649 #define	EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8
650 #define	EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9
651 #define	ERF_DD_EVQ_IND_RPTR_LBN 0
652 #define	ERF_DD_EVQ_IND_RPTR_WIDTH 8
653 #define	ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10
654 #define	ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2
655 #define	EFE_DD_EVQ_IND_TIMER_FLAGS 3
656 #define	ERF_DD_EVQ_IND_TIMER_MODE_LBN 8
657 #define	ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2
658 #define	ERF_DD_EVQ_IND_TIMER_VAL_LBN 0
659 #define	ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8
660 
661 /* Packed stream magic doorbell command */
662 #define	ERF_DZ_RX_DESC_MAGIC_DOORBELL_LBN 11
663 #define	ERF_DZ_RX_DESC_MAGIC_DOORBELL_WIDTH 1
664 
665 #define	ERF_DZ_RX_DESC_MAGIC_CMD_LBN 8
666 #define	ERF_DZ_RX_DESC_MAGIC_CMD_WIDTH 3
667 #define	ERE_DZ_RX_DESC_MAGIC_CMD_PS_CREDITS 0
668 
669 #define	ERF_DZ_RX_DESC_MAGIC_DATA_LBN 0
670 #define	ERF_DZ_RX_DESC_MAGIC_DATA_WIDTH 8
671 
672 /* Packed stream RX packet prefix */
673 #define	ES_DZ_PS_RX_PREFIX_TSTAMP_LBN 0
674 #define	ES_DZ_PS_RX_PREFIX_TSTAMP_WIDTH 32
675 #define	ES_DZ_PS_RX_PREFIX_CAP_LEN_LBN 32
676 #define	ES_DZ_PS_RX_PREFIX_CAP_LEN_WIDTH 16
677 #define	ES_DZ_PS_RX_PREFIX_ORIG_LEN_LBN 48
678 #define	ES_DZ_PS_RX_PREFIX_ORIG_LEN_WIDTH 16
679 
680 /* Equal stride super-buffer RX packet prefix (see SF-119419-TC) */
681 #define	ES_EZ_ESSB_RX_PREFIX_LEN 8
682 #define	ES_EZ_ESSB_RX_PREFIX_DATA_LEN_LBN 0
683 #define	ES_EZ_ESSB_RX_PREFIX_DATA_LEN_WIDTH 16
684 #define	ES_EZ_ESSB_RX_PREFIX_MARK_LBN 16
685 #define	ES_EZ_ESSB_RX_PREFIX_MARK_WIDTH 8
686 #define	ES_EZ_ESSB_RX_PREFIX_HASH_VALID_LBN 28
687 #define	ES_EZ_ESSB_RX_PREFIX_HASH_VALID_WIDTH 1
688 #define	ES_EZ_ESSB_RX_PREFIX_MARK_VALID_LBN 29
689 #define	ES_EZ_ESSB_RX_PREFIX_MARK_VALID_WIDTH 1
690 #define	ES_EZ_ESSB_RX_PREFIX_MATCH_FLAG_LBN 30
691 #define	ES_EZ_ESSB_RX_PREFIX_MATCH_FLAG_WIDTH 1
692 #define	ES_EZ_ESSB_RX_PREFIX_HASH_LBN 32
693 #define	ES_EZ_ESSB_RX_PREFIX_HASH_WIDTH 32
694 
695 /*
696  * An extra flag for the packed stream mode,
697  * signalling the start of a new buffer
698  */
699 #define	ESF_DZ_RX_EV_ROTATE_LBN 53
700 #define	ESF_DZ_RX_EV_ROTATE_WIDTH 1
701 
702 #ifdef	__cplusplus
703 }
704 #endif
705 
706 #endif /* _SYS_EFX_EF10_REGS_H */
707