1 //===-- X86BaseInfo.h - Top level definitions for X86 -------- --*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file contains small standalone helper functions and enum definitions for
10 // the X86 target useful for the compiler back-end and the MC libraries.
11 // As such, it deliberately does not include references to LLVM core
12 // code gen types, passes, etc..
13 //
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
17 #define LLVM_LIB_TARGET_X86_MCTARGETDESC_X86BASEINFO_H
18 
19 #include "X86MCTargetDesc.h"
20 #include "llvm/MC/MCInstrDesc.h"
21 #include "llvm/Support/DataTypes.h"
22 #include "llvm/Support/ErrorHandling.h"
23 
24 namespace llvm {
25 namespace X86 {
26 // Enums for memory operand decoding. Each memory operand is represented with
27 // a 5 operand sequence in the form: [Base, Scale, Index, Disp, Segment]
28 enum {
29   AddrBaseReg = 0,
30   AddrScaleAmt = 1,
31   AddrIndexReg = 2,
32   AddrDisp = 3,
33   // The operand # of the segment in the memory operand.
34   AddrSegmentReg = 4,
35   // Total number of operands in a memory reference.
36   AddrNumOperands = 5
37 };
38 
39 /// AVX512 static rounding constants. These need to match the values in
40 /// avx512fintrin.h.
41 enum STATIC_ROUNDING {
42   TO_NEAREST_INT = 0,
43   TO_NEG_INF = 1,
44   TO_POS_INF = 2,
45   TO_ZERO = 3,
46   CUR_DIRECTION = 4,
47   NO_EXC = 8
48 };
49 
50 /// The constants to describe instr prefixes if there are
51 enum IPREFIXES {
52   IP_NO_PREFIX = 0,
53   IP_HAS_OP_SIZE = 1U << 0,
54   IP_HAS_AD_SIZE = 1U << 1,
55   IP_HAS_REPEAT_NE = 1U << 2,
56   IP_HAS_REPEAT = 1U << 3,
57   IP_HAS_LOCK = 1U << 4,
58   IP_HAS_NOTRACK = 1U << 5,
59   IP_USE_VEX = 1U << 6,
60   IP_USE_VEX2 = 1U << 7,
61   IP_USE_VEX3 = 1U << 8,
62   IP_USE_EVEX = 1U << 9,
63   IP_USE_DISP8 = 1U << 10,
64   IP_USE_DISP32 = 1U << 11,
65 };
66 
67 enum OperandType : unsigned {
68   // AVX512 embedded rounding control. This should only have values 0-3.
69   OPERAND_ROUNDING_CONTROL = MCOI::OPERAND_FIRST_TARGET,
70   OPERAND_COND_CODE,
71 };
72 
73 // X86 specific condition code. These correspond to X86_*_COND in
74 // X86InstrInfo.td. They must be kept in synch.
75 enum CondCode {
76   COND_O = 0,
77   COND_NO = 1,
78   COND_B = 2,
79   COND_AE = 3,
80   COND_E = 4,
81   COND_NE = 5,
82   COND_BE = 6,
83   COND_A = 7,
84   COND_S = 8,
85   COND_NS = 9,
86   COND_P = 10,
87   COND_NP = 11,
88   COND_L = 12,
89   COND_GE = 13,
90   COND_LE = 14,
91   COND_G = 15,
92   LAST_VALID_COND = COND_G,
93   // Artificial condition codes. These are used by analyzeBranch
94   // to indicate a block terminated with two conditional branches that together
95   // form a compound condition. They occur in code using FCMP_OEQ or FCMP_UNE,
96   // which can't be represented on x86 with a single condition. These
97   // are never used in MachineInstrs and are inverses of one another.
98   COND_NE_OR_P,
99   COND_E_AND_NP,
100   COND_INVALID
101 };
102 
103 // The classification for the first instruction in macro fusion.
104 // FIXME: Zen 3 support branch fusion for OR/XOR.
105 enum class FirstMacroFusionInstKind {
106   Test,   // TEST
107   Cmp,    // CMP
108   And,    // AND
109   AddSub, // ADD, SUB
110   IncDec, // INC, DEC
111   Invalid // Not valid as a first macro fusion instruction
112 };
113 
114 enum class SecondMacroFusionInstKind {
115   AB,      // JA, JB and variants
116   ELG,     // JE, JL, JG and variants
117   SPO,     // JS, JP, JO and variants
118   Invalid, // Not a fusible jump.
119 };
120 
121 /// \returns the type of the first instruction in macro-fusion.
122 // FIXME: Zen 3 support branch fusion for OR/XOR.
123 inline FirstMacroFusionInstKind
classifyFirstOpcodeInMacroFusion(unsigned Opcode)124 classifyFirstOpcodeInMacroFusion(unsigned Opcode) {
125   switch (Opcode) {
126   default:
127     return FirstMacroFusionInstKind::Invalid;
128   // TEST
129   case X86::TEST16i16:
130   case X86::TEST16mr:
131   case X86::TEST16ri:
132   case X86::TEST16rr:
133   case X86::TEST32i32:
134   case X86::TEST32mr:
135   case X86::TEST32ri:
136   case X86::TEST32rr:
137   case X86::TEST64i32:
138   case X86::TEST64mr:
139   case X86::TEST64ri32:
140   case X86::TEST64rr:
141   case X86::TEST8i8:
142   case X86::TEST8mr:
143   case X86::TEST8ri:
144   case X86::TEST8rr:
145     return FirstMacroFusionInstKind::Test;
146   case X86::AND16i16:
147   case X86::AND16ri:
148   case X86::AND16ri8:
149   case X86::AND16rm:
150   case X86::AND16rr:
151   case X86::AND16rr_REV:
152   case X86::AND32i32:
153   case X86::AND32ri:
154   case X86::AND32ri8:
155   case X86::AND32rm:
156   case X86::AND32rr:
157   case X86::AND32rr_REV:
158   case X86::AND64i32:
159   case X86::AND64ri32:
160   case X86::AND64ri8:
161   case X86::AND64rm:
162   case X86::AND64rr:
163   case X86::AND64rr_REV:
164   case X86::AND8i8:
165   case X86::AND8ri:
166   case X86::AND8ri8:
167   case X86::AND8rm:
168   case X86::AND8rr:
169   case X86::AND8rr_REV:
170     return FirstMacroFusionInstKind::And;
171   // CMP
172   case X86::CMP16i16:
173   case X86::CMP16mr:
174   case X86::CMP16ri:
175   case X86::CMP16ri8:
176   case X86::CMP16rm:
177   case X86::CMP16rr:
178   case X86::CMP16rr_REV:
179   case X86::CMP32i32:
180   case X86::CMP32mr:
181   case X86::CMP32ri:
182   case X86::CMP32ri8:
183   case X86::CMP32rm:
184   case X86::CMP32rr:
185   case X86::CMP32rr_REV:
186   case X86::CMP64i32:
187   case X86::CMP64mr:
188   case X86::CMP64ri32:
189   case X86::CMP64ri8:
190   case X86::CMP64rm:
191   case X86::CMP64rr:
192   case X86::CMP64rr_REV:
193   case X86::CMP8i8:
194   case X86::CMP8mr:
195   case X86::CMP8ri:
196   case X86::CMP8ri8:
197   case X86::CMP8rm:
198   case X86::CMP8rr:
199   case X86::CMP8rr_REV:
200     return FirstMacroFusionInstKind::Cmp;
201   // ADD
202   case X86::ADD16i16:
203   case X86::ADD16ri:
204   case X86::ADD16ri8:
205   case X86::ADD16rm:
206   case X86::ADD16rr:
207   case X86::ADD16rr_REV:
208   case X86::ADD32i32:
209   case X86::ADD32ri:
210   case X86::ADD32ri8:
211   case X86::ADD32rm:
212   case X86::ADD32rr:
213   case X86::ADD32rr_REV:
214   case X86::ADD64i32:
215   case X86::ADD64ri32:
216   case X86::ADD64ri8:
217   case X86::ADD64rm:
218   case X86::ADD64rr:
219   case X86::ADD64rr_REV:
220   case X86::ADD8i8:
221   case X86::ADD8ri:
222   case X86::ADD8ri8:
223   case X86::ADD8rm:
224   case X86::ADD8rr:
225   case X86::ADD8rr_REV:
226   // SUB
227   case X86::SUB16i16:
228   case X86::SUB16ri:
229   case X86::SUB16ri8:
230   case X86::SUB16rm:
231   case X86::SUB16rr:
232   case X86::SUB16rr_REV:
233   case X86::SUB32i32:
234   case X86::SUB32ri:
235   case X86::SUB32ri8:
236   case X86::SUB32rm:
237   case X86::SUB32rr:
238   case X86::SUB32rr_REV:
239   case X86::SUB64i32:
240   case X86::SUB64ri32:
241   case X86::SUB64ri8:
242   case X86::SUB64rm:
243   case X86::SUB64rr:
244   case X86::SUB64rr_REV:
245   case X86::SUB8i8:
246   case X86::SUB8ri:
247   case X86::SUB8ri8:
248   case X86::SUB8rm:
249   case X86::SUB8rr:
250   case X86::SUB8rr_REV:
251     return FirstMacroFusionInstKind::AddSub;
252   // INC
253   case X86::INC16r:
254   case X86::INC16r_alt:
255   case X86::INC32r:
256   case X86::INC32r_alt:
257   case X86::INC64r:
258   case X86::INC8r:
259   // DEC
260   case X86::DEC16r:
261   case X86::DEC16r_alt:
262   case X86::DEC32r:
263   case X86::DEC32r_alt:
264   case X86::DEC64r:
265   case X86::DEC8r:
266     return FirstMacroFusionInstKind::IncDec;
267   }
268 }
269 
270 /// \returns the type of the second instruction in macro-fusion.
271 inline SecondMacroFusionInstKind
classifySecondCondCodeInMacroFusion(X86::CondCode CC)272 classifySecondCondCodeInMacroFusion(X86::CondCode CC) {
273   if (CC == X86::COND_INVALID)
274     return SecondMacroFusionInstKind::Invalid;
275   switch (CC) {
276   default:
277     return SecondMacroFusionInstKind::Invalid;
278   case X86::COND_E:  // JE,JZ
279   case X86::COND_NE: // JNE,JNZ
280   case X86::COND_L:  // JL,JNGE
281   case X86::COND_LE: // JLE,JNG
282   case X86::COND_G:  // JG,JNLE
283   case X86::COND_GE: // JGE,JNL
284     return SecondMacroFusionInstKind::ELG;
285   case X86::COND_B:  // JB,JC
286   case X86::COND_BE: // JNA,JBE
287   case X86::COND_A:  // JA,JNBE
288   case X86::COND_AE: // JAE,JNC,JNB
289     return SecondMacroFusionInstKind::AB;
290   case X86::COND_S:  // JS
291   case X86::COND_NS: // JNS
292   case X86::COND_P:  // JP,JPE
293   case X86::COND_NP: // JNP,JPO
294   case X86::COND_O:  // JO
295   case X86::COND_NO: // JNO
296     return SecondMacroFusionInstKind::SPO;
297   }
298 }
299 
300 /// \param FirstKind kind of the first instruction in macro fusion.
301 /// \param SecondKind kind of the second instruction in macro fusion.
302 ///
303 /// \returns true if the two instruction can be macro fused.
isMacroFused(FirstMacroFusionInstKind FirstKind,SecondMacroFusionInstKind SecondKind)304 inline bool isMacroFused(FirstMacroFusionInstKind FirstKind,
305                          SecondMacroFusionInstKind SecondKind) {
306   switch (FirstKind) {
307   case X86::FirstMacroFusionInstKind::Test:
308   case X86::FirstMacroFusionInstKind::And:
309     return true;
310   case X86::FirstMacroFusionInstKind::Cmp:
311   case X86::FirstMacroFusionInstKind::AddSub:
312     return SecondKind == X86::SecondMacroFusionInstKind::AB ||
313            SecondKind == X86::SecondMacroFusionInstKind::ELG;
314   case X86::FirstMacroFusionInstKind::IncDec:
315     return SecondKind == X86::SecondMacroFusionInstKind::ELG;
316   case X86::FirstMacroFusionInstKind::Invalid:
317     return false;
318   }
319   llvm_unreachable("unknown fusion type");
320 }
321 
322 /// Defines the possible values of the branch boundary alignment mask.
323 enum AlignBranchBoundaryKind : uint8_t {
324   AlignBranchNone = 0,
325   AlignBranchFused = 1U << 0,
326   AlignBranchJcc = 1U << 1,
327   AlignBranchJmp = 1U << 2,
328   AlignBranchCall = 1U << 3,
329   AlignBranchRet = 1U << 4,
330   AlignBranchIndirect = 1U << 5
331 };
332 
333 /// Defines the encoding values for segment override prefix.
334 enum EncodingOfSegmentOverridePrefix : uint8_t {
335   CS_Encoding = 0x2E,
336   DS_Encoding = 0x3E,
337   ES_Encoding = 0x26,
338   FS_Encoding = 0x64,
339   GS_Encoding = 0x65,
340   SS_Encoding = 0x36
341 };
342 
343 /// Given a segment register, return the encoding of the segment override
344 /// prefix for it.
345 inline EncodingOfSegmentOverridePrefix
getSegmentOverridePrefixForReg(unsigned Reg)346 getSegmentOverridePrefixForReg(unsigned Reg) {
347   switch (Reg) {
348   default:
349     llvm_unreachable("Unknown segment register!");
350   case X86::CS:
351     return CS_Encoding;
352   case X86::DS:
353     return DS_Encoding;
354   case X86::ES:
355     return ES_Encoding;
356   case X86::FS:
357     return FS_Encoding;
358   case X86::GS:
359     return GS_Encoding;
360   case X86::SS:
361     return SS_Encoding;
362   }
363 }
364 
365 } // namespace X86
366 
367 /// X86II - This namespace holds all of the target specific flags that
368 /// instruction info tracks.
369 ///
370 namespace X86II {
371 /// Target Operand Flag enum.
372 enum TOF {
373   //===------------------------------------------------------------------===//
374   // X86 Specific MachineOperand flags.
375   //
376   /// MO_NO_FLAG - No flag for the operand
377   MO_NO_FLAG,
378   /// MO_GOT_ABSOLUTE_ADDRESS - On a symbol operand, this represents a
379   /// relocation of:
380   ///    SYMBOL_LABEL + [. - PICBASELABEL]
381   MO_GOT_ABSOLUTE_ADDRESS,
382   /// MO_PIC_BASE_OFFSET - On a symbol operand this indicates that the
383   /// immediate should get the value of the symbol minus the PIC base label:
384   ///    SYMBOL_LABEL - PICBASELABEL
385   MO_PIC_BASE_OFFSET,
386   /// MO_GOT - On a symbol operand this indicates that the immediate is the
387   /// offset to the GOT entry for the symbol name from the base of the GOT.
388   /// See the X86-64 ELF ABI supplement for more details.
389   ///    SYMBOL_LABEL @GOT
390   MO_GOT,
391   /// MO_GOTOFF - On a symbol operand this indicates that the immediate is
392   /// the offset to the location of the symbol name from the base of the GOT.
393   /// See the X86-64 ELF ABI supplement for more details.
394   ///    SYMBOL_LABEL @GOTOFF
395   MO_GOTOFF,
396   /// MO_GOTPCREL - On a symbol operand this indicates that the immediate is
397   /// offset to the GOT entry for the symbol name from the current code
398   /// location.
399   /// See the X86-64 ELF ABI supplement for more details.
400   ///    SYMBOL_LABEL @GOTPCREL
401   MO_GOTPCREL,
402   /// MO_GOTPCREL_NORELAX - Same as MO_GOTPCREL except that R_X86_64_GOTPCREL
403   /// relocations are guaranteed to be emitted by the integrated assembler
404   /// instead of the relaxable R_X86_64[_REX]_GOTPCRELX relocations.
405   MO_GOTPCREL_NORELAX,
406   /// MO_PLT - On a symbol operand this indicates that the immediate is
407   /// offset to the PLT entry of symbol name from the current code location.
408   /// See the X86-64 ELF ABI supplement for more details.
409   ///    SYMBOL_LABEL @PLT
410   MO_PLT,
411   /// MO_TLSGD - On a symbol operand this indicates that the immediate is
412   /// the offset of the GOT entry with the TLS index structure that contains
413   /// the module number and variable offset for the symbol. Used in the
414   /// general dynamic TLS access model.
415   /// See 'ELF Handling for Thread-Local Storage' for more details.
416   ///    SYMBOL_LABEL @TLSGD
417   MO_TLSGD,
418   /// MO_TLSLD - On a symbol operand this indicates that the immediate is
419   /// the offset of the GOT entry with the TLS index for the module that
420   /// contains the symbol. When this index is passed to a call to
421   /// __tls_get_addr, the function will return the base address of the TLS
422   /// block for the symbol. Used in the x86-64 local dynamic TLS access model.
423   /// See 'ELF Handling for Thread-Local Storage' for more details.
424   ///    SYMBOL_LABEL @TLSLD
425   MO_TLSLD,
426   /// MO_TLSLDM - On a symbol operand this indicates that the immediate is
427   /// the offset of the GOT entry with the TLS index for the module that
428   /// contains the symbol. When this index is passed to a call to
429   /// ___tls_get_addr, the function will return the base address of the TLS
430   /// block for the symbol. Used in the IA32 local dynamic TLS access model.
431   /// See 'ELF Handling for Thread-Local Storage' for more details.
432   ///    SYMBOL_LABEL @TLSLDM
433   MO_TLSLDM,
434   /// MO_GOTTPOFF - On a symbol operand this indicates that the immediate is
435   /// the offset of the GOT entry with the thread-pointer offset for the
436   /// symbol. Used in the x86-64 initial exec TLS access model.
437   /// See 'ELF Handling for Thread-Local Storage' for more details.
438   ///    SYMBOL_LABEL @GOTTPOFF
439   MO_GOTTPOFF,
440   /// MO_INDNTPOFF - On a symbol operand this indicates that the immediate is
441   /// the absolute address of the GOT entry with the negative thread-pointer
442   /// offset for the symbol. Used in the non-PIC IA32 initial exec TLS access
443   /// model.
444   /// See 'ELF Handling for Thread-Local Storage' for more details.
445   ///    SYMBOL_LABEL @INDNTPOFF
446   MO_INDNTPOFF,
447   /// MO_TPOFF - On a symbol operand this indicates that the immediate is
448   /// the thread-pointer offset for the symbol. Used in the x86-64 local
449   /// exec TLS access model.
450   /// See 'ELF Handling for Thread-Local Storage' for more details.
451   ///    SYMBOL_LABEL @TPOFF
452   MO_TPOFF,
453   /// MO_DTPOFF - On a symbol operand this indicates that the immediate is
454   /// the offset of the GOT entry with the TLS offset of the symbol. Used
455   /// in the local dynamic TLS access model.
456   /// See 'ELF Handling for Thread-Local Storage' for more details.
457   ///    SYMBOL_LABEL @DTPOFF
458   MO_DTPOFF,
459   /// MO_NTPOFF - On a symbol operand this indicates that the immediate is
460   /// the negative thread-pointer offset for the symbol. Used in the IA32
461   /// local exec TLS access model.
462   /// See 'ELF Handling for Thread-Local Storage' for more details.
463   ///    SYMBOL_LABEL @NTPOFF
464   MO_NTPOFF,
465   /// MO_GOTNTPOFF - On a symbol operand this indicates that the immediate is
466   /// the offset of the GOT entry with the negative thread-pointer offset for
467   /// the symbol. Used in the PIC IA32 initial exec TLS access model.
468   /// See 'ELF Handling for Thread-Local Storage' for more details.
469   ///    SYMBOL_LABEL @GOTNTPOFF
470   MO_GOTNTPOFF,
471   /// MO_DLLIMPORT - On a symbol operand "FOO", this indicates that the
472   /// reference is actually to the "__imp_FOO" symbol.  This is used for
473   /// dllimport linkage on windows.
474   MO_DLLIMPORT,
475   /// MO_DARWIN_NONLAZY - On a symbol operand "FOO", this indicates that the
476   /// reference is actually to the "FOO$non_lazy_ptr" symbol, which is a
477   /// non-PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
478   MO_DARWIN_NONLAZY,
479   /// MO_DARWIN_NONLAZY_PIC_BASE - On a symbol operand "FOO", this indicates
480   /// that the reference is actually to "FOO$non_lazy_ptr - PICBASE", which is
481   /// a PIC-base-relative reference to a non-hidden dyld lazy pointer stub.
482   MO_DARWIN_NONLAZY_PIC_BASE,
483   /// MO_TLVP - On a symbol operand this indicates that the immediate is
484   /// some TLS offset.
485   /// This is the TLS offset for the Darwin TLS mechanism.
486   MO_TLVP,
487   /// MO_TLVP_PIC_BASE - On a symbol operand this indicates that the immediate
488   /// is some TLS offset from the picbase.
489   /// This is the 32-bit TLS offset for Darwin TLS in PIC mode.
490   MO_TLVP_PIC_BASE,
491   /// MO_SECREL - On a symbol operand this indicates that the immediate is
492   /// the offset from beginning of section.
493   /// This is the TLS offset for the COFF/Windows TLS mechanism.
494   MO_SECREL,
495   /// MO_ABS8 - On a symbol operand this indicates that the symbol is known
496   /// to be an absolute symbol in range [0,128), so we can use the @ABS8
497   /// symbol modifier.
498   MO_ABS8,
499   /// MO_COFFSTUB - On a symbol operand "FOO", this indicates that the
500   /// reference is actually to the ".refptr.FOO" symbol.  This is used for
501   /// stub symbols on windows.
502   MO_COFFSTUB,
503 };
504 
505 enum : uint64_t {
506   //===------------------------------------------------------------------===//
507   // Instruction encodings.  These are the standard/most common forms for X86
508   // instructions.
509   //
510   /// PseudoFrm - This represents an instruction that is a pseudo instruction
511   /// or one that has not been implemented yet.  It is illegal to code generate
512   /// it, but tolerated for intermediate implementation stages.
513   Pseudo = 0,
514   /// Raw - This form is for instructions that don't have any operands, so
515   /// they are just a fixed opcode value, like 'leave'.
516   RawFrm = 1,
517   /// AddRegFrm - This form is used for instructions like 'push r32' that have
518   /// their one register operand added to their opcode.
519   AddRegFrm = 2,
520   /// RawFrmMemOffs - This form is for instructions that store an absolute
521   /// memory offset as an immediate with a possible segment override.
522   RawFrmMemOffs = 3,
523   /// RawFrmSrc - This form is for instructions that use the source index
524   /// register SI/ESI/RSI with a possible segment override.
525   RawFrmSrc = 4,
526   /// RawFrmDst - This form is for instructions that use the destination index
527   /// register DI/EDI/RDI.
528   RawFrmDst = 5,
529   /// RawFrmDstSrc - This form is for instructions that use the source index
530   /// register SI/ESI/RSI with a possible segment override, and also the
531   /// destination index register DI/EDI/RDI.
532   RawFrmDstSrc = 6,
533   /// RawFrmImm8 - This is used for the ENTER instruction, which has two
534   /// immediates, the first of which is a 16-bit immediate (specified by
535   /// the imm encoding) and the second is a 8-bit fixed value.
536   RawFrmImm8 = 7,
537   /// RawFrmImm16 - This is used for CALL FAR instructions, which have two
538   /// immediates, the first of which is a 16 or 32-bit immediate (specified by
539   /// the imm encoding) and the second is a 16-bit fixed value.  In the AMD
540   /// manual, this operand is described as pntr16:32 and pntr16:16
541   RawFrmImm16 = 8,
542   /// AddCCFrm - This form is used for Jcc that encode the condition code
543   /// in the lower 4 bits of the opcode.
544   AddCCFrm = 9,
545   /// PrefixByte - This form is used for instructions that represent a prefix
546   /// byte like data16 or rep.
547   PrefixByte = 10,
548   /// MRMDestMem4VOp3CC - This form is used for instructions that use the Mod/RM
549   /// byte to specify a destination which in this case is memory and operand 3
550   /// with VEX.VVVV, and also encodes a condition code.
551   MRMDestMem4VOp3CC = 20,
552   /// Instructions operate on a register Reg/Opcode operand not the r/m field.
553   MRMr0 = 21,
554   /// MRMSrcMem - But force to use the SIB field.
555   MRMSrcMemFSIB = 22,
556   /// MRMDestMem - But force to use the SIB field.
557   MRMDestMemFSIB = 23,
558   /// MRMDestMem - This form is used for instructions that use the Mod/RM byte
559   /// to specify a destination, which in this case is memory.
560   MRMDestMem = 24,
561   /// MRMSrcMem - This form is used for instructions that use the Mod/RM byte
562   /// to specify a source, which in this case is memory.
563   MRMSrcMem = 25,
564   /// MRMSrcMem4VOp3 - This form is used for instructions that encode
565   /// operand 3 with VEX.VVVV and load from memory.
566   MRMSrcMem4VOp3 = 26,
567   /// MRMSrcMemOp4 - This form is used for instructions that use the Mod/RM
568   /// byte to specify the fourth source, which in this case is memory.
569   MRMSrcMemOp4 = 27,
570   /// MRMSrcMemCC - This form is used for instructions that use the Mod/RM
571   /// byte to specify the operands and also encodes a condition code.
572   MRMSrcMemCC = 28,
573   /// MRMXm - This form is used for instructions that use the Mod/RM byte
574   /// to specify a memory source, but doesn't use the middle field. And has
575   /// a condition code.
576   MRMXmCC = 30,
577   /// MRMXm - This form is used for instructions that use the Mod/RM byte
578   /// to specify a memory source, but doesn't use the middle field.
579   MRMXm = 31,
580   /// MRM0m-MRM7m - Instructions that operate on a memory r/m operand and use
581   /// reg field to hold extended opcode, which is represented as /0, /1, ...
582   MRM0m = 32, // Format /0
583   MRM1m = 33, // Format /1
584   MRM2m = 34, // Format /2
585   MRM3m = 35, // Format /3
586   MRM4m = 36, // Format /4
587   MRM5m = 37, // Format /5
588   MRM6m = 38, // Format /6
589   MRM7m = 39, // Format /7
590   /// MRMDestReg - This form is used for instructions that use the Mod/RM byte
591   /// to specify a destination, which in this case is a register.
592   MRMDestReg = 40,
593   /// MRMSrcReg - This form is used for instructions that use the Mod/RM byte
594   /// to specify a source, which in this case is a register.
595   MRMSrcReg = 41,
596   /// MRMSrcReg4VOp3 - This form is used for instructions that encode
597   /// operand 3 with VEX.VVVV and do not load from memory.
598   MRMSrcReg4VOp3 = 42,
599   /// MRMSrcRegOp4 - This form is used for instructions that use the Mod/RM
600   /// byte to specify the fourth source, which in this case is a register.
601   MRMSrcRegOp4 = 43,
602   /// MRMSrcRegCC - This form is used for instructions that use the Mod/RM
603   /// byte to specify the operands and also encodes a condition code
604   MRMSrcRegCC = 44,
605   /// MRMXCCr - This form is used for instructions that use the Mod/RM byte
606   /// to specify a register source, but doesn't use the middle field. And has
607   /// a condition code.
608   MRMXrCC = 46,
609   /// MRMXr - This form is used for instructions that use the Mod/RM byte
610   /// to specify a register source, but doesn't use the middle field.
611   MRMXr = 47,
612   /// MRM0r-MRM7r - Instructions that operate on a register r/m operand and use
613   /// reg field to hold extended opcode, which is represented as /0, /1, ...
614   MRM0r = 48, // Format /0
615   MRM1r = 49, // Format /1
616   MRM2r = 50, // Format /2
617   MRM3r = 51, // Format /3
618   MRM4r = 52, // Format /4
619   MRM5r = 53, // Format /5
620   MRM6r = 54, // Format /6
621   MRM7r = 55, // Format /7
622   /// MRM0X-MRM7X - Instructions that operate that have mod=11 and an opcode but
623   /// ignore r/m.
624   MRM0X = 56, // Format /0
625   MRM1X = 57, // Format /1
626   MRM2X = 58, // Format /2
627   MRM3X = 59, // Format /3
628   MRM4X = 60, // Format /4
629   MRM5X = 61, // Format /5
630   MRM6X = 62, // Format /6
631   MRM7X = 63, // Format /7
632   /// MRM_XX (XX: C0-FF)- A mod/rm byte of exactly 0xXX.
633   MRM_C0 = 64,
634   MRM_C1 = 65,
635   MRM_C2 = 66,
636   MRM_C3 = 67,
637   MRM_C4 = 68,
638   MRM_C5 = 69,
639   MRM_C6 = 70,
640   MRM_C7 = 71,
641   MRM_C8 = 72,
642   MRM_C9 = 73,
643   MRM_CA = 74,
644   MRM_CB = 75,
645   MRM_CC = 76,
646   MRM_CD = 77,
647   MRM_CE = 78,
648   MRM_CF = 79,
649   MRM_D0 = 80,
650   MRM_D1 = 81,
651   MRM_D2 = 82,
652   MRM_D3 = 83,
653   MRM_D4 = 84,
654   MRM_D5 = 85,
655   MRM_D6 = 86,
656   MRM_D7 = 87,
657   MRM_D8 = 88,
658   MRM_D9 = 89,
659   MRM_DA = 90,
660   MRM_DB = 91,
661   MRM_DC = 92,
662   MRM_DD = 93,
663   MRM_DE = 94,
664   MRM_DF = 95,
665   MRM_E0 = 96,
666   MRM_E1 = 97,
667   MRM_E2 = 98,
668   MRM_E3 = 99,
669   MRM_E4 = 100,
670   MRM_E5 = 101,
671   MRM_E6 = 102,
672   MRM_E7 = 103,
673   MRM_E8 = 104,
674   MRM_E9 = 105,
675   MRM_EA = 106,
676   MRM_EB = 107,
677   MRM_EC = 108,
678   MRM_ED = 109,
679   MRM_EE = 110,
680   MRM_EF = 111,
681   MRM_F0 = 112,
682   MRM_F1 = 113,
683   MRM_F2 = 114,
684   MRM_F3 = 115,
685   MRM_F4 = 116,
686   MRM_F5 = 117,
687   MRM_F6 = 118,
688   MRM_F7 = 119,
689   MRM_F8 = 120,
690   MRM_F9 = 121,
691   MRM_FA = 122,
692   MRM_FB = 123,
693   MRM_FC = 124,
694   MRM_FD = 125,
695   MRM_FE = 126,
696   MRM_FF = 127,
697   FormMask = 127,
698   //===------------------------------------------------------------------===//
699   // Actual flags...
700   /// OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
701   /// OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
702   /// 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
703   /// prefix in 16-bit mode.
704   OpSizeShift = 7,
705   OpSizeMask = 0x3 << OpSizeShift,
706   OpSizeFixed = 0 << OpSizeShift,
707   OpSize16 = 1 << OpSizeShift,
708   OpSize32 = 2 << OpSizeShift,
709   /// AsSize - AdSizeX implies this instruction determines its need of 0x67
710   /// prefix from a normal ModRM memory operand. The other types indicate that
711   /// an operand is encoded with a specific width and a prefix is needed if
712   /// it differs from the current mode.
713   AdSizeShift = OpSizeShift + 2,
714   AdSizeMask = 0x3 << AdSizeShift,
715   AdSizeX = 0 << AdSizeShift,
716   AdSize16 = 1 << AdSizeShift,
717   AdSize32 = 2 << AdSizeShift,
718   AdSize64 = 3 << AdSizeShift,
719   //===------------------------------------------------------------------===//
720   /// OpPrefix - There are several prefix bytes that are used as opcode
721   /// extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
722   /// no prefix.
723   OpPrefixShift = AdSizeShift + 2,
724   OpPrefixMask = 0x3 << OpPrefixShift,
725   /// PD - Prefix code for packed double precision vector floating point
726   /// operations performed in the SSE registers.
727   PD = 1 << OpPrefixShift,
728   /// XS, XD - These prefix codes are for single and double precision scalar
729   /// floating point operations performed in the SSE registers.
730   XS = 2 << OpPrefixShift,
731   XD = 3 << OpPrefixShift,
732   //===------------------------------------------------------------------===//
733   /// OpMap - This field determines which opcode map this instruction
734   /// belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
735   OpMapShift = OpPrefixShift + 2,
736   OpMapMask = 0xF << OpMapShift,
737   /// OB - OneByte - Set if this instruction has a one byte opcode.
738   OB = 0 << OpMapShift,
739   /// TB - TwoByte - Set if this instruction has a two byte opcode, which
740   /// starts with a 0x0F byte before the real opcode.
741   TB = 1 << OpMapShift,
742   /// T8, TA - Prefix after the 0x0F prefix.
743   T8 = 2 << OpMapShift,
744   TA = 3 << OpMapShift,
745   /// XOP8 - Prefix to include use of imm byte.
746   XOP8 = 4 << OpMapShift,
747   /// XOP9 - Prefix to exclude use of imm byte.
748   XOP9 = 5 << OpMapShift,
749   /// XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
750   XOPA = 6 << OpMapShift,
751   /// ThreeDNow - This indicates that the instruction uses the
752   /// wacky 0x0F 0x0F prefix for 3DNow! instructions.  The manual documents
753   /// this as having a 0x0F prefix with a 0x0F opcode, and each instruction
754   /// storing a classifier in the imm8 field.  To simplify our implementation,
755   /// we handle this by storeing the classifier in the opcode field and using
756   /// this flag to indicate that the encoder should do the wacky 3DNow! thing.
757   ThreeDNow = 7 << OpMapShift,
758   /// MAP4, MAP5, MAP6, MAP7 - Prefix after the 0x0F prefix.
759   T_MAP4 = 8 << OpMapShift,
760   T_MAP5 = 9 << OpMapShift,
761   T_MAP6 = 10 << OpMapShift,
762   T_MAP7 = 11 << OpMapShift,
763   //===------------------------------------------------------------------===//
764   /// REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
765   /// They are used to specify GPRs and SSE registers, 64-bit operand size,
766   /// etc. We only cares about REX.W and REX.R bits and only the former is
767   /// statically determined.
768   REXShift = OpMapShift + 4,
769   REX_W = 1 << REXShift,
770   //===------------------------------------------------------------------===//
771   // This 4-bit field describes the size of an immediate operand. Zero is
772   // unused so that we can tell if we forgot to set a value.
773   ImmShift = REXShift + 1,
774   Imm8 = 1 << ImmShift,
775   Imm8PCRel = 2 << ImmShift,
776   Imm8Reg = 3 << ImmShift,
777   Imm16 = 4 << ImmShift,
778   Imm16PCRel = 5 << ImmShift,
779   Imm32 = 6 << ImmShift,
780   Imm32PCRel = 7 << ImmShift,
781   Imm32S = 8 << ImmShift,
782   Imm64 = 9 << ImmShift,
783   ImmMask = 15 << ImmShift,
784   //===------------------------------------------------------------------===//
785   /// FP Instruction Classification...  Zero is non-fp instruction.
786   /// FPTypeMask - Mask for all of the FP types...
787   FPTypeShift = ImmShift + 4,
788   FPTypeMask = 7 << FPTypeShift,
789   /// NotFP - The default, set for instructions that do not use FP registers.
790   NotFP = 0 << FPTypeShift,
791   /// ZeroArgFP - 0 arg FP instruction which implicitly pushes ST(0), f.e. fld0
792   ZeroArgFP = 1 << FPTypeShift,
793   /// OneArgFP - 1 arg FP instructions which implicitly read ST(0), such as fst
794   OneArgFP = 2 << FPTypeShift,
795   /// OneArgFPRW - 1 arg FP instruction which implicitly read ST(0) and write a
796   /// result back to ST(0).  For example, fcos, fsqrt, etc.
797   OneArgFPRW = 3 << FPTypeShift,
798   /// TwoArgFP - 2 arg FP instructions which implicitly read ST(0), and an
799   /// explicit argument, storing the result to either ST(0) or the implicit
800   /// argument.  For example: fadd, fsub, fmul, etc...
801   TwoArgFP = 4 << FPTypeShift,
802   /// CompareFP - 2 arg FP instructions which implicitly read ST(0) and an
803   /// explicit argument, but have no destination.  Example: fucom, fucomi, ...
804   CompareFP = 5 << FPTypeShift,
805   /// CondMovFP - "2 operand" floating point conditional move instructions.
806   CondMovFP = 6 << FPTypeShift,
807   /// SpecialFP - Special instruction forms.  Dispatch by opcode explicitly.
808   SpecialFP = 7 << FPTypeShift,
809   /// Lock prefix
810   LOCKShift = FPTypeShift + 3,
811   LOCK = 1 << LOCKShift,
812   /// REP prefix
813   REPShift = LOCKShift + 1,
814   REP = 1 << REPShift,
815   /// Execution domain for SSE instructions.
816   /// 0 means normal, non-SSE instruction.
817   SSEDomainShift = REPShift + 1,
818   /// Encoding
819   EncodingShift = SSEDomainShift + 2,
820   EncodingMask = 0x3 << EncodingShift,
821   /// LEGACY - encoding using REX/REX2 or w/o opcode prefix.
822   LEGACY = 0 << EncodingShift,
823   /// VEX - encoding using 0xC4/0xC5
824   VEX = 1 << EncodingShift,
825   /// XOP - Opcode prefix used by XOP instructions.
826   XOP = 2 << EncodingShift,
827   /// EVEX - Specifies that this instruction use EVEX form which provides
828   /// syntax support up to 32 512-bit register operands and up to 7 16-bit
829   /// mask operands as well as source operand data swizzling/memory operand
830   /// conversion, eviction hint, and rounding mode.
831   EVEX = 3 << EncodingShift,
832   /// Opcode
833   OpcodeShift = EncodingShift + 2,
834   /// VEX_4V - Used to specify an additional AVX/SSE register. Several 2
835   /// address instructions in SSE are represented as 3 address ones in AVX
836   /// and the additional register is encoded in VEX_VVVV prefix.
837   VEX_4VShift = OpcodeShift + 8,
838   VEX_4V = 1ULL << VEX_4VShift,
839   /// VEX_L - Stands for a bit in the VEX opcode prefix meaning the current
840   /// instruction uses 256-bit wide registers. This is usually auto detected
841   /// if a VR256 register is used, but some AVX instructions also have this
842   /// field marked when using a f256 memory references.
843   VEX_LShift = VEX_4VShift + 1,
844   VEX_L = 1ULL << VEX_LShift,
845   /// EVEX_K - Set if this instruction requires masking
846   EVEX_KShift = VEX_LShift + 1,
847   EVEX_K = 1ULL << EVEX_KShift,
848   /// EVEX_Z - Set if this instruction has EVEX.Z field set.
849   EVEX_ZShift = EVEX_KShift + 1,
850   EVEX_Z = 1ULL << EVEX_ZShift,
851   /// EVEX_L2 - Set if this instruction has EVEX.L' field set.
852   EVEX_L2Shift = EVEX_ZShift + 1,
853   EVEX_L2 = 1ULL << EVEX_L2Shift,
854   /// EVEX_B - Set if this instruction has EVEX.B field set.
855   EVEX_BShift = EVEX_L2Shift + 1,
856   EVEX_B = 1ULL << EVEX_BShift,
857   /// The scaling factor for the AVX512's 8-bit compressed displacement.
858   CD8_Scale_Shift = EVEX_BShift + 1,
859   CD8_Scale_Mask = 7ULL << CD8_Scale_Shift,
860   /// Explicitly specified rounding control
861   EVEX_RCShift = CD8_Scale_Shift + 3,
862   EVEX_RC = 1ULL << EVEX_RCShift,
863   /// NOTRACK prefix
864   NoTrackShift = EVEX_RCShift + 1,
865   NOTRACK = 1ULL << NoTrackShift,
866   /// Force REX2/VEX/EVEX encoding
867   ExplicitOpPrefixShift = NoTrackShift + 1,
868   /// For instructions that require REX2 prefix even if EGPR is not used.
869   ExplicitREX2Prefix = 1ULL << ExplicitOpPrefixShift,
870   /// For instructions that use VEX encoding only when {vex}, {vex2} or {vex3}
871   /// is present.
872   ExplicitVEXPrefix = 2ULL << ExplicitOpPrefixShift,
873   /// For instructions that are promoted to EVEX space for EGPR.
874   ExplicitEVEXPrefix = 3ULL << ExplicitOpPrefixShift,
875   ExplicitOpPrefixMask = 3ULL << ExplicitOpPrefixShift,
876   /// EVEX_NF - Set if this instruction has EVEX.NF field set.
877   EVEX_NFShift = ExplicitOpPrefixShift + 2,
878   EVEX_NF = 1ULL << EVEX_NFShift
879 };
880 
881 /// \returns true if the instruction with given opcode is a prefix.
isPrefix(uint64_t TSFlags)882 inline bool isPrefix(uint64_t TSFlags) {
883   return (TSFlags & X86II::FormMask) == PrefixByte;
884 }
885 
886 /// \returns true if the instruction with given opcode is a pseudo.
isPseudo(uint64_t TSFlags)887 inline bool isPseudo(uint64_t TSFlags) {
888   return (TSFlags & X86II::FormMask) == Pseudo;
889 }
890 
891 /// \returns the "base" X86 opcode for the specified machine
892 /// instruction.
getBaseOpcodeFor(uint64_t TSFlags)893 inline uint8_t getBaseOpcodeFor(uint64_t TSFlags) {
894   return TSFlags >> X86II::OpcodeShift;
895 }
896 
hasImm(uint64_t TSFlags)897 inline bool hasImm(uint64_t TSFlags) { return (TSFlags & X86II::ImmMask) != 0; }
898 
899 /// Decode the "size of immediate" field from the TSFlags field of the
900 /// specified instruction.
getSizeOfImm(uint64_t TSFlags)901 inline unsigned getSizeOfImm(uint64_t TSFlags) {
902   switch (TSFlags & X86II::ImmMask) {
903   default:
904     llvm_unreachable("Unknown immediate size");
905   case X86II::Imm8:
906   case X86II::Imm8PCRel:
907   case X86II::Imm8Reg:
908     return 1;
909   case X86II::Imm16:
910   case X86II::Imm16PCRel:
911     return 2;
912   case X86II::Imm32:
913   case X86II::Imm32S:
914   case X86II::Imm32PCRel:
915     return 4;
916   case X86II::Imm64:
917     return 8;
918   }
919 }
920 
921 /// \returns true if the immediate of the specified instruction's TSFlags
922 /// indicates that it is pc relative.
isImmPCRel(uint64_t TSFlags)923 inline bool isImmPCRel(uint64_t TSFlags) {
924   switch (TSFlags & X86II::ImmMask) {
925   default:
926     llvm_unreachable("Unknown immediate size");
927   case X86II::Imm8PCRel:
928   case X86II::Imm16PCRel:
929   case X86II::Imm32PCRel:
930     return true;
931   case X86II::Imm8:
932   case X86II::Imm8Reg:
933   case X86II::Imm16:
934   case X86II::Imm32:
935   case X86II::Imm32S:
936   case X86II::Imm64:
937     return false;
938   }
939 }
940 
941 /// \returns true if the immediate of the specified instruction's
942 /// TSFlags indicates that it is signed.
isImmSigned(uint64_t TSFlags)943 inline bool isImmSigned(uint64_t TSFlags) {
944   switch (TSFlags & X86II::ImmMask) {
945   default:
946     llvm_unreachable("Unknown immediate signedness");
947   case X86II::Imm32S:
948     return true;
949   case X86II::Imm8:
950   case X86II::Imm8PCRel:
951   case X86II::Imm8Reg:
952   case X86II::Imm16:
953   case X86II::Imm16PCRel:
954   case X86II::Imm32:
955   case X86II::Imm32PCRel:
956   case X86II::Imm64:
957     return false;
958   }
959 }
960 
961 /// Compute whether all of the def operands are repeated in the uses and
962 /// therefore should be skipped.
963 /// This determines the start of the unique operand list. We need to determine
964 /// if all of the defs have a corresponding tied operand in the uses.
965 /// Unfortunately, the tied operand information is encoded in the uses not
966 /// the defs so we have to use some heuristics to find which operands to
967 /// query.
getOperandBias(const MCInstrDesc & Desc)968 inline unsigned getOperandBias(const MCInstrDesc &Desc) {
969   unsigned NumDefs = Desc.getNumDefs();
970   unsigned NumOps = Desc.getNumOperands();
971   switch (NumDefs) {
972   default:
973     llvm_unreachable("Unexpected number of defs");
974   case 0:
975     return 0;
976   case 1:
977     // Common two addr case.
978     if (NumOps > 1 && Desc.getOperandConstraint(1, MCOI::TIED_TO) == 0)
979       return 1;
980     // Check for AVX-512 scatter which has a TIED_TO in the second to last
981     // operand.
982     if (NumOps == 8 && Desc.getOperandConstraint(6, MCOI::TIED_TO) == 0)
983       return 1;
984     return 0;
985   case 2:
986     // XCHG/XADD have two destinations and two sources.
987     if (NumOps >= 4 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
988         Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1)
989       return 2;
990     // Check for gather. AVX-512 has the second tied operand early. AVX2
991     // has it as the last op.
992     if (NumOps == 9 && Desc.getOperandConstraint(2, MCOI::TIED_TO) == 0 &&
993         (Desc.getOperandConstraint(3, MCOI::TIED_TO) == 1 ||
994          Desc.getOperandConstraint(8, MCOI::TIED_TO) == 1))
995       return 2;
996     return 0;
997   }
998 }
999 
1000 /// \returns true if the instruction has a NDD (new data destination).
hasNewDataDest(uint64_t TSFlags)1001 inline bool hasNewDataDest(uint64_t TSFlags) {
1002   return (TSFlags & X86II::OpMapMask) == X86II::T_MAP4 &&
1003          (TSFlags & X86II::EVEX_B) && (TSFlags & X86II::VEX_4V);
1004 }
1005 
1006 /// \returns operand # for the first field of the memory operand or -1 if no
1007 /// memory operands.
1008 /// NOTE: This ignores tied operands.  If there is a tied register which is
1009 /// duplicated in the MCInst (e.g. "EAX = addl EAX, [mem]") it is only counted
1010 /// as one operand.
getMemoryOperandNo(uint64_t TSFlags)1011 inline int getMemoryOperandNo(uint64_t TSFlags) {
1012   bool HasVEX_4V = TSFlags & X86II::VEX_4V;
1013   bool HasEVEX_K = TSFlags & X86II::EVEX_K;
1014 
1015   switch (TSFlags & X86II::FormMask) {
1016   default:
1017     llvm_unreachable("Unknown FormMask value in getMemoryOperandNo!");
1018   case X86II::Pseudo:
1019   case X86II::RawFrm:
1020   case X86II::AddRegFrm:
1021   case X86II::RawFrmImm8:
1022   case X86II::RawFrmImm16:
1023   case X86II::RawFrmMemOffs:
1024   case X86II::RawFrmSrc:
1025   case X86II::RawFrmDst:
1026   case X86II::RawFrmDstSrc:
1027   case X86II::AddCCFrm:
1028   case X86II::PrefixByte:
1029     return -1;
1030   case X86II::MRMDestMem:
1031   case X86II::MRMDestMemFSIB:
1032     return hasNewDataDest(TSFlags);
1033   case X86II::MRMSrcMem:
1034   case X86II::MRMSrcMemFSIB:
1035     // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
1036     // mask register.
1037     return 1 + HasVEX_4V + HasEVEX_K;
1038   case X86II::MRMSrcMem4VOp3:
1039     // Skip registers encoded in reg.
1040     return 1 + HasEVEX_K;
1041   case X86II::MRMSrcMemOp4:
1042     // Skip registers encoded in reg, VEX_VVVV, and I8IMM.
1043     return 3;
1044   case X86II::MRMSrcMemCC:
1045   case X86II::MRMDestMem4VOp3CC:
1046     // Start from 1, skip any registers encoded in VEX_VVVV or I8IMM, or a
1047     // mask register.
1048     return 1;
1049   case X86II::MRMDestReg:
1050   case X86II::MRMSrcReg:
1051   case X86II::MRMSrcReg4VOp3:
1052   case X86II::MRMSrcRegOp4:
1053   case X86II::MRMSrcRegCC:
1054   case X86II::MRMXrCC:
1055   case X86II::MRMr0:
1056   case X86II::MRMXr:
1057   case X86II::MRM0r:
1058   case X86II::MRM1r:
1059   case X86II::MRM2r:
1060   case X86II::MRM3r:
1061   case X86II::MRM4r:
1062   case X86II::MRM5r:
1063   case X86II::MRM6r:
1064   case X86II::MRM7r:
1065     return -1;
1066   case X86II::MRM0X:
1067   case X86II::MRM1X:
1068   case X86II::MRM2X:
1069   case X86II::MRM3X:
1070   case X86II::MRM4X:
1071   case X86II::MRM5X:
1072   case X86II::MRM6X:
1073   case X86II::MRM7X:
1074     return -1;
1075   case X86II::MRMXmCC:
1076   case X86II::MRMXm:
1077   case X86II::MRM0m:
1078   case X86II::MRM1m:
1079   case X86II::MRM2m:
1080   case X86II::MRM3m:
1081   case X86II::MRM4m:
1082   case X86II::MRM5m:
1083   case X86II::MRM6m:
1084   case X86II::MRM7m:
1085     // Start from 0, skip registers encoded in VEX_VVVV or a mask register.
1086     return 0 + HasVEX_4V + HasEVEX_K;
1087   case X86II::MRM_C0:
1088   case X86II::MRM_C1:
1089   case X86II::MRM_C2:
1090   case X86II::MRM_C3:
1091   case X86II::MRM_C4:
1092   case X86II::MRM_C5:
1093   case X86II::MRM_C6:
1094   case X86II::MRM_C7:
1095   case X86II::MRM_C8:
1096   case X86II::MRM_C9:
1097   case X86II::MRM_CA:
1098   case X86II::MRM_CB:
1099   case X86II::MRM_CC:
1100   case X86II::MRM_CD:
1101   case X86II::MRM_CE:
1102   case X86II::MRM_CF:
1103   case X86II::MRM_D0:
1104   case X86II::MRM_D1:
1105   case X86II::MRM_D2:
1106   case X86II::MRM_D3:
1107   case X86II::MRM_D4:
1108   case X86II::MRM_D5:
1109   case X86II::MRM_D6:
1110   case X86II::MRM_D7:
1111   case X86II::MRM_D8:
1112   case X86II::MRM_D9:
1113   case X86II::MRM_DA:
1114   case X86II::MRM_DB:
1115   case X86II::MRM_DC:
1116   case X86II::MRM_DD:
1117   case X86II::MRM_DE:
1118   case X86II::MRM_DF:
1119   case X86II::MRM_E0:
1120   case X86II::MRM_E1:
1121   case X86II::MRM_E2:
1122   case X86II::MRM_E3:
1123   case X86II::MRM_E4:
1124   case X86II::MRM_E5:
1125   case X86II::MRM_E6:
1126   case X86II::MRM_E7:
1127   case X86II::MRM_E8:
1128   case X86II::MRM_E9:
1129   case X86II::MRM_EA:
1130   case X86II::MRM_EB:
1131   case X86II::MRM_EC:
1132   case X86II::MRM_ED:
1133   case X86II::MRM_EE:
1134   case X86II::MRM_EF:
1135   case X86II::MRM_F0:
1136   case X86II::MRM_F1:
1137   case X86II::MRM_F2:
1138   case X86II::MRM_F3:
1139   case X86II::MRM_F4:
1140   case X86II::MRM_F5:
1141   case X86II::MRM_F6:
1142   case X86II::MRM_F7:
1143   case X86II::MRM_F8:
1144   case X86II::MRM_F9:
1145   case X86II::MRM_FA:
1146   case X86II::MRM_FB:
1147   case X86II::MRM_FC:
1148   case X86II::MRM_FD:
1149   case X86II::MRM_FE:
1150   case X86II::MRM_FF:
1151     return -1;
1152   }
1153 }
1154 
1155 /// \returns true if the register is a XMM.
isXMMReg(unsigned RegNo)1156 inline bool isXMMReg(unsigned RegNo) {
1157   assert(X86::XMM15 - X86::XMM0 == 15 &&
1158          "XMM0-15 registers are not continuous");
1159   assert(X86::XMM31 - X86::XMM16 == 15 &&
1160          "XMM16-31 registers are not continuous");
1161   return (RegNo >= X86::XMM0 && RegNo <= X86::XMM15) ||
1162          (RegNo >= X86::XMM16 && RegNo <= X86::XMM31);
1163 }
1164 
1165 /// \returns true if the register is a YMM.
isYMMReg(unsigned RegNo)1166 inline bool isYMMReg(unsigned RegNo) {
1167   assert(X86::YMM15 - X86::YMM0 == 15 &&
1168          "YMM0-15 registers are not continuous");
1169   assert(X86::YMM31 - X86::YMM16 == 15 &&
1170          "YMM16-31 registers are not continuous");
1171   return (RegNo >= X86::YMM0 && RegNo <= X86::YMM15) ||
1172          (RegNo >= X86::YMM16 && RegNo <= X86::YMM31);
1173 }
1174 
1175 /// \returns true if the register is a ZMM.
isZMMReg(unsigned RegNo)1176 inline bool isZMMReg(unsigned RegNo) {
1177   assert(X86::ZMM31 - X86::ZMM0 == 31 && "ZMM registers are not continuous");
1178   return RegNo >= X86::ZMM0 && RegNo <= X86::ZMM31;
1179 }
1180 
1181 /// \returns true if \p RegNo is an apx extended register.
isApxExtendedReg(unsigned RegNo)1182 inline bool isApxExtendedReg(unsigned RegNo) {
1183   assert(X86::R31WH - X86::R16 == 95 && "EGPRs are not continuous");
1184   return RegNo >= X86::R16 && RegNo <= X86::R31WH;
1185 }
1186 
1187 /// \returns true if the MachineOperand is a x86-64 extended (r8 or
1188 /// higher) register,  e.g. r8, xmm8, xmm13, etc.
isX86_64ExtendedReg(unsigned RegNo)1189 inline bool isX86_64ExtendedReg(unsigned RegNo) {
1190   if ((RegNo >= X86::XMM8 && RegNo <= X86::XMM15) ||
1191       (RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
1192       (RegNo >= X86::YMM8 && RegNo <= X86::YMM15) ||
1193       (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
1194       (RegNo >= X86::ZMM8 && RegNo <= X86::ZMM31))
1195     return true;
1196 
1197   if (isApxExtendedReg(RegNo))
1198     return true;
1199 
1200   switch (RegNo) {
1201   default:
1202     break;
1203   case X86::R8:
1204   case X86::R9:
1205   case X86::R10:
1206   case X86::R11:
1207   case X86::R12:
1208   case X86::R13:
1209   case X86::R14:
1210   case X86::R15:
1211   case X86::R8D:
1212   case X86::R9D:
1213   case X86::R10D:
1214   case X86::R11D:
1215   case X86::R12D:
1216   case X86::R13D:
1217   case X86::R14D:
1218   case X86::R15D:
1219   case X86::R8W:
1220   case X86::R9W:
1221   case X86::R10W:
1222   case X86::R11W:
1223   case X86::R12W:
1224   case X86::R13W:
1225   case X86::R14W:
1226   case X86::R15W:
1227   case X86::R8B:
1228   case X86::R9B:
1229   case X86::R10B:
1230   case X86::R11B:
1231   case X86::R12B:
1232   case X86::R13B:
1233   case X86::R14B:
1234   case X86::R15B:
1235   case X86::CR8:
1236   case X86::CR9:
1237   case X86::CR10:
1238   case X86::CR11:
1239   case X86::CR12:
1240   case X86::CR13:
1241   case X86::CR14:
1242   case X86::CR15:
1243   case X86::DR8:
1244   case X86::DR9:
1245   case X86::DR10:
1246   case X86::DR11:
1247   case X86::DR12:
1248   case X86::DR13:
1249   case X86::DR14:
1250   case X86::DR15:
1251     return true;
1252   }
1253   return false;
1254 }
1255 
canUseApxExtendedReg(const MCInstrDesc & Desc)1256 inline bool canUseApxExtendedReg(const MCInstrDesc &Desc) {
1257   uint64_t TSFlags = Desc.TSFlags;
1258   uint64_t Encoding = TSFlags & EncodingMask;
1259   // EVEX can always use egpr.
1260   if (Encoding == X86II::EVEX)
1261     return true;
1262 
1263   unsigned Opcode = Desc.Opcode;
1264   // MOV32r0 is always expanded to XOR32rr
1265   if (Opcode == X86::MOV32r0)
1266     return true;
1267   // To be conservative, egpr is not used for all pseudo instructions
1268   // because we are not sure what instruction it will become.
1269   // FIXME: Could we improve it in X86ExpandPseudo?
1270   if (isPseudo(TSFlags))
1271     return false;
1272 
1273   // MAP OB/TB in legacy encoding space can always use egpr except
1274   // XSAVE*/XRSTOR*.
1275   switch (Opcode) {
1276   default:
1277     break;
1278   case X86::XSAVE:
1279   case X86::XSAVE64:
1280   case X86::XSAVEOPT:
1281   case X86::XSAVEOPT64:
1282   case X86::XSAVEC:
1283   case X86::XSAVEC64:
1284   case X86::XSAVES:
1285   case X86::XSAVES64:
1286   case X86::XRSTOR:
1287   case X86::XRSTOR64:
1288   case X86::XRSTORS:
1289   case X86::XRSTORS64:
1290     return false;
1291   }
1292   uint64_t OpMap = TSFlags & X86II::OpMapMask;
1293   return !Encoding && (OpMap == X86II::OB || OpMap == X86II::TB);
1294 }
1295 
1296 /// \returns true if the MemoryOperand is a 32 extended (zmm16 or higher)
1297 /// registers, e.g. zmm21, etc.
is32ExtendedReg(unsigned RegNo)1298 static inline bool is32ExtendedReg(unsigned RegNo) {
1299   return ((RegNo >= X86::XMM16 && RegNo <= X86::XMM31) ||
1300           (RegNo >= X86::YMM16 && RegNo <= X86::YMM31) ||
1301           (RegNo >= X86::ZMM16 && RegNo <= X86::ZMM31));
1302 }
1303 
isX86_64NonExtLowByteReg(unsigned reg)1304 inline bool isX86_64NonExtLowByteReg(unsigned reg) {
1305   return (reg == X86::SPL || reg == X86::BPL || reg == X86::SIL ||
1306           reg == X86::DIL);
1307 }
1308 
1309 /// \returns true if this is a masked instruction.
isKMasked(uint64_t TSFlags)1310 inline bool isKMasked(uint64_t TSFlags) {
1311   return (TSFlags & X86II::EVEX_K) != 0;
1312 }
1313 
1314 /// \returns true if this is a merge masked instruction.
isKMergeMasked(uint64_t TSFlags)1315 inline bool isKMergeMasked(uint64_t TSFlags) {
1316   return isKMasked(TSFlags) && (TSFlags & X86II::EVEX_Z) == 0;
1317 }
1318 } // namespace X86II
1319 } // namespace llvm
1320 #endif
1321