1 /* $NetBSD: bios_parser_types.h,v 1.2 2021/12/18 23:45:07 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef __DAL_BIOS_PARSER_TYPES_H__ 29 30 #define __DAL_BIOS_PARSER_TYPES_H__ 31 32 #include "dm_services.h" 33 #include "include/signal_types.h" 34 #include "include/grph_object_ctrl_defs.h" 35 #include "include/gpio_types.h" 36 #include "include/link_service_types.h" 37 38 /* TODO: include signal_types.h and remove this enum */ 39 enum as_signal_type { 40 AS_SIGNAL_TYPE_NONE = 0L, /* no signal */ 41 AS_SIGNAL_TYPE_DVI, 42 AS_SIGNAL_TYPE_HDMI, 43 AS_SIGNAL_TYPE_LVDS, 44 AS_SIGNAL_TYPE_DISPLAY_PORT, 45 AS_SIGNAL_TYPE_GPU_PLL, 46 AS_SIGNAL_TYPE_XGMI, 47 AS_SIGNAL_TYPE_UNKNOWN 48 }; 49 50 enum bp_result { 51 BP_RESULT_OK = 0, /* There was no error */ 52 BP_RESULT_BADINPUT, /*Bad input parameter */ 53 BP_RESULT_BADBIOSTABLE, /* Bad BIOS table */ 54 BP_RESULT_UNSUPPORTED, /* BIOS Table is not supported */ 55 BP_RESULT_NORECORD, /* Record can't be found */ 56 BP_RESULT_FAILURE 57 }; 58 59 enum bp_encoder_control_action { 60 /* direct VBIOS translation! Just to simplify the translation */ 61 ENCODER_CONTROL_DISABLE = 0, 62 ENCODER_CONTROL_ENABLE, 63 ENCODER_CONTROL_SETUP, 64 ENCODER_CONTROL_INIT 65 }; 66 67 enum bp_transmitter_control_action { 68 /* direct VBIOS translation! Just to simplify the translation */ 69 TRANSMITTER_CONTROL_DISABLE = 0, 70 TRANSMITTER_CONTROL_ENABLE, 71 TRANSMITTER_CONTROL_BACKLIGHT_OFF, 72 TRANSMITTER_CONTROL_BACKLIGHT_ON, 73 TRANSMITTER_CONTROL_BACKLIGHT_BRIGHTNESS, 74 TRANSMITTER_CONTROL_LCD_SETF_TEST_START, 75 TRANSMITTER_CONTROL_LCD_SELF_TEST_STOP, 76 TRANSMITTER_CONTROL_INIT, 77 TRANSMITTER_CONTROL_DEACTIVATE, 78 TRANSMITTER_CONTROL_ACTIAVATE, 79 TRANSMITTER_CONTROL_SETUP, 80 TRANSMITTER_CONTROL_SET_VOLTAGE_AND_PREEMPASIS, 81 /* ATOM_TRANSMITTER_ACTION_POWER_ON. This action is for eDP only 82 * (power up the panel) 83 */ 84 TRANSMITTER_CONTROL_POWER_ON, 85 /* ATOM_TRANSMITTER_ACTION_POWER_OFF. This action is for eDP only 86 * (power down the panel) 87 */ 88 TRANSMITTER_CONTROL_POWER_OFF 89 }; 90 91 enum bp_external_encoder_control_action { 92 EXTERNAL_ENCODER_CONTROL_DISABLE = 0, 93 EXTERNAL_ENCODER_CONTROL_ENABLE = 1, 94 EXTERNAL_ENCODER_CONTROL_INIT = 0x7, 95 EXTERNAL_ENCODER_CONTROL_SETUP = 0xf, 96 EXTERNAL_ENCODER_CONTROL_UNBLANK = 0x10, 97 EXTERNAL_ENCODER_CONTROL_BLANK = 0x11, 98 }; 99 100 enum bp_pipe_control_action { 101 ASIC_PIPE_DISABLE = 0, 102 ASIC_PIPE_ENABLE, 103 ASIC_PIPE_INIT 104 }; 105 106 struct bp_encoder_control { 107 enum bp_encoder_control_action action; 108 enum engine_id engine_id; 109 enum transmitter transmitter; 110 enum signal_type signal; 111 enum dc_lane_count lanes_number; 112 enum dc_color_depth color_depth; 113 bool enable_dp_audio; 114 uint32_t pixel_clock; /* khz */ 115 }; 116 117 struct bp_external_encoder_control { 118 enum bp_external_encoder_control_action action; 119 enum engine_id engine_id; 120 enum dc_link_rate link_rate; 121 enum dc_lane_count lanes_number; 122 enum signal_type signal; 123 enum dc_color_depth color_depth; 124 bool coherent; 125 struct graphics_object_id encoder_id; 126 struct graphics_object_id connector_obj_id; 127 uint32_t pixel_clock; /* in KHz */ 128 }; 129 130 struct bp_crtc_source_select { 131 enum engine_id engine_id; 132 enum controller_id controller_id; 133 /* from GPU Tx aka asic_signal */ 134 enum signal_type signal; 135 /* sink_signal may differ from asicSignal if Translator encoder */ 136 enum signal_type sink_signal; 137 enum display_output_bit_depth display_output_bit_depth; 138 bool enable_dp_audio; 139 }; 140 141 struct bp_transmitter_control { 142 enum bp_transmitter_control_action action; 143 enum engine_id engine_id; 144 enum transmitter transmitter; /* PhyId */ 145 enum dc_lane_count lanes_number; 146 enum clock_source_id pll_id; /* needed for DCE 4.0 */ 147 enum signal_type signal; 148 enum dc_color_depth color_depth; /* not used for DCE6.0 */ 149 enum hpd_source_id hpd_sel; /* ucHPDSel, used for DCe6.0 */ 150 struct graphics_object_id connector_obj_id; 151 /* symClock; in 10kHz, pixel clock, in HDMI deep color mode, it should 152 * be pixel clock * deep_color_ratio (in KHz) 153 */ 154 uint32_t pixel_clock; 155 uint32_t lane_select; 156 uint32_t lane_settings; 157 bool coherent; 158 bool multi_path; 159 bool single_pll_mode; 160 }; 161 162 struct bp_hw_crtc_timing_parameters { 163 enum controller_id controller_id; 164 /* horizontal part */ 165 uint32_t h_total; 166 uint32_t h_addressable; 167 uint32_t h_overscan_left; 168 uint32_t h_overscan_right; 169 uint32_t h_sync_start; 170 uint32_t h_sync_width; 171 172 /* vertical part */ 173 uint32_t v_total; 174 uint32_t v_addressable; 175 uint32_t v_overscan_top; 176 uint32_t v_overscan_bottom; 177 uint32_t v_sync_start; 178 uint32_t v_sync_width; 179 180 struct timing_flags { 181 uint32_t INTERLACE:1; 182 uint32_t PIXEL_REPETITION:4; 183 uint32_t HSYNC_POSITIVE_POLARITY:1; 184 uint32_t VSYNC_POSITIVE_POLARITY:1; 185 uint32_t HORZ_COUNT_BY_TWO:1; 186 } flags; 187 }; 188 189 struct bp_adjust_pixel_clock_parameters { 190 /* Input: Signal Type - to be converted to Encoder mode */ 191 enum signal_type signal_type; 192 /* Input: Encoder object id */ 193 struct graphics_object_id encoder_object_id; 194 /* Input: Pixel Clock (requested Pixel clock based on Video timing 195 * standard used) in KHz 196 */ 197 uint32_t pixel_clock; 198 /* Output: Adjusted Pixel Clock (after VBIOS exec table) in KHz */ 199 uint32_t adjusted_pixel_clock; 200 /* Output: If non-zero, this refDiv value should be used to calculate 201 * other ppll params */ 202 uint32_t reference_divider; 203 /* Output: If non-zero, this postDiv value should be used to calculate 204 * other ppll params */ 205 uint32_t pixel_clock_post_divider; 206 /* Input: Enable spread spectrum */ 207 bool ss_enable; 208 }; 209 210 struct bp_pixel_clock_parameters { 211 enum controller_id controller_id; /* (Which CRTC uses this PLL) */ 212 enum clock_source_id pll_id; /* Clock Source Id */ 213 /* signal_type -> Encoder Mode - needed by VBIOS Exec table */ 214 enum signal_type signal_type; 215 /* Adjusted Pixel Clock (after VBIOS exec table) 216 * that becomes Target Pixel Clock (100 Hz units) */ 217 uint32_t target_pixel_clock_100hz; 218 /* Calculated Reference divider of Display PLL */ 219 uint32_t reference_divider; 220 /* Calculated Feedback divider of Display PLL */ 221 uint32_t feedback_divider; 222 /* Calculated Fractional Feedback divider of Display PLL */ 223 uint32_t fractional_feedback_divider; 224 /* Calculated Pixel Clock Post divider of Display PLL */ 225 uint32_t pixel_clock_post_divider; 226 struct graphics_object_id encoder_object_id; /* Encoder object id */ 227 /* VBIOS returns a fixed display clock when DFS-bypass feature 228 * is enabled (KHz) */ 229 uint32_t dfs_bypass_display_clock; 230 /* color depth to support HDMI deep color */ 231 enum transmitter_color_depth color_depth; 232 233 struct program_pixel_clock_flags { 234 uint32_t FORCE_PROGRAMMING_OF_PLL:1; 235 /* Use Engine Clock as source for Display Clock when 236 * programming PLL */ 237 uint32_t USE_E_CLOCK_AS_SOURCE_FOR_D_CLOCK:1; 238 /* Use external reference clock (refDivSrc for PLL) */ 239 uint32_t SET_EXTERNAL_REF_DIV_SRC:1; 240 /* Use DFS bypass for Display clock. */ 241 uint32_t SET_DISPCLK_DFS_BYPASS:1; 242 /* Force program PHY PLL only */ 243 uint32_t PROGRAM_PHY_PLL_ONLY:1; 244 /* Support for YUV420 */ 245 uint32_t SUPPORT_YUV_420:1; 246 /* Use XTALIN reference clock source */ 247 uint32_t SET_XTALIN_REF_SRC:1; 248 /* Use GENLK reference clock source */ 249 uint32_t SET_GENLOCK_REF_DIV_SRC:1; 250 } flags; 251 }; 252 253 enum bp_dce_clock_type { 254 DCECLOCK_TYPE_DISPLAY_CLOCK = 0, 255 DCECLOCK_TYPE_DPREFCLK = 1 256 }; 257 258 /* DCE Clock Parameters structure for SetDceClock Exec command table */ 259 struct bp_set_dce_clock_parameters { 260 enum clock_source_id pll_id; /* Clock Source Id */ 261 /* Display clock or DPREFCLK value */ 262 uint32_t target_clock_frequency; 263 /* Clock to set: =0: DISPCLK =1: DPREFCLK =2: PIXCLK */ 264 enum bp_dce_clock_type clock_type; 265 266 struct set_dce_clock_flags { 267 uint32_t USE_GENERICA_AS_SOURCE_FOR_DPREFCLK:1; 268 /* Use XTALIN reference clock source */ 269 uint32_t USE_XTALIN_AS_SOURCE_FOR_DPREFCLK:1; 270 /* Use PCIE reference clock source */ 271 uint32_t USE_PCIE_AS_SOURCE_FOR_DPREFCLK:1; 272 /* Use GENLK reference clock source */ 273 uint32_t USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK:1; 274 } flags; 275 }; 276 277 struct spread_spectrum_flags { 278 /* 1 = Center Spread; 0 = down spread */ 279 uint32_t CENTER_SPREAD:1; 280 /* 1 = external; 0 = internal */ 281 uint32_t EXTERNAL_SS:1; 282 /* 1 = delta-sigma type parameter; 0 = ver1 */ 283 uint32_t DS_TYPE:1; 284 }; 285 286 struct bp_spread_spectrum_parameters { 287 enum clock_source_id pll_id; 288 uint32_t percentage; 289 uint32_t ds_frac_amount; 290 291 union { 292 struct { 293 uint32_t step; 294 uint32_t delay; 295 uint32_t range; /* In Hz unit */ 296 } ver1; 297 struct { 298 uint32_t feedback_amount; 299 uint32_t nfrac_amount; 300 uint32_t ds_frac_size; 301 } ds; 302 }; 303 304 struct spread_spectrum_flags flags; 305 }; 306 307 struct bp_encoder_cap_info { 308 uint32_t DP_HBR2_CAP:1; 309 uint32_t DP_HBR2_EN:1; 310 uint32_t DP_HBR3_EN:1; 311 uint32_t HDMI_6GB_EN:1; 312 uint32_t DP_IS_USB_C:1; 313 uint32_t RESERVED:27; 314 }; 315 316 #endif /*__DAL_BIOS_PARSER_TYPES_H__ */ 317