1 /*-
2 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
24 * POSSIBILITY OF SUCH DAMAGE.
25 */
26
27 /*
28 * Driver for the AMD Family 15h and 17h CPU System Management Network.
29 */
30
31 #include <sys/param.h>
32 #include <sys/bus.h>
33 #include <sys/conf.h>
34 #include <sys/lock.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/sysctl.h>
39 #include <sys/systm.h>
40
41 #include <machine/cpufunc.h>
42 #include <machine/cputypes.h>
43 #include <machine/md_var.h>
44 #include <machine/specialreg.h>
45
46 #include <dev/pci/pcivar.h>
47 #include <x86/pci_cfgreg.h>
48
49 #include <dev/amdsmn/amdsmn.h>
50
51 #define F15H_SMN_ADDR_REG 0xb8
52 #define F15H_SMN_DATA_REG 0xbc
53 #define F17H_SMN_ADDR_REG 0x60
54 #define F17H_SMN_DATA_REG 0x64
55
56 #define PCI_DEVICE_ID_AMD_15H_M60H_ROOT 0x1576
57 #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450
58 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0
59 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */
60 #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630
61 #define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4
62 #define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14d8
63
64 struct pciid;
65 struct amdsmn_softc {
66 struct mtx smn_lock;
67 const struct pciid *smn_pciid;
68 };
69
70 static const struct pciid {
71 uint16_t amdsmn_vendorid;
72 uint16_t amdsmn_deviceid;
73 uint8_t amdsmn_addr_reg;
74 uint8_t amdsmn_data_reg;
75 } amdsmn_ids[] = {
76 {
77 .amdsmn_vendorid = CPU_VENDOR_AMD,
78 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_15H_M60H_ROOT,
79 .amdsmn_addr_reg = F15H_SMN_ADDR_REG,
80 .amdsmn_data_reg = F15H_SMN_DATA_REG,
81 },
82 {
83 .amdsmn_vendorid = CPU_VENDOR_AMD,
84 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_ROOT,
85 .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
86 .amdsmn_data_reg = F17H_SMN_DATA_REG,
87 },
88 {
89 .amdsmn_vendorid = CPU_VENDOR_AMD,
90 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_M10H_ROOT,
91 .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
92 .amdsmn_data_reg = F17H_SMN_DATA_REG,
93 },
94 {
95 .amdsmn_vendorid = CPU_VENDOR_AMD,
96 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_M30H_ROOT,
97 .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
98 .amdsmn_data_reg = F17H_SMN_DATA_REG,
99 },
100 {
101 .amdsmn_vendorid = CPU_VENDOR_AMD,
102 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_M60H_ROOT,
103 .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
104 .amdsmn_data_reg = F17H_SMN_DATA_REG,
105 },
106 {
107 .amdsmn_vendorid = CPU_VENDOR_AMD,
108 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M10H_ROOT,
109 .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
110 .amdsmn_data_reg = F17H_SMN_DATA_REG,
111 },
112 {
113 .amdsmn_vendorid = CPU_VENDOR_AMD,
114 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M60H_ROOT,
115 .amdsmn_addr_reg = F17H_SMN_ADDR_REG,
116 .amdsmn_data_reg = F17H_SMN_DATA_REG,
117 },
118 };
119
120 /*
121 * Device methods.
122 */
123 static void amdsmn_identify(driver_t *driver, device_t parent);
124 static int amdsmn_probe(device_t dev);
125 static int amdsmn_attach(device_t dev);
126 static int amdsmn_detach(device_t dev);
127
128 static device_method_t amdsmn_methods[] = {
129 /* Device interface */
130 DEVMETHOD(device_identify, amdsmn_identify),
131 DEVMETHOD(device_probe, amdsmn_probe),
132 DEVMETHOD(device_attach, amdsmn_attach),
133 DEVMETHOD(device_detach, amdsmn_detach),
134 DEVMETHOD_END
135 };
136
137 static driver_t amdsmn_driver = {
138 "amdsmn",
139 amdsmn_methods,
140 sizeof(struct amdsmn_softc),
141 };
142
143 DRIVER_MODULE(amdsmn, hostb, amdsmn_driver, NULL, NULL);
144 MODULE_VERSION(amdsmn, 1);
145 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdsmn, amdsmn_ids,
146 nitems(amdsmn_ids));
147
148 static bool
amdsmn_match(device_t parent,const struct pciid ** pciid_out)149 amdsmn_match(device_t parent, const struct pciid **pciid_out)
150 {
151 uint16_t vendor, device;
152 size_t i;
153
154 vendor = pci_get_vendor(parent);
155 device = pci_get_device(parent);
156
157 for (i = 0; i < nitems(amdsmn_ids); i++) {
158 if (vendor == amdsmn_ids[i].amdsmn_vendorid &&
159 device == amdsmn_ids[i].amdsmn_deviceid) {
160 if (pciid_out != NULL)
161 *pciid_out = &amdsmn_ids[i];
162 return (true);
163 }
164 }
165 return (false);
166 }
167
168 static void
amdsmn_identify(driver_t * driver,device_t parent)169 amdsmn_identify(driver_t *driver, device_t parent)
170 {
171 device_t child;
172
173 /* Make sure we're not being doubly invoked. */
174 if (device_find_child(parent, "amdsmn", -1) != NULL)
175 return;
176 if (!amdsmn_match(parent, NULL))
177 return;
178
179 child = device_add_child(parent, "amdsmn", -1);
180 if (child == NULL)
181 device_printf(parent, "add amdsmn child failed\n");
182 }
183
184 static int
amdsmn_probe(device_t dev)185 amdsmn_probe(device_t dev)
186 {
187 uint32_t family;
188
189 if (resource_disabled("amdsmn", 0))
190 return (ENXIO);
191 if (!amdsmn_match(device_get_parent(dev), NULL))
192 return (ENXIO);
193
194 family = CPUID_TO_FAMILY(cpu_id);
195
196 switch (family) {
197 case 0x15:
198 case 0x17:
199 case 0x19:
200 break;
201 default:
202 return (ENXIO);
203 }
204 device_set_descf(dev, "AMD Family %xh System Management Network",
205 family);
206
207 return (BUS_PROBE_GENERIC);
208 }
209
210 static int
amdsmn_attach(device_t dev)211 amdsmn_attach(device_t dev)
212 {
213 struct amdsmn_softc *sc = device_get_softc(dev);
214
215 if (!amdsmn_match(device_get_parent(dev), &sc->smn_pciid))
216 return (ENXIO);
217
218 mtx_init(&sc->smn_lock, "SMN mtx", "SMN", MTX_DEF);
219 return (0);
220 }
221
222 int
amdsmn_detach(device_t dev)223 amdsmn_detach(device_t dev)
224 {
225 struct amdsmn_softc *sc = device_get_softc(dev);
226
227 mtx_destroy(&sc->smn_lock);
228 return (0);
229 }
230
231 int
amdsmn_read(device_t dev,uint32_t addr,uint32_t * value)232 amdsmn_read(device_t dev, uint32_t addr, uint32_t *value)
233 {
234 struct amdsmn_softc *sc = device_get_softc(dev);
235 device_t parent;
236
237 parent = device_get_parent(dev);
238
239 mtx_lock(&sc->smn_lock);
240 pci_write_config(parent, sc->smn_pciid->amdsmn_addr_reg, addr, 4);
241 *value = pci_read_config(parent, sc->smn_pciid->amdsmn_data_reg, 4);
242 mtx_unlock(&sc->smn_lock);
243
244 return (0);
245 }
246
247 int
amdsmn_write(device_t dev,uint32_t addr,uint32_t value)248 amdsmn_write(device_t dev, uint32_t addr, uint32_t value)
249 {
250 struct amdsmn_softc *sc = device_get_softc(dev);
251 device_t parent;
252
253 parent = device_get_parent(dev);
254
255 mtx_lock(&sc->smn_lock);
256 pci_write_config(parent, sc->smn_pciid->amdsmn_addr_reg, addr, 4);
257 pci_write_config(parent, sc->smn_pciid->amdsmn_data_reg, value, 4);
258 mtx_unlock(&sc->smn_lock);
259
260 return (0);
261 }
262