1 /* 2 * SPDX-FileCopyrightText: Copyright (c) 2018-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #ifndef _FLCN_NVSWITCH_H_ 25 #define _FLCN_NVSWITCH_H_ 26 27 #include "flcn/flcnrtosdebug_nvswitch.h" // <TODO - HEADER CLEANUP> 28 #include "flcnifcmn.h" 29 #include "flcn/flcnqueue_nvswitch.h" 30 31 #include "flcn/haldefs_flcn_nvswitch.h" 32 #include "common_nvswitch.h" 33 34 /**************** Resource Manager Defines and Structures ******************\ 35 * * 36 * Module: FLCN_NVSWITCH.H * 37 * Defines and structures used for the Falcon Object. The Falcon * 38 * object is the base object for all Falcon-derived engines. * 39 \***************************************************************************/ 40 41 /*! 42 * Compares an unit id against the values in the unit_id enumeration and 43 * verifies that the id is valid. It is expected that the id is specified 44 * as an unsigned integer. 45 */ 46 #define RM_FLCN_UNIT_ID_IS_VALID(pQeueInfo, id) \ 47 ((id) < (pQeueInfo)->maxUnitId) 48 49 50 /*! 51 * Verifies that the given queue identifier is a valid command queue id. It 52 * is expected that the id is specified as an unsigned integer. 53 */ 54 #define RM_FLCN_QUEUEID_IS_COMMAND_QUEUE(pQeueInfo, id) \ 55 ((id) <= (pQeueInfo)->maxCmdQueueIndex) 56 57 /*! 58 * Define a sequence descriptor that may be used during initialization that 59 * represents an invalid sequence descriptor (one in which will never be 60 * assigned when a sequence/command is submitted). 61 */ 62 #define FLCN_INVALID_SEQ_DESC NV_U32_MAX 63 64 /*! 65 * Define a event descriptor that may be used during initialization that 66 * represents an invalid event descriptor (one in which will never be assigned 67 * when a event is registered). 68 */ 69 #define FLCN_INVALID_EVT_DESC NV_U32_MAX 70 71 /*! 72 * Defines the alignment/granularity of falcon memory blocks 73 */ 74 #define FLCN_BLK_ALIGNMENT (256) 75 76 /*! 77 * Defines the required address/offset alignment for all DMEM accesses 78 */ 79 #define FLCN_DMEM_ACCESS_ALIGNMENT (4) 80 81 typedef struct FLCN_EVENT_INFO FLCN_EVENT_INFO, *PFLCN_EVENT_INFO; 82 83 /*! 84 * @brief Tracks all information for each client that has registered for a 85 * specific type of event-notification. 86 */ 87 struct FLCN_EVENT_INFO 88 { 89 /*! 90 * A unique identifier given to each event info instance to provide a 91 * fast way to identify and track an event registration. 92 */ 93 NvU32 evtDesc; 94 95 /*! 96 * An identifier that describes the type of event the client wants 97 * notification of. 98 */ 99 NvU32 unitId; 100 101 /*! 102 * The client's pre-allocated message buffer. This is the buffer that 103 * the message data will be written to when extracted from the Message 104 * Queue. This buffer must be sufficiently sized to hold the largest 105 * possible event for type 'unitId'. 106 */ 107 union RM_FLCN_MSG *pMsg; 108 109 /*! The client function to be called when the event triggers. */ 110 FlcnQMgrClientCallback pCallback; 111 112 /*! 113 * Any client-specified private parameters that must be provided in the 114 * callback function. 115 */ 116 void *pCallbackParams; 117 118 /*! 119 * Client's are tracked as a linked list. This is a pointer to the next 120 * client in the list. The ordering of this list implies no association 121 * between the clients. 122 */ 123 FLCN_EVENT_INFO *pNext; 124 }; 125 126 /*! 127 * @brief Enumeration for each discrete command state. 128 */ 129 typedef enum FLCN_CMD_STATE 130 { 131 /*! 132 * Indicates the the command does not have a state. Commands/sequences 133 * that have never been submitted while possess this state. 134 */ 135 FLCN_CMD_STATE_NONE = 0, 136 137 /*! Indicates that the command is being processed by the FLCN. */ 138 FLCN_CMD_STATE_RUNNING, 139 140 /*! Indicates that the command has finished execution on the FLCN. */ 141 FLCN_CMD_STATE_DONE 142 } FLCN_CMD_STATE; 143 144 145 typedef struct FALCON_EXTERNAL_CONFIG 146 { 147 NvBool bResetInPmc; // If TRUE, Reset Falcon using PMC Enable 148 NvU32 riscvRegisterBase; // Falcon's RISCV base offset. 149 NvU32 fbifBase; // Falcon's FB Interface base. 150 NvU32 blkcgBase; // Falcon's BLKCG base. 151 } FALCON_EXTERNAL_CONFIG, *PFALCON_EXTERNAL_CONFIG; 152 153 typedef struct 154 { 155 NvU8 maxUnitId; //<! Maximum valid Unit Id 156 NvU8 initEventUnitId; //<! INIT event unit id 157 NvU8 cmdQHeadSize; //<! Command Queue Head Size 158 NvU8 cmdQTailSize; //<! Command Queue Tail size 159 NvU8 msgQHeadSize; //<! Message Queue Head Size 160 NvU8 msgQTailSize; //<! Message Queue Tail Size 161 NvU32 maxCmdQueueIndex; //<! Maximum command queue Index 162 NvU32 maxMsgSize; //<! Maximum valid MSG size 163 NvU32 cmdQHeadBaseAddress; //<! Base Register Address of Command Queue Head. 164 NvU32 cmdQHeadStride; //<! Stride used to access indexed Command Queue Head registers. 165 NvU32 cmdQTailBaseAddress; //<! Base Register Address of Command Queue Tail. 166 NvU32 cmdQTailStride; //<! Stride used to access indexed Command Queue Tail registers. 167 NvU32 msgQHeadBaseAddress; //<! Base Register Address of Message Queue Head. 168 NvU32 msgQHeadStride; //<! Stride used to access indexed Message Queue Head registers. 169 NvU32 msgQTailBaseAddress; //<! Base Register Address of Message Queue Tail. 170 NvU32 msgQTailStride; //<! Stride used to access indexed Message Queue Head registers. 171 FLCNQUEUE *pQueues; //<! Queues allocated 172 173 /*! 174 * A linked-list of event information structures tracking all clients that 175 * have registered for event notification. 176 */ 177 PFLCN_EVENT_INFO pEventInfo; 178 179 /*! 180 * Each time a client registers for an event notification, an internal 181 * data structure is created and attached to the event-info list. Each 182 * structure will have a unique identifier/descriptor assigned that will 183 * be used to track and manage the registration. This variable keeps track 184 * of the next descriptor that will be assigned at any given time. 185 */ 186 NvU32 nextEvtDesc; 187 188 /*! 189 * Similar to 'nextEvtDesc' keeps track of the command descriptor that 190 * will be assigned to the next queued command. 191 */ 192 NvU32 nextSeqDesc; 193 194 /*! 195 * Keeps track the latest used sequence number. We always search the free 196 * sequence starting from the next to the latest used sequence since it is 197 * the most possible free sequence if we consume the sequence in serial. 198 */ 199 NvU32 latestUsedSeqNum; 200 201 } FALCON_QUEUE_INFO, 202 *PFALCON_QUEUE_INFO; 203 204 205 /*! 206 * Data specific Falcon debugging features. 207 */ 208 typedef struct 209 { 210 NvU32 dumpEngineTag; // NVDUMP_COMPONENT_ENG_xyz. 211 NvU32 pbFalconId; // Protobuf falcon ID. RTOS_FLCN_xyz. 212 NvU16 debugInfoDmemOffset; // DMEM address of the Falcon's 213 // DEBUG_INFO structure. 214 NvBool bCrashed; // Falcon has crashed at least once 215 // since RM was initialized. 216 NvBool bCallbackTriggered; // Flag indicating that callback 217 // was actually called. 218 } FLCN_DEBUG, *PFLCN_DEBUG; 219 220 struct FLCNABLE; 221 222 typedef struct ENGINE_DESCRIPTOR_TYPE 223 { 224 NvU32 base; 225 NvBool initialized; 226 } ENGINE_DESCRIPTOR_TYPE, *PENGINE_DESCRIPTOR_TYPE; 227 228 typedef enum ENGINE_TAG 229 { 230 ENG_TAG_INVALID, 231 ENG_TAG_SOE, 232 ENG_TAG_END_INVALID 233 } ENGINE_TAG, *PENGINE_TAG; 234 235 typedef struct FLCN 236 { 237 // pointer to our function table - should always be the first thing in any object 238 flcn_hal *pHal; 239 240 // we don't have a parent class, so we go straight to our members 241 const char *name; 242 243 ENGINE_DESCRIPTOR_TYPE engDescUc; 244 ENGINE_DESCRIPTOR_TYPE engDescBc; 245 246 FALCON_EXTERNAL_CONFIG extConfig; 247 248 // 249 // State variables 250 // 251 NvBool bConstructed; 252 253 /*! The FLCN is ready to accept work from the RM. */ 254 NvBool bOSReady; 255 256 /*! This Falcon will have queue support */ 257 NvBool bQueuesEnabled; 258 NvU8 numQueues; //<! Number of queues constructed 259 NvU32 numSequences; //<! Number of sequences constructed 260 261 FLCN_DEBUG debug; //<! Data specific to debugging 262 NvU8 coreRev; //<! Core revision. 0x51 is 5.1. 263 NvU8 securityModel; //<! Follows _FALCON_HWCFG1_SECURITY_MODEL_xyz 264 // Replacement for a PDB Property: PDB_PROP_FLCN_SUPPORTS_DMEM_APERTURES 265 NvBool supportsDmemApertures; 266 267 // We need to save a pointer to the FLCNABLE interface 268 struct FLCNABLE *pFlcnable; 269 270 ENGINE_TAG engineTag; 271 272 PFALCON_QUEUE_INFO pQueueInfo; 273 274 /*! 275 * Determines whether to use EMEM in place of DMEM for RM queues and 276 * the RM managed heap. EMEM is a memory region outside of the core engine 277 * of some falcons which allows for RM access even when the falcon is 278 * locked down in HS mode. This is required so that engines like SEC2 279 * can receive new commands from RM without blocking. 280 */ 281 NvBool bEmemEnabled; 282 283 /*! HW arch that is enabled and running on corresponding uproc engine. */ 284 NvU32 engArch; 285 286 /*! Flcn debug buffer object */ 287 288 } FLCN, *PFLCN; 289 290 // hal functions 291 292 // OBJECT Interfaces 293 NV_STATUS flcnQueueReadData(struct nvswitch_device *, PFLCN, NvU32 queueId, void *pData, NvBool bMsg); 294 NV_STATUS flcnQueueCmdWrite(struct nvswitch_device *, PFLCN, NvU32 queueId, union RM_FLCN_CMD *pCmd, struct NVSWITCH_TIMEOUT *pTimeout); 295 NV_STATUS flcnQueueCmdCancel(struct nvswitch_device *, PFLCN, NvU32 seqDesc); 296 NV_STATUS flcnQueueCmdPostNonBlocking(struct nvswitch_device *, PFLCN, union RM_FLCN_CMD *pCmd, union RM_FLCN_MSG *pMsg, void *pPayload, NvU32 queueIdLogical, FlcnQMgrClientCallback pCallback, void *pCallbackParams, NvU32 *pSeqDesc, struct NVSWITCH_TIMEOUT *pTimeout); 297 NV_STATUS flcnQueueCmdPostBlocking(struct nvswitch_device *, PFLCN, union RM_FLCN_CMD *pCmd, union RM_FLCN_MSG *pMsg, void *pPayload, NvU32 queueIdLogical, NvU32 *pSeqDesc, struct NVSWITCH_TIMEOUT *pTimeout); 298 NV_STATUS flcnQueueCmdWait(struct nvswitch_device *, PFLCN, NvU32, struct NVSWITCH_TIMEOUT *pTimeout); 299 NvU8 flcnCoreRevisionGet(struct nvswitch_device *, PFLCN); 300 void flcnMarkNotReady(struct nvswitch_device *, PFLCN); 301 NV_STATUS flcnCmdQueueHeadGet(struct nvswitch_device *, PFLCN, FLCNQUEUE *pQueue, NvU32 *pHead); 302 NV_STATUS flcnMsgQueueHeadGet(struct nvswitch_device *, PFLCN, FLCNQUEUE *pQueue, NvU32 *pHead); 303 NV_STATUS flcnCmdQueueTailGet(struct nvswitch_device *, PFLCN, FLCNQUEUE *pQueue, NvU32 *pTail); 304 NV_STATUS flcnMsgQueueTailGet(struct nvswitch_device *, PFLCN, FLCNQUEUE *pQueue, NvU32 *pTail); 305 NV_STATUS flcnCmdQueueHeadSet(struct nvswitch_device *, PFLCN, FLCNQUEUE *pQueue, NvU32 head); 306 NV_STATUS flcnMsgQueueHeadSet(struct nvswitch_device *, PFLCN, FLCNQUEUE *pQueue, NvU32 head); 307 NV_STATUS flcnCmdQueueTailSet(struct nvswitch_device *, PFLCN, FLCNQUEUE *pQueue, NvU32 tail); 308 NV_STATUS flcnMsgQueueTailSet(struct nvswitch_device *, PFLCN, FLCNQUEUE *pQueue, NvU32 tail); 309 PFLCN_QMGR_SEQ_INFO flcnQueueSeqInfoFind(struct nvswitch_device *, PFLCN, NvU32 seqDesc); 310 PFLCN_QMGR_SEQ_INFO flcnQueueSeqInfoAcq(struct nvswitch_device *, PFLCN); 311 void flcnQueueSeqInfoRel(struct nvswitch_device *, PFLCN, PFLCN_QMGR_SEQ_INFO pSeqInfo); 312 void flcnQueueSeqInfoStateInit(struct nvswitch_device *, PFLCN); 313 void flcnQueueSeqInfoCancelAll(struct nvswitch_device *, PFLCN); 314 NV_STATUS flcnQueueSeqInfoFree(struct nvswitch_device *, PFLCN, PFLCN_QMGR_SEQ_INFO); 315 NV_STATUS flcnQueueEventRegister(struct nvswitch_device *, PFLCN, NvU32 unitId, NvU8 *pMsg, FlcnQMgrClientCallback pCallback, void *pParams, NvU32 *pEvtDesc); 316 NV_STATUS flcnQueueEventUnregister(struct nvswitch_device *, PFLCN, NvU32 evtDesc); 317 NV_STATUS flcnQueueEventHandle(struct nvswitch_device *, PFLCN, union RM_FLCN_MSG *pMsg, NV_STATUS evtStatus); 318 NV_STATUS flcnQueueResponseHandle(struct nvswitch_device *, PFLCN, union RM_FLCN_MSG *pMsg); 319 NvU32 flcnQueueCmdStatus(struct nvswitch_device *, PFLCN, NvU32 seqDesc); 320 NV_STATUS flcnDmemCopyFrom(struct nvswitch_device *, PFLCN, NvU32 src, NvU8 *pDst, NvU32 sizeBytes, NvU8 port); 321 NV_STATUS flcnDmemCopyTo(struct nvswitch_device *, PFLCN, NvU32 dst, NvU8 *pSrc, NvU32 sizeBytes, NvU8 port); 322 void flcnPostDiscoveryInit(struct nvswitch_device *, PFLCN); 323 void flcnDbgInfoDmemOffsetSet(struct nvswitch_device *, PFLCN, NvU16 debugInfoDmemOffset); 324 325 // HAL Interfaces 326 NV_STATUS flcnConstruct_HAL (struct nvswitch_device *, PFLCN); 327 void flcnDestruct_HAL (struct nvswitch_device *, PFLCN); 328 NvU32 flcnRegRead_HAL (struct nvswitch_device *, PFLCN, NvU32 offset); 329 void flcnRegWrite_HAL (struct nvswitch_device *, PFLCN, NvU32 offset, NvU32 data); 330 const char *flcnGetName_HAL (struct nvswitch_device *, PFLCN); 331 NvU8 flcnReadCoreRev_HAL (struct nvswitch_device *, PFLCN); 332 void flcnGetCoreInfo_HAL (struct nvswitch_device *, PFLCN); 333 NV_STATUS flcnDmemTransfer_HAL (struct nvswitch_device *, PFLCN, NvU32 src, NvU8 *pDst, NvU32 sizeBytes, NvU8 port, NvBool bCopyFrom); 334 void flcnIntrRetrigger_HAL (struct nvswitch_device *, PFLCN); 335 NvBool flcnAreEngDescsInitialized_HAL (struct nvswitch_device *, PFLCN); 336 NV_STATUS flcnWaitForResetToFinish_HAL (struct nvswitch_device *, PFLCN); 337 void flcnDbgInfoCapturePcTrace_HAL (struct nvswitch_device *, PFLCN); 338 void flcnDbgInfoCaptureRiscvPcTrace_HAL (struct nvswitch_device *, PFLCN); 339 NvU32 flcnDmemSize_HAL (struct nvswitch_device *, struct FLCN *); 340 NvU32 flcnSetImemAddr_HAL (struct nvswitch_device *, struct FLCN *, NvU32 dst); 341 void flcnImemCopyTo_HAL (struct nvswitch_device *, struct FLCN *, NvU32 dst, NvU8 *pSrc, NvU32 sizeBytes, NvBool bSecure, NvU32 tag, NvU8 port); 342 NvU32 flcnSetDmemAddr_HAL (struct nvswitch_device *, struct FLCN *, NvU32 dst); 343 NvU32 flcnRiscvRegRead_HAL (struct nvswitch_device *, PFLCN, NvU32 offset); 344 void flcnRiscvRegWrite_HAL (struct nvswitch_device *, PFLCN, NvU32 offset, NvU32 data); 345 NV_STATUS flcnDebugBufferInit_HAL (struct nvswitch_device *, struct FLCN *, NvU32 debugBufferMaxSize, NvU32 writeRegAddr, NvU32 readRegAddr); 346 NV_STATUS flcnDebugBufferDestroy_HAL (struct nvswitch_device *, struct FLCN *); 347 NV_STATUS flcnDebugBufferDisplay_HAL (struct nvswitch_device *, struct FLCN *); 348 NvBool flcnDebugBufferIsEmpty_HAL (struct nvswitch_device *, struct FLCN *); 349 350 // Falcon core revision / subversion definitions. 351 #define NV_FLCN_CORE_REV_3_0 0x30 // 3.0 - Core revision 3 subversion 0. 352 #define NV_FLCN_CORE_REV_4_0 0x40 // 4.0 - Core revision 4 subversion 0. 353 #define NV_FLCN_CORE_REV_4_1 0x41 // 4.1 - Core revision 4 subversion 1. 354 #define NV_FLCN_CORE_REV_5_0 0x50 // 5.0 - Core revision 5 subversion 0. 355 #define NV_FLCN_CORE_REV_5_1 0x51 // 5.1 - Core revision 5 subversion 1. 356 #define NV_FLCN_CORE_REV_6_0 0x60 // 6.0 - Core revision 6 subversion 0. 357 358 // 359 // Convert Falcon core rev/subver to the IP version format that can be recognized 360 // by the chip-config dynamic HAL infra. 361 // 362 #define NV_FLCN_CORE_REV_TO_IP_VER(coreVer) \ 363 (DRF_NUM(_PFALCON, _IP_VER, _MAJOR, ((coreVer >> 4) & 0xf)) | \ 364 DRF_NUM(_PFALCON, _IP_VER, _MINOR, (coreVer & 0xf))) 365 366 #define NV_PFALCON_IP_VER_MINOR 23:16 367 #define NV_PFALCON_IP_VER_MAJOR 31:24 368 369 // Some mailbox defines (should be shared with MSDEC OS) 370 #define NV_FALCON_MAILBOX0_MSDECOS_STATUS 11:0 371 #define NV_FALCON_MAILBOX0_MSDECOS_INVALID_METHOD_MTHDCNT 19:12 372 #define NV_FALCON_MAILBOX0_MSDECOS_INVALID_METHOD_MTHDID 31:20 373 #define NV_FALCON_MAILBOX1_MSDECOS_INVALID_METHOD_MTHDDATA 31:0 374 375 PFLCN flcnAllocNew(void); 376 NvlStatus flcnInit(nvswitch_device *device, PFLCN pFlcn, NvU32 pci_device_id); 377 void flcnDestroy(nvswitch_device *device, FLCN *pFlcn); 378 379 /*! 380 * The HW arch (e.g. FALCON or FALCON + RISCV) that can be actively enabled and 381 * running on an uproc engine. 382 */ 383 #define NV_UPROC_ENGINE_ARCH_DEFAULT (0x0) 384 #define NV_UPROC_ENGINE_ARCH_FALCON (0x1) 385 #define NV_UPROC_ENGINE_ARCH_FALCON_RISCV (0x2) 386 387 /*! 388 * Hepler macro to check what HW arch is enabled and running on an uproc engine. 389 */ 390 #define UPROC_ENG_ARCH_FALCON(pFlcn) (pFlcn->engArch == NV_UPROC_ENGINE_ARCH_FALCON) 391 #define UPROC_ENG_ARCH_FALCON_RISCV(pFlcn) (pFlcn->engArch == NV_UPROC_ENGINE_ARCH_FALCON_RISCV) 392 393 // Falcon Register index 394 #define NV_FALCON_REG_R0 (0) 395 #define NV_FALCON_REG_R1 (1) 396 #define NV_FALCON_REG_R2 (2) 397 #define NV_FALCON_REG_R3 (3) 398 #define NV_FALCON_REG_R4 (4) 399 #define NV_FALCON_REG_R5 (5) 400 #define NV_FALCON_REG_R6 (6) 401 #define NV_FALCON_REG_R7 (7) 402 #define NV_FALCON_REG_R8 (8) 403 #define NV_FALCON_REG_R9 (9) 404 #define NV_FALCON_REG_R10 (10) 405 #define NV_FALCON_REG_R11 (11) 406 #define NV_FALCON_REG_R12 (12) 407 #define NV_FALCON_REG_R13 (13) 408 #define NV_FALCON_REG_R14 (14) 409 #define NV_FALCON_REG_R15 (15) 410 #define NV_FALCON_REG_IV0 (16) 411 #define NV_FALCON_REG_IV1 (17) 412 #define NV_FALCON_REG_UNDEFINED (18) 413 #define NV_FALCON_REG_EV (19) 414 #define NV_FALCON_REG_SP (20) 415 #define NV_FALCON_REG_PC (21) 416 #define NV_FALCON_REG_IMB (22) 417 #define NV_FALCON_REG_DMB (23) 418 #define NV_FALCON_REG_CSW (24) 419 #define NV_FALCON_REG_CCR (25) 420 #define NV_FALCON_REG_SEC (26) 421 #define NV_FALCON_REG_CTX (27) 422 #define NV_FALCON_REG_EXCI (28) 423 #define NV_FALCON_REG_RSVD0 (29) 424 #define NV_FALCON_REG_RSVD1 (30) 425 #define NV_FALCON_REG_RSVD2 (31) 426 427 #define NV_FALCON_REG_SIZE (32) 428 429 #define FALC_REG(x) NV_FALCON_REG_##x 430 431 432 #endif // _FLCN_NVSWITCH_H_ 433 434 /*! 435 * Defines the Falcon IMEM block-size (as a power-of-2). 436 */ 437 #define FALCON_IMEM_BLKSIZE2 (8) 438 439 /*! 440 * Defines the Falcon DMEM block-size (as a power-of-2). 441 */ 442 #define FALCON_DMEM_BLKSIZE2 (8) 443 444