1 /* $OpenBSD: armreg.h,v 1.43 2019/09/30 21:48:32 kettenis Exp $ */ 2 /* $NetBSD: armreg.h,v 1.27 2003/09/06 08:43:02 rearnsha Exp $ */ 3 4 /* 5 * Copyright (c) 1998, 2001 Ben Harris 6 * Copyright (c) 1994-1996 Mark Brinicombe. 7 * Copyright (c) 1994 Brini. 8 * All rights reserved. 9 * 10 * This code is derived from software written for Brini by Mark Brinicombe 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by Brini. 23 * 4. The name of the company nor the name of the author may be used to 24 * endorse or promote products derived from this software without specific 25 * prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 28 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 29 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 31 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 32 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 33 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 37 * SUCH DAMAGE. 38 */ 39 40 #ifndef _ARM_ARMREG_H 41 #define _ARM_ARMREG_H 42 43 /* CCSIDR - Current Cache Size ID Register */ 44 #define CCSIDR_SETS_MASK 0x0fffe000 45 #define CCSIDR_SETS_SHIFT 13 46 #define CCSIDR_SETS(reg) \ 47 ((((reg) & CCSIDR_SETS_MASK) >> CCSIDR_SETS_SHIFT) + 1) 48 #define CCSIDR_WAYS_MASK 0x00001ff8 49 #define CCSIDR_WAYS_SHIFT 3 50 #define CCSIDR_WAYS(reg) \ 51 ((((reg) & CCSIDR_WAYS_MASK) >> CCSIDR_WAYS_SHIFT) + 1) 52 #define CCSIDR_LINE_MASK 0x00000007 53 #define CCSIDR_LINE_SIZE(reg) (1 << (((reg) & CCSIDR_LINE_MASK) + 4)) 54 55 /* CLIDR - Cache Level ID Register */ 56 #define CLIDR_CTYPE_MASK 0x7 57 #define CLIDR_CTYPE_INSN 0x1 58 #define CLIDR_CTYPE_DATA 0x2 59 #define CLIDR_CTYPE_UNIFIED 0x4 60 61 /* CSSELR - Cache Size Selection Register */ 62 #define CSSELR_IND (1 << 0) 63 #define CSSELR_LEVEL_SHIFT 1 64 65 /* CTR - Cache Type Register */ 66 #define CTR_DLINE_SHIFT 16 67 #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) 68 #define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT) 69 #define CTR_IL1P_SHIFT 14 70 #define CTR_IL1P_MASK (0x3 << CTR_IL1P_SHIFT) 71 #define CTR_IL1P_AIVIVT (0x1 << CTR_IL1P_SHIFT) 72 #define CTR_IL1P_VIPT (0x2 << CTR_IL1P_SHIFT) 73 #define CTR_IL1P_PIPT (0x3 << CTR_IL1P_SHIFT) 74 #define CTR_ILINE_SHIFT 0 75 #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) 76 #define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) 77 78 /* 79 * ARM Process Status Register 80 * 81 * The picture in early ARM manuals looks like this: 82 * 3 3 2 2 2 2 83 * 1 0 9 8 7 6 8 7 6 5 4 0 84 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 85 * |N|Z|C|V|Q| reserved |I|F|T|M M M M M| 86 * | | | | | | | | | |4 3 2 1 0| 87 * +-+-+-+-+-+-------------------------------------+-+-+-+---------+ 88 * 89 * The picture in the ARMv7-A manuals looks like this: 90 * 3 3 2 2 2 2 2 2 2 2 1 1 1 1 91 * 1 0 9 8 7 6 5 4 3 0 9 6 5 0 9 8 7 6 5 4 0 92 * +-+-+-+-+-+---+-+-------+-------+-----------+-+-+-+-+-+---------+ 93 * |N|Z|C|V|Q|I I|J|reserv-|G G G G|I I I I I I|E|A|I|F|T|M M M M M| 94 * | | | | | |T T| |ed |E E E E|T T T T T T| | | | | | | 95 * | | | | | |1 0| | |3 2 1 0|7 6 5 4 3 2| | | | | |4 3 2 1 0| 96 * +-+-+-+-+-+---+-+-------+-------+-----------+-+-+-+-+-+---------+ 97 * | flags 'f' | status 's' | extension 'x' | control 'c' | 98 */ 99 100 #define PSR_FLAGS 0xf0000000 /* flags */ 101 #define PSR_N (1U << 31) /* negative */ 102 #define PSR_Z (1 << 30) /* zero */ 103 #define PSR_C (1 << 29) /* carry */ 104 #define PSR_V (1 << 28) /* overflow */ 105 106 #define PSR_Q (1 << 27) /* saturation */ 107 108 #define PSR_A (1 << 8) /* Asynchronous abort disable */ 109 #define PSR_I (1 << 7) /* IRQ disable */ 110 #define PSR_F (1 << 6) /* FIQ disable */ 111 112 #define PSR_T (1 << 5) /* Thumb state */ 113 #define PSR_J (1 << 24) /* Java mode */ 114 115 #define PSR_MODE 0x0000001f /* mode mask */ 116 #define PSR_USR26_MODE 0x00000000 117 #define PSR_FIQ26_MODE 0x00000001 118 #define PSR_IRQ26_MODE 0x00000002 119 #define PSR_SVC26_MODE 0x00000003 120 #define PSR_USR32_MODE 0x00000010 121 #define PSR_FIQ32_MODE 0x00000011 122 #define PSR_IRQ32_MODE 0x00000012 123 #define PSR_SVC32_MODE 0x00000013 124 #define PSR_MON32_MODE 0x00000016 125 #define PSR_ABT32_MODE 0x00000017 126 #define PSR_HYP32_MODE 0x0000001a 127 #define PSR_UND32_MODE 0x0000001b 128 #define PSR_SYS32_MODE 0x0000001f 129 #define PSR_32_MODE 0x00000010 130 131 #define PSR_IN_USR_MODE(psr) (!((psr) & 3)) /* XXX */ 132 133 /* 134 * Co-processor 15: The system control co-processor. 135 */ 136 137 #define ARM_CP15_CPU_ID 0 138 139 /* 140 * The CPU ID register is theoretically structured, but the definitions of 141 * the fields keep changing. 142 */ 143 144 /* The high-order byte is always the implementor */ 145 #define CPU_ID_IMPLEMENTOR_MASK 0xff000000 146 #define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 147 148 #define CPU_ID_ARCH_MASK 0x000f0000 149 #define CPU_ID_ARCH_V6 0x00070000 150 #define CPU_ID_ARCH_CPUID 0x000f0000 151 #define CPU_ID_VARIANT_MASK 0x00f00000 152 153 /* Next three nybbles are part number */ 154 #define CPU_ID_PARTNO_MASK 0x0000fff0 155 156 /* And finally, the revision number. */ 157 #define CPU_ID_REVISION_MASK 0x0000000f 158 159 /* Individual CPUs are probably best IDed by everything but the revision. */ 160 #define CPU_ID_CPU_MASK 0xfffffff0 161 #define CPU_ID_CORTEX_MASK 0xff0ffff0 162 #define CPU_ID_CORTEX_A5 0x410fc050 163 #define CPU_ID_CORTEX_A5_MASK 0xff0ffff0 164 #define CPU_ID_CORTEX_A7 0x410fc070 165 #define CPU_ID_CORTEX_A7_MASK 0xff0ffff0 166 #define CPU_ID_CORTEX_A8_R1 0x411fc080 167 #define CPU_ID_CORTEX_A8_R2 0x412fc080 168 #define CPU_ID_CORTEX_A8_R3 0x413fc080 169 #define CPU_ID_CORTEX_A8 0x410fc080 170 #define CPU_ID_CORTEX_A8_MASK 0xff0ffff0 171 #define CPU_ID_CORTEX_A9 0x410fc090 172 #define CPU_ID_CORTEX_A9_R1 0x411fc090 173 #define CPU_ID_CORTEX_A9_R2 0x412fc090 174 #define CPU_ID_CORTEX_A9_R3 0x413fc090 175 #define CPU_ID_CORTEX_A9_R4 0x414fc090 176 #define CPU_ID_CORTEX_A9_MASK 0xff0ffff0 177 #define CPU_ID_CORTEX_A12 0x410fc0d0 178 #define CPU_ID_CORTEX_A12_MASK 0xff0ffff0 179 #define CPU_ID_CORTEX_A15 0x410fc0f0 180 #define CPU_ID_CORTEX_A15_R1 0x411fc0f0 181 #define CPU_ID_CORTEX_A15_R2 0x412fc0f0 182 #define CPU_ID_CORTEX_A15_R3 0x413fc0f0 183 #define CPU_ID_CORTEX_A15_R4 0x414fc0f0 184 #define CPU_ID_CORTEX_A15_MASK 0xff0ffff0 185 #define CPU_ID_CORTEX_A17 0x410fc0e0 186 #define CPU_ID_CORTEX_A17_R1 0x411fc0e0 187 #define CPU_ID_CORTEX_A17_MASK 0xff0ffff0 188 #define CPU_ID_CORTEX_A32 0x410fd010 189 #define CPU_ID_CORTEX_A32_MASK 0xff0ffff0 190 #define CPU_ID_CORTEX_A35 0x410fd040 191 #define CPU_ID_CORTEX_A35_MASK 0xff0ffff0 192 #define CPU_ID_CORTEX_A53 0x410fd030 193 #define CPU_ID_CORTEX_A53_R1 0x411fd030 194 #define CPU_ID_CORTEX_A53_MASK 0xff0ffff0 195 #define CPU_ID_CORTEX_A55 0x410fd050 196 #define CPU_ID_CORTEX_A55_MASK 0xff0ffff0 197 #define CPU_ID_CORTEX_A57 0x410fd070 198 #define CPU_ID_CORTEX_A57_R1 0x411fd070 199 #define CPU_ID_CORTEX_A57_MASK 0xff0ffff0 200 #define CPU_ID_CORTEX_A72 0x410fd080 201 #define CPU_ID_CORTEX_A72_R1 0x411fd080 202 #define CPU_ID_CORTEX_A72_MASK 0xff0ffff0 203 #define CPU_ID_CORTEX_A73 0x410fd090 204 #define CPU_ID_CORTEX_A73_MASK 0xff0ffff0 205 #define CPU_ID_CORTEX_A75 0x410fd0a0 206 #define CPU_ID_CORTEX_A75_MASK 0xff0ffff0 207 208 /* CPUID on >= v7 */ 209 #define ID_MMFR0_VMSA_MASK 0x0000000f 210 211 #define VMSA_V7 3 212 #define VMSA_V7_PXN 4 213 #define VMSA_V7_LDT 5 214 215 /* 216 * Post-ARM3 CP15 registers: 217 * 218 * 1 Control register 219 * 220 * 2 Translation Table Base 221 * 222 * 3 Domain Access Control 223 * 224 * 4 Reserved 225 * 226 * 5 Fault Status 227 * 228 * 6 Fault Address 229 * 230 * 7 Cache/write-buffer Control 231 * 232 * 8 TLB Control 233 * 234 * 9 Cache Lockdown 235 * 236 * 10 TLB Lockdown 237 * 238 * 11 Reserved 239 * 240 * 12 Reserved 241 * 242 * 13 Process ID (for FCSE) 243 * 244 * 14 Reserved 245 * 246 * 15 Implementation Dependent 247 */ 248 249 /* Some of the definitions below need cleaning up for V3/V4 architectures */ 250 251 /* CPU control register (CP15 register 1) */ 252 #define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 253 #define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 254 #define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 255 #define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 256 #define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 257 #define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 258 #define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 259 #define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 260 #define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 261 #define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 262 #define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 263 #define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 264 #define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 265 #define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 266 #define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 267 #define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 268 269 /* below were added by V6 */ 270 #define CPU_CONTROL_FI (1<<21) /* FI: fast interrupts */ 271 #define CPU_CONTROL_U (1<<22) /* U: Unaligned */ 272 #define CPU_CONTROL_VE (1<<24) /* VE: Vector enable */ 273 #define CPU_CONTROL_EE (1<<25) /* EE: Exception Endianness */ 274 #define CPU_CONTROL_L2 (1<<25) /* L2: L2 cache enable */ 275 276 /* added with v7 */ 277 #define CPU_CONTROL_WXN (1<<19) /* WXN: Write implies XN */ 278 #define CPU_CONTROL_UWXN (1<<20) /* UWXN: Unpriv write implies XN */ 279 #define CPU_CONTROL_NMFI (1<<27) /* NMFI: Non Maskable fast interrupt */ 280 #define CPU_CONTROL_TRE (1<<28) /* TRE: TEX Remap Enable */ 281 #define CPU_CONTROL_AFE (1<<29) /* AFE: Access Flag Enable */ 282 #define CPU_CONTROL_TE (1<<30) /* TE: Thumb Exception Enable */ 283 284 #define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 285 286 /* Cortex-A9 Auxiliary Control Register (CP15 register 1, opcode 1) */ 287 #define CORTEXA9_AUXCTL_FW (1 << 0) /* Cache and TLB updates broadcast */ 288 #define CORTEXA9_AUXCTL_L2PE (1 << 1) /* Prefetch hint enable */ 289 #define CORTEXA9_AUXCTL_L1PE (1 << 2) /* Data prefetch hint enable */ 290 #define CORTEXA9_AUXCTL_WR_ZERO (1 << 3) /* Ena. write full line of 0s mode */ 291 #define CORTEXA9_AUXCTL_SMP (1 << 6) /* Coherency is active */ 292 #define CORTEXA9_AUXCTL_EXCL (1 << 7) /* Exclusive cache bit */ 293 #define CORTEXA9_AUXCTL_ONEWAY (1 << 8) /* Allocate in on cache way only */ 294 #define CORTEXA9_AUXCTL_PARITY (1 << 9) /* Support parity checking */ 295 296 /* Cache type register definitions */ 297 #define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 298 #define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 299 #define CPU_CT_S (1U << 24) /* split cache */ 300 #define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 301 /* Cache type register definitions for ARM v7 */ 302 #define CPU_CT_IMINLINE(x) ((x) & 0xf) /* I$ min line size */ 303 #define CPU_CT_DMINLINE(x) (((x) >> 16) & 0xf) /* D$ min line size */ 304 305 #define CPU_CT_CTYPE_WT 0 /* write-through */ 306 #define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 307 #define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 308 #define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 309 #define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 310 311 #define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 312 #define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 313 #define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 314 #define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 315 316 /* MPIDR, Multiprocessor Affinity Register */ 317 #define MPIDR_AFF2 (0xffU << 16) 318 #define MPIDR_AFF1 (0xffU << 8) 319 #define MPIDR_AFF0 (0xffU << 0) 320 #define MPIDR_AFF (MPIDR_AFF2|MPIDR_AFF1|MPIDR_AFF0) 321 322 /* Fault status register definitions */ 323 324 #define FAULT_USER 0x20 325 326 #define FAULT_WRTBUF_0 0x00 /* Vector Exception */ 327 #define FAULT_WRTBUF_1 0x02 /* Terminal Exception */ 328 #define FAULT_BUSERR_0 0x04 /* External Abort on Linefetch -- Section */ 329 #define FAULT_BUSERR_1 0x06 /* External Abort on Linefetch -- Page */ 330 #define FAULT_BUSERR_2 0x08 /* External Abort on Non-linefetch -- Section */ 331 #define FAULT_BUSERR_3 0x0a /* External Abort on Non-linefetch -- Page */ 332 #define FAULT_BUSTRNL1 0x0c /* External abort on Translation -- Level 1 */ 333 #define FAULT_BUSTRNL2 0x0e /* External abort on Translation -- Level 2 */ 334 #define FAULT_ALIGN_0 0x01 /* Alignment */ 335 #define FAULT_ALIGN_1 0x03 /* Alignment */ 336 #define FAULT_TRANS_S 0x05 /* Translation -- Section */ 337 #define FAULT_TRANS_P 0x07 /* Translation -- Page */ 338 #define FAULT_DOMAIN_S 0x09 /* Domain -- Section */ 339 #define FAULT_DOMAIN_P 0x0b /* Domain -- Page */ 340 #define FAULT_PERM_S 0x0d /* Permission -- Section */ 341 #define FAULT_PERM_P 0x0f /* Permission -- Page */ 342 343 /* Fault type definitions for ARM v7 */ 344 #define FAULT_ACCESS_1 0x03 /* Access flag fault -- Level 1 */ 345 #define FAULT_ACCESS_2 0x06 /* Access flag fault -- Level 2 */ 346 347 #define FAULT_IMPRECISE 0x400 /* Imprecise exception (XSCALE) */ 348 349 #define FAULT_EXT 0x00001000 /* external abort */ 350 #define FAULT_WNR 0x00000800 /* write fault */ 351 352 #define FAULT_TYPE(fsr) ((fsr) & 0x0f) 353 #define FAULT_TYPE_V7(fsr) (((fsr) & 0x0f) | (((fsr) & 0x00000400) >> 6)) 354 355 /* 356 * Address of the vector page, low and high versions. 357 */ 358 #define ARM_VECTORS_LOW 0x00000000U 359 #define ARM_VECTORS_HIGH 0xffff0000U 360 361 /* 362 * ARM Instructions 363 * 364 * 3 3 2 2 2 365 * 1 0 9 8 7 0 366 * +-------+-------------------------------------------------------+ 367 * | cond | instruction dependant | 368 * |c c c c| | 369 * +-------+-------------------------------------------------------+ 370 */ 371 372 #define INSN_SIZE 4 /* Always 4 bytes */ 373 #define INSN_COND_MASK 0xf0000000 /* Condition mask */ 374 #define INSN_COND_AL 0xe0000000 /* Always condition */ 375 376 /* Translation Table Base Register */ 377 #define TTBR_C (1 << 0) /* without MPE */ 378 #define TTBR_S (1 << 1) 379 #define TTBR_IMP (1 << 2) 380 #define TTBR_RGN_MASK (3 << 3) 381 #define TTBR_RGN_NC (0 << 3) 382 #define TTBR_RGN_WBWA (1 << 3) 383 #define TTBR_RGN_WT (2 << 3) 384 #define TTBR_RGN_WBNWA (3 << 3) 385 #define TTBR_NOS (1 << 5) 386 #define TTBR_IRGN_MASK ((1 << 0) | (1 << 6)) 387 #define TTBR_IRGN_NC ((0 << 0) | (0 << 6)) 388 #define TTBR_IRGN_WBWA ((0 << 0) | (1 << 6)) 389 #define TTBR_IRGN_WT ((1 << 0) | (0 << 6)) 390 #define TTBR_IRGN_WBNWA ((1 << 0) | (1 << 6)) 391 392 #endif 393