1 /* 2 Z88DK Z80 Macro Assembler 3 4 Copyright (C) Gunther Strube, InterLogic 1993-99 5 Copyright (C) Paulo Custodio, 2011-2020 6 License: The Artistic License 2.0, http://www.perlfoundation.org/artistic_license_2_0 7 Repository: https://github.com/z88dk/z88dk 8 9 Define CPU opcodes 10 */ 11 12 #pragma once 13 14 #include "errors.h" 15 #include "options.h" 16 17 /* forward declaration without include cycle */ 18 struct Expr; 19 20 /* add 1 to 4 bytes opcode opcode to object code 21 * bytes in big-endian format, e.g. 0xED46 */ 22 void add_opcode(int opcode); 23 24 /* add opcode followed by jump relative offset expression */ 25 void add_opcode_jr(int opcode, struct Expr *expr); 26 void add_opcode_jr_n(int opcode, struct Expr* expr, int asmpc_offset); 27 28 /* add opcode followed by 8-bit unsigned expression */ 29 void add_opcode_n(int opcode, struct Expr *expr); 30 31 /* add opcode followed by 8-bit unsigned expression and a zero byte */ 32 void add_opcode_n_0(int opcode, struct Expr* expr); 33 34 /* add opcode followed by 8-bit signed expression and a zero or 0xff byte depending on sign */ 35 void add_opcode_s_0(int opcode, struct Expr* expr); 36 37 /* add opcode followed by 8-bit signed expression */ 38 void add_opcode_d(int opcode, struct Expr *expr); 39 40 /* add opcode followed by 16-bit expression */ 41 void add_opcode_nn(int opcode, struct Expr *expr); 42 43 /* add opcode followed by big-endian 16-bit expression */ 44 void add_opcode_NN(int opcode, struct Expr *expr); 45 46 /* add opcode followed by IX/IY offset expression */ 47 void add_opcode_idx(int opcode, struct Expr *expr); 48 49 /* add opcode followed by IX/IY offset expression and 8 bit expression */ 50 void add_opcode_idx_n(int opcode, struct Expr *idx_expr, 51 struct Expr *n_expr ); 52 53 /* add opcode followed by two 8-bit expressions */ 54 void add_opcode_n_n(int opcode, struct Expr *n1_expr, 55 struct Expr *n2_expr ); 56 57 /* call emulation function by name */ 58 void add_call_emul_func(char *emul_func); 59 60 /* add Z88's opcodes */ 61 void add_Z88_CALL_OZ(int argument); 62 void add_Z88_CALL_PKG(int argument); 63 void add_Z88_FPP(int argument); 64 void add_Z88_INVOKE(int argument); 65 66 /* add COPPER UNIT opcodes (ZX Next) */ 67 void add_copper_unit_wait(struct Expr *ver, struct Expr *hor); 68 void add_copper_unit_move(struct Expr *reg, struct Expr *val); 69 void add_copper_unit_stop(); 70 void add_copper_unit_nop(); 71 72 /* assert we are on a Z80 */ 73 #define _Z80_ONLY(x) (!(opts.cpu & (CPU_Z80|CPU_Z80N)) ? \ 74 (error_illegal_ident(), 0) : \ 75 (x)) 76 #define _EXCEPT_Z80(x) ((opts.cpu & (CPU_Z80|CPU_Z80N)) ? \ 77 (error_illegal_ident(), 0) : \ 78 (x)) 79 #define _Z180_ONLY(x) (!(opts.cpu & CPU_Z180) ? \ 80 (error_illegal_ident(), 0) : \ 81 (x)) 82 #define _RCM2000_ONLY(x) (!(opts.cpu & CPU_R2K) ? \ 83 (error_illegal_ident(), 0) : \ 84 (x)) 85 #define _RCM3000_ONLY(x) (!(opts.cpu & CPU_R3K) ? \ 86 (error_illegal_ident(), 0) : \ 87 (x)) 88 89 #define _ZILOG_ONLY(x) (!(opts.cpu & CPU_ZILOG) ? \ 90 (error_illegal_ident(), 0) : \ 91 (x)) 92 #define _RABBIT_ONLY(x) (!(opts.cpu & CPU_RABBIT) ? \ 93 (error_illegal_ident(), 0) : \ 94 (x)) 95 96 /* Index prefix constants */ 97 #define P_BC 0 98 #define P_DE 0 99 #define P_HL 0 100 #define P_AF 0 101 #define P_SP 0 102 #define P_IX (opts.swap_ix_iy ? 0xFD00 : 0xDD00) 103 #define P_IY (opts.swap_ix_iy ? 0xDD00 : 0xFD00) 104 105 /* Flags constants */ 106 enum { FLAG_NZ, FLAG_Z, FLAG_NC, FLAG_C, FLAG_PO_LZ, FLAG_PE_LO, FLAG_P, FLAG_M }; 107 108 #define FLAG_PO FLAG_PO_LZ 109 #define FLAG_PE FLAG_PE_LO 110 111 #define FLAG_LZ _RABBIT_ONLY(FLAG_PO_LZ) 112 #define FLAG_LO _RABBIT_ONLY(FLAG_PE_LO) 113 114 #define NOT_FLAG(flag) ((flag) ^ 1) 115 116 /* 8-bit registers */ 117 enum { REG_B, REG_C, REG_D, REG_E, REG_H, REG_L, REG_idx, REG_A, REG_F=6 }; 118 #define REG_IXH _Z80_ONLY(REG_H) 119 #define REG_IYH _Z80_ONLY(REG_H) 120 #define REG_IXL _Z80_ONLY(REG_L) 121 #define REG_IYL _Z80_ONLY(REG_L) 122 123 /* 16-bit registers */ 124 enum { REG_BC, REG_DE, REG_HL, REG_SP, 125 REG_AF = REG_SP, 126 REG_IX = REG_HL, REG_IY = REG_HL, 127 REG_IND_BC = 0, REG_IND_DE }; 128 129 /* ALU operations */ 130 enum { ALU_ADD, ALU_ADC, ALU_SUB, ALU_SBC, ALU_AND, ALU_XOR, ALU_OR, ALU_CP }; 131 #define _Z80_ALU(alu,reg) (0x80 + ((alu) << 3) + (reg)) 132 #define _Z80_ALU_n(alu) (0xC0 + ((alu) << 3) + REG_idx) 133 134 /* Rotate and shift operations */ 135 enum { RS_RLC, RS_RRC, RS_RL, RS_RR, RS_SLA, RS_SRA, RS_SLL, RS_SRL }; 136 #define _Z80_RS(rs,reg) (0xCB00 + ((rs) << 3) + (reg)) 137 138 /* Bit instructions */ 139 enum { BRS_BIT = 0x40, BRS_RES = 0x80, BRS_SET = 0xC0 }; 140 #define _CHECK_BIT(bit) ((bit) >= 0 && (bit) < 8 ? \ 141 (bit) : \ 142 (error_int_range(bit),0) \ 143 ) 144 #define _Z80_BRS(brs,bit,reg) (0xCB00 + (brs) + (_CHECK_BIT(bit) << 3) + (reg)) 145 146 /* choose value, error if none */ 147 #define _CHOOSE2_(n, i1, o1, i2, o2) \ 148 ((n) == (i1) ? (o1) : \ 149 (n) == (i2) ? (o2) : \ 150 (error_int_range(n), 0)) /* ,0 to transform (void) into (int) */ 151 #define _CHOOSE3_(n, i1, o1, i2, o2, i3, o3) \ 152 ((n) == (i1) ? (o1) : \ 153 _CHOOSE2_((n), (i2), (o2), (i3), (o3))) 154 #define _CHOOSE4_(n, i1, o1, i2, o2, i3, o3, i4, o4) \ 155 ((n) == (i1) ? (o1) : \ 156 _CHOOSE3_((n), (i2), (o2), (i3), (o3), (i4), (o4))) 157 158 /* choose RST opcode */ 159 #define _RST_ARG(n) ((n) < 0 || (n) > 0x38 || (((n) & 7) != 0) ? \ 160 (error_int_range(n),0) : \ 161 ((opts.cpu & CPU_RABBIT) && \ 162 ((n) == 0 || (n) == 8 || (n) == 0x30) ? \ 163 (error_illegal_ident(),0) : \ 164 0xC7 + (n))) 165 166 /* Z80 opcodes 167 * n is a constant 168 * flag is FLAG_NZ, FLAG_... 169 * reg is REG_BC, ... */ 170 #define Z80_ADC(reg) _Z80_ALU(ALU_ADC, (reg)) 171 #define Z80_ADC16(reg) (0xED4A + ((reg) << 4)) 172 #define Z80_ADC_n _Z80_ALU_n(ALU_ADC) 173 #define Z80_ADD(reg) _Z80_ALU(ALU_ADD, (reg)) 174 #define Z80_ADD16(reg) (0x09 + ((reg) << 4)) 175 #define Z80_ADD_n _Z80_ALU_n(ALU_ADD) 176 #define Z80_AND(reg) _Z80_ALU(ALU_AND, (reg)) 177 #define Z80_AND_n _Z80_ALU_n(ALU_AND) 178 #define Z80_BIT(bit,reg) _Z80_BRS(BRS_BIT, (bit), (reg)) 179 #define Z80_CALL 0xCD 180 #define Z80_CALL_FLAG(flag) (0xC4 + ((flag) << 3)) 181 #define Z80_CCF 0x3F 182 #define Z80_CP(reg) _Z80_ALU(ALU_CP, (reg)) 183 #define Z80_CPD 0xEDA9 184 #define Z80_CPDR 0xEDB9 185 #define Z80_CPI 0xEDA1 186 #define Z80_CPIR 0xEDB1 187 #define Z80_CPL 0x2F 188 #define Z80_CP_n _Z80_ALU_n(ALU_CP) 189 #define Z80_DAA _ZILOG_ONLY(0x27) 190 #define Z80_DEC(reg) (0x05 + ((reg) << 3)) 191 #define Z80_DEC16(reg) (0x0B + ((reg) << 4)) 192 #define Z80_DI _ZILOG_ONLY(0xF3) 193 #define Z80_DJNZ 0x10 194 #define Z80_EI _ZILOG_ONLY(0xFB) 195 #define Z80_EXX 0xD9 196 #define Z80_EX_AF_AF 0x08 197 #define Z80_EX_DE_HL 0xEB 198 #define Z80_EX_IND_SP_HL ((opts.cpu & CPU_RABBIT) ? 0xED54 : 0xE3) 199 #define Z80_EX_IND_SP_idx 0xE3 /* (IX) or (IY) */ 200 #define Z80_HALT _ZILOG_ONLY(0x76) 201 #define Z80_IM(n) _ZILOG_ONLY(_CHOOSE3_((n), 0, 0xED46, 1, 0xED56, 2, 0xED5E)) 202 #define Z80_INC(reg) (0x04 + ((reg) << 3)) 203 #define Z80_INC16(reg) (0x03 + ((reg) << 4)) 204 #define Z80_IND _ZILOG_ONLY(0xEDAA) 205 #define Z80_INDR _ZILOG_ONLY(0xEDBA) 206 #define Z80_INI _ZILOG_ONLY(0xEDA2) 207 #define Z80_INIR _ZILOG_ONLY(0xEDB2) 208 #define Z80_IN_A_n _ZILOG_ONLY(0xDB) 209 #define Z80_IN_REG_C(reg) _ZILOG_ONLY((0xED40 + ((reg) << 3))) 210 #define Z80_JP 0xC3 211 #define Z80_JP_FLAG(flag) (0xC2 + ((flag) << 3)) 212 #define Z80_JP_idx 0xE9 /* (HL) or (IX) or (IY) */ 213 #define Z80_JR 0x18 214 #define Z80_JR_FLAG(flag) (0x20 + ((flag) << 3)) 215 #define Z80_LDD 0xEDA8 216 #define Z80_LDDR 0xEDB8 217 #define Z80_LDI 0xEDA0 218 #define Z80_LDIR 0xEDB0 219 #define Z80_LD_A_IND_NN 0x3A 220 #define Z80_LD_A_IND_dd(dd) (0x0A + ((dd) << 4)) 221 #define Z80_LD_IND_NN_A 0x32 222 #define Z80_LD_IND_dd_A(dd) (0x02 + ((dd) << 4)) 223 #define Z80_LD_IND_nn_dd(dd) (0xED43 + ((dd) << 4)) 224 #define Z80_LD_IND_nn_idx 0x22 225 #define Z80_LD_SP_idx 0xF9 226 #define Z80_LD_dd_IND_nn(dd) (0xED4B + ((dd) << 4)) 227 #define Z80_LD_dd_nn(dd) (0x01 + ((dd) << 4)) 228 #define Z80_LD_idx_IND_nn 0x2A 229 #define Z80_LD_r_n(r) (0x06 + ((r) << 3)) 230 #define Z80_LD_r_r(r1,r2) (0x40 + ((r1) << 3) + (r2)) 231 #define Z80_NEG 0xED44 232 #define Z80_NOP 0x00 233 #define Z80_OR(reg) _Z80_ALU(ALU_OR, (reg)) 234 #define Z80_OR_n _Z80_ALU_n(ALU_OR) 235 #define Z80_OTDR _ZILOG_ONLY(0xEDBB) 236 #define Z80_OTIR _ZILOG_ONLY(0xEDB3) 237 #define Z80_OUTD _ZILOG_ONLY(0xEDAB) 238 #define Z80_OUTI _ZILOG_ONLY(0xEDA3) 239 #define Z80_OUT_C_REG(reg) _ZILOG_ONLY((0xED41 + ((reg) << 3))) 240 #define Z80_OUT_n_A _ZILOG_ONLY(0xD3) 241 #define Z80_POP(reg) (0xC1 + ((reg) << 4)) 242 #define Z80_PUSH(reg) (0xC5 + ((reg) << 4)) 243 #define Z80_RES(bit,reg) _Z80_BRS(BRS_RES, (bit), (reg)) 244 #define Z80_RET 0xC9 245 #define Z80_RETI 0xED4D 246 #define Z80_RETN _ZILOG_ONLY(0xED45) 247 #define Z80_RET_FLAG(flag) (0xC0 + ((flag) << 3)) 248 #define Z80_RL(reg) _Z80_RS(RS_RL, (reg)) 249 #define Z80_RLA 0x17 250 #define Z80_RLC(reg) _Z80_RS(RS_RLC, (reg)) 251 #define Z80_RLCA 0x07 252 #define Z80_RLD 0xED6F 253 #define Z80_RR(reg) _Z80_RS(RS_RR, (reg)) 254 #define Z80_RRA 0x1F 255 #define Z80_RRC(reg) _Z80_RS(RS_RRC, (reg)) 256 #define Z80_RRCA 0x0F 257 #define Z80_RRD 0xED67 258 #define Z80_RST(n) _RST_ARG(n) 259 #define Z80_SBC(reg) _Z80_ALU(ALU_SBC, (reg)) 260 #define Z80_SBC16(reg) (0xED42 + ((reg) << 4)) 261 #define Z80_SBC_n _Z80_ALU_n(ALU_SBC) 262 #define Z80_SCF 0x37 263 #define Z80_SET(bit,reg) _Z80_BRS(BRS_SET, (bit), (reg)) 264 #define Z80_SLA(reg) _Z80_RS(RS_SLA, (reg)) 265 #define Z80_SLL(reg) _ZILOG_ONLY(_Z80_RS(RS_SLL, (reg))) 266 #define Z80_SRA(reg) _Z80_RS(RS_SRA, (reg)) 267 #define Z80_SRL(reg) _Z80_RS(RS_SRL, (reg)) 268 #define Z80_SUB(reg) _Z80_ALU(ALU_SUB, (reg)) 269 #define Z80_SUB_n _Z80_ALU_n(ALU_SUB) 270 #define Z80_XOR(reg) _Z80_ALU(ALU_XOR, (reg)) 271 #define Z80_XOR_n _Z80_ALU_n(ALU_XOR) 272 273 #define Z80_LD_I_A _ZILOG_ONLY(0xED47) 274 #define Z80_LD_A_I _ZILOG_ONLY(0xED57) 275 276 #define Z80_LD_R_A _ZILOG_ONLY(0xED4F) 277 #define Z80_LD_A_R _ZILOG_ONLY(0xED5F) 278 279 #define Z80_LD_EIR_A _RABBIT_ONLY(0xED47) 280 #define Z80_LD_A_EIR _RABBIT_ONLY(0xED57) 281 282 #define Z80_LD_IIR_A _RABBIT_ONLY(0xED4F) 283 #define Z80_LD_A_IIR _RABBIT_ONLY(0xED5F) 284 285 /* Z180 opcodes */ 286 #define Z80_SLP _Z180_ONLY(0xED76) 287 #define Z80_MLT(dd) ((opts.cpu & CPU_Z80) ? \ 288 (error_illegal_ident(), 0) : \ 289 (opts.cpu & CPU_RABBIT) && (dd) == REG_SP ? \ 290 (error_illegal_ident(), 0) : \ 291 0xED4C + ((dd) << 4)) 292 #define Z80_IN0(r) _Z180_ONLY(0xED00 + ((r) << 3)) 293 #define Z80_OUT0(r) _Z180_ONLY(0xED01 + ((r) << 3)) 294 #define Z80_OTIM _Z180_ONLY(0xED83) 295 #define Z80_OTIMR _Z180_ONLY(0xED93) 296 #define Z80_OTDM _Z180_ONLY(0xED8B) 297 #define Z80_OTDMR _Z180_ONLY(0xED9B) 298 #define Z80_TSTIO _Z180_ONLY(0xED74) 299 #define Z80_TST(r) _EXCEPT_Z80(0xED04 + ((r) << 3)) 300 #define Z80_TST_n _EXCEPT_Z80(0xED64) 301 302 /* Rabbit opcodes */ 303 #define Z80_IOI _RABBIT_ONLY(0xD3) 304 #define Z80_IOE _RABBIT_ONLY(0xDB) 305 #define Z80_ALTD _RABBIT_ONLY(0x76) 306 #define Z80_IPRES _RABBIT_ONLY(0xED5D) 307 #define Z80_IPSET(n) _RABBIT_ONLY(_CHOOSE4_((n), 0, 0xED46, 1, 0xED56, 2, 0xED4E, 3, 0xED5E)) 308 #define Z80_BOOL _RABBIT_ONLY(0xCC) 309 #define Z80_ADD_SP_d _RABBIT_ONLY(0x27) 310 #define Z80_AND_HL_DE _RABBIT_ONLY(0xDC) 311 #define Z80_OR_HL_DE _RABBIT_ONLY(0xEC) 312 #define Z80_BOOL _RABBIT_ONLY(0xCC) 313 #define Z80_EX_DE1_HL _RABBIT_ONLY(0xE3) 314 #define Z80_EX_DE_HL1 _RABBIT_ONLY(0x76EB) 315 #define Z80_EX_DE1_HL1 _RABBIT_ONLY(0x76E3) 316 #define Z80_MUL _RABBIT_ONLY(0xF7) 317 #define Z80_IDET _RCM3000_ONLY(0x5B) 318 #define Z80_RDMODE _RCM3000_ONLY(0xED7F) 319 #define Z80_SETUSR _RCM3000_ONLY(0xED6F) 320 #define Z80_SURES _RCM3000_ONLY(0xED7D) 321 #define Z80_SYSCALL _RCM3000_ONLY(0xED75) 322 #define Z80_UMA _RCM3000_ONLY(0xEDC0) 323 #define Z80_UMS _RCM3000_ONLY(0xEDC8) 324 325 #define Z80_LD_IND_HL_d_HL _RABBIT_ONLY(0xDDF4) 326 #define Z80_LD_IND_IX_d_HL _RABBIT_ONLY( 0xF4) 327 #define Z80_LD_IND_IY_d_HL _RABBIT_ONLY(0xFDF4) 328 329 #define Z80_LD_HL_IND_HL_d _RABBIT_ONLY(0xDDE4) 330 #define Z80_LD_HL_IND_IX_d _RABBIT_ONLY( 0xE4) 331 #define Z80_LD_HL_IND_IY_d _RABBIT_ONLY(0xFDE4) 332 333 #define Z80_LD_IND_SP_n_HL _RABBIT_ONLY(0xD4) 334 #define Z80_LD_HL_IND_SP_n _RABBIT_ONLY(0xC4) 335 336 #define Z80_LD_A_XPC _RABBIT_ONLY(0xED77) 337 #define Z80_LD_XPC_A _RABBIT_ONLY(0xED67) 338 #define Z80_LD_dd1_BC(dd) _RABBIT_ONLY(0xED49 + ((dd) << 4)) 339 #define Z80_LD_dd1_DE(dd) _RABBIT_ONLY(0xED41 + ((dd) << 4)) 340 341 #define Z80_LD_HL_IX _RABBIT_ONLY(0xDD7C) 342 #define Z80_LD_HL_IY _RABBIT_ONLY(0xFD7C) 343 344 #define Z80_LD_IX_HL _RABBIT_ONLY(0xDD7D) 345 #define Z80_LD_IY_HL _RABBIT_ONLY(0xFD7D) 346 347 #define Z80_LDISR _RCM3000_ONLY(0xED90) 348 #define Z80_LDDSR _RCM3000_ONLY(0xED98) 349 #define Z80_LSDR _RCM3000_ONLY(0xEDF8) 350 #define Z80_LSIR _RCM3000_ONLY(0xEDF0) 351 #define Z80_LSDDR _RCM3000_ONLY(0xEDD8) 352 #define Z80_LSIDR _RCM3000_ONLY(0xEDD0) 353 354 #define Z80_LDP_IND_HL_HL _RABBIT_ONLY(0xED64) 355 #define Z80_LDP_IND_IX_HL _RABBIT_ONLY(0xDD64) 356 #define Z80_LDP_IND_IY_HL _RABBIT_ONLY(0xFD64) 357 358 #define Z80_LDP_HL_IND_HL _RABBIT_ONLY(0xED6C) 359 #define Z80_LDP_HL_IND_IX _RABBIT_ONLY(0xDD6C) 360 #define Z80_LDP_HL_IND_IY _RABBIT_ONLY(0xFD6C) 361 362 #define Z80_LDP_IND_mn_HL _RABBIT_ONLY(0xED65) 363 #define Z80_LDP_IND_mn_IX _RABBIT_ONLY(0xDD65) 364 #define Z80_LDP_IND_mn_IY _RABBIT_ONLY(0xFD65) 365 366 #define Z80_LDP_HL_IND_mn _RABBIT_ONLY(0xED6D) 367 #define Z80_LDP_IX_IND_mn _RABBIT_ONLY(0xDD6D) 368 #define Z80_LDP_IY_IND_mn _RABBIT_ONLY(0xFD6D) 369 370 #define Z80_POP_IP _RABBIT_ONLY(0xED7E) 371 #define Z80_POP_SU _RCM3000_ONLY(0xED6E) 372 #define Z80_PUSH_IP _RABBIT_ONLY(0xED76) 373 #define Z80_PUSH_SU _RCM3000_ONLY(0xED66) 374 375 #define Z80_RL_DE _RABBIT_ONLY(0xF3) 376 #define Z80_RR_DE _RABBIT_ONLY(0xFB) 377 #define Z80_RR_HL _RABBIT_ONLY(0xFC) 378 #define Z80_RR_IX _RABBIT_ONLY(0xDDFC) 379 #define Z80_RR_IY _RABBIT_ONLY(0xFDFC) 380