1 /* 2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and 3 * VA Linux Systems Inc., Fremont, California. 4 * 5 * All Rights Reserved. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining 8 * a copy of this software and associated documentation files (the 9 * "Software"), to deal in the Software without restriction, including 10 * without limitation on the rights to use, copy, modify, merge, 11 * publish, distribute, sublicense, and/or sell copies of the Software, 12 * and to permit persons to whom the Software is furnished to do so, 13 * subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the 16 * next paragraph) shall be included in all copies or substantial 17 * portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 20 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 22 * NON-INFRINGEMENT. IN NO EVENT SHALL ATI, VA LINUX SYSTEMS AND/OR 23 * THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 24 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 26 * DEALINGS IN THE SOFTWARE. 27 */ 28 /* 29 * Authors: 30 * Kevin E. Martin <martin@xfree86.org> 31 * Rickard E. Faith <faith@valinux.com> 32 * Alan Hourihane <alanh@fairlite.demon.co.uk> 33 * 34 * References: 35 * 36 * !!!! FIXME !!!! 37 * RAGE 128 VR/ RAGE 128 GL Register Reference Manual (Technical 38 * Reference Manual P/N RRG-G04100-C Rev. 0.04), ATI Technologies: April 39 * 1999. 40 * 41 * !!!! FIXME !!!! 42 * RAGE 128 Software Development Manual (Technical Reference Manual P/N 43 * SDK-G04000 Rev. 0.01), ATI Technologies: June 1999. 44 * 45 */ 46 47 /* !!!! FIXME !!!! NOTE: THIS FILE HAS BEEN CONVERTED FROM r128_reg.h 48 * AND CONTAINS REGISTERS AND REGISTER DEFINITIONS THAT ARE NOT CORRECT 49 * ON THE RADEON. A FULL AUDIT OF THIS CODE IS NEEDED! */ 50 51 #ifndef __RADEON_REGS_H__ 52 #define __RADEON_REGS_H__ 53 54 #ifdef ROP_XOR 55 #undef ROP_XOR 56 #endif 57 58 #ifdef ROP_COPY 59 #undef ROP_COPY 60 #endif 61 62 63 /* Registers for 2D/Video/Overlay */ 64 #define CONFIG_VENDOR_ID 0x0f00 /* PCI */ 65 #define CONFIG_DEVICE_ID 0x0f02 /* PCI */ 66 #define CONFIG_ADAPTER_ID 0x0f2c /* PCI */ 67 68 #define AGP_BASE 0x0170 69 #define AGP_CNTL 0x0174 70 # define AGP_APER_SIZE_256MB (0x00 << 0) 71 # define AGP_APER_SIZE_128MB (0x20 << 0) 72 # define AGP_APER_SIZE_64MB (0x30 << 0) 73 # define AGP_APER_SIZE_32MB (0x38 << 0) 74 # define AGP_APER_SIZE_16MB (0x3c << 0) 75 # define AGP_APER_SIZE_8MB (0x3e << 0) 76 # define AGP_APER_SIZE_4MB (0x3f << 0) 77 # define AGP_APER_SIZE_MASK (0x3f << 0) 78 #define AGP_COMMAND 0x0f60 /* PCI */ 79 #define AGP_COMMAND_PCI_CONFIG 0x0060 /* offset in PCI config*/ 80 # define AGP_ENABLE (1<<8) 81 #define AGP_PLL_CNTL 0x000b /* PLL */ 82 #define AGP_STATUS 0x0f5c /* PCI */ 83 # define AGP_1X_MODE 0x01 84 # define AGP_2X_MODE 0x02 85 # define AGP_4X_MODE 0x04 86 # define AGP_FW_MODE 0x10 87 # define AGP_MODE_MASK 0x17 88 #define ATTRDR 0x03c1 /* VGA */ 89 #define ATTRDW 0x03c0 /* VGA */ 90 #define ATTRX 0x03c0 /* VGA */ 91 #define AUX_SC_CNTL 0x1660 92 # define AUX1_SC_EN (1 << 0) 93 # define AUX1_SC_MODE_OR (0 << 1) 94 # define AUX1_SC_MODE_NAND (1 << 1) 95 # define AUX2_SC_EN (1 << 2) 96 # define AUX2_SC_MODE_OR (0 << 3) 97 # define AUX2_SC_MODE_NAND (1 << 3) 98 # define AUX3_SC_EN (1 << 4) 99 # define AUX3_SC_MODE_OR (0 << 5) 100 # define AUX3_SC_MODE_NAND (1 << 5) 101 #define AUX1_SC_BOTTOM 0x1670 102 #define AUX1_SC_LEFT 0x1664 103 #define AUX1_SC_RIGHT 0x1668 104 #define AUX1_SC_TOP 0x166c 105 #define AUX2_SC_BOTTOM 0x1680 106 #define AUX2_SC_LEFT 0x1674 107 #define AUX2_SC_RIGHT 0x1678 108 #define AUX2_SC_TOP 0x167c 109 #define AUX3_SC_BOTTOM 0x1690 110 #define AUX3_SC_LEFT 0x1684 111 #define AUX3_SC_RIGHT 0x1688 112 #define AUX3_SC_TOP 0x168c 113 #define AUX_WINDOW_HORZ_CNTL 0x02d8 114 #define AUX_WINDOW_VERT_CNTL 0x02dc 115 116 #define BASE_CODE 0x0f0b 117 #define BIOS_0_SCRATCH 0x0010 118 #define BIOS_1_SCRATCH 0x0014 119 #define BIOS_2_SCRATCH 0x0018 120 #define BIOS_3_SCRATCH 0x001c 121 #define BIOS_4_SCRATCH 0x0020 122 #define BIOS_5_SCRATCH 0x0024 123 #define BIOS_6_SCRATCH 0x0028 124 #define BIOS_7_SCRATCH 0x002c 125 #define BIOS_ROM 0x0f30 /* PCI */ 126 #define BIST 0x0f0f /* PCI */ 127 #define BRUSH_DATA0 0x1480 128 #define BRUSH_DATA1 0x1484 129 #define BRUSH_DATA10 0x14a8 130 #define BRUSH_DATA11 0x14ac 131 #define BRUSH_DATA12 0x14b0 132 #define BRUSH_DATA13 0x14b4 133 #define BRUSH_DATA14 0x14b8 134 #define BRUSH_DATA15 0x14bc 135 #define BRUSH_DATA16 0x14c0 136 #define BRUSH_DATA17 0x14c4 137 #define BRUSH_DATA18 0x14c8 138 #define BRUSH_DATA19 0x14cc 139 #define BRUSH_DATA2 0x1488 140 #define BRUSH_DATA20 0x14d0 141 #define BRUSH_DATA21 0x14d4 142 #define BRUSH_DATA22 0x14d8 143 #define BRUSH_DATA23 0x14dc 144 #define BRUSH_DATA24 0x14e0 145 #define BRUSH_DATA25 0x14e4 146 #define BRUSH_DATA26 0x14e8 147 #define BRUSH_DATA27 0x14ec 148 #define BRUSH_DATA28 0x14f0 149 #define BRUSH_DATA29 0x14f4 150 #define BRUSH_DATA3 0x148c 151 #define BRUSH_DATA30 0x14f8 152 #define BRUSH_DATA31 0x14fc 153 #define BRUSH_DATA32 0x1500 154 #define BRUSH_DATA33 0x1504 155 #define BRUSH_DATA34 0x1508 156 #define BRUSH_DATA35 0x150c 157 #define BRUSH_DATA36 0x1510 158 #define BRUSH_DATA37 0x1514 159 #define BRUSH_DATA38 0x1518 160 #define BRUSH_DATA39 0x151c 161 #define BRUSH_DATA4 0x1490 162 #define BRUSH_DATA40 0x1520 163 #define BRUSH_DATA41 0x1524 164 #define BRUSH_DATA42 0x1528 165 #define BRUSH_DATA43 0x152c 166 #define BRUSH_DATA44 0x1530 167 #define BRUSH_DATA45 0x1534 168 #define BRUSH_DATA46 0x1538 169 #define BRUSH_DATA47 0x153c 170 #define BRUSH_DATA48 0x1540 171 #define BRUSH_DATA49 0x1544 172 #define BRUSH_DATA5 0x1494 173 #define BRUSH_DATA50 0x1548 174 #define BRUSH_DATA51 0x154c 175 #define BRUSH_DATA52 0x1550 176 #define BRUSH_DATA53 0x1554 177 #define BRUSH_DATA54 0x1558 178 #define BRUSH_DATA55 0x155c 179 #define BRUSH_DATA56 0x1560 180 #define BRUSH_DATA57 0x1564 181 #define BRUSH_DATA58 0x1568 182 #define BRUSH_DATA59 0x156c 183 #define BRUSH_DATA6 0x1498 184 #define BRUSH_DATA60 0x1570 185 #define BRUSH_DATA61 0x1574 186 #define BRUSH_DATA62 0x1578 187 #define BRUSH_DATA63 0x157c 188 #define BRUSH_DATA7 0x149c 189 #define BRUSH_DATA8 0x14a0 190 #define BRUSH_DATA9 0x14a4 191 #define BRUSH_SCALE 0x1470 192 #define BRUSH_Y_X 0x1474 193 #define BUS_CNTL 0x0030 194 # define BUS_MASTER_DIS (1 << 6) 195 # define BUS_RD_DISCARD_EN (1 << 24) 196 # define BUS_RD_ABORT_EN (1 << 25) 197 # define BUS_MSTR_DISCONNECT_EN (1 << 28) 198 # define BUS_WRT_BURST (1 << 29) 199 # define BUS_READ_BURST (1 << 30) 200 #define BUS_CNTL1 0x0034 201 # define BUS_WAIT_ON_LOCK_EN (1 << 4) 202 203 #define CACHE_CNTL 0x1724 204 #define CACHE_LINE 0x0f0c /* PCI */ 205 #define CAP0_TRIG_CNTL 0x0950 /* ? */ 206 #define CAP1_TRIG_CNTL 0x09c0 /* ? */ 207 #define CAPABILITIES_ID 0x0f50 /* PCI */ 208 #define CAPABILITIES_PTR 0x0f34 /* PCI */ 209 #define CLK_PIN_CNTL 0x0001 /* PLL */ 210 # define SCLK_DYN_START_CNTL (1 << 15) 211 #define CLOCK_CNTL_DATA 0x000c 212 #define CLOCK_CNTL_INDEX 0x0008 213 # define PLL_WR_EN (1 << 7) 214 # define PLL_DIV_SEL (3 << 8) 215 # define PLL2_DIV_SEL_MASK ~(3 << 8) 216 #define CLK_PWRMGT_CNTL 0x0014 217 # define ENGIN_DYNCLK_MODE (1 << 12) 218 # define ACTIVE_HILO_LAT_MASK (3 << 13) 219 # define ACTIVE_HILO_LAT_SHIFT 13 220 # define DISP_DYN_STOP_LAT_MASK (1 << 12) 221 # define DYN_STOP_MODE_MASK (7 << 21) 222 #define PLL_PWRMGT_CNTL 0x0015 223 # define TCL_BYPASS_DISABLE (1 << 20) 224 #define CLR_CMP_CLR_3D 0x1a24 225 #define CLR_CMP_CLR_DST 0x15c8 226 #define CLR_CMP_CLR_SRC 0x15c4 227 #define CLR_CMP_CNTL 0x15c0 228 # define SRC_CMP_EQ_COLOR (4 << 0) 229 # define SRC_CMP_NEQ_COLOR (5 << 0) 230 # define CLR_CMP_SRC_SOURCE (1 << 24) 231 #define CLR_CMP_MASK 0x15cc 232 # define CLR_CMP_MSK 0xffffffff 233 #define CLR_CMP_MASK_3D 0x1A28 234 #define COMMAND 0x0f04 /* PCI */ 235 #define COMPOSITE_SHADOW_ID 0x1a0c 236 #define CONFIG_APER_0_BASE 0x0100 237 #define CONFIG_APER_1_BASE 0x0104 238 #define CONFIG_APER_SIZE 0x0108 239 #define CONFIG_BONDS 0x00e8 240 #define CONFIG_CNTL 0x00e0 241 # define CFG_ATI_REV_A11 (0 << 16) 242 # define CFG_ATI_REV_A12 (1 << 16) 243 # define CFG_ATI_REV_A13 (2 << 16) 244 # define CFG_ATI_REV_ID_MASK (0xf << 16) 245 #define CONFIG_MEMSIZE 0x00f8 246 #define CONFIG_MEMSIZE_EMBEDDED 0x0114 247 #define CONFIG_REG_1_BASE 0x010c 248 #define CONFIG_REG_APER_SIZE 0x0110 249 #define CONFIG_XSTRAP 0x00e4 250 #define CONSTANT_COLOR_C 0x1d34 251 # define CONSTANT_COLOR_MASK 0x00ffffff 252 # define CONSTANT_COLOR_ONE 0x00ffffff 253 # define CONSTANT_COLOR_ZERO 0x00000000 254 #define CRC_CMDFIFO_ADDR 0x0740 255 #define CRC_CMDFIFO_DOUT 0x0744 256 #define GRPH_BUFFER_CNTL 0x02f0 257 # define GRPH_START_REQ_MASK (0x7f) 258 # define GRPH_START_REQ_SHIFT 0 259 # define GRPH_STOP_REQ_MASK (0x7f<<8) 260 # define GRPH_STOP_REQ_SHIFT 8 261 # define GRPH_CRITICAL_POINT_MASK (0x7f<<16) 262 # define GRPH_CRITICAL_POINT_SHIFT 16 263 # define GRPH_CRITICAL_CNTL (1<<28) 264 # define GRPH_BUFFER_SIZE (1<<29) 265 # define GRPH_CRITICAL_AT_SOF (1<<30) 266 # define GRPH_STOP_CNTL (1<<31) 267 #define GRPH2_BUFFER_CNTL 0x03f0 268 # define GRPH2_START_REQ_MASK (0x7f) 269 # define GRPH2_START_REQ_SHIFT 0 270 # define GRPH2_STOP_REQ_MASK (0x7f<<8) 271 # define GRPH2_STOP_REQ_SHIFT 8 272 # define GRPH2_CRITICAL_POINT_MASK (0x7f<<16) 273 # define GRPH2_CRITICAL_POINT_SHIFT 16 274 # define GRPH2_CRITICAL_CNTL (1<<28) 275 # define GRPH2_BUFFER_SIZE (1<<29) 276 # define GRPH2_CRITICAL_AT_SOF (1<<30) 277 # define GRPH2_STOP_CNTL (1<<31) 278 #define CRTC_CRNT_FRAME 0x0214 279 #define CRTC_EXT_CNTL 0x0054 280 # define CRTC_VGA_XOVERSCAN (1 << 0) 281 # define VGA_ATI_LINEAR (1 << 3) 282 # define XCRT_CNT_EN (1 << 6) 283 # define CRTC_HSYNC_DIS (1 << 8) 284 # define CRTC_VSYNC_DIS (1 << 9) 285 # define CRTC_DISPLAY_DIS (1 << 10) 286 # define CRTC_SYNC_TRISTAT (1 << 11) 287 # define CRTC_CRT_ON (1 << 15) 288 #define CRTC_EXT_CNTL_DPMS_BYTE 0x0055 289 # define CRTC_HSYNC_DIS_BYTE (1 << 0) 290 # define CRTC_VSYNC_DIS_BYTE (1 << 1) 291 # define CRTC_DISPLAY_DIS_BYTE (1 << 2) 292 #define CRTC_GEN_CNTL 0x0050 293 # define CRTC_DBL_SCAN_EN (1 << 0) 294 # define CRTC_INTERLACE_EN (1 << 1) 295 # define CRTC_CSYNC_EN (1 << 4) 296 # define CRTC_CUR_EN (1 << 16) 297 # define CRTC_CUR_MODE_MASK (7 << 17) 298 # define CRTC_ICON_EN (1 << 20) 299 # define CRTC_EXT_DISP_EN (1 << 24) 300 # define CRTC_EN (1 << 25) 301 # define CRTC_DISP_REQ_EN_B (1 << 26) 302 #define CRTC2_GEN_CNTL 0x03f8 303 # define CRTC2_DBL_SCAN_EN (1 << 0) 304 # define CRTC2_INTERLACE_EN (1 << 1) 305 # define CRTC2_SYNC_TRISTAT (1 << 4) 306 # define CRTC2_HSYNC_TRISTAT (1 << 5) 307 # define CRTC2_VSYNC_TRISTAT (1 << 6) 308 # define CRTC2_CRT2_ON (1 << 7) 309 # define CRTC2_ICON_EN (1 << 15) 310 # define CRTC2_CUR_EN (1 << 16) 311 # define CRTC2_CUR_MODE_MASK (7 << 20) 312 # define CRTC2_DISP_DIS (1 << 23) 313 # define CRTC2_EN (1 << 25) 314 # define CRTC2_DISP_REQ_EN_B (1 << 26) 315 # define CRTC2_CSYNC_EN (1 << 27) 316 # define CRTC2_HSYNC_DIS (1 << 28) 317 # define CRTC2_VSYNC_DIS (1 << 29) 318 #define CRTC_MORE_CNTL 0x27c 319 # define CRTC_H_CUTOFF_ACTIVE_EN (1<<4) 320 # define CRTC_V_CUTOFF_ACTIVE_EN (1<<5) 321 #define CRTC_GUI_TRIG_VLINE 0x0218 322 #define CRTC_H_SYNC_STRT_WID 0x0204 323 # define CRTC_H_SYNC_STRT_PIX (0x07 << 0) 324 # define CRTC_H_SYNC_STRT_CHAR (0x3ff << 3) 325 # define CRTC_H_SYNC_STRT_CHAR_SHIFT 3 326 # define CRTC_H_SYNC_WID (0x3f << 16) 327 # define CRTC_H_SYNC_WID_SHIFT 16 328 # define CRTC_H_SYNC_POL (1 << 23) 329 #define CRTC2_H_SYNC_STRT_WID 0x0304 330 # define CRTC2_H_SYNC_STRT_PIX (0x07 << 0) 331 # define CRTC2_H_SYNC_STRT_CHAR (0x3ff << 3) 332 # define CRTC2_H_SYNC_STRT_CHAR_SHIFT 3 333 # define CRTC2_H_SYNC_WID (0x3f << 16) 334 # define CRTC2_H_SYNC_WID_SHIFT 16 335 # define CRTC2_H_SYNC_POL (1 << 23) 336 #define CRTC_H_TOTAL_DISP 0x0200 337 # define CRTC_H_TOTAL (0x03ff << 0) 338 # define CRTC_H_TOTAL_SHIFT 0 339 # define CRTC_H_DISP (0x01ff << 16) 340 # define CRTC_H_DISP_SHIFT 16 341 #define CRTC2_H_TOTAL_DISP 0x0300 342 # define CRTC2_H_TOTAL (0x03ff << 0) 343 # define CRTC2_H_TOTAL_SHIFT 0 344 # define CRTC2_H_DISP (0x01ff << 16) 345 # define CRTC2_H_DISP_SHIFT 16 346 #define CRTC_OFFSET 0x0224 347 #define CRTC2_OFFSET 0x0324 348 #define CRTC_OFFSET_CNTL 0x0228 349 # define CRTC_TILE_EN (1 << 15) 350 # define CRTC_HSYNC_EN (1 << 16) 351 #define CRTC2_OFFSET_CNTL 0x0328 352 # define CRTC2_TILE_EN (1 << 15) 353 #define CRTC_PITCH 0x022c 354 #define CRTC2_PITCH 0x032c 355 #define CRTC_STATUS 0x005c 356 # define CRTC_VBLANK_SAVE (1 << 1) 357 # define CRTC_VBLANK_SAVE_CLEAR (1 << 1) 358 #define CRTC2_STATUS 0x03fc 359 # define CRTC2_VBLANK_SAVE (1 << 1) 360 # define CRTC2_VBLANK_SAVE_CLEAR (1 << 1) 361 #define CRTC_V_SYNC_STRT_WID 0x020c 362 # define CRTC_V_SYNC_STRT (0x7ff << 0) 363 # define CRTC_V_SYNC_STRT_SHIFT 0 364 # define CRTC_V_SYNC_WID (0x1f << 16) 365 # define CRTC_V_SYNC_WID_SHIFT 16 366 # define CRTC_V_SYNC_POL (1 << 23) 367 #define CRTC2_V_SYNC_STRT_WID 0x030c 368 # define CRTC2_V_SYNC_STRT (0x7ff << 0) 369 # define CRTC2_V_SYNC_STRT_SHIFT 0 370 # define CRTC2_V_SYNC_WID (0x1f << 16) 371 # define CRTC2_V_SYNC_WID_SHIFT 16 372 # define CRTC2_V_SYNC_POL (1 << 23) 373 #define CRTC_V_TOTAL_DISP 0x0208 374 # define CRTC_V_TOTAL (0x07ff << 0) 375 # define CRTC_V_TOTAL_SHIFT 0 376 # define CRTC_V_DISP (0x07ff << 16) 377 # define CRTC_V_DISP_SHIFT 16 378 #define CRTC2_V_TOTAL_DISP 0x0308 379 # define CRTC2_V_TOTAL (0x07ff << 0) 380 # define CRTC2_V_TOTAL_SHIFT 0 381 # define CRTC2_V_DISP (0x07ff << 16) 382 # define CRTC2_V_DISP_SHIFT 16 383 #define CRTC_VLINE_CRNT_VLINE 0x0210 384 # define CRTC_CRNT_VLINE_MASK (0x7ff << 16) 385 #define CRTC2_CRNT_FRAME 0x0314 386 #define CRTC2_GUI_TRIG_VLINE 0x0318 387 #define CRTC2_STATUS 0x03fc 388 #define CRTC2_VLINE_CRNT_VLINE 0x0310 389 #define CRTC8_DATA 0x03d5 /* VGA, 0x3b5 */ 390 #define CRTC8_IDX 0x03d4 /* VGA, 0x3b4 */ 391 #define CUR_CLR0 0x026c 392 #define CUR_CLR1 0x0270 393 #define CUR_HORZ_VERT_OFF 0x0268 394 #define CUR_HORZ_VERT_POSN 0x0264 395 #define CUR_OFFSET 0x0260 396 # define CUR_LOCK (1 << 31) 397 #define CUR2_CLR0 0x036c 398 #define CUR2_CLR1 0x0370 399 #define CUR2_HORZ_VERT_OFF 0x0368 400 #define CUR2_HORZ_VERT_POSN 0x0364 401 #define CUR2_OFFSET 0x0360 402 # define CUR2_LOCK (1 << 31) 403 404 #define DAC_CNTL 0x0058 405 # define DAC_RANGE_CNTL (3 << 0) 406 # define DAC_RANGE_CNTL_MASK 0x03 407 # define DAC_BLANKING (1 << 2) 408 # define DAC_CMP_EN (1 << 3) 409 # define DAC_CMP_OUTPUT (1 << 7) 410 # define DAC_8BIT_EN (1 << 8) 411 # define DAC_TVO_EN (1 << 10) 412 # define DAC_VGA_ADR_EN (1 << 13) 413 # define DAC_PDWN (1 << 15) 414 # define DAC_MASK_ALL (0xff << 24) 415 #define DAC_CNTL2 0x007c 416 # define DAC2_DAC_CLK_SEL (1 << 0) 417 # define DAC2_DAC2_CLK_SEL (1 << 1) 418 # define DAC2_PALETTE_ACC_CTL (1 << 5) 419 #define DAC_EXT_CNTL 0x0280 420 # define DAC_FORCE_BLANK_OFF_EN (1 << 4) 421 # define DAC_FORCE_DATA_EN (1 << 5) 422 # define DAC_FORCE_DATA_SEL_MASK (3 << 6) 423 # define DAC_FORCE_DATA_MASK 0x0003ff00 424 # define DAC_FORCE_DATA_SHIFT 8 425 #define DAC_MACRO_CNTL 0x0d04 426 # define DAC_PDWN_R (1 << 16) 427 # define DAC_PDWN_G (1 << 17) 428 # define DAC_PDWN_B (1 << 18) 429 #define DISP_HW_DEBUG 0x0d14 430 # define CRT2_DISP1_SEL (1 << 5) 431 #define DISP_OUTPUT_CNTL 0x0d64 432 # define DISP_DAC_SOURCE_MASK 0x03 433 # define DISP_DAC2_SOURCE_MASK 0x0c 434 # define DISP_DAC_SOURCE_CRTC2 0x01 435 # define DISP_DAC2_SOURCE_CRTC2 0x04 436 # define DISP_TV_SOURCE (1 << 16) 437 # define DISP_TV_MODE_MASK (3 << 17) 438 # define DISP_TV_MODE_888 (0 << 17) 439 # define DISP_TV_MODE_565 (1 << 17) 440 # define DISP_TV_YG_DITH_EN (1 << 19) 441 # define DISP_TV_CBB_CRR_DITH_EN (1 << 20) 442 # define DISP_TV_BIT_WIDTH (1 << 21) 443 # define DISP_TV_SYNC_MODE_MASK (3 << 22) 444 # define DISP_TV_SYNC_COLOR_MASK (3 << 25) 445 #define DAC_CRC_SIG 0x02cc 446 #define DAC_DATA 0x03c9 /* VGA */ 447 #define DAC_MASK 0x03c6 /* VGA */ 448 #define DAC_R_INDEX 0x03c7 /* VGA */ 449 #define DAC_W_INDEX 0x03c8 /* VGA */ 450 #define DDA_CONFIG 0x02e0 451 #define DDA_ON_OFF 0x02e4 452 #define DEFAULT_OFFSET 0x16e0 453 #define DEFAULT_PITCH 0x16e4 454 #define DEFAULT_SC_BOTTOM_RIGHT 0x16e8 455 # define DEFAULT_SC_RIGHT_MAX (0x1fff << 0) 456 # define DEFAULT_SC_BOTTOM_MAX (0x1fff << 16) 457 #define DESTINATION_3D_CLR_CMP_VAL 0x1820 458 #define DESTINATION_3D_CLR_CMP_MSK 0x1824 459 #define DISP_MISC_CNTL 0x0d00 460 # define SOFT_RESET_GRPH_PP (1 << 0) 461 #define DISP_MERGE_CNTL 0x0d60 462 # define DISP_ALPHA_MODE_MASK 0x03 463 # define DISP_ALPHA_MODE_KEY 0 464 # define DISP_ALPHA_MODE_PER_PIXEL 1 465 # define DISP_ALPHA_MODE_GLOBAL 2 466 # define DISP_RGB_OFFSET_EN (1<<8) 467 # define DISP_GRPH_ALPHA_MASK (0xff << 16) 468 # define DISP_OV0_ALPHA_MASK (0xff << 24) 469 # define DISP_LIN_TRANS_BYPASS (0x01 << 9) 470 #define DISP2_MERGE_CNTL 0x0d68 471 # define DISP2_RGB_OFFSET_EN (1<<8) 472 #define DISP_LIN_TRANS_GRPH_A 0x0d80 473 #define DISP_LIN_TRANS_GRPH_B 0x0d84 474 #define DISP_LIN_TRANS_GRPH_C 0x0d88 475 #define DISP_LIN_TRANS_GRPH_D 0x0d8c 476 #define DISP_LIN_TRANS_GRPH_E 0x0d90 477 #define DISP_LIN_TRANS_GRPH_F 0x0d98 478 #define DP_BRUSH_BKGD_CLR 0x1478 479 #define DP_BRUSH_FRGD_CLR 0x147c 480 #define DP_CNTL 0x16c0 481 # define DST_X_LEFT_TO_RIGHT (1 << 0) 482 # define DST_Y_TOP_TO_BOTTOM (1 << 1) 483 #define DP_CNTL_XDIR_YDIR_YMAJOR 0x16d0 484 # define DST_Y_MAJOR (1 << 2) 485 # define DST_Y_DIR_TOP_TO_BOTTOM (1 << 15) 486 # define DST_X_DIR_LEFT_TO_RIGHT (1 << 31) 487 #define DP_DATATYPE 0x16c4 488 # define DST_8BPP 0x00000002 489 # define DST_15BPP 0x00000003 490 # define DST_16BPP 0x00000004 491 # define DST_24BPP 0x00000005 492 # define DST_32BPP 0x00000006 493 # define DST_8BPP_RGB332 0x00000007 494 # define DST_8BPP_Y8 0x00000008 495 # define DST_8BPP_RGB8 0x00000009 496 # define DST_16BPP_VYUY422 0x0000000b 497 # define DST_16BPP_YVYU422 0x0000000c 498 # define DST_32BPP_AYUV444 0x0000000e 499 # define DST_16BPP_ARGB4444 0x0000000f 500 # define BRUSH_SOLIDCOLOR 0x00000d00 501 # define SRC_MONO 0x00000000 502 # define SRC_MONO_LBKGD 0x00010000 503 # define SRC_DSTCOLOR 0x00030000 504 # define BYTE_ORDER_MSB_TO_LSB 0x00000000 505 # define BYTE_ORDER_LSB_TO_MSB 0x40000000 506 # define DP_CONVERSION_TEMP 0x80000000 507 # define HOST_BIG_ENDIAN_EN (1 << 29) 508 #define DP_GUI_MASTER_CNTL 0x146c 509 # define GMC_SRC_PITCH_OFFSET_CNTL (1 << 0) 510 # define GMC_DST_PITCH_OFFSET_CNTL (1 << 1) 511 # define GMC_SRC_CLIPPING (1 << 2) 512 # define GMC_DST_CLIPPING (1 << 3) 513 # define GMC_BRUSH_DATATYPE_MASK (0x0f << 4) 514 # define GMC_BRUSH_8X8_MONO_FG_BG (0 << 4) 515 # define GMC_BRUSH_8X8_MONO_FG_LA (1 << 4) 516 # define GMC_BRUSH_1X8_MONO_FG_BG (4 << 4) 517 # define GMC_BRUSH_1X8_MONO_FG_LA (5 << 4) 518 # define GMC_BRUSH_32x1_MONO_FG_BG (6 << 4) 519 # define GMC_BRUSH_32x1_MONO_FG_LA (7 << 4) 520 # define GMC_BRUSH_32x32_MONO_FG_BG (8 << 4) 521 # define GMC_BRUSH_32x32_MONO_FG_LA (9 << 4) 522 # define GMC_BRUSH_8x8_COLOR (10 << 4) 523 # define GMC_BRUSH_1X8_COLOR (12 << 4) 524 # define GMC_BRUSH_SOLID_COLOR (13 << 4) 525 # define GMC_BRUSH_NONE (15 << 4) 526 # define GMC_DST_8BPP (2 << 8) 527 # define GMC_DST_15BPP (3 << 8) 528 # define GMC_DST_16BPP (4 << 8) 529 # define GMC_DST_24BPP (5 << 8) 530 # define GMC_DST_32BPP (6 << 8) 531 # define GMC_DST_8BPP_RGB (7 << 8) 532 # define GMC_DST_Y8 (8 << 8) 533 # define GMC_DST_RGB8 (9 << 8) 534 # define GMC_DST_VYUY (11 << 8) 535 # define GMC_DST_YVYU (12 << 8) 536 # define GMC_DST_AYUV444 (14 << 8) 537 # define GMC_DST_ARGB4444 (15 << 8) 538 # define GMC_DST_DATATYPE_MASK (0x0f << 8) 539 # define GMC_DST_DATATYPE_SHIFT 8 540 # define GMC_SRC_DATATYPE_MASK (3 << 12) 541 # define GMC_SRC_DATATYPE_MONO_FG_BG (0 << 12) 542 # define GMC_SRC_DATATYPE_MONO_FG_LA (1 << 12) 543 # define GMC_SRC_DATATYPE_COLOR (3 << 12) 544 # define GMC_BYTE_PIX_ORDER (1 << 14) 545 # define GMC_BYTE_MSB_TO_LSB (0 << 14) 546 # define GMC_BYTE_LSB_TO_MSB (1 << 14) 547 # define GMC_CONVERSION_TEMP (1 << 15) 548 # define GMC_CONVERSION_TEMP_6500 (0 << 15) 549 # define GMC_CONVERSION_TEMP_9300 (1 << 15) 550 # define GMC_ROP3_MASK (0xff << 16) 551 # define GMC_ROP3_PATCOPY 0x00f00000 552 # define GMC_ROP3_SRCCOPY 0x00cc0000 553 # define GMC_ROP3_PATXOR 0x005a0000 554 # define GMC_ROP3_XOR 0x00660000 555 # define GMC_DP_SRC_SOURCE_MASK (7 << 24) 556 # define GMC_DP_SRC_SOURCE_MEMORY (2 << 24) 557 # define GMC_DP_SRC_SOURCE_HOST_DATA (3 << 24) 558 # define GMC_3D_FCN_EN (1 << 27) 559 # define GMC_CLR_CMP_CNTL_DIS (1 << 28) 560 # define GMC_AUX_CLIP_DIS (1 << 29) 561 # define GMC_WR_MSK_DIS (1 << 30) 562 # define GMC_LD_BRUSH_Y_X (1 << 31) 563 #define DP_GUI_MASTER_CNTL_C 0x1c84 564 #define DP_MIX 0x16c8 565 #define DP_SRC_BKGD_CLR 0x15dc 566 #define DP_SRC_FRGD_CLR 0x15d8 567 #define DP_WRITE_MASK 0x16cc 568 #define DST_BRES_DEC 0x1630 569 #define DST_BRES_ERR 0x1628 570 #define DST_BRES_INC 0x162c 571 #define DST_BRES_LNTH 0x1634 572 #define DST_BRES_LNTH_SUB 0x1638 573 #define DST_HEIGHT 0x1410 574 #define DST_HEIGHT_WIDTH 0x143c 575 #define DST_HEIGHT_WIDTH_8 0x158c 576 #define DST_HEIGHT_WIDTH_BW 0x15b4 577 #define DST_HEIGHT_Y 0x15a0 578 #define DST_LINE_START 0x1600 579 #define DST_LINE_END 0x1604 580 #define DST_LINE_PATCOUNT 0x1608 581 # define BRES_CNTL_SHIFT 8 582 #define DST_OFFSET 0x1404 583 #define DST_PITCH 0x1408 584 #define DST_PITCH_OFFSET 0x142c 585 #define DST_PITCH_OFFSET_C 0x1c80 586 # define PITCH_SHIFT 21 587 # define DST_TILE_LINEAR (0 << 30) 588 # define DST_TILE_MACRO (1 << 30) 589 # define DST_TILE_MICRO (2 << 30) 590 # define DST_TILE_BOTH (3 << 30) 591 #define DST_WIDTH 0x140c 592 #define DST_WIDTH_HEIGHT 0x1598 593 #define DST_WIDTH_X 0x1588 594 #define DST_WIDTH_X_INCY 0x159c 595 #define DST_X 0x141c 596 #define DST_X_SUB 0x15a4 597 #define DST_X_Y 0x1594 598 #define DST_Y 0x1420 599 #define DST_Y_SUB 0x15a8 600 #define DST_Y_X 0x1438 601 602 #define FCP_CNTL 0x0910 603 # define FCP0_SRC_PCICLK 0 604 # define FCP0_SRC_PCLK 1 605 # define FCP0_SRC_PCLKb 2 606 # define FCP0_SRC_HREF 3 607 # define FCP0_SRC_GND 4 608 # define FCP0_SRC_HREFb 5 609 #define FLUSH_1 0x1704 610 #define FLUSH_2 0x1708 611 #define FLUSH_3 0x170c 612 #define FLUSH_4 0x1710 613 #define FLUSH_5 0x1714 614 #define FLUSH_6 0x1718 615 #define FLUSH_7 0x171c 616 #define FOG_3D_TABLE_START 0x1810 617 #define FOG_3D_TABLE_END 0x1814 618 #define FOG_3D_TABLE_DENSITY 0x181c 619 #define FOG_TABLE_INDEX 0x1a14 620 #define FOG_TABLE_DATA 0x1a18 621 #define FP_CRTC_H_TOTAL_DISP 0x0250 622 #define FP_CRTC_V_TOTAL_DISP 0x0254 623 #define FP_CRTC2_H_TOTAL_DISP 0x0350 624 #define FP_CRTC2_V_TOTAL_DISP 0x0354 625 # define FP_CRTC_H_TOTAL_MASK 0x000003ff 626 # define FP_CRTC_H_DISP_MASK 0x01ff0000 627 # define FP_CRTC_V_TOTAL_MASK 0x00000fff 628 # define FP_CRTC_V_DISP_MASK 0x0fff0000 629 # define FP_H_SYNC_STRT_CHAR_MASK 0x00001ff8 630 # define FP_H_SYNC_WID_MASK 0x003f0000 631 # define FP_V_SYNC_STRT_MASK 0x00000fff 632 # define FP_V_SYNC_WID_MASK 0x001f0000 633 # define FP_CRTC_H_TOTAL_SHIFT 0x00000000 634 # define FP_CRTC_H_DISP_SHIFT 0x00000010 635 # define FP_CRTC_V_TOTAL_SHIFT 0x00000000 636 # define FP_CRTC_V_DISP_SHIFT 0x00000010 637 # define FP_H_SYNC_STRT_CHAR_SHIFT 0x00000003 638 # define FP_H_SYNC_WID_SHIFT 0x00000010 639 # define FP_V_SYNC_STRT_SHIFT 0x00000000 640 # define FP_V_SYNC_WID_SHIFT 0x00000010 641 #define FP_GEN_CNTL 0x0284 642 # define FP_FPON (1 << 0) 643 # define FP_BLANK_EN (1 << 1) 644 # define FP_TMDS_EN (1 << 2) 645 # define FP_PANEL_FORMAT (1 << 3) 646 # define FP_EN_TMDS (1 << 7) 647 # define FP_DETECT_SENSE (1 << 8) 648 # define R200_FP_SOURCE_SEL_MASK (3 << 10) 649 # define R200_FP_SOURCE_SEL_CRTC1 (0 << 10) 650 # define R200_FP_SOURCE_SEL_CRTC2 (1 << 10) 651 # define R200_FP_SOURCE_SEL_RMX (2 << 10) 652 # define R200_FP_SOURCE_SEL_TRANS (3 << 10) 653 # define FP_SEL_CRTC1 (0 << 13) 654 # define FP_SEL_CRTC2 (1 << 13) 655 # define FP_CRTC_DONT_SHADOW_HPAR (1 << 15) 656 # define FP_CRTC_DONT_SHADOW_VPAR (1 << 16) 657 # define FP_CRTC_DONT_SHADOW_HEND (1 << 17) 658 # define FP_CRTC_USE_SHADOW_VEND (1 << 18) 659 # define FP_RMX_HVSYNC_CONTROL_EN (1 << 20) 660 # define FP_DFP_SYNC_SEL (1 << 21) 661 # define FP_CRTC_LOCK_8DOT (1 << 22) 662 # define FP_CRT_SYNC_SEL (1 << 23) 663 # define FP_USE_SHADOW_EN (1 << 24) 664 # define FP_CRT_SYNC_ALT (1 << 26) 665 #define FP2_GEN_CNTL 0x0288 666 # define FP2_BLANK_EN (1 << 1) 667 # define FP2_ON (1 << 2) 668 # define FP2_PANEL_FORMAT (1 << 3) 669 # define R200_FP2_SOURCE_SEL_MASK (3 << 10) 670 # define R200_FP2_SOURCE_SEL_CRTC1 (0 << 10) 671 # define R200_FP2_SOURCE_SEL_CRTC2 (1 << 10) 672 # define R200_FP2_SOURCE_SEL_RMX (2 << 10) 673 # define FP2_SRC_SEL_MASK (3 << 13) 674 # define FP2_SRC_SEL_CRTC2 (1 << 13) 675 # define FP2_FP_POL (1 << 16) 676 # define FP2_LP_POL (1 << 17) 677 # define FP2_SCK_POL (1 << 18) 678 # define FP2_LCD_CNTL_MASK (7 << 19) 679 # define FP2_PAD_FLOP_EN (1 << 22) 680 # define FP2_CRC_EN (1 << 23) 681 # define FP2_CRC_READ_EN (1 << 24) 682 # define FP2_DVO_EN (1 << 25) 683 # define FP2_DVO_RATE_SEL_SDR (1 << 26) 684 #define FP_H_SYNC_STRT_WID 0x02c4 685 #define FP2_H_SYNC_STRT_WID 0x03c4 686 #define FP_HORZ_STRETCH 0x028c 687 #define FP_HORZ2_STRETCH 0x038c 688 # define HORZ_STRETCH_RATIO_MASK 0xffff 689 # define HORZ_STRETCH_RATIO_MAX 4096 690 # define HORZ_PANEL_SIZE (0x1ff << 16) 691 # define HORZ_PANEL_SHIFT 16 692 # define HORZ_STRETCH_PIXREP (0 << 25) 693 # define HORZ_STRETCH_BLEND (1 << 26) 694 # define HORZ_STRETCH_ENABLE (1 << 25) 695 # define HORZ_AUTO_RATIO (1 << 27) 696 # define HORZ_FP_LOOP_STRETCH (0x7 << 28) 697 # define HORZ_AUTO_RATIO_INC (1 << 31) 698 #define FP_V_SYNC_STRT_WID 0x02c8 699 #define FP_VERT_STRETCH 0x0290 700 #define FP2_V_SYNC_STRT_WID 0x03c8 701 #define FP_VERT2_STRETCH 0x0390 702 # define VERT_PANEL_SIZE (0xfff << 12) 703 # define VERT_PANEL_SHIFT 12 704 # define VERT_STRETCH_RATIO_MASK 0xfff 705 # define VERT_STRETCH_RATIO_SHIFT 0 706 # define VERT_STRETCH_RATIO_MAX 4096 707 # define VERT_STRETCH_ENABLE (1 << 25) 708 # define VERT_STRETCH_LINEREP (0 << 26) 709 # define VERT_STRETCH_BLEND (1 << 26) 710 # define VERT_AUTO_RATIO_EN (1 << 27) 711 # define VERT_STRETCH_RESERVED 0xf1000000 712 713 #define GEN_INT_CNTL 0x0040 714 #define GEN_INT_STATUS 0x0044 715 # define VSYNC_INT_AK (1 << 2) 716 # define VSYNC_INT (1 << 2) 717 # define VSYNC2_INT_AK (1 << 6) 718 # define VSYNC2_INT (1 << 6) 719 #define GENENB 0x03c3 /* VGA */ 720 #define GENFC_RD 0x03ca /* VGA */ 721 #define GENFC_WT 0x03da /* VGA, 0x03ba */ 722 #define GENMO_RD 0x03cc /* VGA */ 723 #define GENMO_WT 0x03c2 /* VGA */ 724 #define GENS0 0x03c2 /* VGA */ 725 #define GENS1 0x03da /* VGA, 0x03ba */ 726 #define GPIO_MONID 0x0068 /* DDC interface via I2C */ 727 #define GPIO_MONIDB 0x006c 728 #define GPIO_CRT2_DDC 0x006c 729 #define GPIO_DVI_DDC 0x0064 730 #define GPIO_VGA_DDC 0x0060 731 # define GPIO_A_0 (1 << 0) 732 # define GPIO_A_1 (1 << 1) 733 # define GPIO_Y_0 (1 << 8) 734 # define GPIO_Y_1 (1 << 9) 735 # define GPIO_Y_SHIFT_0 8 736 # define GPIO_Y_SHIFT_1 9 737 # define GPIO_EN_0 (1 << 16) 738 # define GPIO_EN_1 (1 << 17) 739 # define GPIO_MASK_0 (1 << 24) /*??*/ 740 # define GPIO_MASK_1 (1 << 25) /*??*/ 741 #define GRPH8_DATA 0x03cf /* VGA */ 742 #define GRPH8_IDX 0x03ce /* VGA */ 743 #define GUI_SCRATCH_REG0 0x15e0 744 #define GUI_SCRATCH_REG1 0x15e4 745 #define GUI_SCRATCH_REG2 0x15e8 746 #define GUI_SCRATCH_REG3 0x15ec 747 #define GUI_SCRATCH_REG4 0x15f0 748 #define GUI_SCRATCH_REG5 0x15f4 749 750 #define HEADER 0x0f0e /* PCI */ 751 #define HOST_DATA0 0x17c0 752 #define HOST_DATA1 0x17c4 753 #define HOST_DATA2 0x17c8 754 #define HOST_DATA3 0x17cc 755 #define HOST_DATA4 0x17d0 756 #define HOST_DATA5 0x17d4 757 #define HOST_DATA6 0x17d8 758 #define HOST_DATA7 0x17dc 759 #define HOST_DATA_LAST 0x17e0 760 #define HOST_PATH_CNTL 0x0130 761 # define HDP_SOFT_RESET (1 << 26) 762 #define HTOTAL_CNTL 0x0009 /* PLL */ 763 #define HTOTAL2_CNTL 0x002e /* PLL */ 764 765 #define I2C_CNTL_1 0x0094 /* ? */ 766 #define DVI_I2C_CNTL_1 0x02e4 /* ? */ 767 #define INTERRUPT_LINE 0x0f3c /* PCI */ 768 #define INTERRUPT_PIN 0x0f3d /* PCI */ 769 #define IO_BASE 0x0f14 /* PCI */ 770 771 #define LATENCY 0x0f0d /* PCI */ 772 #define LEAD_BRES_DEC 0x1608 773 #define LEAD_BRES_LNTH 0x161c 774 #define LEAD_BRES_LNTH_SUB 0x1624 775 #define LVDS_GEN_CNTL 0x02d0 776 # define LVDS_ON (1 << 0) 777 # define LVDS_DISPLAY_DIS (1 << 1) 778 # define LVDS_PANEL_TYPE (1 << 2) 779 # define LVDS_PANEL_FORMAT (1 << 3) 780 # define LVDS_EN (1 << 7) 781 # define LVDS_DIGON (1 << 18) 782 # define LVDS_BLON (1 << 19) 783 # define LVDS_SEL_CRTC2 (1 << 23) 784 #define LVDS_PLL_CNTL 0x02d4 785 # define HSYNC_DELAY_SHIFT 28 786 # define HSYNC_DELAY_MASK (0xf << 28) 787 788 #define MAX_LATENCY 0x0f3f /* PCI */ 789 #define MC_AGP_LOCATION 0x014c 790 #define MC_FB_LOCATION 0x0148 791 #define CRTC_BASE_ADDR 0x023c 792 #define CRTC2_BASE_ADDR 0x033c 793 #define DISPLAY_TEST_DEBUG_CNTL 0x0d10 794 #define NB_TOM 0x015c 795 #define MCLK_CNTL 0x0012 /* PLL */ 796 # define FORCEON_MCLKA (1 << 16) 797 # define FORCEON_MCLKB (1 << 17) 798 # define FORCEON_YCLKA (1 << 18) 799 # define FORCEON_YCLKB (1 << 19) 800 # define FORCEON_MC (1 << 20) 801 # define FORCEON_AIC (1 << 21) 802 # define R300_DISABLE_MC_MCLKA (1 << 21) 803 # define R300_DISABLE_MC_MCLKB (1 << 21) 804 #define MCLK_MISC 0x001f /* PLL */ 805 # define MC_MCLK_MAX_DYN_STOP_LAT (1<<12) 806 # define IO_MCLK_MAX_DYN_STOP_LAT (1<<13) 807 # define MC_MCLK_DYN_ENABLE (1 << 14) 808 # define IO_MCLK_DYN_ENABLE (1 << 14) 809 #define MDGPIO_A_REG 0x01ac 810 #define MDGPIO_EN_REG 0x01b0 811 #define MDGPIO_MASK 0x0198 812 #define MDGPIO_Y_REG 0x01b4 813 #define MEM_ADDR_CONFIG 0x0148 814 #define MEM_BASE 0x0f10 /* PCI */ 815 #define MEM_CNTL 0x0140 816 # define MEM_NUM_CHANNELS_MASK 0x01 817 # define MEM_USE_B_CH_ONLY (1<<1) 818 # define RV100_HALF_MODE (1<<3) 819 # define R300_MEM_NUM_CHANNELS_MASK 0x03 820 # define R300_MEM_USE_CD_CH_ONLY (1<<2) 821 #define MEM_TIMING_CNTL 0x0144 /* EXT_MEM_CNTL */ 822 #define MEM_INIT_LAT_TIMER 0x0154 823 #define MEM_INTF_CNTL 0x014c 824 #define MEM_SDRAM_MODE_REG 0x0158 825 #define MEM_STR_CNTL 0x0150 826 #define MEM_VGA_RP_SEL 0x003c 827 #define MEM_VGA_WP_SEL 0x0038 828 #define MIN_GRANT 0x0f3e /* PCI */ 829 #define MM_DATA 0x0004 830 #define MM_INDEX 0x0000 831 #define MPLL_CNTL 0x000e /* PLL */ 832 #define MPP_TB_CONFIG 0x01c0 /* ? */ 833 #define MPP_GP_CONFIG 0x01c8 /* ? */ 834 #define R300_MC_IND_INDEX 0x01f8 835 # define R300_MC_IND_ADDR_MASK 0x3f 836 #define R300_MC_IND_DATA 0x01fc 837 #define R300_MC_READ_CNTL_AB 0x017c 838 # define R300_MEM_RBS_POSITION_A_MASK 0x03 839 #define R300_MC_READ_CNTL_CD_mcind 0x24 840 # define R300_MEM_RBS_POSITION_C_MASK 0x03 841 842 #define N_VIF_COUNT 0x0248 843 844 /* overlay */ 845 #define OV0_Y_X_START 0x0400 846 #define OV0_Y_X_END 0x0404 847 #define OV0_PIPELINE_CNTL 0x0408 848 #define OV0_EXCLUSIVE_HORZ 0x0408 849 # define EXCL_HORZ_START_MASK 0x000000ff 850 # define EXCL_HORZ_END_MASK 0x0000ff00 851 # define EXCL_HORZ_BACK_PORCH_MASK 0x00ff0000 852 # define EXCL_HORZ_EXCLUSIVE_EN 0x80000000 853 #define OV0_EXCLUSIVE_VERT 0x040C 854 # define EXCL_VERT_START_MASK 0x000003ff 855 # define EXCL_VERT_END_MASK 0x03ff0000 856 #define OV0_REG_LOAD_CNTL 0x0410 857 # define REG_LD_CTL_LOCK 0x00000001 858 # define REG_LD_CTL_VBLANK_DURING_LOCK 0x00000002 859 # define REG_LD_CTL_STALL_GUI_UNTIL_FLIP 0x00000004 860 # define REG_LD_CTL_LOCK_READBACK 0x00000008 861 #define OV0_SCALE_CNTL 0x0420 862 # define SCALER_PIX_EXPAND 0x00000001 863 # define SCALER_Y2R_TEMP 0x00000002 864 # define SCALER_HORZ_PICK_NEAREST 0x00000004 865 # define SCALER_VERT_PICK_NEAREST 0x00000008 866 # define SCALER_SIGNED_UV 0x00000010 867 # define SCALER_GAMMA_SEL_MASK 0x00000060 868 # define SCALER_GAMMA_SEL_BRIGHT 0x00000000 869 # define SCALER_GAMMA_SEL_G22 0x00000020 870 # define SCALER_GAMMA_SEL_G18 0x00000040 871 # define SCALER_GAMMA_SEL_G14 0x00000060 872 # define SCALER_COMCORE_SHIFT_UP_ONE 0x00000080 873 # define SCALER_SURFAC_FORMAT 0x00000f00 874 # define SCALER_SOURCE_UNK0 0x00000000 /* 2 bpp ??? */ 875 # define SCALER_SOURCE_UNK1 0x00000100 /* 4 bpp ??? */ 876 # define SCALER_SOURCE_UNK2 0x00000200 /* 8 bpp ??? */ 877 # define SCALER_SOURCE_15BPP 0x00000300 878 # define SCALER_SOURCE_16BPP 0x00000400 879 /*# define SCALER_SOURCE_24BPP 0x00000500*/ 880 # define SCALER_SOURCE_32BPP 0x00000600 881 # define SCALER_SOURCE_UNK3 0x00000700 /* 8BPP_RGB332 ??? */ 882 # define SCALER_SOURCE_UNK4 0x00000800 /* 8BPP_Y8 ??? */ 883 # define SCALER_SOURCE_YUV9 0x00000900 /* 8BPP_RGB8 */ 884 # define SCALER_SOURCE_YUV12 0x00000A00 885 # define SCALER_SOURCE_VYUY422 0x00000B00 886 # define SCALER_SOURCE_YVYU422 0x00000C00 887 # define SCALER_SOURCE_UNK5 0x00000D00 /* ??? */ 888 # define SCALER_SOURCE_UNK6 0x00000E00 /* 32BPP_AYUV444 */ 889 # define SCALER_SOURCE_UNK7 0x00000F00 /* 16BPP_ARGB4444 */ 890 # define SCALER_ADAPTIVE_DEINT 0x00001000 891 # define R200_SCALER_TEMPORAL_DEINT 0x00002000 892 # define SCALER_UNKNOWN_FLAG1 0x00004000 /* ??? */ 893 # define SCALER_SMART_SWITCH 0x00008000 894 # define SCALER_BURST_PER_PLANE 0x007f0000 895 # define SCALER_DOUBLE_BUFFER 0x01000000 896 # define SCALER_UNKNOWN_FLAG3 0x02000000 /* ??? */ 897 # define SCALER_UNKNOWN_FLAG4 0x04000000 /* ??? */ 898 # define SCALER_DIS_LIMIT 0x08000000 899 # define SCALER_PRG_LOAD_START 0x10000000 900 # define SCALER_INT_EMU 0x20000000 901 # define SCALER_ENABLE 0x40000000 902 # define SCALER_SOFT_RESET 0x80000000 903 #define OV0_V_INC 0x0424 904 #define OV0_P1_V_ACCUM_INIT 0x0428 905 # define OV0_P1_MAX_LN_IN_PER_LN_OUT 0x00000003 906 # define OV0_P1_V_ACCUM_INIT_MASK 0x01ff8000 907 #define OV0_P23_V_ACCUM_INIT 0x042C 908 # define OV0_P23_MAX_LN_IN_PER_LN_OUT 0x00000003 909 # define OV0_P23_V_ACCUM_INIT_MASK 0x01ff8000 910 #define OV0_P1_BLANK_LINES_AT_TOP 0x0430 911 # define P1_BLNK_LN_AT_TOP_M1_MASK 0x00000fff 912 # define P1_ACTIVE_LINES_M1 0x0fff0000 913 #define OV0_P23_BLANK_LINES_AT_TOP 0x0434 914 # define P23_BLNK_LN_AT_TOP_M1_MASK 0x000007ff 915 # define P23_ACTIVE_LINES_M1 0x07ff0000 916 #define OV0_BASE_ADDR 0x043C 917 #define OV0_VID_BUF0_BASE_ADRS 0x0440 918 # define VIF_BUF0_PITCH_SEL 0x00000001 919 # define VIF_BUF0_TILE_ADRS 0x00000002 920 # define VIF_BUF0_BASE_ADRS_MASK 0xfffffff0 921 # define VIF_BUF0_1ST_LINE_LSBS_MASK 0x48000000 922 #define OV0_VID_BUF1_BASE_ADRS 0x0444 923 # define VIF_BUF1_PITCH_SEL 0x00000001 924 # define VIF_BUF1_TILE_ADRS 0x00000002 925 # define VIF_BUF1_BASE_ADRS_MASK 0xfffffff0 926 # define VIF_BUF1_1ST_LINE_LSBS_MASK 0x48000000 927 #define OV0_VID_BUF2_BASE_ADRS 0x0448 928 # define VIF_BUF2_PITCH_SEL 0x00000001 929 # define VIF_BUF2_TILE_ADRS 0x00000002 930 # define VIF_BUF2_BASE_ADRS_MASK 0xfffffff0 931 # define VIF_BUF2_1ST_LINE_LSBS_MASK 0x48000000 932 #define OV0_VID_BUF3_BASE_ADRS 0x044C 933 # define VIF_BUF3_PITCH_SEL 0x00000001 934 # define VIF_BUF3_TILE_ADRS 0x00000002 935 # define VIF_BUF3_BASE_ADRS_MASK 0xfffffff0 936 # define VIF_BUF3_1ST_LINE_LSBS_MASK 0x48000000 937 #define OV0_VID_BUF4_BASE_ADRS 0x0450 938 # define VIF_BUF4_PITCH_SEL 0x00000001 939 # define VIF_BUF4_TILE_ADRS 0x00000002 940 # define VIF_BUF4_BASE_ADRS_MASK 0xfffffff0 941 # define VIF_BUF4_1ST_LINE_LSBS_MASK 0x48000000 942 #define OV0_VID_BUF5_BASE_ADRS 0x0454 943 # define VIF_BUF5_PITCH_SEL 0x00000001 944 # define VIF_BUF5_TILE_ADRS 0x00000002 945 # define VIF_BUF5_BASE_ADRS_MASK 0xfffffff0 946 # define VIF_BUF5_1ST_LINE_LSBS_MASK 0x48000000 947 #define OV0_VID_BUF_PITCH0_VALUE 0x0460 948 #define OV0_VID_BUF_PITCH1_VALUE 0x0464 949 #define OV0_AUTO_FLIP_CNTL 0x0470 950 # define OV0_AUTO_FLIP_CNTL_SOFT_BUF_NUM 0x00000007 951 # define OV0_AUTO_FLIP_CNTL_SOFT_REPEAT_FIELD 0x00000008 952 # define OV0_AUTO_FLIP_CNTL_SOFT_BUF_ODD 0x00000010 953 # define OV0_AUTO_FLIP_CNTL_IGNORE_REPEAT_FIELD 0x00000020 954 # define OV0_AUTO_FLIP_CNTL_SOFT_EOF_TOGGLE 0x00000040 955 # define OV0_AUTO_FLIP_CNTL_VID_PORT_SELECT 0x00000300 956 # define OV0_AUTO_FLIP_CNTL_P1_FIRST_LINE_EVEN 0x00010000 957 # define OV0_AUTO_FLIP_CNTL_SHIFT_EVEN_DOWN 0x00040000 958 # define OV0_AUTO_FLIP_CNTL_SHIFT_ODD_DOWN 0x00080000 959 # define OV0_AUTO_FLIP_CNTL_FIELD_POL_SOURCE 0x00800000 960 #define OV0_DEINTERLACE_PATTERN 0x0474 961 #define OV0_SUBMIT_HISTORY 0x0478 962 #define OV0_H_INC 0x0480 963 #define OV0_STEP_BY 0x0484 964 #define OV0_P1_H_ACCUM_INIT 0x0488 965 #define OV0_P23_H_ACCUM_INIT 0x048C 966 #define OV0_P1_X_START_END 0x0494 967 #define OV0_P2_X_START_END 0x0498 968 #define OV0_P3_X_START_END 0x049C 969 #define OV0_FILTER_CNTL 0x04A0 970 # define FILTER_PROGRAMMABLE_COEF 0x00000000 971 # define FILTER_HARD_SCALE_HORZ_Y 0x00000001 972 # define FILTER_HARD_SCALE_HORZ_UV 0x00000002 973 # define FILTER_HARD_SCALE_VERT_Y 0x00000004 974 # define FILTER_HARD_SCALE_VERT_UV 0x00000008 975 # define FILTER_HARDCODED_COEF 0x0000000F 976 # define FILTER_COEF_MASK 0x0000000F 977 #define OV0_FOUR_TAP_COEF_0 0x04B0 978 # define OV0_FOUR_TAP_PHASE_0_TAP_0 0x0000000F 979 # define OV0_FOUR_TAP_PHASE_0_TAP_1 0x00007F00 980 # define OV0_FOUR_TAP_PHASE_0_TAP_2 0x007F0000 981 # define OV0_FOUR_TAP_PHASE_0_TAP_3 0x0F000000 982 #define OV0_FOUR_TAP_COEF_1 0x04B4 983 # define OV0_FOUR_TAP_PHASE_1_5_TAP_0 0x0000000F 984 # define OV0_FOUR_TAP_PHASE_1_5_TAP_1 0x00007F00 985 # define OV0_FOUR_TAP_PHASE_1_5_TAP_2 0x007F0000 986 # define OV0_FOUR_TAP_PHASE_1_5_TAP_3 0x0F000000 987 #define OV0_FOUR_TAP_COEF_2 0x04B8 988 # define OV0_FOUR_TAP_PHASE_2_6_TAP_0 0x0000000F 989 # define OV0_FOUR_TAP_PHASE_2_6_TAP_1 0x00007F00 990 # define OV0_FOUR_TAP_PHASE_2_6_TAP_2 0x007F0000 991 # define OV0_FOUR_TAP_PHASE_2_6_TAP_3 0x0F000000 992 #define OV0_FOUR_TAP_COEF_3 0x04BC 993 # define OV0_FOUR_TAP_PHASE_3_7_TAP_0 0x0000000F 994 # define OV0_FOUR_TAP_PHASE_3_7_TAP_1 0x00007F00 995 # define OV0_FOUR_TAP_PHASE_3_7_TAP_2 0x007F0000 996 # define OV0_FOUR_TAP_PHASE_3_7_TAP_3 0x0F000000 997 #define OV0_FOUR_TAP_COEF_4 0x04C0 998 # define OV0_FOUR_TAP_PHASE_4_TAP_0 0x0000000F 999 # define OV0_FOUR_TAP_PHASE_4_TAP_1 0x00007F00 1000 # define OV0_FOUR_TAP_PHASE_4_TAP_2 0x007F0000 1001 # define OV0_FOUR_TAP_PHASE_4_TAP_3 0x0F000000 1002 #define OV0_FLAG_CNTL 0x04DC 1003 #define OV0_SLICE_CNTL 0x04E0 1004 # define SLICE_CNTL_DISABLE 0x40000000 1005 #define OV0_VID_KEY_CLR_LOW 0x04E4 1006 #define OV0_VID_KEY_CLR_HIGH 0x04E8 1007 #define OV0_GRPH_KEY_CLR_LOW 0x04EC 1008 #define OV0_GRPH_KEY_CLR_HIGH 0x04F0 1009 #define OV0_KEY_CNTL 0x04F4 1010 # define VIDEO_KEY_FN_MASK 0x00000003 1011 # define VIDEO_KEY_FN_FALSE 0x00000000 1012 # define VIDEO_KEY_FN_TRUE 0x00000001 1013 # define VIDEO_KEY_FN_EQ 0x00000002 1014 # define VIDEO_KEY_FN_NE 0x00000003 1015 # define GRAPHIC_KEY_FN_MASK 0x00000030 1016 # define GRAPHIC_KEY_FN_FALSE 0x00000000 1017 # define GRAPHIC_KEY_FN_TRUE 0x00000010 1018 # define GRAPHIC_KEY_FN_EQ 0x00000020 1019 # define GRAPHIC_KEY_FN_NE 0x00000030 1020 # define CMP_MIX_MASK 0x00000100 1021 # define CMP_MIX_OR 0x00000000 1022 # define CMP_MIX_AND 0x00000100 1023 #define OV0_TEST 0x04F8 1024 # define OV0_SCALER_Y2R_DISABLE 0x00000001 1025 # define OV0_SUBPIC_ONLY 0x00000008 1026 # define OV0_EXTENSE 0x00000010 1027 # define OV0_SWAP_UV 0x00000020 1028 #define OV0_COL_CONV 0x04FC 1029 # define OV0_CB_TO_B 0x0000007F 1030 # define OV0_CB_TO_G 0x0000FF00 1031 # define OV0_CR_TO_G 0x00FF0000 1032 # define OV0_CR_TO_R 0x7F000000 1033 # define OV0_NEW_COL_CONV 0x80000000 1034 #define OV1_Y_X_START 0x0600 1035 #define OV1_Y_X_END 0x0604 1036 #define OV0_LIN_TRANS_A 0x0D20 1037 #define OV0_LIN_TRANS_B 0x0D24 1038 #define OV0_LIN_TRANS_C 0x0D28 1039 #define OV0_LIN_TRANS_D 0x0D2C 1040 #define OV0_LIN_TRANS_E 0x0D30 1041 #define OV0_LIN_TRANS_F 0x0D34 1042 #define OV0_GAMMA_000_00F 0x0d40 1043 #define OV0_GAMMA_010_01F 0x0d44 1044 #define OV0_GAMMA_020_03F 0x0d48 1045 #define OV0_GAMMA_040_07F 0x0d4c 1046 #define OV0_GAMMA_080_0BF 0x0e00 1047 #define OV0_GAMMA_0C0_0FF 0x0e04 1048 #define OV0_GAMMA_100_13F 0x0e08 1049 #define OV0_GAMMA_140_17F 0x0e0c 1050 #define OV0_GAMMA_180_1BF 0x0e10 1051 #define OV0_GAMMA_1C0_1FF 0x0e14 1052 #define OV0_GAMMA_200_23F 0x0e18 1053 #define OV0_GAMMA_240_27F 0x0e1c 1054 #define OV0_GAMMA_280_2BF 0x0e20 1055 #define OV0_GAMMA_2C0_2FF 0x0e24 1056 #define OV0_GAMMA_300_33F 0x0e28 1057 #define OV0_GAMMA_340_37F 0x0e2c 1058 #define OV0_GAMMA_380_3BF 0x0d50 1059 #define OV0_GAMMA_3C0_3FF 0x0d54 1060 1061 #define OVR_CLR 0x0230 1062 #define OVR_WID_LEFT_RIGHT 0x0234 1063 #define OVR_WID_TOP_BOTTOM 0x0238 1064 1065 /* subpicture */ 1066 #define SUBPIC_CNTL 0x0540 1067 #define SUBPIC_DEFCOLCON 0x0544 1068 #define SUBPIC_Y_X_START 0x054C 1069 #define SUBPIC_Y_X_END 0x0550 1070 #define SUBPIC_V_INC 0x0554 1071 #define SUBPIC_H_INC 0x0558 1072 #define SUBPIC_BUF0_OFFSET 0x055C 1073 #define SUBPIC_BUF1_OFFSET 0x0560 1074 #define SUBPIC_LC0_OFFSET 0x0564 1075 #define SUBPIC_LC1_OFFSET 0x0568 1076 #define SUBPIC_PITCH 0x056C 1077 #define SUBPIC_BTN_HLI_COLCON 0x0570 1078 #define SUBPIC_BTN_HLI_Y_X_START 0x0574 1079 #define SUBPIC_BTN_HLI_Y_X_END 0x0578 1080 #define SUBPIC_PALETTE_INDEX 0x057C 1081 #define SUBPIC_PALETTE_DATA 0x0580 1082 #define SUBPIC_H_ACCUM_INIT 0x0584 1083 #define SUBPIC_V_ACCUM_INIT 0x0588 1084 1085 #define P2PLL_CNTL 0x002a /* P2PLL */ 1086 # define P2PLL_RESET (1 << 0) 1087 # define P2PLL_SLEEP (1 << 1) 1088 # define P2PLL_ATOMIC_UPDATE_EN (1 << 16) 1089 # define P2PLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 1090 # define P2PLL_ATOMIC_UPDATE_VSYNC (1 << 18) 1091 #define P2PLL_DIV_0 0x002c 1092 # define P2PLL_FB0_DIV_MASK 0x07ff 1093 # define P2PLL_POST0_DIV_MASK 0x00070000 1094 #define P2PLL_REF_DIV 0x002B /* PLL */ 1095 # define P2PLL_REF_DIV_MASK 0x03ff 1096 # define P2PLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 1097 # define P2PLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 1098 # define R300_PPLL_REF_DIV_ACC_MASK (0x3ff << 18) 1099 # define R300_PPLL_REF_DIV_ACC_SHIFT 18 1100 #define PALETTE_DATA 0x00b4 1101 #define PALETTE_30_DATA 0x00b8 1102 #define PALETTE_INDEX 0x00b0 1103 #define PCI_GART_PAGE 0x017c 1104 #define PIXCLKS_CNTL 0x002d 1105 # define PIX2CLK_SRC_SEL_MASK 0x03 1106 # define PIX2CLK_SRC_SEL_CPUCLK 0x00 1107 # define PIX2CLK_SRC_SEL_PSCANCLK 0x01 1108 # define PIX2CLK_SRC_SEL_BYTECLK 0x02 1109 # define PIX2CLK_SRC_SEL_P2PLLCLK 0x03 1110 # define PIX2CLK_ALWAYS_ONb (1<<6) 1111 # define PIX2CLK_DAC_ALWAYS_ONb (1<<7) 1112 # define PIXCLK_TV_SRC_SEL (1 << 8) 1113 # define DISP_TVOUT_PIXCLK_TV_ALWAYS_ONb (1 << 9) 1114 # define R300_DVOCLK_ALWAYS_ONb (1 << 10) 1115 # define PIXCLK_BLEND_ALWAYS_ONb (1 << 11) 1116 # define PIXCLK_GV_ALWAYS_ONb (1 << 12) 1117 # define PIXCLK_DIG_TMDS_ALWAYS_ONb (1 << 13) 1118 # define R300_PIXCLK_DVO_ALWAYS_ONb (1 << 13) 1119 # define PIXCLK_LVDS_ALWAYS_ONb (1 << 14) 1120 # define PIXCLK_TMDS_ALWAYS_ONb (1 << 15) 1121 # define R300_PIXCLK_TRANS_ALWAYS_ONb (1 << 16) 1122 # define R300_PIXCLK_TVO_ALWAYS_ONb (1 << 17) 1123 # define R300_P2G2CLK_ALWAYS_ONb (1 << 18) 1124 # define R300_P2G2CLK_DAC_ALWAYS_ONb (1 << 19) 1125 # define R300_DISP_DAC_PIXCLK_DAC2_BLANK_OFF (1 << 23) 1126 #define PLANE_3D_MASK_C 0x1d44 1127 #define PLL_TEST_CNTL 0x0013 /* PLL */ 1128 #define PMI_CAP_ID 0x0f5c /* PCI */ 1129 #define PMI_DATA 0x0f63 /* PCI */ 1130 #define PMI_NXT_CAP_PTR 0x0f5d /* PCI */ 1131 #define PMI_PMC_REG 0x0f5e /* PCI */ 1132 #define PMI_PMCSR_REG 0x0f60 /* PCI */ 1133 #define PMI_REGISTER 0x0f5c /* PCI */ 1134 #define PPLL_CNTL 0x0002 /* PLL */ 1135 # define PPLL_RESET (1 << 0) 1136 # define PPLL_SLEEP (1 << 1) 1137 # define PPLL_ATOMIC_UPDATE_EN (1 << 16) 1138 # define PPLL_VGA_ATOMIC_UPDATE_EN (1 << 17) 1139 # define PPLL_ATOMIC_UPDATE_VSYNC (1 << 18) 1140 #define PPLL_DIV_0 0x0004 /* PLL */ 1141 #define PPLL_DIV_1 0x0005 /* PLL */ 1142 #define PPLL_DIV_2 0x0006 /* PLL */ 1143 #define PPLL_DIV_3 0x0007 /* PLL */ 1144 # define PPLL_FB3_DIV_MASK 0x07ff 1145 # define PPLL_POST3_DIV_MASK 0x00070000 1146 #define PPLL_REF_DIV 0x0003 /* PLL */ 1147 # define PPLL_REF_DIV_MASK 0x03ff 1148 # define PPLL_ATOMIC_UPDATE_R (1 << 15) /* same as _W */ 1149 # define PPLL_ATOMIC_UPDATE_W (1 << 15) /* same as _R */ 1150 #define PWR_MNGMT_CNTL_STATUS 0x0f60 /* PCI */ 1151 1152 /* ERT registers */ 1153 #define TV_MASTER_CNTL 0x0800 1154 # define TV_MASTER_TVCLK_ALWAYS_ONb (1 << 30) 1155 # define TV_MASTER_TV_ON (1 << 31) 1156 #define TV_RGB_CNTL 0x0804 1157 # define TV_RGB_CNTL_INI 0x007b0004 1158 #define TV_SYNC_CNTL 0x0808 1159 #define TV_HTOTAL 0x080c 1160 #define TV_HDISP 0x0810 1161 #define TV_HSTART 0x0818 1162 #define TV_HCOUNT 0x081c 1163 #define TV_VTOTAL 0x0820 1164 #define TV_VDISP 0x0824 1165 #define TV_VCOUNT 0x0828 1166 #define TV_FTOTAL 0x082c 1167 #define TV_FCOUNT 0x0830 1168 #define TV_FRESTART 0x0834 1169 #define TV_HRESTART 0x0838 1170 #define TV_VRESTART 0x083c 1171 #define TV_HOST_READ_DATA 0x0840 1172 #define TV_HOST_WRITE_DATA 0x0844 1173 #define TV_HOST_RD_WT_CNTL 0x0848 1174 #define TV_VSCALER_CNTL1 0x084c 1175 # define TV_VSCALER_RESTART_FIELD (1 << 29) 1176 #define TV_TIMING_CNTL 0x0850 1177 #define TV_VSCALER_CNTL2 0x0854 1178 #define TV_Y_FALL_CNTL 0x0858 1179 #define TV_Y_RISE_CNTL 0x085c 1180 #define TV_Y_SAWTOOTH_CNTL 0x0860 1181 #define TV_UPSAMP_AND_GAIN_CNTL 0x0864 1182 #define TV_GAIN_LIMIT_SETTINGS 0x0868 1183 #define TV_LINEAR_GAIN_SETTINGS 0x086c 1184 #define TV_MODULATOR_CNTL1 0x0870 1185 #define TV_MODULATOR_CNTL2 0x0874 1186 #define TV_PRE_DAC_MUX_CNTL 0x0888 1187 # define TV_PRE_DAC_Y_RED_EN (1 << 0) 1188 # define TV_PRE_DAC_C_GRN_EN (1 << 1) 1189 # define TV_PRE_DAC_CMP_BLU_EN (1 << 2) 1190 # define TV_PRE_DAC_RED_MX_FORCE_DAC_DATA (6 << 4) 1191 # define TV_PRE_DAC_GRN_MX_FORCE_DAC_DATA (6 << 8) 1192 # define TV_PRE_DAC_BLU_MX_FORCE_DAC_DATA (6 << 12) 1193 # define TV_FORCE_DAC_DATA_SHIFT 16 1194 #define TV_DAC_CNTL 0x088c 1195 # define TV_DAC_NBLANK (1 << 0) 1196 # define TV_DAC_NHOLD (1 << 1) 1197 # define TV_DAC_CMPOUT (1 << 5) 1198 # define TV_DAC_BGSLEEP (1 << 6) 1199 # define TV_DAC_RDACPD (1 << 24) 1200 # define TV_DAC_GDACPD (1 << 25) 1201 # define TV_DAC_BDACPD (1 << 26) 1202 #define TV_CRC_CNTL 0x0890 1203 #define TV_UV_ADR 0x08ac 1204 /* ERT PLL registers */ 1205 #define TV_PLL_CNTL 0x21 1206 #define TV_PLL_CNTL1 0x22 1207 # define TV_PLL_CNTL1_TVPLL_RESET (1 << 1) 1208 # define TV_PLL_CNTL1_TVPLL_SLEEP (1 << 3) 1209 # define TV_PLL_CNTL1_TVPDC_SHIFT 14 1210 # define TV_PLL_CNTL1_TVPDC_MASK (3 << 14) 1211 # define TV_PLL_CNTL1_TVCLK_SRC_SEL (1 << 30) 1212 1213 1214 #define RBBM_GUICNTL 0x172c 1215 # define HOST_DATA_SWAP_NONE (0 << 0) 1216 # define HOST_DATA_SWAP_16BIT (1 << 0) 1217 # define HOST_DATA_SWAP_32BIT (2 << 0) 1218 # define HOST_DATA_SWAP_HDW (3 << 0) 1219 #define RBBM_SOFT_RESET 0x00f0 1220 # define SOFT_RESET_CP (1 << 0) 1221 # define SOFT_RESET_HI (1 << 1) 1222 # define SOFT_RESET_SE (1 << 2) 1223 # define SOFT_RESET_RE (1 << 3) 1224 # define SOFT_RESET_PP (1 << 4) 1225 # define SOFT_RESET_E2 (1 << 5) 1226 # define SOFT_RESET_RB (1 << 6) 1227 # define SOFT_RESET_HDP (1 << 7) 1228 #define RBBM_STATUS 0x0e40 1229 # define RBBM_FIFOCNT_MASK 0x007f 1230 # define RBBM_ACTIVE (1 << 31) 1231 #define RB2D_DSTCACHE_MODE 0x3428 1232 # define RB2D_DC_CACHE_ENABLE (0) 1233 # define RB2D_DC_2D_CACHE_DISABLE (1) 1234 # define RB2D_DC_3D_CACHE_DISABLE (2) 1235 # define RB2D_DC_CACHE_DISABLE (3) 1236 # define RB2D_DC_2D_CACHE_LINESIZE_128 (1 << 2) 1237 # define RB2D_DC_3D_CACHE_LINESIZE_128 (2 << 2) 1238 # define RB2D_DC_2D_CACHE_AUTOFLUSH (1 << 8) 1239 # define RB2D_DC_3D_CACHE_AUTOFLUSH (2 << 8) 1240 # define R200_RB2D_DC_2D_CACHE_AUTOFREE (1 << 10) 1241 # define R200_RB2D_DC_3D_CACHE_AUTOFREE (2 << 10) 1242 # define RB2D_DC_FORCE_RMW (1 << 16) 1243 # define R300_RB2D_DC_ENABLE (1 << 17) 1244 # define RB2D_DC_DISABLE_RI_FILL (1 << 24) 1245 # define RB2D_DC_DISABLE_RI_READ (1 << 25) 1246 # define RB2D_DC_DISABLE_MASK_CHK (1 << 26) 1247 #define RB2D_DSTCACHE_CTLSTAT 0x342c 1248 # define RB2D_DC_FLUSH (3 << 0) 1249 # define RB2D_DC_FREE (3 << 2) 1250 # define RB2D_DC_FLUSH_ALL 0xf 1251 # define RB2D_DC_BUSY (1 << 31) 1252 #define RB3D_DSTCACHE_MODE 0x3258 1253 # define RB3D_DC_CACHE_ENABLE (0) 1254 # define RB3D_DC_2D_CACHE_DISABLE (1) 1255 # define RB3D_DC_3D_CACHE_DISABLE (2) 1256 # define RB3D_DC_CACHE_DISABLE (3) 1257 # define RB3D_DC_2D_CACHE_LINESIZE_128 (1 << 2) 1258 # define RB3D_DC_3D_CACHE_LINESIZE_128 (2 << 2) 1259 # define RB3D_DC_2D_CACHE_AUTOFLUSH (1 << 8) 1260 # define RB3D_DC_3D_CACHE_AUTOFLUSH (2 << 8) 1261 # define R200_RB3D_DC_2D_CACHE_AUTOFREE (1 << 10) 1262 # define R200_RB3D_DC_3D_CACHE_AUTOFREE (2 << 10) 1263 # define RB3D_DC_FORCE_RMW (1 << 16) 1264 # define R300_RB3D_DC_ENABLE (1 << 17) 1265 # define RB3D_DC_DISABLE_RI_FILL (1 << 24) 1266 # define RB3D_DC_DISABLE_RI_READ (1 << 25) 1267 # define RB3D_DC_DISABLE_MASK_CHK (1 << 26) 1268 #define RB3D_DSTCACHE_CTLSTAT 0x325C 1269 # define RB3D_DC_FLUSH (3 << 0) 1270 # define RB3D_DC_FREE (3 << 2) 1271 # define RB3D_DC_FLUSH_ALL 0xf 1272 # define RB3D_DC_BUSY (1 << 31) 1273 #define REG_BASE 0x0f18 /* PCI */ 1274 #define REGPROG_INF 0x0f09 /* PCI */ 1275 #define REVISION_ID 0x0f08 /* PCI */ 1276 1277 #define SC_BOTTOM 0x164c 1278 #define SC_BOTTOM_RIGHT 0x16f0 1279 #define SC_BOTTOM_RIGHT_C 0x1c8c 1280 #define SC_LEFT 0x1640 1281 #define SC_RIGHT 0x1644 1282 #define SC_TOP 0x1648 1283 #define SC_TOP_LEFT 0x16ec 1284 #define SC_TOP_LEFT_C 0x1c88 1285 # define SC_SIGN_MASK_LO 0x8000 1286 # define SC_SIGN_MASK_HI 0x80000000 1287 #define SCLK_CNTL 0x000d /* PLL */ 1288 # define SCLK_SRC_SEL_MASK 0x0007 1289 # define DYN_STOP_LAT_MASK 0x00007ff8 1290 # define CP_MAX_DYN_STOP_LAT 0x0008 1291 # define SCLK_FORCEON_MASK 0xffff8000 1292 # define SCLK_FORCE_DISP2 (1<<15) 1293 # define SCLK_FORCE_CP (1<<16) 1294 # define SCLK_FORCE_HDP (1<<17) 1295 # define SCLK_FORCE_DISP1 (1<<18) 1296 # define SCLK_FORCE_TOP (1<<19) 1297 # define SCLK_FORCE_E2 (1<<20) 1298 # define SCLK_FORCE_SE (1<<21) 1299 # define SCLK_FORCE_IDCT (1<<22) 1300 # define SCLK_FORCE_VIP (1<<23) 1301 # define SCLK_FORCE_RE (1<<24) 1302 # define SCLK_FORCE_PB (1<<25) 1303 # define SCLK_FORCE_TAM (1<<26) 1304 # define SCLK_FORCE_TDM (1<<27) 1305 # define SCLK_FORCE_RB (1<<28) 1306 # define SCLK_FORCE_TV_SCLK (1<<29) 1307 # define SCLK_FORCE_SUBPIC (1<<30) 1308 # define SCLK_FORCE_OV0 (1<<31) 1309 # define R300_SCLK_FORCE_VAP (1<<21) 1310 # define R300_SCLK_FORCE_SR (1<<25) 1311 # define R300_SCLK_FORCE_PX (1<<26) 1312 # define R300_SCLK_FORCE_TX (1<<27) 1313 # define R300_SCLK_FORCE_US (1<<28) 1314 # define R300_SCLK_FORCE_SU (1<<30) 1315 #define R300_SCLK_CNTL2 0x1e /* PLL */ 1316 # define R300_SCLK_TCL_MAX_DYN_STOP_LAT (1<<10) 1317 # define R300_SCLK_GA_MAX_DYN_STOP_LAT (1<<11) 1318 # define R300_SCLK_CBA_MAX_DYN_STOP_LAT (1<<12) 1319 # define R300_SCLK_FORCE_TCL (1<<13) 1320 # define R300_SCLK_FORCE_CBA (1<<14) 1321 # define R300_SCLK_FORCE_GA (1<<15) 1322 #define SCLK_MORE_CNTL 0x0035 /* PLL */ 1323 # define SCLK_MORE_MAX_DYN_STOP_LAT 0x0007 1324 # define SCLK_MORE_FORCEON 0x0700 1325 #define SDRAM_MODE_REG 0x0158 1326 #define SEQ8_DATA 0x03c5 /* VGA */ 1327 #define SEQ8_IDX 0x03c4 /* VGA */ 1328 #define SNAPSHOT_F_COUNT 0x0244 1329 #define SNAPSHOT_VH_COUNTS 0x0240 1330 #define SNAPSHOT_VIF_COUNT 0x024c 1331 #define SRC_OFFSET 0x15ac 1332 #define SRC_PITCH 0x15b0 1333 #define SRC_PITCH_OFFSET 0x1428 1334 #define SRC_SC_BOTTOM 0x165c 1335 #define SRC_SC_BOTTOM_RIGHT 0x16f4 1336 #define SRC_SC_RIGHT 0x1654 1337 #define SRC_X 0x1414 1338 #define SRC_X_Y 0x1590 1339 #define SRC_Y 0x1418 1340 #define SRC_Y_X 0x1434 1341 #define STATUS 0x0f06 /* PCI */ 1342 #define SUB_CLASS 0x0f0a /* PCI */ 1343 #define SURFACE_CNTL 0x0b00 1344 # define SURF_TRANSLATION_DIS (1 << 8) 1345 # define NONSURF_AP0_SWP_16BPP (1 << 20) 1346 # define NONSURF_AP0_SWP_32BPP (1 << 21) 1347 # define NONSURF_AP1_SWP_16BPP (1 << 22) 1348 # define NONSURF_AP1_SWP_32BPP (1 << 23) 1349 #define SURFACE0_INFO 0x0b0c 1350 #define SURFACE0_LOWER_BOUND 0x0b04 1351 #define SURFACE0_UPPER_BOUND 0x0b08 1352 #define SURFACE1_INFO 0x0b1c 1353 #define SURFACE1_LOWER_BOUND 0x0b14 1354 #define SURFACE1_UPPER_BOUND 0x0b18 1355 #define SURFACE2_INFO 0x0b2c 1356 #define SURFACE2_LOWER_BOUND 0x0b24 1357 #define SURFACE2_UPPER_BOUND 0x0b28 1358 #define SURFACE3_INFO 0x0b3c 1359 #define SURFACE3_LOWER_BOUND 0x0b34 1360 #define SURFACE3_UPPER_BOUND 0x0b38 1361 #define SURFACE4_INFO 0x0b4c 1362 #define SURFACE4_LOWER_BOUND 0x0b44 1363 #define SURFACE4_UPPER_BOUND 0x0b48 1364 #define SURFACE5_INFO 0x0b5c 1365 #define SURFACE5_LOWER_BOUND 0x0b54 1366 #define SURFACE5_UPPER_BOUND 0x0b58 1367 #define SURFACE6_INFO 0x0b6c 1368 #define SURFACE6_LOWER_BOUND 0x0b64 1369 #define SURFACE6_UPPER_BOUND 0x0b68 1370 #define SURFACE7_INFO 0x0b7c 1371 #define SURFACE7_LOWER_BOUND 0x0b74 1372 #define SURFACE7_UPPER_BOUND 0x0b78 1373 #define SW_SEMAPHORE 0x013c 1374 1375 #define TEST_DEBUG_CNTL 0x0120 1376 #define TEST_DEBUG_MUX 0x0124 1377 #define TEST_DEBUG_OUT 0x012c 1378 #define TMDS_PLL_CNTL 0x02a8 1379 #define TMDS_TRANSMITTER_CNTL 0x02a4 1380 # define TMDS_TRANSMITTER_PLLEN 1 1381 # define TMDS_TRANSMITTER_PLLRST 2 1382 #define TRAIL_BRES_DEC 0x1614 1383 #define TRAIL_BRES_ERR 0x160c 1384 #define TRAIL_BRES_INC 0x1610 1385 #define TRAIL_X 0x1618 1386 #define TRAIL_X_SUB 0x1620 1387 1388 #define VCLK_ECP_CNTL 0x0008 /* PLL */ 1389 # define VCLK_SRC_SEL_MASK 0x03 1390 # define VCLK_SRC_SEL_CPUCLK 0x00 1391 # define VCLK_SRC_SEL_PSCANCLK 0x01 1392 # define VCLK_SRC_SEL_BYTECLK 0x02 1393 # define VCLK_SRC_SEL_PPLLCLK 0x03 1394 # define PIXCLK_ALWAYS_ONb (1<<6) 1395 # define PIXCLK_DAC_ALWAYS_ONb (1<<7) 1396 # define R300_DISP_DAC_PIXCLK_DAC_BLANK_OFF (1<<23) 1397 1398 #define VGA_DDA_CONFIG 0x02e8 1399 #define VGA_DDA_ON_OFF 0x02ec 1400 #define VID_BUFFER_CONTROL 0x0900 1401 #define VIDEOMUX_CNTL 0x0190 1402 #define VIPH_CONTROL 0x0c40 /* ? */ 1403 1404 #define WAIT_UNTIL 0x1720 1405 # define WAIT_CRTC_PFLIP (1 << 0) 1406 # define R300_WAIT_2D_IDLE (1 << 0) 1407 # define R300_WAIT_3D_IDLE (2 << 0) 1408 # define R300_WAIT_2D_IDLECLEAN (3 << 0) 1409 # define R300_WAIT_3D_IDLECLEAN (4 << 0) 1410 # define WAIT_2D_IDLE (1 << 14) 1411 # define WAIT_3D_IDLE (1 << 15) 1412 # define WAIT_2D_IDLECLEAN (1 << 16) 1413 # define WAIT_3D_IDLECLEAN (1 << 17) 1414 # define WAIT_HOST_IDLECLEAN (1 << 18) 1415 1416 #define ISYNC_CNTL 0x1724 1417 # define ISYNC_ANY2D_IDLE3D (1 << 0) 1418 # define ISYNC_ANY3D_IDLE2D (1 << 1) 1419 # define ISYNC_TRIG2D_IDLE3D (1 << 2) 1420 # define ISYNC_TRIG3D_IDLE2D (1 << 3) 1421 # define ISYNC_WAIT_IDLEGUI (1 << 4) 1422 # define ISYNC_CPSCRATCH_IDLEGUI (1 << 5) 1423 1424 #define X_MPLL_REF_FB_DIV 0x000a /* PLL */ 1425 #define XCLK_CNTL 0x000d /* PLL */ 1426 #define XDLL_CNTL 0x000c /* PLL */ 1427 #define XPLL_CNTL 0x000b /* PLL */ 1428 1429 1430 1431 /* Registers for 3D/TCL */ 1432 #define PP_BORDER_COLOR_0 0x1d40 1433 #define PP_BORDER_COLOR_1 0x1d44 1434 #define PP_BORDER_COLOR_2 0x1d48 1435 #define PP_CNTL 0x1c38 1436 # define STIPPLE_ENABLE (1 << 0) 1437 # define SCISSOR_ENABLE (1 << 1) 1438 # define PATTERN_ENABLE (1 << 2) 1439 # define SHADOW_ENABLE (1 << 3) 1440 # define TEX_ENABLE_MASK (0xf << 4) 1441 # define TEX_0_ENABLE (1 << 4) 1442 # define TEX_1_ENABLE (1 << 5) 1443 # define TEX_2_ENABLE (1 << 6) 1444 # define TEX_3_ENABLE (1 << 7) 1445 # define TEX_BLEND_ENABLE_MASK (0xf << 12) 1446 # define TEX_BLEND_0_ENABLE (1 << 12) 1447 # define TEX_BLEND_1_ENABLE (1 << 13) 1448 # define TEX_BLEND_2_ENABLE (1 << 14) 1449 # define TEX_BLEND_3_ENABLE (1 << 15) 1450 # define PLANAR_YUV_ENABLE (1 << 20) 1451 # define SPECULAR_ENABLE (1 << 21) 1452 # define FOG_ENABLE (1 << 22) 1453 # define ALPHA_TEST_ENABLE (1 << 23) 1454 # define ANTI_ALIAS_NONE (0 << 24) 1455 # define ANTI_ALIAS_LINE (1 << 24) 1456 # define ANTI_ALIAS_POLY (2 << 24) 1457 # define ANTI_ALIAS_LINE_POLY (3 << 24) 1458 # define BUMP_MAP_ENABLE (1 << 26) 1459 # define BUMPED_MAP_T0 (0 << 27) 1460 # define BUMPED_MAP_T1 (1 << 27) 1461 # define BUMPED_MAP_T2 (2 << 27) 1462 # define TEX_3D_ENABLE_0 (1 << 29) 1463 # define TEX_3D_ENABLE_1 (1 << 30) 1464 # define MC_ENABLE (1 << 31) 1465 #define PP_FOG_COLOR 0x1c18 1466 # define FOG_COLOR_MASK 0x00ffffff 1467 # define FOG_VERTEX (0 << 24) 1468 # define FOG_TABLE (1 << 24) 1469 # define FOG_USE_DEPTH (0 << 25) 1470 # define FOG_USE_DIFFUSE_ALPHA (2 << 25) 1471 # define FOG_USE_SPEC_ALPHA (3 << 25) 1472 #define PP_LUM_MATRIX 0x1d00 1473 #define PP_MISC 0x1c14 1474 # define REF_ALPHA_MASK 0x000000ff 1475 # define ALPHA_TEST_FAIL (0 << 8) 1476 # define ALPHA_TEST_LESS (1 << 8) 1477 # define ALPHA_TEST_LEQUAL (2 << 8) 1478 # define ALPHA_TEST_EQUAL (3 << 8) 1479 # define ALPHA_TEST_GEQUAL (4 << 8) 1480 # define ALPHA_TEST_GREATER (5 << 8) 1481 # define ALPHA_TEST_NEQUAL (6 << 8) 1482 # define ALPHA_TEST_PASS (7 << 8) 1483 # define ALPHA_TEST_OP_MASK (7 << 8) 1484 # define CHROMA_FUNC_FAIL (0 << 16) 1485 # define CHROMA_FUNC_PASS (1 << 16) 1486 # define CHROMA_FUNC_NEQUAL (2 << 16) 1487 # define CHROMA_FUNC_EQUAL (3 << 16) 1488 # define CHROMA_KEY_NEAREST (0 << 18) 1489 # define CHROMA_KEY_ZERO (1 << 18) 1490 # define SHADOW_ID_AUTO_INC (1 << 20) 1491 # define SHADOW_FUNC_EQUAL (0 << 21) 1492 # define SHADOW_FUNC_NEQUAL (1 << 21) 1493 # define SHADOW_PASS_1 (0 << 22) 1494 # define SHADOW_PASS_2 (1 << 22) 1495 # define RIGHT_HAND_CUBE_D3D (0 << 24) 1496 # define RIGHT_HAND_CUBE_OGL (1 << 24) 1497 #define PP_ROT_MATRIX_0 0x1d58 1498 #define PP_ROT_MATRIX_1 0x1d5c 1499 #define PP_TXFILTER_0 0x1c54 1500 #define PP_TXFILTER_1 0x1c6c 1501 #define PP_TXFILTER_2 0x1c84 1502 # define MAG_FILTER_NEAREST (0 << 0) 1503 # define MAG_FILTER_LINEAR (1 << 0) 1504 # define MAG_FILTER_MASK (1 << 0) 1505 # define MIN_FILTER_NEAREST (0 << 1) 1506 # define MIN_FILTER_LINEAR (1 << 1) 1507 # define MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) 1508 # define MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) 1509 # define MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) 1510 # define MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) 1511 # define MIN_FILTER_ANISO_NEAREST (8 << 1) 1512 # define MIN_FILTER_ANISO_LINEAR (9 << 1) 1513 # define MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) 1514 # define MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) 1515 # define MIN_FILTER_MASK (15 << 1) 1516 # define MAX_ANISO_1_TO_1 (0 << 5) 1517 # define MAX_ANISO_2_TO_1 (1 << 5) 1518 # define MAX_ANISO_4_TO_1 (2 << 5) 1519 # define MAX_ANISO_8_TO_1 (3 << 5) 1520 # define MAX_ANISO_16_TO_1 (4 << 5) 1521 # define MAX_ANISO_MASK (7 << 5) 1522 # define LOD_BIAS_MASK (0xff << 8) 1523 # define LOD_BIAS_SHIFT 8 1524 # define MAX_MIP_LEVEL_MASK (0x0f << 16) 1525 # define MAX_MIP_LEVEL_SHIFT 16 1526 # define YUV_TO_RGB (1 << 20) 1527 # define YUV_TEMPERATURE_COOL (0 << 21) 1528 # define YUV_TEMPERATURE_HOT (1 << 21) 1529 # define YUV_TEMPERATURE_MASK (1 << 21) 1530 # define WRAPEN_S (1 << 22) 1531 # define CLAMP_S_WRAP (0 << 23) 1532 # define CLAMP_S_MIRROR (1 << 23) 1533 # define CLAMP_S_CLAMP_LAST (2 << 23) 1534 # define CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) 1535 # define CLAMP_S_CLAMP_BORDER (4 << 23) 1536 # define CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) 1537 # define CLAMP_S_CLAMP_GL (6 << 23) 1538 # define CLAMP_S_MIRROR_CLAMP_GL (7 << 23) 1539 # define CLAMP_S_MASK (7 << 23) 1540 # define WRAPEN_T (1 << 26) 1541 # define CLAMP_T_WRAP (0 << 27) 1542 # define CLAMP_T_MIRROR (1 << 27) 1543 # define CLAMP_T_CLAMP_LAST (2 << 27) 1544 # define CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) 1545 # define CLAMP_T_CLAMP_BORDER (4 << 27) 1546 # define CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) 1547 # define CLAMP_T_CLAMP_GL (6 << 27) 1548 # define CLAMP_T_MIRROR_CLAMP_GL (7 << 27) 1549 # define CLAMP_T_MASK (7 << 27) 1550 # define BORDER_MODE_OGL (0 << 31) 1551 # define BORDER_MODE_D3D (1 << 31) 1552 #define PP_TXFORMAT_0 0x1c58 1553 #define PP_TXFORMAT_1 0x1c70 1554 #define PP_TXFORMAT_2 0x1c88 1555 # define TXFORMAT_I8 (0 << 0) 1556 # define TXFORMAT_AI88 (1 << 0) 1557 # define TXFORMAT_RGB332 (2 << 0) 1558 # define TXFORMAT_ARGB1555 (3 << 0) 1559 # define TXFORMAT_RGB565 (4 << 0) 1560 # define TXFORMAT_ARGB4444 (5 << 0) 1561 # define TXFORMAT_ARGB8888 (6 << 0) 1562 # define TXFORMAT_RGBA8888 (7 << 0) 1563 # define TXFORMAT_Y8 (8 << 0) 1564 # define TXFORMAT_VYUY422 (10 << 0) 1565 # define TXFORMAT_YVYU422 (11 << 0) 1566 # define TXFORMAT_DXT1 (12 << 0) 1567 # define TXFORMAT_DXT23 (14 << 0) 1568 # define TXFORMAT_DXT45 (15 << 0) 1569 # define TXFORMAT_FORMAT_MASK (31 << 0) 1570 # define TXFORMAT_FORMAT_SHIFT 0 1571 # define TXFORMAT_APPLE_YUV_MODE (1 << 5) 1572 # define TXFORMAT_ALPHA_IN_MAP (1 << 6) 1573 # define TXFORMAT_NON_POWER2 (1 << 7) 1574 # define TXFORMAT_WIDTH_MASK (15 << 8) 1575 # define TXFORMAT_WIDTH_SHIFT 8 1576 # define TXFORMAT_HEIGHT_MASK (15 << 12) 1577 # define TXFORMAT_HEIGHT_SHIFT 12 1578 # define TXFORMAT_F5_WIDTH_MASK (15 << 16) 1579 # define TXFORMAT_F5_WIDTH_SHIFT 16 1580 # define TXFORMAT_F5_HEIGHT_MASK (15 << 20) 1581 # define TXFORMAT_F5_HEIGHT_SHIFT 20 1582 # define TXFORMAT_ST_ROUTE_STQ0 (0 << 24) 1583 # define TXFORMAT_ST_ROUTE_MASK (3 << 24) 1584 # define TXFORMAT_ST_ROUTE_STQ1 (1 << 24) 1585 # define TXFORMAT_ST_ROUTE_STQ2 (2 << 24) 1586 # define TXFORMAT_ENDIAN_NO_SWAP (0 << 26) 1587 # define TXFORMAT_ENDIAN_16BPP_SWAP (1 << 26) 1588 # define TXFORMAT_ENDIAN_32BPP_SWAP (2 << 26) 1589 # define TXFORMAT_ENDIAN_HALFDW_SWAP (3 << 26) 1590 # define TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) 1591 # define TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) 1592 # define TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) 1593 # define TXFORMAT_PERSPECTIVE_ENABLE (1 << 31) 1594 #define PP_CUBIC_FACES_0 0x1d24 1595 #define PP_CUBIC_FACES_1 0x1d28 1596 #define PP_CUBIC_FACES_2 0x1d2c 1597 # define FACE_WIDTH_1_SHIFT 0 1598 # define FACE_HEIGHT_1_SHIFT 4 1599 # define FACE_WIDTH_1_MASK (0xf << 0) 1600 # define FACE_HEIGHT_1_MASK (0xf << 4) 1601 # define FACE_WIDTH_2_SHIFT 8 1602 # define FACE_HEIGHT_2_SHIFT 12 1603 # define FACE_WIDTH_2_MASK (0xf << 8) 1604 # define FACE_HEIGHT_2_MASK (0xf << 12) 1605 # define FACE_WIDTH_3_SHIFT 16 1606 # define FACE_HEIGHT_3_SHIFT 20 1607 # define FACE_WIDTH_3_MASK (0xf << 16) 1608 # define FACE_HEIGHT_3_MASK (0xf << 20) 1609 # define FACE_WIDTH_4_SHIFT 24 1610 # define FACE_HEIGHT_4_SHIFT 28 1611 # define FACE_WIDTH_4_MASK (0xf << 24) 1612 # define FACE_HEIGHT_4_MASK (0xf << 28) 1613 1614 #define PP_TXOFFSET_0 0x1c5c 1615 #define PP_TXOFFSET_1 0x1c74 1616 #define PP_TXOFFSET_2 0x1c8c 1617 # define TXO_ENDIAN_NO_SWAP (0 << 0) 1618 # define TXO_ENDIAN_BYTE_SWAP (1 << 0) 1619 # define TXO_ENDIAN_WORD_SWAP (2 << 0) 1620 # define TXO_ENDIAN_HALFDW_SWAP (3 << 0) 1621 # define TXO_MACRO_LINEAR (0 << 2) 1622 # define TXO_MACRO_TILE (1 << 2) 1623 # define TXO_MICRO_LINEAR (0 << 3) 1624 # define TXO_MICRO_TILE_X2 (1 << 3) 1625 # define TXO_MICRO_TILE_OPT (2 << 3) 1626 # define TXO_OFFSET_MASK 0xffffffe0 1627 # define TXO_OFFSET_SHIFT 5 1628 1629 #define PP_CUBIC_OFFSET_T0_0 0x1dd0 /* bits [31:5] */ 1630 #define PP_CUBIC_OFFSET_T0_1 0x1dd4 1631 #define PP_CUBIC_OFFSET_T0_2 0x1dd8 1632 #define PP_CUBIC_OFFSET_T0_3 0x1ddc 1633 #define PP_CUBIC_OFFSET_T0_4 0x1de0 1634 #define PP_CUBIC_OFFSET_T1_0 0x1e00 1635 #define PP_CUBIC_OFFSET_T1_1 0x1e04 1636 #define PP_CUBIC_OFFSET_T1_2 0x1e08 1637 #define PP_CUBIC_OFFSET_T1_3 0x1e0c 1638 #define PP_CUBIC_OFFSET_T1_4 0x1e10 1639 #define PP_CUBIC_OFFSET_T2_0 0x1e14 1640 #define PP_CUBIC_OFFSET_T2_1 0x1e18 1641 #define PP_CUBIC_OFFSET_T2_2 0x1e1c 1642 #define PP_CUBIC_OFFSET_T2_3 0x1e20 1643 #define PP_CUBIC_OFFSET_T2_4 0x1e24 1644 1645 #define PP_TEX_SIZE_0 0x1d04 /* NPOT */ 1646 #define PP_TEX_SIZE_1 0x1d0c 1647 #define PP_TEX_SIZE_2 0x1d14 1648 # define TEX_USIZE_MASK (0x7ff << 0) 1649 # define TEX_USIZE_SHIFT 0 1650 # define TEX_VSIZE_MASK (0x7ff << 16) 1651 # define TEX_VSIZE_SHIFT 16 1652 # define SIGNED_RGB_MASK (1 << 30) 1653 # define SIGNED_RGB_SHIFT 30 1654 # define SIGNED_ALPHA_MASK (1 << 31) 1655 # define SIGNED_ALPHA_SHIFT 31 1656 #define PP_TEX_PITCH_0 0x1d08 /* NPOT */ 1657 #define PP_TEX_PITCH_1 0x1d10 /* NPOT */ 1658 #define PP_TEX_PITCH_2 0x1d18 /* NPOT */ 1659 /* note: bits 13-5: 32 byte aligned stride of texture map */ 1660 1661 #define PP_TXCBLEND_0 0x1c60 1662 #define PP_TXCBLEND_1 0x1c78 1663 #define PP_TXCBLEND_2 0x1c90 1664 # define COLOR_ARG_A_SHIFT 0 1665 # define COLOR_ARG_A_MASK (0x1f << 0) 1666 # define COLOR_ARG_A_ZERO (0 << 0) 1667 # define COLOR_ARG_A_CURRENT_COLOR (2 << 0) 1668 # define COLOR_ARG_A_CURRENT_ALPHA (3 << 0) 1669 # define COLOR_ARG_A_DIFFUSE_COLOR (4 << 0) 1670 # define COLOR_ARG_A_DIFFUSE_ALPHA (5 << 0) 1671 # define COLOR_ARG_A_SPECULAR_COLOR (6 << 0) 1672 # define COLOR_ARG_A_SPECULAR_ALPHA (7 << 0) 1673 # define COLOR_ARG_A_TFACTOR_COLOR (8 << 0) 1674 # define COLOR_ARG_A_TFACTOR_ALPHA (9 << 0) 1675 # define COLOR_ARG_A_T0_COLOR (10 << 0) 1676 # define COLOR_ARG_A_T0_ALPHA (11 << 0) 1677 # define COLOR_ARG_A_T1_COLOR (12 << 0) 1678 # define COLOR_ARG_A_T1_ALPHA (13 << 0) 1679 # define COLOR_ARG_A_T2_COLOR (14 << 0) 1680 # define COLOR_ARG_A_T2_ALPHA (15 << 0) 1681 # define COLOR_ARG_A_T3_COLOR (16 << 0) 1682 # define COLOR_ARG_A_T3_ALPHA (17 << 0) 1683 # define COLOR_ARG_B_SHIFT 5 1684 # define COLOR_ARG_B_MASK (0x1f << 5) 1685 # define COLOR_ARG_B_ZERO (0 << 5) 1686 # define COLOR_ARG_B_CURRENT_COLOR (2 << 5) 1687 # define COLOR_ARG_B_CURRENT_ALPHA (3 << 5) 1688 # define COLOR_ARG_B_DIFFUSE_COLOR (4 << 5) 1689 # define COLOR_ARG_B_DIFFUSE_ALPHA (5 << 5) 1690 # define COLOR_ARG_B_SPECULAR_COLOR (6 << 5) 1691 # define COLOR_ARG_B_SPECULAR_ALPHA (7 << 5) 1692 # define COLOR_ARG_B_TFACTOR_COLOR (8 << 5) 1693 # define COLOR_ARG_B_TFACTOR_ALPHA (9 << 5) 1694 # define COLOR_ARG_B_T0_COLOR (10 << 5) 1695 # define COLOR_ARG_B_T0_ALPHA (11 << 5) 1696 # define COLOR_ARG_B_T1_COLOR (12 << 5) 1697 # define COLOR_ARG_B_T1_ALPHA (13 << 5) 1698 # define COLOR_ARG_B_T2_COLOR (14 << 5) 1699 # define COLOR_ARG_B_T2_ALPHA (15 << 5) 1700 # define COLOR_ARG_B_T3_COLOR (16 << 5) 1701 # define COLOR_ARG_B_T3_ALPHA (17 << 5) 1702 # define COLOR_ARG_C_SHIFT 10 1703 # define COLOR_ARG_C_MASK (0x1f << 10) 1704 # define COLOR_ARG_C_ZERO (0 << 10) 1705 # define COLOR_ARG_C_CURRENT_COLOR (2 << 10) 1706 # define COLOR_ARG_C_CURRENT_ALPHA (3 << 10) 1707 # define COLOR_ARG_C_DIFFUSE_COLOR (4 << 10) 1708 # define COLOR_ARG_C_DIFFUSE_ALPHA (5 << 10) 1709 # define COLOR_ARG_C_SPECULAR_COLOR (6 << 10) 1710 # define COLOR_ARG_C_SPECULAR_ALPHA (7 << 10) 1711 # define COLOR_ARG_C_TFACTOR_COLOR (8 << 10) 1712 # define COLOR_ARG_C_TFACTOR_ALPHA (9 << 10) 1713 # define COLOR_ARG_C_T0_COLOR (10 << 10) 1714 # define COLOR_ARG_C_T0_ALPHA (11 << 10) 1715 # define COLOR_ARG_C_T1_COLOR (12 << 10) 1716 # define COLOR_ARG_C_T1_ALPHA (13 << 10) 1717 # define COLOR_ARG_C_T2_COLOR (14 << 10) 1718 # define COLOR_ARG_C_T2_ALPHA (15 << 10) 1719 # define COLOR_ARG_C_T3_COLOR (16 << 10) 1720 # define COLOR_ARG_C_T3_ALPHA (17 << 10) 1721 # define COMP_ARG_A (1 << 15) 1722 # define COMP_ARG_A_SHIFT 15 1723 # define COMP_ARG_B (1 << 16) 1724 # define COMP_ARG_B_SHIFT 16 1725 # define COMP_ARG_C (1 << 17) 1726 # define COMP_ARG_C_SHIFT 17 1727 # define BLEND_CTL_MASK (7 << 18) 1728 # define BLEND_CTL_ADD (0 << 18) 1729 # define BLEND_CTL_SUBTRACT (1 << 18) 1730 # define BLEND_CTL_ADDSIGNED (2 << 18) 1731 # define BLEND_CTL_BLEND (3 << 18) 1732 # define BLEND_CTL_DOT3 (4 << 18) 1733 # define SCALE_SHIFT 21 1734 # define SCALE_MASK (3 << 21) 1735 # define SCALE_1X (0 << 21) 1736 # define SCALE_2X (1 << 21) 1737 # define SCALE_4X (2 << 21) 1738 # define CLAMP_TX (1 << 23) 1739 # define T0_EQ_TCUR (1 << 24) 1740 # define T1_EQ_TCUR (1 << 25) 1741 # define T2_EQ_TCUR (1 << 26) 1742 # define T3_EQ_TCUR (1 << 27) 1743 # define COLOR_ARG_MASK 0x1f 1744 # define COMP_ARG_SHIFT 15 1745 #define PP_TXABLEND_0 0x1c64 1746 #define PP_TXABLEND_1 0x1c7c 1747 #define PP_TXABLEND_2 0x1c94 1748 # define ALPHA_ARG_A_SHIFT 0 1749 # define ALPHA_ARG_A_MASK (0xf << 0) 1750 # define ALPHA_ARG_A_ZERO (0 << 0) 1751 # define ALPHA_ARG_A_CURRENT_ALPHA (1 << 0) 1752 # define ALPHA_ARG_A_DIFFUSE_ALPHA (2 << 0) 1753 # define ALPHA_ARG_A_SPECULAR_ALPHA (3 << 0) 1754 # define ALPHA_ARG_A_TFACTOR_ALPHA (4 << 0) 1755 # define ALPHA_ARG_A_T0_ALPHA (5 << 0) 1756 # define ALPHA_ARG_A_T1_ALPHA (6 << 0) 1757 # define ALPHA_ARG_A_T2_ALPHA (7 << 0) 1758 # define ALPHA_ARG_A_T3_ALPHA (8 << 0) 1759 # define ALPHA_ARG_B_SHIFT 4 1760 # define ALPHA_ARG_B_MASK (0xf << 4) 1761 # define ALPHA_ARG_B_ZERO (0 << 4) 1762 # define ALPHA_ARG_B_CURRENT_ALPHA (1 << 4) 1763 # define ALPHA_ARG_B_DIFFUSE_ALPHA (2 << 4) 1764 # define ALPHA_ARG_B_SPECULAR_ALPHA (3 << 4) 1765 # define ALPHA_ARG_B_TFACTOR_ALPHA (4 << 4) 1766 # define ALPHA_ARG_B_T0_ALPHA (5 << 4) 1767 # define ALPHA_ARG_B_T1_ALPHA (6 << 4) 1768 # define ALPHA_ARG_B_T2_ALPHA (7 << 4) 1769 # define ALPHA_ARG_B_T3_ALPHA (8 << 4) 1770 # define ALPHA_ARG_C_SHIFT 8 1771 # define ALPHA_ARG_C_MASK (0xf << 8) 1772 # define ALPHA_ARG_C_ZERO (0 << 8) 1773 # define ALPHA_ARG_C_CURRENT_ALPHA (1 << 8) 1774 # define ALPHA_ARG_C_DIFFUSE_ALPHA (2 << 8) 1775 # define ALPHA_ARG_C_SPECULAR_ALPHA (3 << 8) 1776 # define ALPHA_ARG_C_TFACTOR_ALPHA (4 << 8) 1777 # define ALPHA_ARG_C_T0_ALPHA (5 << 8) 1778 # define ALPHA_ARG_C_T1_ALPHA (6 << 8) 1779 # define ALPHA_ARG_C_T2_ALPHA (7 << 8) 1780 # define ALPHA_ARG_C_T3_ALPHA (8 << 8) 1781 # define DOT_ALPHA_DONT_REPLICATE (1 << 9) 1782 # define ALPHA_ARG_MASK 0xf 1783 1784 #define PP_TFACTOR_0 0x1c68 1785 #define PP_TFACTOR_1 0x1c80 1786 #define PP_TFACTOR_2 0x1c98 1787 1788 #define RB3D_BLENDCNTL 0x1c20 1789 # define COMB_FCN_MASK (3 << 12) 1790 # define COMB_FCN_ADD_CLAMP (0 << 12) 1791 # define COMB_FCN_ADD_NOCLAMP (1 << 12) 1792 # define COMB_FCN_SUB_CLAMP (2 << 12) 1793 # define COMB_FCN_SUB_NOCLAMP (3 << 12) 1794 # define SRC_BLEND_GL_ZERO (32 << 16) 1795 # define SRC_BLEND_GL_ONE (33 << 16) 1796 # define SRC_BLEND_GL_SRC_COLOR (34 << 16) 1797 # define SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) 1798 # define SRC_BLEND_GL_DST_COLOR (36 << 16) 1799 # define SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) 1800 # define SRC_BLEND_GL_SRC_ALPHA (38 << 16) 1801 # define SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) 1802 # define SRC_BLEND_GL_DST_ALPHA (40 << 16) 1803 # define SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) 1804 # define SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) 1805 # define SRC_BLEND_MASK (63 << 16) 1806 # define DST_BLEND_GL_ZERO (32 << 24) 1807 # define DST_BLEND_GL_ONE (33 << 24) 1808 # define DST_BLEND_GL_SRC_COLOR (34 << 24) 1809 # define DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) 1810 # define DST_BLEND_GL_DST_COLOR (36 << 24) 1811 # define DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) 1812 # define DST_BLEND_GL_SRC_ALPHA (38 << 24) 1813 # define DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) 1814 # define DST_BLEND_GL_DST_ALPHA (40 << 24) 1815 # define DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) 1816 # define DST_BLEND_MASK (63 << 24) 1817 #define RB3D_CNTL 0x1c3c 1818 # define ALPHA_BLEND_ENABLE (1 << 0) 1819 # define PLANE_MASK_ENABLE (1 << 1) 1820 # define DITHER_ENABLE (1 << 2) 1821 # define ROUND_ENABLE (1 << 3) 1822 # define SCALE_DITHER_ENABLE (1 << 4) 1823 # define DITHER_INIT (1 << 5) 1824 # define ROP_ENABLE (1 << 6) 1825 # define STENCIL_ENABLE (1 << 7) 1826 # define Z_ENABLE (1 << 8) 1827 # define DEPTH_XZ_OFFEST_ENABLE (1 << 9) 1828 # define COLOR_FORMAT_ARGB1555 (3 << 10) 1829 # define COLOR_FORMAT_RGB565 (4 << 10) 1830 # define COLOR_FORMAT_ARGB8888 (6 << 10) 1831 # define COLOR_FORMAT_RGB332 (7 << 10) 1832 # define COLOR_FORMAT_Y8 (8 << 10) 1833 # define COLOR_FORMAT_RGB8 (9 << 10) 1834 # define COLOR_FORMAT_YUV422_VYUY (11 << 10) 1835 # define COLOR_FORMAT_YUV422_YVYU (12 << 10) 1836 # define COLOR_FORMAT_AVYU (14 << 10) 1837 # define COLOR_FORMAT_ARGB4444 (15 << 10) 1838 # define CLRCMP_FLIP_ENABLE (1 << 14) 1839 # define SEPARATE_ALPHA_ENABLE (1 << 16) 1840 #define RB3D_COLOROFFSET 0x1c40 1841 # define COLOROFFSET_MASK 0xfffffff0 1842 #define RB3D_COLORPITCH 0x1c48 1843 # define COLORPITCH_MASK 0x000001ff8 1844 # define COLOR_TILE_ENABLE (1 << 16) 1845 # define COLOR_MICROTILE_ENABLE (1 << 17) 1846 # define COLOR_ENDIAN_NO_SWAP (0 << 18) 1847 # define COLOR_ENDIAN_WORD_SWAP (1 << 18) 1848 # define COLOR_ENDIAN_DWORD_SWAP (2 << 18) 1849 #define RB3D_DEPTHOFFSET 0x1c24 1850 #define RB3D_DEPTHPITCH 0x1c28 1851 # define DEPTHPITCH_MASK 0x00001ff8 1852 # define DEPTH_ENDIAN_NO_SWAP (0 << 18) 1853 # define DEPTH_ENDIAN_WORD_SWAP (1 << 18) 1854 # define DEPTH_ENDIAN_DWORD_SWAP (2 << 18) 1855 #define RB3D_PLANEMASK 0x1d84 1856 #define RB3D_ROPCNTL 0x1d80 1857 # define ROP_MASK (15 << 8) 1858 # define ROP_CLEAR (0 << 8) 1859 # define ROP_NOR (1 << 8) 1860 # define ROP_AND_INVERTED (2 << 8) 1861 # define ROP_COPY_INVERTED (3 << 8) 1862 # define ROP_AND_REVERSE (4 << 8) 1863 # define ROP_INVERT (5 << 8) 1864 # define ROP_XOR (6 << 8) 1865 # define ROP_NAND (7 << 8) 1866 # define ROP_AND (8 << 8) 1867 # define ROP_EQUIV (9 << 8) 1868 # define ROP_NOOP (10 << 8) 1869 # define ROP_OR_INVERTED (11 << 8) 1870 # define ROP_COPY (12 << 8) 1871 # define ROP_OR_REVERSE (13 << 8) 1872 # define ROP_OR (14 << 8) 1873 # define ROP_SET (15 << 8) 1874 #define RB3D_STENCILREFMASK 0x1d7c 1875 # define STENCIL_REF_SHIFT 0 1876 # define STENCIL_REF_MASK (0xff << 0) 1877 # define STENCIL_MASK_SHIFT 16 1878 # define STENCIL_VALUE_MASK (0xff << 16) 1879 # define STENCIL_WRITEMASK_SHIFT 24 1880 # define STENCIL_WRITE_MASK (0xff << 24) 1881 #define RB3D_ZSTENCILCNTL 0x1c2c 1882 # define DEPTH_FORMAT_MASK (0xf << 0) 1883 # define DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 1884 # define DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 1885 # define DEPTH_FORMAT_24BIT_FLOAT_Z (3 << 0) 1886 # define DEPTH_FORMAT_32BIT_INT_Z (4 << 0) 1887 # define DEPTH_FORMAT_32BIT_FLOAT_Z (5 << 0) 1888 # define DEPTH_FORMAT_16BIT_FLOAT_W (7 << 0) 1889 # define DEPTH_FORMAT_24BIT_FLOAT_W (9 << 0) 1890 # define DEPTH_FORMAT_32BIT_FLOAT_W (11 << 0) 1891 # define Z_TEST_NEVER (0 << 4) 1892 # define Z_TEST_LESS (1 << 4) 1893 # define Z_TEST_LEQUAL (2 << 4) 1894 # define Z_TEST_EQUAL (3 << 4) 1895 # define Z_TEST_GEQUAL (4 << 4) 1896 # define Z_TEST_GREATER (5 << 4) 1897 # define Z_TEST_NEQUAL (6 << 4) 1898 # define Z_TEST_ALWAYS (7 << 4) 1899 # define Z_TEST_MASK (7 << 4) 1900 # define STENCIL_TEST_NEVER (0 << 12) 1901 # define STENCIL_TEST_LESS (1 << 12) 1902 # define STENCIL_TEST_LEQUAL (2 << 12) 1903 # define STENCIL_TEST_EQUAL (3 << 12) 1904 # define STENCIL_TEST_GEQUAL (4 << 12) 1905 # define STENCIL_TEST_GREATER (5 << 12) 1906 # define STENCIL_TEST_NEQUAL (6 << 12) 1907 # define STENCIL_TEST_ALWAYS (7 << 12) 1908 # define STENCIL_TEST_MASK (0x7 << 12) 1909 # define STENCIL_FAIL_KEEP (0 << 16) 1910 # define STENCIL_FAIL_ZERO (1 << 16) 1911 # define STENCIL_FAIL_REPLACE (2 << 16) 1912 # define STENCIL_FAIL_INC (3 << 16) 1913 # define STENCIL_FAIL_DEC (4 << 16) 1914 # define STENCIL_FAIL_INVERT (5 << 16) 1915 # define STENCIL_FAIL_MASK (0x7 << 16) 1916 # define STENCIL_ZPASS_KEEP (0 << 20) 1917 # define STENCIL_ZPASS_ZERO (1 << 20) 1918 # define STENCIL_ZPASS_REPLACE (2 << 20) 1919 # define STENCIL_ZPASS_INC (3 << 20) 1920 # define STENCIL_ZPASS_DEC (4 << 20) 1921 # define STENCIL_ZPASS_INVERT (5 << 20) 1922 # define STENCIL_ZPASS_MASK (0x7 << 20) 1923 # define STENCIL_ZFAIL_KEEP (0 << 24) 1924 # define STENCIL_ZFAIL_ZERO (1 << 24) 1925 # define STENCIL_ZFAIL_REPLACE (2 << 24) 1926 # define STENCIL_ZFAIL_INC (3 << 24) 1927 # define STENCIL_ZFAIL_DEC (4 << 24) 1928 # define STENCIL_ZFAIL_INVERT (5 << 24) 1929 # define STENCIL_ZFAIL_MASK (0x7 << 24) 1930 # define Z_COMPRESSION_ENABLE (1 << 28) 1931 # define FORCE_Z_DIRTY (1 << 29) 1932 # define Z_WRITE_ENABLE (1 << 30) 1933 #define RE_LINE_PATTERN 0x1cd0 1934 # define LINE_PATTERN_MASK 0x0000ffff 1935 # define LINE_REPEAT_COUNT_SHIFT 16 1936 # define LINE_PATTERN_START_SHIFT 24 1937 # define LINE_PATTERN_LITTLE_BIT_ORDER (0 << 28) 1938 # define LINE_PATTERN_BIG_BIT_ORDER (1 << 28) 1939 # define LINE_PATTERN_AUTO_RESET (1 << 29) 1940 #define RE_LINE_STATE 0x1cd4 1941 # define LINE_CURRENT_PTR_SHIFT 0 1942 # define LINE_CURRENT_COUNT_SHIFT 8 1943 #define RE_MISC 0x26c4 1944 # define STIPPLE_COORD_MASK 0x1f 1945 # define STIPPLE_X_OFFSET_SHIFT 0 1946 # define STIPPLE_X_OFFSET_MASK (0x1f << 0) 1947 # define STIPPLE_Y_OFFSET_SHIFT 8 1948 # define STIPPLE_Y_OFFSET_MASK (0x1f << 8) 1949 # define STIPPLE_LITTLE_BIT_ORDER (0 << 16) 1950 # define STIPPLE_BIG_BIT_ORDER (1 << 16) 1951 #define RE_SOLID_COLOR 0x1c1c 1952 #define RE_POINTSIZE 0x2648 1953 # define RE_POINTSIZE_SHIFT 0 1954 # define RE_MAXPOINTSIZE_SHIFT 16 1955 #define RE_TOP_LEFT 0x26c0 1956 # define RE_LEFT_SHIFT 0 1957 # define RE_TOP_SHIFT 16 1958 #define RE_BOTTOM_RIGHT 0x1c44 1959 # define RE_RIGHT_SHIFT 0 1960 # define RE_BOTTOM_SHIFT 16 1961 1962 #define SE_CNTL 0x1c4c 1963 # define FFACE_CULL_CW (0 << 0) 1964 # define FFACE_CULL_CCW (1 << 0) 1965 # define FFACE_CULL_DIR_MASK (1 << 0) 1966 # define BFACE_CULL (0 << 1) 1967 # define BFACE_SOLID (3 << 1) 1968 # define FFACE_CULL (0 << 3) 1969 # define FFACE_SOLID (3 << 3) 1970 # define FFACE_CULL_MASK (3 << 3) 1971 # define BADVTX_CULL_DISABLE (1 << 5) 1972 # define FLAT_SHADE_VTX_0 (0 << 6) 1973 # define FLAT_SHADE_VTX_1 (1 << 6) 1974 # define FLAT_SHADE_VTX_2 (2 << 6) 1975 # define FLAT_SHADE_VTX_LAST (3 << 6) 1976 # define DIFFUSE_SHADE_SOLID (0 << 8) 1977 # define DIFFUSE_SHADE_FLAT (1 << 8) 1978 # define DIFFUSE_SHADE_GOURAUD (2 << 8) 1979 # define DIFFUSE_SHADE_MASK (3 << 8) 1980 # define ALPHA_SHADE_SOLID (0 << 10) 1981 # define ALPHA_SHADE_FLAT (1 << 10) 1982 # define ALPHA_SHADE_GOURAUD (2 << 10) 1983 # define ALPHA_SHADE_MASK (3 << 10) 1984 # define SPECULAR_SHADE_SOLID (0 << 12) 1985 # define SPECULAR_SHADE_FLAT (1 << 12) 1986 # define SPECULAR_SHADE_GOURAUD (2 << 12) 1987 # define SPECULAR_SHADE_MASK (3 << 12) 1988 # define FOG_SHADE_SOLID (0 << 14) 1989 # define FOG_SHADE_FLAT (1 << 14) 1990 # define FOG_SHADE_GOURAUD (2 << 14) 1991 # define FOG_SHADE_MASK (3 << 14) 1992 # define ZBIAS_ENABLE_POINT (1 << 16) 1993 # define ZBIAS_ENABLE_LINE (1 << 17) 1994 # define ZBIAS_ENABLE_TRI (1 << 18) 1995 # define WIDELINE_ENABLE (1 << 20) 1996 # define VPORT_XY_XFORM_ENABLE (1 << 24) 1997 # define VPORT_Z_XFORM_ENABLE (1 << 25) 1998 # define VTX_PIX_CENTER_D3D (0 << 27) 1999 # define VTX_PIX_CENTER_OGL (1 << 27) 2000 # define ROUND_MODE_TRUNC (0 << 28) 2001 # define ROUND_MODE_ROUND (1 << 28) 2002 # define ROUND_MODE_ROUND_EVEN (2 << 28) 2003 # define ROUND_MODE_ROUND_ODD (3 << 28) 2004 # define ROUND_PREC_16TH_PIX (0 << 30) 2005 # define ROUND_PREC_8TH_PIX (1 << 30) 2006 # define ROUND_PREC_4TH_PIX (2 << 30) 2007 # define ROUND_PREC_HALF_PIX (3 << 30) 2008 #define R200_RE_CNTL 0x1c50 2009 # define R200_STIPPLE_ENABLE 0x1 2010 # define R200_SCISSOR_ENABLE 0x2 2011 # define R200_PATTERN_ENABLE 0x4 2012 # define R200_PERSPECTIVE_ENABLE 0x8 2013 # define R200_POINT_SMOOTH 0x20 2014 # define R200_VTX_STQ0_D3D 0x00010000 2015 # define R200_VTX_STQ1_D3D 0x00040000 2016 # define R200_VTX_STQ2_D3D 0x00100000 2017 # define R200_VTX_STQ3_D3D 0x00400000 2018 # define R200_VTX_STQ4_D3D 0x01000000 2019 # define R200_VTX_STQ5_D3D 0x04000000 2020 #define SE_CNTL_STATUS 0x2140 2021 # define VC_NO_SWAP (0 << 0) 2022 # define VC_16BIT_SWAP (1 << 0) 2023 # define VC_32BIT_SWAP (2 << 0) 2024 # define VC_HALF_DWORD_SWAP (3 << 0) 2025 # define TCL_BYPASS (1 << 8) 2026 #define SE_COORD_FMT 0x1c50 2027 # define VTX_XY_PRE_MULT_1_OVER_W0 (1 << 0) 2028 # define VTX_Z_PRE_MULT_1_OVER_W0 (1 << 1) 2029 # define VTX_ST0_NONPARAMETRIC (1 << 8) 2030 # define VTX_ST1_NONPARAMETRIC (1 << 9) 2031 # define VTX_ST2_NONPARAMETRIC (1 << 10) 2032 # define VTX_ST3_NONPARAMETRIC (1 << 11) 2033 # define VTX_W0_NORMALIZE (1 << 12) 2034 # define VTX_W0_IS_NOT_1_OVER_W0 (1 << 16) 2035 # define VTX_ST0_PRE_MULT_1_OVER_W0 (1 << 17) 2036 # define VTX_ST1_PRE_MULT_1_OVER_W0 (1 << 19) 2037 # define VTX_ST2_PRE_MULT_1_OVER_W0 (1 << 21) 2038 # define VTX_ST3_PRE_MULT_1_OVER_W0 (1 << 23) 2039 # define TEX1_W_ROUTING_USE_W0 (0 << 26) 2040 # define TEX1_W_ROUTING_USE_Q1 (1 << 26) 2041 #define SE_LINE_WIDTH 0x1db8 2042 #define SE_TCL_LIGHT_MODEL_CTL 0x226c 2043 # define LIGHTING_ENABLE (1 << 0) 2044 # define LIGHT_IN_MODELSPACE (1 << 1) 2045 # define LOCAL_VIEWER (1 << 2) 2046 # define NORMALIZE_NORMALS (1 << 3) 2047 # define RESCALE_NORMALS (1 << 4) 2048 # define SPECULAR_LIGHTS (1 << 5) 2049 # define DIFFUSE_SPECULAR_COMBINE (1 << 6) 2050 # define LIGHT_ALPHA (1 << 7) 2051 # define LOCAL_LIGHT_VEC_GL (1 << 8) 2052 # define LIGHT_NO_NORMAL_AMBIENT_ONLY (1 << 9) 2053 # define LM_SOURCE_STATE_PREMULT 0 2054 # define LM_SOURCE_STATE_MULT 1 2055 # define LM_SOURCE_VERTEX_DIFFUSE 2 2056 # define LM_SOURCE_VERTEX_SPECULAR 3 2057 # define EMISSIVE_SOURCE_SHIFT 16 2058 # define AMBIENT_SOURCE_SHIFT 18 2059 # define DIFFUSE_SOURCE_SHIFT 20 2060 # define SPECULAR_SOURCE_SHIFT 22 2061 #define SE_TCL_MATERIAL_AMBIENT_RED 0x2220 2062 #define SE_TCL_MATERIAL_AMBIENT_GREEN 0x2224 2063 #define SE_TCL_MATERIAL_AMBIENT_BLUE 0x2228 2064 #define SE_TCL_MATERIAL_AMBIENT_ALPHA 0x222c 2065 #define SE_TCL_MATERIAL_DIFFUSE_RED 0x2230 2066 #define SE_TCL_MATERIAL_DIFFUSE_GREEN 0x2234 2067 #define SE_TCL_MATERIAL_DIFFUSE_BLUE 0x2238 2068 #define SE_TCL_MATERIAL_DIFFUSE_ALPHA 0x223c 2069 #define SE_TCL_MATERIAL_EMMISSIVE_RED 0x2210 2070 #define SE_TCL_MATERIAL_EMMISSIVE_GREEN 0x2214 2071 #define SE_TCL_MATERIAL_EMMISSIVE_BLUE 0x2218 2072 #define SE_TCL_MATERIAL_EMMISSIVE_ALPHA 0x221c 2073 #define SE_TCL_MATERIAL_SPECULAR_RED 0x2240 2074 #define SE_TCL_MATERIAL_SPECULAR_GREEN 0x2244 2075 #define SE_TCL_MATERIAL_SPECULAR_BLUE 0x2248 2076 #define SE_TCL_MATERIAL_SPECULAR_ALPHA 0x224c 2077 #define SE_TCL_MATRIX_SELECT_0 0x225c 2078 # define MODELVIEW_0_SHIFT 0 2079 # define MODELVIEW_1_SHIFT 4 2080 # define MODELVIEW_2_SHIFT 8 2081 # define MODELVIEW_3_SHIFT 12 2082 # define IT_MODELVIEW_0_SHIFT 16 2083 # define IT_MODELVIEW_1_SHIFT 20 2084 # define IT_MODELVIEW_2_SHIFT 24 2085 # define IT_MODELVIEW_3_SHIFT 28 2086 #define SE_TCL_MATRIX_SELECT_1 0x2260 2087 # define MODELPROJECT_0_SHIFT 0 2088 # define MODELPROJECT_1_SHIFT 4 2089 # define MODELPROJECT_2_SHIFT 8 2090 # define MODELPROJECT_3_SHIFT 12 2091 # define TEXMAT_0_SHIFT 16 2092 # define TEXMAT_1_SHIFT 20 2093 # define TEXMAT_2_SHIFT 24 2094 # define TEXMAT_3_SHIFT 28 2095 2096 2097 #define SE_TCL_OUTPUT_VTX_FMT 0x2254 2098 # define TCL_VTX_W0 (1 << 0) 2099 # define TCL_VTX_FP_DIFFUSE (1 << 1) 2100 # define TCL_VTX_FP_ALPHA (1 << 2) 2101 # define TCL_VTX_PK_DIFFUSE (1 << 3) 2102 # define TCL_VTX_FP_SPEC (1 << 4) 2103 # define TCL_VTX_FP_FOG (1 << 5) 2104 # define TCL_VTX_PK_SPEC (1 << 6) 2105 # define TCL_VTX_ST0 (1 << 7) 2106 # define TCL_VTX_ST1 (1 << 8) 2107 # define TCL_VTX_Q1 (1 << 9) 2108 # define TCL_VTX_ST2 (1 << 10) 2109 # define TCL_VTX_Q2 (1 << 11) 2110 # define TCL_VTX_ST3 (1 << 12) 2111 # define TCL_VTX_Q3 (1 << 13) 2112 # define TCL_VTX_Q0 (1 << 14) 2113 # define TCL_VTX_WEIGHT_COUNT_SHIFT 15 2114 # define TCL_VTX_NORM0 (1 << 18) 2115 # define TCL_VTX_XY1 (1 << 27) 2116 # define TCL_VTX_Z1 (1 << 28) 2117 # define TCL_VTX_W1 (1 << 29) 2118 # define TCL_VTX_NORM1 (1 << 30) 2119 # define TCL_VTX_Z0 (1 << 31) 2120 2121 #define SE_TCL_OUTPUT_VTX_SEL 0x2258 2122 # define TCL_COMPUTE_XYZW (1 << 0) 2123 # define TCL_COMPUTE_DIFFUSE (1 << 1) 2124 # define TCL_COMPUTE_SPECULAR (1 << 2) 2125 # define TCL_FORCE_NAN_IF_COLOR_NAN (1 << 3) 2126 # define TCL_FORCE_INORDER_PROC (1 << 4) 2127 # define TCL_TEX_INPUT_TEX_0 0 2128 # define TCL_TEX_INPUT_TEX_1 1 2129 # define TCL_TEX_INPUT_TEX_2 2 2130 # define TCL_TEX_INPUT_TEX_3 3 2131 # define TCL_TEX_COMPUTED_TEX_0 8 2132 # define TCL_TEX_COMPUTED_TEX_1 9 2133 # define TCL_TEX_COMPUTED_TEX_2 10 2134 # define TCL_TEX_COMPUTED_TEX_3 11 2135 # define TCL_TEX_0_OUTPUT_SHIFT 16 2136 # define TCL_TEX_1_OUTPUT_SHIFT 20 2137 # define TCL_TEX_2_OUTPUT_SHIFT 24 2138 # define TCL_TEX_3_OUTPUT_SHIFT 28 2139 2140 #define SE_TCL_PER_LIGHT_CTL_0 0x2270 2141 # define LIGHT_0_ENABLE (1 << 0) 2142 # define LIGHT_0_ENABLE_AMBIENT (1 << 1) 2143 # define LIGHT_0_ENABLE_SPECULAR (1 << 2) 2144 # define LIGHT_0_IS_LOCAL (1 << 3) 2145 # define LIGHT_0_IS_SPOT (1 << 4) 2146 # define LIGHT_0_DUAL_CONE (1 << 5) 2147 # define LIGHT_0_ENABLE_RANGE_ATTEN (1 << 6) 2148 # define LIGHT_0_CONSTANT_RANGE_ATTEN (1 << 7) 2149 # define LIGHT_0_SHIFT 0 2150 # define LIGHT_1_ENABLE (1 << 16) 2151 # define LIGHT_1_ENABLE_AMBIENT (1 << 17) 2152 # define LIGHT_1_ENABLE_SPECULAR (1 << 18) 2153 # define LIGHT_1_IS_LOCAL (1 << 19) 2154 # define LIGHT_1_IS_SPOT (1 << 20) 2155 # define LIGHT_1_DUAL_CONE (1 << 21) 2156 # define LIGHT_1_ENABLE_RANGE_ATTEN (1 << 22) 2157 # define LIGHT_1_CONSTANT_RANGE_ATTEN (1 << 23) 2158 # define LIGHT_1_SHIFT 16 2159 #define SE_TCL_PER_LIGHT_CTL_1 0x2274 2160 # define LIGHT_2_SHIFT 0 2161 # define LIGHT_3_SHIFT 16 2162 #define SE_TCL_PER_LIGHT_CTL_2 0x2278 2163 # define LIGHT_4_SHIFT 0 2164 # define LIGHT_5_SHIFT 16 2165 #define SE_TCL_PER_LIGHT_CTL_3 0x227c 2166 # define LIGHT_6_SHIFT 0 2167 # define LIGHT_7_SHIFT 16 2168 2169 #define SE_TCL_SHININESS 0x2250 2170 2171 #define SE_TCL_TEXTURE_PROC_CTL 0x2268 2172 # define TEXGEN_TEXMAT_0_ENABLE (1 << 0) 2173 # define TEXGEN_TEXMAT_1_ENABLE (1 << 1) 2174 # define TEXGEN_TEXMAT_2_ENABLE (1 << 2) 2175 # define TEXGEN_TEXMAT_3_ENABLE (1 << 3) 2176 # define TEXMAT_0_ENABLE (1 << 4) 2177 # define TEXMAT_1_ENABLE (1 << 5) 2178 # define TEXMAT_2_ENABLE (1 << 6) 2179 # define TEXMAT_3_ENABLE (1 << 7) 2180 # define TEXGEN_INPUT_MASK 0xf 2181 # define TEXGEN_INPUT_TEXCOORD_0 0 2182 # define TEXGEN_INPUT_TEXCOORD_1 1 2183 # define TEXGEN_INPUT_TEXCOORD_2 2 2184 # define TEXGEN_INPUT_TEXCOORD_3 3 2185 # define TEXGEN_INPUT_OBJ 4 2186 # define TEXGEN_INPUT_EYE 5 2187 # define TEXGEN_INPUT_EYE_NORMAL 6 2188 # define TEXGEN_INPUT_EYE_REFLECT 7 2189 # define TEXGEN_INPUT_EYE_NORMALIZED 8 2190 # define TEXGEN_0_INPUT_SHIFT 16 2191 # define TEXGEN_1_INPUT_SHIFT 20 2192 # define TEXGEN_2_INPUT_SHIFT 24 2193 # define TEXGEN_3_INPUT_SHIFT 28 2194 2195 #define SE_TCL_UCP_VERT_BLEND_CTL 0x2264 2196 # define UCP_IN_CLIP_SPACE (1 << 0) 2197 # define UCP_IN_MODEL_SPACE (1 << 1) 2198 # define UCP_ENABLE_0 (1 << 2) 2199 # define UCP_ENABLE_1 (1 << 3) 2200 # define UCP_ENABLE_2 (1 << 4) 2201 # define UCP_ENABLE_3 (1 << 5) 2202 # define UCP_ENABLE_4 (1 << 6) 2203 # define UCP_ENABLE_5 (1 << 7) 2204 # define TCL_FOG_MASK (3 << 8) 2205 # define TCL_FOG_DISABLE (0 << 8) 2206 # define TCL_FOG_EXP (1 << 8) 2207 # define TCL_FOG_EXP2 (2 << 8) 2208 # define TCL_FOG_LINEAR (3 << 8) 2209 # define RNG_BASED_FOG (1 << 10) 2210 # define LIGHT_TWOSIDE (1 << 11) 2211 # define BLEND_OP_COUNT_MASK (7 << 12) 2212 # define BLEND_OP_COUNT_SHIFT 12 2213 # define POSITION_BLEND_OP_ENABLE (1 << 16) 2214 # define NORMAL_BLEND_OP_ENABLE (1 << 17) 2215 # define VERTEX_BLEND_SRC_0_PRIMARY (1 << 18) 2216 # define VERTEX_BLEND_SRC_0_SECONDARY (1 << 18) 2217 # define VERTEX_BLEND_SRC_1_PRIMARY (1 << 19) 2218 # define VERTEX_BLEND_SRC_1_SECONDARY (1 << 19) 2219 # define VERTEX_BLEND_SRC_2_PRIMARY (1 << 20) 2220 # define VERTEX_BLEND_SRC_2_SECONDARY (1 << 20) 2221 # define VERTEX_BLEND_SRC_3_PRIMARY (1 << 21) 2222 # define VERTEX_BLEND_SRC_3_SECONDARY (1 << 21) 2223 # define VERTEX_BLEND_WGT_MINUS_ONE (1 << 22) 2224 # define CULL_FRONT_IS_CW (0 << 28) 2225 # define CULL_FRONT_IS_CCW (1 << 28) 2226 # define CULL_FRONT (1 << 29) 2227 # define CULL_BACK (1 << 30) 2228 # define FORCE_W_TO_ONE (1 << 31) 2229 2230 #define SE_VPORT_XSCALE 0x1d98 2231 #define SE_VPORT_XOFFSET 0x1d9c 2232 #define SE_VPORT_YSCALE 0x1da0 2233 #define SE_VPORT_YOFFSET 0x1da4 2234 #define SE_VPORT_ZSCALE 0x1da8 2235 #define SE_VPORT_ZOFFSET 0x1dac 2236 #define SE_ZBIAS_FACTOR 0x1db0 2237 #define SE_ZBIAS_CONSTANT 0x1db4 2238 2239 #define SE_VTX_FMT 0x2080 2240 # define SE_VTX_FMT_XY 0x00000000 2241 # define SE_VTX_FMT_W0 0x00000001 2242 # define SE_VTX_FMT_FPCOLOR 0x00000002 2243 # define SE_VTX_FMT_FPALPHA 0x00000004 2244 # define SE_VTX_FMT_PKCOLOR 0x00000008 2245 # define SE_VTX_FMT_FPSPEC 0x00000010 2246 # define SE_VTX_FMT_FPFOG 0x00000020 2247 # define SE_VTX_FMT_PKSPEC 0x00000040 2248 # define SE_VTX_FMT_ST0 0x00000080 2249 # define SE_VTX_FMT_ST1 0x00000100 2250 # define SE_VTX_FMT_Q1 0x00000200 2251 # define SE_VTX_FMT_ST2 0x00000400 2252 # define SE_VTX_FMT_Q2 0x00000800 2253 # define SE_VTX_FMT_ST3 0x00001000 2254 # define SE_VTX_FMT_Q3 0x00002000 2255 # define SE_VTX_FMT_Q0 0x00004000 2256 # define SE_VTX_FMT_BLND_WEIGHT_CNT_MASK 0x00038000 2257 # define SE_VTX_FMT_N0 0x00040000 2258 # define SE_VTX_FMT_XY1 0x08000000 2259 # define SE_VTX_FMT_Z1 0x10000000 2260 # define SE_VTX_FMT_W1 0x20000000 2261 # define SE_VTX_FMT_N1 0x40000000 2262 # define SE_VTX_FMT_Z 0x80000000 2263 2264 #define SE_VF_CNTL 0x2084 2265 # define VF_PRIM_TYPE_POINT_LIST 1 2266 # define VF_PRIM_TYPE_LINE_LIST 2 2267 # define VF_PRIM_TYPE_LINE_STRIP 3 2268 # define VF_PRIM_TYPE_TRIANGLE_LIST 4 2269 # define VF_PRIM_TYPE_TRIANGLE_FAN 5 2270 # define VF_PRIM_TYPE_TRIANGLE_STRIP 6 2271 # define VF_PRIM_TYPE_TRIANGLE_FLAG 7 2272 # define VF_PRIM_TYPE_RECTANGLE_LIST 8 2273 # define VF_PRIM_TYPE_POINT_LIST_3 9 2274 # define VF_PRIM_TYPE_LINE_LIST_3 10 2275 # define VF_PRIM_TYPE_SPIRIT_LIST 11 2276 # define VF_PRIM_TYPE_LINE_LOOP 12 2277 # define VF_PRIM_TYPE_QUAD_LIST 13 2278 # define VF_PRIM_TYPE_QUAD_STRIP 14 2279 # define VF_PRIM_TYPE_POLYGON 15 2280 # define VF_PRIM_WALK_STATE (0<<4) 2281 # define VF_PRIM_WALK_INDEX (1<<4) 2282 # define VF_PRIM_WALK_LIST (2<<4) 2283 # define VF_PRIM_WALK_DATA (3<<4) 2284 # define VF_COLOR_ORDER_RGBA (1<<6) 2285 # define VF_RADEON_MODE (1<<8) 2286 # define VF_TCL_OUTPUT_CTL_ENA (1<<9) 2287 # define VF_PROG_STREAM_ENA (1<<10) 2288 # define VF_INDEX_SIZE_SHIFT 11 2289 # define VF_NUM_VERTICES_SHIFT 16 2290 2291 #define SE_PORT_DATA0 0x2000 2292 2293 #define R200_SE_VAP_CNTL 0x2080 2294 # define R200_VAP_TCL_ENABLE 0x00000001 2295 # define R200_VAP_SINGLE_BUF_STATE_ENABLE 0x00000010 2296 # define R200_VAP_FORCE_W_TO_ONE 0x00010000 2297 # define R200_VAP_D3D_TEX_DEFAULT 0x00020000 2298 # define R200_VAP_VF_MAX_VTX_NUM__SHIFT 18 2299 # define R200_VAP_VF_MAX_VTX_NUM (9 << 18) 2300 # define R200_VAP_DX_CLIP_SPACE_DEF 0x00400000 2301 #define R200_VF_MAX_VTX_INDX 0x210c 2302 #define R200_VF_MIN_VTX_INDX 0x2110 2303 #define R200_SE_VTE_CNTL 0x20b0 2304 # define R200_VPORT_X_SCALE_ENA 0x00000001 2305 # define R200_VPORT_X_OFFSET_ENA 0x00000002 2306 # define R200_VPORT_Y_SCALE_ENA 0x00000004 2307 # define R200_VPORT_Y_OFFSET_ENA 0x00000008 2308 # define R200_VPORT_Z_SCALE_ENA 0x00000010 2309 # define R200_VPORT_Z_OFFSET_ENA 0x00000020 2310 # define R200_VTX_XY_FMT 0x00000100 2311 # define R200_VTX_Z_FMT 0x00000200 2312 # define R200_VTX_W0_FMT 0x00000400 2313 # define R200_VTX_W0_NORMALIZE 0x00000800 2314 # define R200_VTX_ST_DENORMALIZED 0x00001000 2315 #define R200_SE_VAP_CNTL_STATUS 0x2140 2316 # define R200_VC_NO_SWAP (0 << 0) 2317 # define R200_VC_16BIT_SWAP (1 << 0) 2318 # define R200_VC_32BIT_SWAP (2 << 0) 2319 # define R200_TCL_BYPASS (1 << 8) 2320 #define R200_PP_TXFILTER_0 0x2c00 2321 #define R200_PP_TXFILTER_1 0x2c20 2322 # define R200_MAG_FILTER_NEAREST (0 << 0) 2323 # define R200_MAG_FILTER_LINEAR (1 << 0) 2324 # define R200_MAG_FILTER_MASK (1 << 0) 2325 # define R200_MIN_FILTER_NEAREST (0 << 1) 2326 # define R200_MIN_FILTER_LINEAR (1 << 1) 2327 # define R200_MIN_FILTER_NEAREST_MIP_NEAREST (2 << 1) 2328 # define R200_MIN_FILTER_NEAREST_MIP_LINEAR (3 << 1) 2329 # define R200_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 1) 2330 # define R200_MIN_FILTER_LINEAR_MIP_LINEAR (7 << 1) 2331 # define R200_MIN_FILTER_ANISO_NEAREST (8 << 1) 2332 # define R200_MIN_FILTER_ANISO_LINEAR (9 << 1) 2333 # define R200_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST (10 << 1) 2334 # define R200_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR (11 << 1) 2335 # define R200_MIN_FILTER_MASK (15 << 1) 2336 # define R200_MAX_ANISO_1_TO_1 (0 << 5) 2337 # define R200_MAX_ANISO_2_TO_1 (1 << 5) 2338 # define R200_MAX_ANISO_4_TO_1 (2 << 5) 2339 # define R200_MAX_ANISO_8_TO_1 (3 << 5) 2340 # define R200_MAX_ANISO_16_TO_1 (4 << 5) 2341 # define R200_MAX_ANISO_MASK (7 << 5) 2342 # define R200_MAX_MIP_LEVEL_MASK (0x0f << 16) 2343 # define R200_MAX_MIP_LEVEL_SHIFT 16 2344 # define R200_YUV_TO_RGB (1 << 20) 2345 # define R200_YUV_TEMPERATURE_COOL (0 << 21) 2346 # define R200_YUV_TEMPERATURE_HOT (1 << 21) 2347 # define R200_YUV_TEMPERATURE_MASK (1 << 21) 2348 # define R200_WRAPEN_S (1 << 22) 2349 # define R200_CLAMP_S_WRAP (0 << 23) 2350 # define R200_CLAMP_S_MIRROR (1 << 23) 2351 # define R200_CLAMP_S_CLAMP_LAST (2 << 23) 2352 # define R200_CLAMP_S_MIRROR_CLAMP_LAST (3 << 23) 2353 # define R200_CLAMP_S_CLAMP_BORDER (4 << 23) 2354 # define R200_CLAMP_S_MIRROR_CLAMP_BORDER (5 << 23) 2355 # define R200_CLAMP_S_CLAMP_GL (6 << 23) 2356 # define R200_CLAMP_S_MIRROR_CLAMP_GL (7 << 23) 2357 # define R200_CLAMP_S_MASK (7 << 23) 2358 # define R200_WRAPEN_T (1 << 26) 2359 # define R200_CLAMP_T_WRAP (0 << 27) 2360 # define R200_CLAMP_T_MIRROR (1 << 27) 2361 # define R200_CLAMP_T_CLAMP_LAST (2 << 27) 2362 # define R200_CLAMP_T_MIRROR_CLAMP_LAST (3 << 27) 2363 # define R200_CLAMP_T_CLAMP_BORDER (4 << 27) 2364 # define R200_CLAMP_T_MIRROR_CLAMP_BORDER (5 << 27) 2365 # define R200_CLAMP_T_CLAMP_GL (6 << 27) 2366 # define R200_CLAMP_T_MIRROR_CLAMP_GL (7 << 27) 2367 # define R200_CLAMP_T_MASK (7 << 27) 2368 # define R200_KILL_LT_ZERO (1 << 30) 2369 # define R200_BORDER_MODE_OGL (0 << 31) 2370 # define R200_BORDER_MODE_D3D (1 << 31) 2371 #define R200_PP_TXFORMAT_0 0x2c04 2372 #define R200_PP_TXFORMAT_1 0x2c24 2373 # define R200_TXFORMAT_I8 (0 << 0) 2374 # define R200_TXFORMAT_AI88 (1 << 0) 2375 # define R200_TXFORMAT_RGB332 (2 << 0) 2376 # define R200_TXFORMAT_ARGB1555 (3 << 0) 2377 # define R200_TXFORMAT_RGB565 (4 << 0) 2378 # define R200_TXFORMAT_ARGB4444 (5 << 0) 2379 # define R200_TXFORMAT_ARGB8888 (6 << 0) 2380 # define R200_TXFORMAT_RGBA8888 (7 << 0) 2381 # define R200_TXFORMAT_Y8 (8 << 0) 2382 # define R200_TXFORMAT_AVYU (9 << 0) 2383 # define R200_TXFORMAT_VYUY422 (10 << 0) 2384 # define R200_TXFORMAT_YVYU422 (11 << 0) 2385 # define R200_TXFORMAT_DXT1 (12 << 0) 2386 # define R200_TXFORMAT_DXT23 (14 << 0) 2387 # define R200_TXFORMAT_DXT45 (15 << 0) 2388 # define R200_TXFORMAT_FORMAT_MASK (31 << 0) 2389 # define R200_TXFORMAT_FORMAT_SHIFT 0 2390 # define R200_TXFORMAT_ALPHA_IN_MAP (1 << 6) 2391 # define R200_TXFORMAT_NON_POWER2 (1 << 7) 2392 # define R200_TXFORMAT_WIDTH_MASK (15 << 8) 2393 # define R200_TXFORMAT_WIDTH_SHIFT 8 2394 # define R200_TXFORMAT_HEIGHT_MASK (15 << 12) 2395 # define R200_TXFORMAT_HEIGHT_SHIFT 12 2396 # define R200_TXFORMAT_F5_WIDTH_MASK (15 << 16) /* cube face 5 */ 2397 # define R200_TXFORMAT_F5_WIDTH_SHIFT 16 2398 # define R200_TXFORMAT_F5_HEIGHT_MASK (15 << 20) 2399 # define R200_TXFORMAT_F5_HEIGHT_SHIFT 20 2400 # define R200_TXFORMAT_ST_ROUTE_STQ0 (0 << 24) 2401 # define R200_TXFORMAT_ST_ROUTE_STQ1 (1 << 24) 2402 # define R200_TXFORMAT_ST_ROUTE_STQ2 (2 << 24) 2403 # define R200_TXFORMAT_ST_ROUTE_STQ3 (3 << 24) 2404 # define R200_TXFORMAT_ST_ROUTE_STQ4 (4 << 24) 2405 # define R200_TXFORMAT_ST_ROUTE_STQ5 (5 << 24) 2406 # define R200_TXFORMAT_ST_ROUTE_MASK (7 << 24) 2407 # define R200_TXFORMAT_ST_ROUTE_SHIFT 24 2408 # define R200_TXFORMAT_ALPHA_MASK_ENABLE (1 << 28) 2409 # define R200_TXFORMAT_CHROMA_KEY_ENABLE (1 << 29) 2410 # define R200_TXFORMAT_CUBIC_MAP_ENABLE (1 << 30) 2411 #define R200_PP_TXFORMAT_X_0 0x2c08 2412 #define R200_PP_TXFORMAT_X_1 0x2c28 2413 #define R200_DEPTH_LOG2_MASK (0xf << 0) 2414 #define R200_DEPTH_LOG2_SHIFT 0 2415 #define R200_VOLUME_FILTER_SHIFT 4 2416 #define R200_VOLUME_FILTER_MASK (1 << 4) 2417 #define R200_VOLUME_FILTER_NEAREST (0 << 4) 2418 #define R200_VOLUME_FILTER_LINEAR (1 << 4) 2419 #define R200_WRAPEN_Q (1 << 8) 2420 #define R200_CLAMP_Q_WRAP (0 << 9) 2421 #define R200_CLAMP_Q_MIRROR (1 << 9) 2422 #define R200_CLAMP_Q_CLAMP_LAST (2 << 9) 2423 #define R200_CLAMP_Q_MIRROR_CLAMP_LAST (3 << 9) 2424 #define R200_CLAMP_Q_CLAMP_BORDER (4 << 9) 2425 #define R200_CLAMP_Q_MIRROR_CLAMP_BORDER (5 << 9) 2426 #define R200_CLAMP_Q_CLAMP_GL (6 << 9) 2427 #define R200_CLAMP_Q_MIRROR_CLAMP_GL (7 << 9) 2428 #define R200_CLAMP_Q_MASK (7 << 9) 2429 #define R200_MIN_MIP_LEVEL_MASK (0xff << 12) 2430 #define R200_MIN_MIP_LEVEL_SHIFT 12 2431 #define R200_TEXCOORD_NONPROJ (0 << 16) 2432 #define R200_TEXCOORD_CUBIC_ENV (1 << 16) 2433 #define R200_TEXCOORD_VOLUME (2 << 16) 2434 #define R200_TEXCOORD_PROJ (3 << 16) 2435 #define R200_TEXCOORD_DEPTH (4 << 16) 2436 #define R200_TEXCOORD_1D_PROJ (5 << 16) 2437 #define R200_TEXCOORD_1D (6 << 16) 2438 #define R200_TEXCOORD_ZERO (7 << 16) 2439 #define R200_TEXCOORD_MASK (7 << 16) 2440 #define R200_LOD_BIAS_MASK (0xfff80000) 2441 #define R200_LOD_BIAS_SHIFT 19 2442 #define R200_PP_TXSIZE_0 0x2c0c /* NPOT only */ 2443 #define R200_PP_TXSIZE_1 0x2c2c 2444 #define R200_PP_TXPITCH_0 0x2c10 /* NPOT only */ 2445 #define R200_PP_TXPITCH_1 0x2c30 2446 #define R200_PP_BORDER_COLOR_0 0x2c14 2447 #define R200_PP_BORDER_COLOR_1 0x2c34 2448 #define R200_PP_TXOFFSET_0 0x2d00 2449 #define R200_PP_TXOFFSET_1 0x2d18 2450 # define R200_TXO_ENDIAN_NO_SWAP (0 << 0) 2451 # define R200_TXO_ENDIAN_BYTE_SWAP (1 << 0) 2452 # define R200_TXO_ENDIAN_WORD_SWAP (2 << 0) 2453 # define R200_TXO_ENDIAN_HALFDW_SWAP (3 << 0) 2454 # define R200_TXO_OFFSET_MASK 0xffffffe0 2455 # define R200_TXO_OFFSET_SHIFT 5 2456 2457 2458 #define R200_PP_TFACTOR_0 0x2ee0 2459 #define R200_PP_TFACTOR_1 0x2ee4 2460 #define R200_PP_TFACTOR_2 0x2ee8 2461 #define R200_PP_TFACTOR_3 0x2eec 2462 #define R200_PP_TFACTOR_4 0x2ef0 2463 #define R200_PP_TFACTOR_5 0x2ef4 2464 2465 #define R200_PP_TXCBLEND_0 0x2f00 2466 #define R200_PP_TXCBLEND_1 0x2f10 2467 # define R200_TXC_ARG_A_ZERO (0) 2468 # define R200_TXC_ARG_A_CURRENT_COLOR (2) 2469 # define R200_TXC_ARG_A_CURRENT_ALPHA (3) 2470 # define R200_TXC_ARG_A_DIFFUSE_COLOR (4) 2471 # define R200_TXC_ARG_A_DIFFUSE_ALPHA (5) 2472 # define R200_TXC_ARG_A_SPECULAR_COLOR (6) 2473 # define R200_TXC_ARG_A_SPECULAR_ALPHA (7) 2474 # define R200_TXC_ARG_A_TFACTOR_COLOR (8) 2475 # define R200_TXC_ARG_A_TFACTOR_ALPHA (9) 2476 # define R200_TXC_ARG_A_R0_COLOR (10) 2477 # define R200_TXC_ARG_A_R0_ALPHA (11) 2478 # define R200_TXC_ARG_A_R1_COLOR (12) 2479 # define R200_TXC_ARG_A_R1_ALPHA (13) 2480 # define R200_TXC_ARG_A_R2_COLOR (14) 2481 # define R200_TXC_ARG_A_R2_ALPHA (15) 2482 # define R200_TXC_ARG_A_R3_COLOR (16) 2483 # define R200_TXC_ARG_A_R3_ALPHA (17) 2484 # define R200_TXC_ARG_A_R4_COLOR (18) 2485 # define R200_TXC_ARG_A_R4_ALPHA (19) 2486 # define R200_TXC_ARG_A_R5_COLOR (20) 2487 # define R200_TXC_ARG_A_R5_ALPHA (21) 2488 # define R200_TXC_ARG_A_TFACTOR1_COLOR (26) 2489 # define R200_TXC_ARG_A_TFACTOR1_ALPHA (27) 2490 # define R200_TXC_ARG_A_MASK (31 << 0) 2491 # define R200_TXC_ARG_A_SHIFT 0 2492 # define R200_TXC_ARG_B_ZERO (0 << 5) 2493 # define R200_TXC_ARG_B_CURRENT_COLOR (2 << 5) 2494 # define R200_TXC_ARG_B_CURRENT_ALPHA (3 << 5) 2495 # define R200_TXC_ARG_B_DIFFUSE_COLOR (4 << 5) 2496 # define R200_TXC_ARG_B_DIFFUSE_ALPHA (5 << 5) 2497 # define R200_TXC_ARG_B_SPECULAR_COLOR (6 << 5) 2498 # define R200_TXC_ARG_B_SPECULAR_ALPHA (7 << 5) 2499 # define R200_TXC_ARG_B_TFACTOR_COLOR (8 << 5) 2500 # define R200_TXC_ARG_B_TFACTOR_ALPHA (9 << 5) 2501 # define R200_TXC_ARG_B_R0_COLOR (10 << 5) 2502 # define R200_TXC_ARG_B_R0_ALPHA (11 << 5) 2503 # define R200_TXC_ARG_B_R1_COLOR (12 << 5) 2504 # define R200_TXC_ARG_B_R1_ALPHA (13 << 5) 2505 # define R200_TXC_ARG_B_R2_COLOR (14 << 5) 2506 # define R200_TXC_ARG_B_R2_ALPHA (15 << 5) 2507 # define R200_TXC_ARG_B_R3_COLOR (16 << 5) 2508 # define R200_TXC_ARG_B_R3_ALPHA (17 << 5) 2509 # define R200_TXC_ARG_B_R4_COLOR (18 << 5) 2510 # define R200_TXC_ARG_B_R4_ALPHA (19 << 5) 2511 # define R200_TXC_ARG_B_R5_COLOR (20 << 5) 2512 # define R200_TXC_ARG_B_R5_ALPHA (21 << 5) 2513 # define R200_TXC_ARG_B_TFACTOR1_COLOR (26 << 5) 2514 # define R200_TXC_ARG_B_TFACTOR1_ALPHA (27 << 5) 2515 # define R200_TXC_ARG_B_MASK (31 << 5) 2516 # define R200_TXC_ARG_B_SHIFT 5 2517 # define R200_TXC_ARG_C_ZERO (0 << 10) 2518 # define R200_TXC_ARG_C_CURRENT_COLOR (2 << 10) 2519 # define R200_TXC_ARG_C_CURRENT_ALPHA (3 << 10) 2520 # define R200_TXC_ARG_C_DIFFUSE_COLOR (4 << 10) 2521 # define R200_TXC_ARG_C_DIFFUSE_ALPHA (5 << 10) 2522 # define R200_TXC_ARG_C_SPECULAR_COLOR (6 << 10) 2523 # define R200_TXC_ARG_C_SPECULAR_ALPHA (7 << 10) 2524 # define R200_TXC_ARG_C_TFACTOR_COLOR (8 << 10) 2525 # define R200_TXC_ARG_C_TFACTOR_ALPHA (9 << 10) 2526 # define R200_TXC_ARG_C_R0_COLOR (10 << 10) 2527 # define R200_TXC_ARG_C_R0_ALPHA (11 << 10) 2528 # define R200_TXC_ARG_C_R1_COLOR (12 << 10) 2529 # define R200_TXC_ARG_C_R1_ALPHA (13 << 10) 2530 # define R200_TXC_ARG_C_R2_COLOR (14 << 10) 2531 # define R200_TXC_ARG_C_R2_ALPHA (15 << 10) 2532 # define R200_TXC_ARG_C_R3_COLOR (16 << 10) 2533 # define R200_TXC_ARG_C_R3_ALPHA (17 << 10) 2534 # define R200_TXC_ARG_C_R4_COLOR (18 << 10) 2535 # define R200_TXC_ARG_C_R4_ALPHA (19 << 10) 2536 # define R200_TXC_ARG_C_R5_COLOR (20 << 10) 2537 # define R200_TXC_ARG_C_R5_ALPHA (21 << 10) 2538 # define R200_TXC_ARG_C_TFACTOR1_COLOR (26 << 10) 2539 # define R200_TXC_ARG_C_TFACTOR1_ALPHA (27 << 10) 2540 # define R200_TXC_ARG_C_MASK (31 << 10) 2541 # define R200_TXC_ARG_C_SHIFT 10 2542 # define R200_TXC_COMP_ARG_A (1 << 16) 2543 # define R200_TXC_COMP_ARG_A_SHIFT (16) 2544 # define R200_TXC_BIAS_ARG_A (1 << 17) 2545 # define R200_TXC_SCALE_ARG_A (1 << 18) 2546 # define R200_TXC_NEG_ARG_A (1 << 19) 2547 # define R200_TXC_COMP_ARG_B (1 << 20) 2548 # define R200_TXC_COMP_ARG_B_SHIFT (20) 2549 # define R200_TXC_BIAS_ARG_B (1 << 21) 2550 # define R200_TXC_SCALE_ARG_B (1 << 22) 2551 # define R200_TXC_NEG_ARG_B (1 << 23) 2552 # define R200_TXC_COMP_ARG_C (1 << 24) 2553 # define R200_TXC_COMP_ARG_C_SHIFT (24) 2554 # define R200_TXC_BIAS_ARG_C (1 << 25) 2555 # define R200_TXC_SCALE_ARG_C (1 << 26) 2556 # define R200_TXC_NEG_ARG_C (1 << 27) 2557 # define R200_TXC_OP_MADD (0 << 28) 2558 # define R200_TXC_OP_CND0 (2 << 28) 2559 # define R200_TXC_OP_LERP (3 << 28) 2560 # define R200_TXC_OP_DOT3 (4 << 28) 2561 # define R200_TXC_OP_DOT4 (5 << 28) 2562 # define R200_TXC_OP_CONDITIONAL (6 << 28) 2563 # define R200_TXC_OP_DOT2_ADD (7 << 28) 2564 # define R200_TXC_OP_MASK (7 << 28) 2565 #define R200_PP_TXCBLEND2_0 0x2f04 2566 #define R200_PP_TXCBLEND2_1 0x2f14 2567 # define R200_TXC_TFACTOR_SEL_SHIFT 0 2568 # define R200_TXC_TFACTOR_SEL_MASK 0x7 2569 # define R200_TXC_TFACTOR1_SEL_SHIFT 4 2570 # define R200_TXC_TFACTOR1_SEL_MASK (0x7 << 4) 2571 # define R200_TXC_SCALE_SHIFT 8 2572 # define R200_TXC_SCALE_MASK (7 << 8) 2573 # define R200_TXC_SCALE_1X (0 << 8) 2574 # define R200_TXC_SCALE_2X (1 << 8) 2575 # define R200_TXC_SCALE_4X (2 << 8) 2576 # define R200_TXC_SCALE_8X (3 << 8) 2577 # define R200_TXC_SCALE_INV2 (5 << 8) 2578 # define R200_TXC_SCALE_INV4 (6 << 8) 2579 # define R200_TXC_SCALE_INV8 (7 << 8) 2580 # define R200_TXC_CLAMP_SHIFT 12 2581 # define R200_TXC_CLAMP_MASK (3 << 12) 2582 # define R200_TXC_CLAMP_WRAP (0 << 12) 2583 # define R200_TXC_CLAMP_0_1 (1 << 12) 2584 # define R200_TXC_CLAMP_8_8 (2 << 12) 2585 # define R200_TXC_OUTPUT_REG_MASK (7 << 16) 2586 # define R200_TXC_OUTPUT_REG_NONE (0 << 16) 2587 # define R200_TXC_OUTPUT_REG_R0 (1 << 16) 2588 # define R200_TXC_OUTPUT_REG_R1 (2 << 16) 2589 # define R200_TXC_OUTPUT_REG_R2 (3 << 16) 2590 # define R200_TXC_OUTPUT_REG_R3 (4 << 16) 2591 # define R200_TXC_OUTPUT_REG_R4 (5 << 16) 2592 # define R200_TXC_OUTPUT_REG_R5 (6 << 16) 2593 # define R200_TXC_OUTPUT_MASK_MASK (7 << 20) 2594 # define R200_TXC_OUTPUT_MASK_RGB (0 << 20) 2595 # define R200_TXC_OUTPUT_MASK_RG (1 << 20) 2596 # define R200_TXC_OUTPUT_MASK_RB (2 << 20) 2597 # define R200_TXC_OUTPUT_MASK_R (3 << 20) 2598 # define R200_TXC_OUTPUT_MASK_GB (4 << 20) 2599 # define R200_TXC_OUTPUT_MASK_G (5 << 20) 2600 # define R200_TXC_OUTPUT_MASK_B (6 << 20) 2601 # define R200_TXC_OUTPUT_MASK_NONE (7 << 20) 2602 # define R200_TXC_REPL_NORMAL 0 2603 # define R200_TXC_REPL_RED 1 2604 # define R200_TXC_REPL_GREEN 2 2605 # define R200_TXC_REPL_BLUE 3 2606 # define R200_TXC_REPL_ARG_A_SHIFT 26 2607 # define R200_TXC_REPL_ARG_A_MASK (3 << 26) 2608 # define R200_TXC_REPL_ARG_B_SHIFT 28 2609 # define R200_TXC_REPL_ARG_B_MASK (3 << 28) 2610 # define R200_TXC_REPL_ARG_C_SHIFT 30 2611 # define R200_TXC_REPL_ARG_C_MASK (3 << 30) 2612 #define R200_PP_TXABLEND_0 0x2f08 2613 #define R200_PP_TXABLEND_1 0x2f18 2614 # define R200_TXA_ARG_A_ZERO (0) 2615 # define R200_TXA_ARG_A_CURRENT_ALPHA (2) /* guess */ 2616 # define R200_TXA_ARG_A_CURRENT_BLUE (3) /* guess */ 2617 # define R200_TXA_ARG_A_DIFFUSE_ALPHA (4) 2618 # define R200_TXA_ARG_A_DIFFUSE_BLUE (5) 2619 # define R200_TXA_ARG_A_SPECULAR_ALPHA (6) 2620 # define R200_TXA_ARG_A_SPECULAR_BLUE (7) 2621 # define R200_TXA_ARG_A_TFACTOR_ALPHA (8) 2622 # define R200_TXA_ARG_A_TFACTOR_BLUE (9) 2623 # define R200_TXA_ARG_A_R0_ALPHA (10) 2624 # define R200_TXA_ARG_A_R0_BLUE (11) 2625 # define R200_TXA_ARG_A_R1_ALPHA (12) 2626 # define R200_TXA_ARG_A_R1_BLUE (13) 2627 # define R200_TXA_ARG_A_R2_ALPHA (14) 2628 # define R200_TXA_ARG_A_R2_BLUE (15) 2629 # define R200_TXA_ARG_A_R3_ALPHA (16) 2630 # define R200_TXA_ARG_A_R3_BLUE (17) 2631 # define R200_TXA_ARG_A_R4_ALPHA (18) 2632 # define R200_TXA_ARG_A_R4_BLUE (19) 2633 # define R200_TXA_ARG_A_R5_ALPHA (20) 2634 # define R200_TXA_ARG_A_R5_BLUE (21) 2635 # define R200_TXA_ARG_A_TFACTOR1_ALPHA (26) 2636 # define R200_TXA_ARG_A_TFACTOR1_BLUE (27) 2637 # define R200_TXA_ARG_A_MASK (31 << 0) 2638 # define R200_TXA_ARG_A_SHIFT 0 2639 # define R200_TXA_ARG_B_ZERO (0 << 5) 2640 # define R200_TXA_ARG_B_CURRENT_ALPHA (2 << 5) /* guess */ 2641 # define R200_TXA_ARG_B_CURRENT_BLUE (3 << 5) /* guess */ 2642 # define R200_TXA_ARG_B_DIFFUSE_ALPHA (4 << 5) 2643 # define R200_TXA_ARG_B_DIFFUSE_BLUE (5 << 5) 2644 # define R200_TXA_ARG_B_SPECULAR_ALPHA (6 << 5) 2645 # define R200_TXA_ARG_B_SPECULAR_BLUE (7 << 5) 2646 # define R200_TXA_ARG_B_TFACTOR_ALPHA (8 << 5) 2647 # define R200_TXA_ARG_B_TFACTOR_BLUE (9 << 5) 2648 # define R200_TXA_ARG_B_R0_ALPHA (10 << 5) 2649 # define R200_TXA_ARG_B_R0_BLUE (11 << 5) 2650 # define R200_TXA_ARG_B_R1_ALPHA (12 << 5) 2651 # define R200_TXA_ARG_B_R1_BLUE (13 << 5) 2652 # define R200_TXA_ARG_B_R2_ALPHA (14 << 5) 2653 # define R200_TXA_ARG_B_R2_BLUE (15 << 5) 2654 # define R200_TXA_ARG_B_R3_ALPHA (16 << 5) 2655 # define R200_TXA_ARG_B_R3_BLUE (17 << 5) 2656 # define R200_TXA_ARG_B_R4_ALPHA (18 << 5) 2657 # define R200_TXA_ARG_B_R4_BLUE (19 << 5) 2658 # define R200_TXA_ARG_B_R5_ALPHA (20 << 5) 2659 # define R200_TXA_ARG_B_R5_BLUE (21 << 5) 2660 # define R200_TXA_ARG_B_TFACTOR1_ALPHA (26 << 5) 2661 # define R200_TXA_ARG_B_TFACTOR1_BLUE (27 << 5) 2662 # define R200_TXA_ARG_B_MASK (31 << 5) 2663 # define R200_TXA_ARG_B_SHIFT 5 2664 # define R200_TXA_ARG_C_ZERO (0 << 10) 2665 # define R200_TXA_ARG_C_CURRENT_ALPHA (2 << 10) /* guess */ 2666 # define R200_TXA_ARG_C_CURRENT_BLUE (3 << 10) /* guess */ 2667 # define R200_TXA_ARG_C_DIFFUSE_ALPHA (4 << 10) 2668 # define R200_TXA_ARG_C_DIFFUSE_BLUE (5 << 10) 2669 # define R200_TXA_ARG_C_SPECULAR_ALPHA (6 << 10) 2670 # define R200_TXA_ARG_C_SPECULAR_BLUE (7 << 10) 2671 # define R200_TXA_ARG_C_TFACTOR_ALPHA (8 << 10) 2672 # define R200_TXA_ARG_C_TFACTOR_BLUE (9 << 10) 2673 # define R200_TXA_ARG_C_R0_ALPHA (10 << 10) 2674 # define R200_TXA_ARG_C_R0_BLUE (11 << 10) 2675 # define R200_TXA_ARG_C_R1_ALPHA (12 << 10) 2676 # define R200_TXA_ARG_C_R1_BLUE (13 << 10) 2677 # define R200_TXA_ARG_C_R2_ALPHA (14 << 10) 2678 # define R200_TXA_ARG_C_R2_BLUE (15 << 10) 2679 # define R200_TXA_ARG_C_R3_ALPHA (16 << 10) 2680 # define R200_TXA_ARG_C_R3_BLUE (17 << 10) 2681 # define R200_TXA_ARG_C_R4_ALPHA (18 << 10) 2682 # define R200_TXA_ARG_C_R4_BLUE (19 << 10) 2683 # define R200_TXA_ARG_C_R5_ALPHA (20 << 10) 2684 # define R200_TXA_ARG_C_R5_BLUE (21 << 10) 2685 # define R200_TXA_ARG_C_TFACTOR1_ALPHA (26 << 10) 2686 # define R200_TXA_ARG_C_TFACTOR1_BLUE (27 << 10) 2687 # define R200_TXA_ARG_C_MASK (31 << 10) 2688 # define R200_TXA_ARG_C_SHIFT 10 2689 # define R200_TXA_COMP_ARG_A (1 << 16) 2690 # define R200_TXA_COMP_ARG_A_SHIFT (16) 2691 # define R200_TXA_BIAS_ARG_A (1 << 17) 2692 # define R200_TXA_SCALE_ARG_A (1 << 18) 2693 # define R200_TXA_NEG_ARG_A (1 << 19) 2694 # define R200_TXA_COMP_ARG_B (1 << 20) 2695 # define R200_TXA_COMP_ARG_B_SHIFT (20) 2696 # define R200_TXA_BIAS_ARG_B (1 << 21) 2697 # define R200_TXA_SCALE_ARG_B (1 << 22) 2698 # define R200_TXA_NEG_ARG_B (1 << 23) 2699 # define R200_TXA_COMP_ARG_C (1 << 24) 2700 # define R200_TXA_COMP_ARG_C_SHIFT (24) 2701 # define R200_TXA_BIAS_ARG_C (1 << 25) 2702 # define R200_TXA_SCALE_ARG_C (1 << 26) 2703 # define R200_TXA_NEG_ARG_C (1 << 27) 2704 # define R200_TXA_OP_MADD (0 << 28) 2705 # define R200_TXA_OP_CND0 (2 << 28) 2706 # define R200_TXA_OP_LERP (3 << 28) 2707 # define R200_TXA_OP_CONDITIONAL (6 << 28) 2708 # define R200_TXA_OP_MASK (7 << 28) 2709 #define R200_PP_TXABLEND2_0 0x2f0c 2710 #define R200_PP_TXABLEND2_1 0x2f1c 2711 # define R200_TXA_TFACTOR_SEL_SHIFT 0 2712 # define R200_TXA_TFACTOR_SEL_MASK 0x7 2713 # define R200_TXA_TFACTOR1_SEL_SHIFT 4 2714 # define R200_TXA_TFACTOR1_SEL_MASK (0x7 << 4) 2715 # define R200_TXA_SCALE_SHIFT 8 2716 # define R200_TXA_SCALE_MASK (7 << 8) 2717 # define R200_TXA_SCALE_1X (0 << 8) 2718 # define R200_TXA_SCALE_2X (1 << 8) 2719 # define R200_TXA_SCALE_4X (2 << 8) 2720 # define R200_TXA_SCALE_8X (3 << 8) 2721 # define R200_TXA_SCALE_INV2 (5 << 8) 2722 # define R200_TXA_SCALE_INV4 (6 << 8) 2723 # define R200_TXA_SCALE_INV8 (7 << 8) 2724 # define R200_TXA_CLAMP_SHIFT 12 2725 # define R200_TXA_CLAMP_MASK (3 << 12) 2726 # define R200_TXA_CLAMP_WRAP (0 << 12) 2727 # define R200_TXA_CLAMP_0_1 (1 << 12) 2728 # define R200_TXA_CLAMP_8_8 (2 << 12) 2729 # define R200_TXA_OUTPUT_REG_MASK (7 << 16) 2730 # define R200_TXA_OUTPUT_REG_NONE (0 << 16) 2731 # define R200_TXA_OUTPUT_REG_R0 (1 << 16) 2732 # define R200_TXA_OUTPUT_REG_R1 (2 << 16) 2733 # define R200_TXA_OUTPUT_REG_R2 (3 << 16) 2734 # define R200_TXA_OUTPUT_REG_R3 (4 << 16) 2735 # define R200_TXA_OUTPUT_REG_R4 (5 << 16) 2736 # define R200_TXA_OUTPUT_REG_R5 (6 << 16) 2737 # define R200_TXA_DOT_ALPHA (1 << 20) 2738 # define R200_TXA_REPL_NORMAL 0 2739 # define R200_TXA_REPL_RED 1 2740 # define R200_TXA_REPL_GREEN 2 2741 # define R200_TXA_REPL_ARG_A_SHIFT 26 2742 # define R200_TXA_REPL_ARG_A_MASK (3 << 26) 2743 # define R200_TXA_REPL_ARG_B_SHIFT 28 2744 # define R200_TXA_REPL_ARG_B_MASK (3 << 28) 2745 # define R200_TXA_REPL_ARG_C_SHIFT 30 2746 # define R200_TXA_REPL_ARG_C_MASK (3 << 30) 2747 #define R200_RB3D_BLENDCOLOR 0x3218 /* ARGB 8888 */ 2748 #define R200_RB3D_ABLENDCNTL 0x321C /* see BLENDCNTL */ 2749 #define R200_RB3D_CBLENDCNTL 0x3220 /* see BLENDCNTL */ 2750 2751 #define R200_SE_VTX_FMT_0 0x2088 2752 # define R200_VTX_XY 0 /* always have xy */ 2753 # define R200_VTX_Z0 (1<<0) 2754 # define R200_VTX_W0 (1<<1) 2755 # define R200_VTX_WEIGHT_COUNT_SHIFT (2) 2756 # define R200_VTX_PV_MATRIX_SEL (1<<5) 2757 # define R200_VTX_N0 (1<<6) 2758 # define R200_VTX_POINT_SIZE (1<<7) 2759 # define R200_VTX_DISCRETE_FOG (1<<8) 2760 # define R200_VTX_SHININESS_0 (1<<9) 2761 # define R200_VTX_SHININESS_1 (1<<10) 2762 # define R200_VTX_COLOR_NOT_PRESENT 0 2763 # define R200_VTX_PK_RGBA 1 2764 # define R200_VTX_FP_RGB 2 2765 # define R200_VTX_FP_RGBA 3 2766 # define R200_VTX_COLOR_MASK 3 2767 # define R200_VTX_COLOR_0_SHIFT 11 2768 # define R200_VTX_COLOR_1_SHIFT 13 2769 # define R200_VTX_COLOR_2_SHIFT 15 2770 # define R200_VTX_COLOR_3_SHIFT 17 2771 # define R200_VTX_COLOR_4_SHIFT 19 2772 # define R200_VTX_COLOR_5_SHIFT 21 2773 # define R200_VTX_COLOR_6_SHIFT 23 2774 # define R200_VTX_COLOR_7_SHIFT 25 2775 # define R200_VTX_XY1 (1<<28) 2776 # define R200_VTX_Z1 (1<<29) 2777 # define R200_VTX_W1 (1<<30) 2778 # define R200_VTX_N1 (1<<31) 2779 #define R200_SE_VTX_FMT_1 0x208c 2780 # define R200_VTX_TEX0_COMP_CNT_SHIFT 0 2781 # define R200_VTX_TEX1_COMP_CNT_SHIFT 3 2782 # define R200_VTX_TEX2_COMP_CNT_SHIFT 6 2783 # define R200_VTX_TEX3_COMP_CNT_SHIFT 9 2784 # define R200_VTX_TEX4_COMP_CNT_SHIFT 12 2785 # define R200_VTX_TEX5_COMP_CNT_SHIFT 15 2786 2787 #define R200_SE_TCL_OUTPUT_VTX_FMT_0 0x2090 2788 #define R200_SE_TCL_OUTPUT_VTX_FMT_1 0x2094 2789 #define R200_SE_TCL_OUTPUT_VTX_COMP_SEL 0x2250 2790 # define R200_OUTPUT_XYZW (1<<0) 2791 # define R200_OUTPUT_COLOR_0 (1<<8) 2792 # define R200_OUTPUT_COLOR_1 (1<<9) 2793 # define R200_OUTPUT_TEX_0 (1<<16) 2794 # define R200_OUTPUT_TEX_1 (1<<17) 2795 # define R200_OUTPUT_TEX_2 (1<<18) 2796 # define R200_OUTPUT_TEX_3 (1<<19) 2797 # define R200_OUTPUT_TEX_4 (1<<20) 2798 # define R200_OUTPUT_TEX_5 (1<<21) 2799 # define R200_OUTPUT_TEX_MASK (0x3f<<16) 2800 # define R200_OUTPUT_DISCRETE_FOG (1<<24) 2801 # define R200_OUTPUT_PT_SIZE (1<<25) 2802 # define R200_FORCE_INORDER_PROC (1<<31) 2803 #define R200_PP_CNTL_X 0x2cc4 2804 #define R200_PP_TXMULTI_CTL_0 0x2c1c 2805 #define R200_SE_VTX_STATE_CNTL 0x2180 2806 # define R200_UPDATE_USER_COLOR_0_ENA_MASK (1<<16) 2807 2808 2809 /* R300 3D registers */ 2810 #define R300_MC_INIT_MISC_LAT_TIMER 0x180 2811 # define R300_MC_MISC__MC_CPR_INIT_LAT_SHIFT 0 2812 # define R300_MC_MISC__MC_VF_INIT_LAT_SHIFT 4 2813 # define R300_MC_MISC__MC_DISP0R_INIT_LAT_SHIFT 8 2814 # define R300_MC_MISC__MC_DISP1R_INIT_LAT_SHIFT 12 2815 # define R300_MC_MISC__MC_FIXED_INIT_LAT_SHIFT 16 2816 # define R300_MC_MISC__MC_E2R_INIT_LAT_SHIFT 20 2817 # define R300_MC_MISC__MC_SAME_PAGE_PRIO_SHIFT 24 2818 # define R300_MC_MISC__MC_GLOBW_INIT_LAT_SHIFT 28 2819 2820 2821 #define R300_MC_INIT_GFX_LAT_TIMER 0x154 2822 # define R300_MC_MISC__MC_G3D0R_INIT_LAT_SHIFT 0 2823 # define R300_MC_MISC__MC_G3D1R_INIT_LAT_SHIFT 4 2824 # define R300_MC_MISC__MC_G3D2R_INIT_LAT_SHIFT 8 2825 # define R300_MC_MISC__MC_G3D3R_INIT_LAT_SHIFT 12 2826 # define R300_MC_MISC__MC_TX0R_INIT_LAT_SHIFT 16 2827 # define R300_MC_MISC__MC_TX1R_INIT_LAT_SHIFT 20 2828 # define R300_MC_MISC__MC_GLOBR_INIT_LAT_SHIFT 24 2829 # define R300_MC_MISC__MC_GLOBW_FULL_LAT_SHIFT 28 2830 2831 /* 2832 This file contains registers and constants for the R300. They have been 2833 found mostly by examining command buffers captured using glxtest, as well 2834 as by extrapolating some known registers and constants from the R200. 2835 2836 I am fairly certain that they are correct unless stated otherwise in comments. 2837 */ 2838 2839 #define R300_SE_VPORT_XSCALE 0x1D98 2840 #define R300_SE_VPORT_XOFFSET 0x1D9C 2841 #define R300_SE_VPORT_YSCALE 0x1DA0 2842 #define R300_SE_VPORT_YOFFSET 0x1DA4 2843 #define R300_SE_VPORT_ZSCALE 0x1DA8 2844 #define R300_SE_VPORT_ZOFFSET 0x1DAC 2845 2846 /* BEGIN: Wild guesses */ 2847 #define R300_VAP_OUTPUT_VTX_FMT_0 0x2090 2848 # define R300_VAP_OUTPUT_VTX_FMT_0__POS_PRESENT (1<<0) 2849 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_PRESENT (1<<1) 2850 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_1_PRESENT (1<<2) /* GUESS */ 2851 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_2_PRESENT (1<<3) /* GUESS */ 2852 # define R300_VAP_OUTPUT_VTX_FMT_0__COLOR_3_PRESENT (1<<4) /* GUESS */ 2853 # define R300_VAP_OUTPUT_VTX_FMT_0__PT_SIZE_PRESENT (1<<16) /* GUESS */ 2854 2855 #define R300_VAP_OUTPUT_VTX_FMT_1 0x2094 2856 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 2857 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 2858 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 2859 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 2860 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 2861 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 2862 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 2863 # define R300_VAP_OUTPUT_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 2864 /* END */ 2865 2866 #define R300_SE_VTE_CNTL 0x20b0 2867 # define R300_VPORT_X_SCALE_ENA 0x00000001 2868 # define R300_VPORT_X_OFFSET_ENA 0x00000002 2869 # define R300_VPORT_Y_SCALE_ENA 0x00000004 2870 # define R300_VPORT_Y_OFFSET_ENA 0x00000008 2871 # define R300_VPORT_Z_SCALE_ENA 0x00000010 2872 # define R300_VPORT_Z_OFFSET_ENA 0x00000020 2873 # define R300_VTX_XY_FMT 0x00000100 2874 # define R300_VTX_Z_FMT 0x00000200 2875 # define R300_VTX_W0_FMT 0x00000400 2876 # define R300_VTX_W0_NORMALIZE 0x00000800 2877 # define R300_VTX_ST_DENORMALIZED 0x00001000 2878 2879 /* BEGIN: Vertex data assembly - lots of uncertainties */ 2880 /* gap */ 2881 /* Where do we get our vertex data? 2882 // 2883 // Vertex data either comes either from immediate mode registers or from 2884 // vertex arrays. 2885 // There appears to be no mixed mode (though we can force the pitch of 2886 // vertex arrays to 0, effectively reusing the same element over and over 2887 // again). 2888 // 2889 // Immediate mode is controlled by the INPUT_CNTL registers. I am not sure 2890 // if these registers influence vertex array processing. 2891 // 2892 // Vertex arrays are controlled via the 3D_LOAD_VBPNTR packet3. 2893 // 2894 // In both cases, vertex attributes are then passed through INPUT_ROUTE. 2895 2896 // Beginning with INPUT_ROUTE_0_0 is a list of WORDs that route vertex data 2897 // into the vertex processor's input registers. 2898 // The first word routes the first input, the second word the second, etc. 2899 // The corresponding input is routed into the register with the given index. 2900 // The list is ended by a word with INPUT_ROUTE_END set. 2901 // 2902 // Always set COMPONENTS_4 in immediate mode. */ 2903 2904 #define R300_VAP_INPUT_ROUTE_0_0 0x2150 2905 # define R300_INPUT_ROUTE_COMPONENTS_1 (0 << 0) 2906 # define R300_INPUT_ROUTE_COMPONENTS_2 (1 << 0) 2907 # define R300_INPUT_ROUTE_COMPONENTS_3 (2 << 0) 2908 # define R300_INPUT_ROUTE_COMPONENTS_4 (3 << 0) 2909 # define R300_INPUT_ROUTE_COMPONENTS_RGBA (4 << 0) /* GUESS */ 2910 # define R300_VAP_INPUT_ROUTE_IDX_SHIFT 8 2911 # define R300_VAP_INPUT_ROUTE_IDX_MASK (31 << 8) /* GUESS */ 2912 # define R300_VAP_INPUT_ROUTE_END (1 << 13) 2913 # define R300_INPUT_ROUTE_IMMEDIATE_MODE (0 << 14) /* GUESS */ 2914 # define R300_INPUT_ROUTE_FLOAT (1 << 14) /* GUESS */ 2915 # define R300_INPUT_ROUTE_UNSIGNED_BYTE (2 << 14) /* GUESS */ 2916 # define R300_INPUT_ROUTE_FLOAT_COLOR (3 << 14) /* GUESS */ 2917 #define R300_VAP_INPUT_ROUTE_0_1 0x2154 2918 #define R300_VAP_INPUT_ROUTE_0_2 0x2158 2919 #define R300_VAP_INPUT_ROUTE_0_3 0x215C 2920 #define R300_VAP_INPUT_ROUTE_0_4 0x2160 2921 #define R300_VAP_INPUT_ROUTE_0_5 0x2164 2922 #define R300_VAP_INPUT_ROUTE_0_6 0x2168 2923 #define R300_VAP_INPUT_ROUTE_0_7 0x216C 2924 2925 /* gap */ 2926 /* Notes: 2927 // - always set up to produce at least two attributes: 2928 // if vertex program uses only position, fglrx will set normal, too 2929 // - INPUT_CNTL_0_COLOR and INPUT_CNTL_COLOR bits are always equal */ 2930 #define R300_VAP_INPUT_CNTL_0 0x2180 2931 # define R300_INPUT_CNTL_0_COLOR 0x00000001 2932 #define R300_VAP_INPUT_CNTL_1 0x2184 2933 # define R300_INPUT_CNTL_POS 0x00000001 2934 # define R300_INPUT_CNTL_NORMAL 0x00000002 2935 # define R300_INPUT_CNTL_COLOR 0x00000004 2936 # define R300_INPUT_CNTL_TC0 0x00000400 2937 # define R300_INPUT_CNTL_TC1 0x00000800 2938 # define R300_INPUT_CNTL_TC2 0x00001000 /* GUESS */ 2939 # define R300_INPUT_CNTL_TC3 0x00002000 /* GUESS */ 2940 # define R300_INPUT_CNTL_TC4 0x00004000 /* GUESS */ 2941 # define R300_INPUT_CNTL_TC5 0x00008000 /* GUESS */ 2942 # define R300_INPUT_CNTL_TC6 0x00010000 /* GUESS */ 2943 # define R300_INPUT_CNTL_TC7 0x00020000 /* GUESS */ 2944 2945 /* gap */ 2946 /* Words parallel to INPUT_ROUTE_0; All words that are active in INPUT_ROUTE_0 2947 // are set to a swizzling bit pattern, other words are 0. 2948 // 2949 // In immediate mode, the pattern is always set to xyzw. In vertex array 2950 // mode, the swizzling pattern is e.g. used to set zw components in texture 2951 // coordinates with only tweo components. */ 2952 #define R300_VAP_INPUT_ROUTE_1_0 0x21E0 2953 # define R300_INPUT_ROUTE_SELECT_X 0 2954 # define R300_INPUT_ROUTE_SELECT_Y 1 2955 # define R300_INPUT_ROUTE_SELECT_Z 2 2956 # define R300_INPUT_ROUTE_SELECT_W 3 2957 # define R300_INPUT_ROUTE_SELECT_ZERO 4 2958 # define R300_INPUT_ROUTE_SELECT_ONE 5 2959 # define R300_INPUT_ROUTE_SELECT_MASK 7 2960 # define R300_INPUT_ROUTE_X_SHIFT 0 2961 # define R300_INPUT_ROUTE_Y_SHIFT 3 2962 # define R300_INPUT_ROUTE_Z_SHIFT 6 2963 # define R300_INPUT_ROUTE_W_SHIFT 9 2964 # define R300_INPUT_ROUTE_ENABLE (15 << 12) 2965 #define R300_VAP_INPUT_ROUTE_1_1 0x21E4 2966 #define R300_VAP_INPUT_ROUTE_1_2 0x21E8 2967 #define R300_VAP_INPUT_ROUTE_1_3 0x21EC 2968 #define R300_VAP_INPUT_ROUTE_1_4 0x21F0 2969 #define R300_VAP_INPUT_ROUTE_1_5 0x21F4 2970 #define R300_VAP_INPUT_ROUTE_1_6 0x21F8 2971 #define R300_VAP_INPUT_ROUTE_1_7 0x21FC 2972 2973 /* END */ 2974 2975 /* gap */ 2976 /* BEGIN: Upload vertex program and data 2977 // The programmable vertex shader unit has a memory bank of unknown size 2978 // that can be written to in 16 byte units by writing the address into 2979 // UPLOAD_ADDRESS, followed by data in UPLOAD_DATA (multiples of 4 DWORDs). 2980 // 2981 // Pointers into the memory bank are always in multiples of 16 bytes. 2982 // 2983 // The memory bank is divided into areas with fixed meaning. 2984 // 2985 // Starting at address UPLOAD_PROGRAM: Vertex program instructions. 2986 // Native limits reported by drivers from ATI suggest size 256 (i.e. 4KB), 2987 // whereas the difference between known addresses suggests size 512. 2988 // 2989 // Starting at address UPLOAD_PARAMETERS: Vertex program parameters. 2990 // Native reported limits and the VPI layout suggest size 256, whereas 2991 // difference between known addresses suggests size 512. 2992 // 2993 // At address UPLOAD_POINTSIZE is a vector (0, 0, ps, 0), where ps is the 2994 // floating point pointsize. The exact purpose of this state is uncertain, 2995 // as there is also the R300_RE_POINTSIZE register. 2996 // 2997 // Multiple vertex programs and parameter sets can be loaded at once, 2998 // which could explain the size discrepancy. */ 2999 #define R300_VAP_PVS_UPLOAD_ADDRESS 0x2200 3000 # define R300_PVS_UPLOAD_PROGRAM 0x00000000 3001 # define R300_PVS_UPLOAD_PARAMETERS 0x00000200 3002 # define R300_PVS_UPLOAD_POINTSIZE 0x00000406 3003 /* gap */ 3004 #define R300_VAP_PVS_UPLOAD_DATA 0x2208 3005 /* END */ 3006 3007 /* gap */ 3008 /* I do not know the purpose of this register. However, I do know that 3009 // it is set to 221C_CLEAR for clear operations and to 221C_NORMAL 3010 // for normal rendering. */ 3011 #define R300_VAP_UNKNOWN_221C 0x221C 3012 # define R300_221C_NORMAL 0x00000000 3013 # define R300_221C_CLEAR 0x0001C000 3014 3015 /* gap */ 3016 /* Sometimes, END_OF_PKT and 0x2284=0 are the only commands sent between 3017 // rendering commands and overwriting vertex program parameters. 3018 // Therefore, I suspect writing zero to 0x2284 synchronizes the engine and 3019 // avoids bugs caused by still running shaders reading bad data from memory. */ 3020 #define R300_VAP_PVS_WAITIDLE 0x2284 /* GUESS */ 3021 3022 /* Absolutely no clue what this register is about. */ 3023 #define R300_VAP_UNKNOWN_2288 0x2288 3024 # define R300_2288_R300 0x00750000 /* -- nh */ 3025 # define R300_2288_RV350 0x0000FFFF /* -- Vladimir */ 3026 3027 /* gap */ 3028 /* Addresses are relative to the vertex program instruction area of the 3029 // memory bank. PROGRAM_END points to the last instruction of the active 3030 // program 3031 // 3032 // The meaning of the two UNKNOWN fields is obviously not known. However, 3033 // experiments so far have shown that both *must* point to an instruction 3034 // inside the vertex program, otherwise the GPU locks up. 3035 // fglrx usually sets CNTL_3_UNKNOWN to the end of the program and 3036 // CNTL_1_UNKNOWN points to instruction where last write to position takes place. 3037 // Most likely this is used to ignore rest of the program in cases where group of verts arent visible. 3038 // For some reason this "section" is sometimes accepted other instruction that have 3039 // no relationship with position calculations. 3040 */ 3041 #define R300_VAP_PVS_CNTL_1 0x22D0 3042 # define R300_PVS_CNTL_1_PROGRAM_START_SHIFT 0 3043 # define R300_PVS_CNTL_1_POS_END_SHIFT 10 3044 # define R300_PVS_CNTL_1_PROGRAM_END_SHIFT 20 3045 /* Addresses are relative the the vertex program parameters area. */ 3046 #define R300_VAP_PVS_CNTL_2 0x22D4 3047 # define R300_PVS_CNTL_2_PARAM_OFFSET_SHIFT 0 3048 # define R300_PVS_CNTL_2_PARAM_COUNT_SHIFT 16 3049 #define R300_VAP_PVS_CNTL_3 0x22D8 3050 # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN_SHIFT 10 3051 # define R300_PVS_CNTL_3_PROGRAM_UNKNOWN2_SHIFT 0 3052 3053 /* The entire range from 0x2300 to 0x2AC inclusive seems to be used for 3054 // immediate vertices */ 3055 #define R300_VAP_VTX_COLOR_R 0x2464 3056 #define R300_VAP_VTX_COLOR_G 0x2468 3057 #define R300_VAP_VTX_COLOR_B 0x246C 3058 #define R300_VAP_VTX_POS_0_X_1 0x2490 /* used for glVertex2*() */ 3059 #define R300_VAP_VTX_POS_0_Y_1 0x2494 3060 #define R300_VAP_VTX_COLOR_PKD 0x249C /* RGBA */ 3061 #define R300_VAP_VTX_POS_0_X_2 0x24A0 /* used for glVertex3*() */ 3062 #define R300_VAP_VTX_POS_0_Y_2 0x24A4 3063 #define R300_VAP_VTX_POS_0_Z_2 0x24A8 3064 #define R300_VAP_VTX_END_OF_PKT 0x24AC /* write 0 to indicate end of packet? */ 3065 3066 /* gap */ 3067 3068 /* These are values from r300_reg/r300_reg.h - they are known to be correct 3069 and are here so we can use one register file instead of several 3070 - Vladimir */ 3071 #define R300_GB_VAP_RASTER_VTX_FMT_0 0x4000 3072 # define R300_GB_VAP_RASTER_VTX_FMT_0__POS_PRESENT (1<<0) 3073 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_0_PRESENT (1<<1) 3074 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_1_PRESENT (1<<2) 3075 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_2_PRESENT (1<<3) 3076 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_3_PRESENT (1<<4) 3077 # define R300_GB_VAP_RASTER_VTX_FMT_0__COLOR_SPACE (0xf<<5) 3078 # define R300_GB_VAP_RASTER_VTX_FMT_0__PT_SIZE_PRESENT (0x1<<16) 3079 3080 #define R300_GB_VAP_RASTER_VTX_FMT_1 0x4004 3081 /* each of the following is 3 bits wide, specifies number 3082 of components */ 3083 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_0_COMP_CNT_SHIFT 0 3084 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_1_COMP_CNT_SHIFT 3 3085 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_2_COMP_CNT_SHIFT 6 3086 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_3_COMP_CNT_SHIFT 9 3087 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_4_COMP_CNT_SHIFT 12 3088 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_5_COMP_CNT_SHIFT 15 3089 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_6_COMP_CNT_SHIFT 18 3090 # define R300_GB_VAP_RASTER_VTX_FMT_1__TEX_7_COMP_CNT_SHIFT 21 3091 3092 /* UNK30 seems to enables point to quad transformation on textures 3093 (or something closely related to that). 3094 This bit is rather fatal at the time being due to lackings at pixel shader side */ 3095 #define R300_GB_ENABLE 0x4008 3096 # define R300_GB_POINT_STUFF_ENABLE (1<<0) 3097 # define R300_GB_LINE_STUFF_ENABLE (1<<1) 3098 # define R300_GB_TRIANGLE_STUFF_ENABLE (1<<2) 3099 # define R300_GB_STENCIL_AUTO_ENABLE (1<<4) 3100 # define R300_GB_UNK30 (1<<30) 3101 /* each of the following is 2 bits wide */ 3102 #define R300_GB_TEX_REPLICATE 0 3103 #define R300_GB_TEX_ST 1 3104 #define R300_GB_TEX_STR 2 3105 # define R300_GB_TEX0_SOURCE_SHIFT 16 3106 # define R300_GB_TEX1_SOURCE_SHIFT 18 3107 # define R300_GB_TEX2_SOURCE_SHIFT 20 3108 # define R300_GB_TEX3_SOURCE_SHIFT 22 3109 # define R300_GB_TEX4_SOURCE_SHIFT 24 3110 # define R300_GB_TEX5_SOURCE_SHIFT 26 3111 # define R300_GB_TEX6_SOURCE_SHIFT 28 3112 # define R300_GB_TEX7_SOURCE_SHIFT 30 3113 3114 /* MSPOS - positions for multisample antialiasing (?) */ 3115 #define R300_GB_MSPOS0 0x4010 3116 /* shifts - each of the fields is 4 bits */ 3117 # define R300_GB_MSPOS0__MS_X0_SHIFT 0 3118 # define R300_GB_MSPOS0__MS_Y0_SHIFT 4 3119 # define R300_GB_MSPOS0__MS_X1_SHIFT 8 3120 # define R300_GB_MSPOS0__MS_Y1_SHIFT 12 3121 # define R300_GB_MSPOS0__MS_X2_SHIFT 16 3122 # define R300_GB_MSPOS0__MS_Y2_SHIFT 20 3123 # define R300_GB_MSPOS0__MSBD0_Y 24 3124 # define R300_GB_MSPOS0__MSBD0_X 28 3125 3126 #define R300_GB_MSPOS1 0x4014 3127 # define R300_GB_MSPOS1__MS_X3_SHIFT 0 3128 # define R300_GB_MSPOS1__MS_Y3_SHIFT 4 3129 # define R300_GB_MSPOS1__MS_X4_SHIFT 8 3130 # define R300_GB_MSPOS1__MS_Y4_SHIFT 12 3131 # define R300_GB_MSPOS1__MS_X5_SHIFT 16 3132 # define R300_GB_MSPOS1__MS_Y5_SHIFT 20 3133 # define R300_GB_MSPOS1__MSBD1 24 3134 3135 3136 #define R300_GB_TILE_CONFIG 0x4018 3137 # define R300_GB_TILE_ENABLE (1<<0) 3138 # define R300_GB_TILE_PIPE_COUNT_RV300 0 3139 # define R300_GB_TILE_PIPE_COUNT_R300 (3<<1) 3140 # define R300_GB_TILE_PIPE_COUNT_R420 (7<<1) 3141 # define R300_GB_TILE_SIZE_8 0 3142 # define R300_GB_TILE_SIZE_16 (1<<4) 3143 # define R300_GB_TILE_SIZE_32 (2<<4) 3144 # define R300_GB_SUPER_SIZE_1 (0<<6) 3145 # define R300_GB_SUPER_SIZE_2 (1<<6) 3146 # define R300_GB_SUPER_SIZE_4 (2<<6) 3147 # define R300_GB_SUPER_SIZE_8 (3<<6) 3148 # define R300_GB_SUPER_SIZE_16 (4<<6) 3149 # define R300_GB_SUPER_SIZE_32 (5<<6) 3150 # define R300_GB_SUPER_SIZE_64 (6<<6) 3151 # define R300_GB_SUPER_SIZE_128 (7<<6) 3152 # define R300_GB_SUPER_X_SHIFT 9 /* 3 bits wide */ 3153 # define R300_GB_SUPER_Y_SHIFT 12 /* 3 bits wide */ 3154 # define R300_GB_SUPER_TILE_A 0 3155 # define R300_GB_SUPER_TILE_B (1<<15) 3156 # define R300_GB_SUBPIXEL_1_12 0 3157 # define R300_GB_SUBPIXEL_1_16 (1<<16) 3158 3159 #define R300_GB_FIFO_SIZE 0x4024 3160 /* each of the following is 2 bits wide */ 3161 #define R300_GB_FIFO_SIZE_32 0 3162 #define R300_GB_FIFO_SIZE_64 1 3163 #define R300_GB_FIFO_SIZE_128 2 3164 #define R300_GB_FIFO_SIZE_256 3 3165 # define R300_SC_IFIFO_SIZE_SHIFT 0 3166 # define R300_SC_TZFIFO_SIZE_SHIFT 2 3167 # define R300_SC_BFIFO_SIZE_SHIFT 4 3168 3169 # define R300_US_OFIFO_SIZE_SHIFT 12 3170 # define R300_US_WFIFO_SIZE_SHIFT 14 3171 /* the following use the same constants as above, but meaning is 3172 is times 2 (i.e. instead of 32 words it means 64 */ 3173 # define R300_RS_TFIFO_SIZE_SHIFT 6 3174 # define R300_RS_CFIFO_SIZE_SHIFT 8 3175 # define R300_US_RAM_SIZE_SHIFT 10 3176 /* watermarks, 3 bits wide */ 3177 # define R300_RS_HIGHWATER_COL_SHIFT 16 3178 # define R300_RS_HIGHWATER_TEX_SHIFT 19 3179 # define R300_OFIFO_HIGHWATER_SHIFT 22 /* two bits only */ 3180 # define R300_CUBE_FIFO_HIGHWATER_COL_SHIFT 24 3181 3182 #define R300_GB_SELECT 0x401C 3183 # define R300_GB_FOG_SELECT_C0A 0 3184 # define R300_GB_FOG_SELECT_C1A 1 3185 # define R300_GB_FOG_SELECT_C2A 2 3186 # define R300_GB_FOG_SELECT_C3A 3 3187 # define R300_GB_FOG_SELECT_1_1_W 4 3188 # define R300_GB_FOG_SELECT_Z 5 3189 # define R300_GB_DEPTH_SELECT_Z 0 3190 # define R300_GB_DEPTH_SELECT_1_1_W (1<<3) 3191 # define R300_GB_W_SELECT_1_W 0 3192 # define R300_GB_W_SELECT_1 (1<<4) 3193 3194 #define R300_GB_AA_CONFIG 0x4020 3195 # define R300_AA_ENABLE 0x01 3196 # define R300_AA_SUBSAMPLES_2 0 3197 # define R300_AA_SUBSAMPLES_3 (1<<1) 3198 # define R300_AA_SUBSAMPLES_4 (2<<1) 3199 # define R300_AA_SUBSAMPLES_6 (3<<1) 3200 3201 /* END */ 3202 3203 /* gap */ 3204 /* Zero to flush caches. */ 3205 #define R300_TX_CNTL 0x4100 3206 3207 /* The upper enable bits are guessed, based on fglrx reported limits. */ 3208 #define R300_TX_ENABLE 0x4104 3209 # define R300_TX_ENABLE_0 (1 << 0) 3210 # define R300_TX_ENABLE_1 (1 << 1) 3211 # define R300_TX_ENABLE_2 (1 << 2) 3212 # define R300_TX_ENABLE_3 (1 << 3) 3213 # define R300_TX_ENABLE_4 (1 << 4) 3214 # define R300_TX_ENABLE_5 (1 << 5) 3215 # define R300_TX_ENABLE_6 (1 << 6) 3216 # define R300_TX_ENABLE_7 (1 << 7) 3217 # define R300_TX_ENABLE_8 (1 << 8) 3218 # define R300_TX_ENABLE_9 (1 << 9) 3219 # define R300_TX_ENABLE_10 (1 << 10) 3220 # define R300_TX_ENABLE_11 (1 << 11) 3221 # define R300_TX_ENABLE_12 (1 << 12) 3222 # define R300_TX_ENABLE_13 (1 << 13) 3223 # define R300_TX_ENABLE_14 (1 << 14) 3224 # define R300_TX_ENABLE_15 (1 << 15) 3225 3226 /* The pointsize is given in multiples of 6. The pointsize can be 3227 // enormous: Clear() renders a single point that fills the entire 3228 // framebuffer. */ 3229 #define R300_RE_POINTSIZE 0x421C 3230 # define R300_POINTSIZE_Y_SHIFT 0 3231 # define R300_POINTSIZE_Y_MASK (0xFFFF << 0) /* GUESS */ 3232 # define R300_POINTSIZE_X_SHIFT 16 3233 # define R300_POINTSIZE_X_MASK (0xFFFF << 16) /* GUESS */ 3234 # define R300_POINTSIZE_MAX (R300_POINTSIZE_Y_MASK / 6) 3235 3236 /* The line width is given in multiples of 6. 3237 In default mode lines are classified as vertical lines. 3238 HO: horizontal 3239 VE: vertical or horizontal 3240 HO & VE: no classification 3241 */ 3242 #define R300_RE_LINE_CNT 0x4234 3243 # define R300_LINESIZE_SHIFT 0 3244 # define R300_LINESIZE_MASK (0xFFFF << 0) /* GUESS */ 3245 # define R300_LINESIZE_MAX (R300_LINESIZE_MASK / 6) 3246 # define R300_LINE_CNT_HO (1 << 16) 3247 # define R300_LINE_CNT_VE (1 << 17) 3248 3249 /* Some sort of scale or clamp value for texcoordless textures. */ 3250 #define R300_RE_UNK4238 0x4238 3251 3252 #define R300_RE_SHADE_MODEL 0x4278 3253 # define R300_RE_SHADE_MODEL_SMOOTH 0x3aaaa 3254 # define R300_RE_SHADE_MODEL_FLAT 0x39595 3255 3256 /* Dangerous */ 3257 #define R300_RE_POLYGON_MODE 0x4288 3258 # define R300_PM_ENABLED (1 << 0) 3259 # define R300_PM_FRONT_POINT (0 << 0) 3260 # define R300_PM_BACK_POINT (0 << 0) 3261 # define R300_PM_FRONT_LINE (1 << 4) 3262 # define R300_PM_FRONT_FILL (1 << 5) 3263 # define R300_PM_BACK_LINE (1 << 7) 3264 # define R300_PM_BACK_FILL (1 << 8) 3265 3266 /* Not sure why there are duplicate of factor and constant values. 3267 My best guess so far is that there are seperate zbiases for test and write. 3268 Ordering might be wrong. 3269 Some of the tests indicate that fgl has a fallback implementation of zbias 3270 via pixel shaders. */ 3271 #define R300_RE_ZBIAS_T_FACTOR 0x42A4 3272 #define R300_RE_ZBIAS_T_CONSTANT 0x42A8 3273 #define R300_RE_ZBIAS_W_FACTOR 0x42AC 3274 #define R300_RE_ZBIAS_W_CONSTANT 0x42B0 3275 3276 /* This register needs to be set to (1<<1) for RV350 to correctly 3277 perform depth test (see --vb-triangles in r300_demo) 3278 Don't know about other chips. - Vladimir 3279 This is set to 3 when GL_POLYGON_OFFSET_FILL is on. 3280 My guess is that there are two bits for each zbias primitive (FILL, LINE, POINT). 3281 One to enable depth test and one for depth write. 3282 Yet this doesnt explain why depth writes work ... 3283 */ 3284 #define R300_RE_OCCLUSION_CNTL 0x42B4 3285 # define R300_OCCLUSION_ON (1<<1) 3286 3287 #define R300_RE_CULL_CNTL 0x42B8 3288 # define R300_CULL_FRONT (1 << 0) 3289 # define R300_CULL_BACK (1 << 1) 3290 # define R300_FRONT_FACE_CCW (0 << 2) 3291 # define R300_FRONT_FACE_CW (1 << 2) 3292 3293 3294 /* BEGIN: Rasterization / Interpolators - many guesses 3295 // 0_UNKNOWN_18 has always been set except for clear operations. 3296 // TC_CNT is the number of incoming texture coordinate sets (i.e. it depends 3297 // on the vertex program, *not* the fragment program) */ 3298 #define R300_RS_CNTL_0 0x4300 3299 # define R300_RS_CNTL_TC_CNT_SHIFT 2 3300 # define R300_RS_CNTL_TC_CNT_MASK (7 << 2) 3301 # define R300_RS_CNTL_CI_CNT_SHIFT 7 /* number of color interpolators used */ 3302 # define R300_RS_CNTL_0_UNKNOWN_18 (1 << 18) 3303 /* Guess: RS_CNTL_1 holds the index of the highest used RS_ROUTE_n register. */ 3304 #define R300_RS_CNTL_1 0x4304 3305 3306 /* gap */ 3307 /* Only used for texture coordinates. 3308 // Use the source field to route texture coordinate input from the vertex program 3309 // to the desired interpolator. Note that the source field is relative to the 3310 // outputs the vertex program *actually* writes. If a vertex program only writes 3311 // texcoord[1], this will be source index 0. 3312 // Set INTERP_USED on all interpolators that produce data used by the 3313 // fragment program. INTERP_USED looks like a swizzling mask, but 3314 // I haven't seen it used that way. 3315 // 3316 // Note: The _UNKNOWN constants are always set in their respective register. 3317 // I don't know if this is necessary. */ 3318 #define R300_RS_INTERP_0 0x4310 3319 #define R300_RS_INTERP_1 0x4314 3320 # define R300_RS_INTERP_1_UNKNOWN 0x40 3321 #define R300_RS_INTERP_2 0x4318 3322 # define R300_RS_INTERP_2_UNKNOWN 0x80 3323 #define R300_RS_INTERP_3 0x431C 3324 # define R300_RS_INTERP_3_UNKNOWN 0xC0 3325 #define R300_RS_INTERP_4 0x4320 3326 #define R300_RS_INTERP_5 0x4324 3327 #define R300_RS_INTERP_6 0x4328 3328 #define R300_RS_INTERP_7 0x432C 3329 # define R300_RS_INTERP_SRC_SHIFT 2 3330 # define R300_RS_INTERP_SRC_MASK (7 << 2) 3331 # define R300_RS_INTERP_USED 0x00D10000 3332 3333 /* These DWORDs control how vertex data is routed into fragment program 3334 // registers, after interpolators. */ 3335 #define R300_RS_ROUTE_0 0x4330 3336 #define R300_RS_ROUTE_1 0x4334 3337 #define R300_RS_ROUTE_2 0x4338 3338 #define R300_RS_ROUTE_3 0x433C /* GUESS */ 3339 #define R300_RS_ROUTE_4 0x4340 /* GUESS */ 3340 #define R300_RS_ROUTE_5 0x4344 /* GUESS */ 3341 #define R300_RS_ROUTE_6 0x4348 /* GUESS */ 3342 #define R300_RS_ROUTE_7 0x434C /* GUESS */ 3343 # define R300_RS_ROUTE_SOURCE_INTERP_0 0 3344 # define R300_RS_ROUTE_SOURCE_INTERP_1 1 3345 # define R300_RS_ROUTE_SOURCE_INTERP_2 2 3346 # define R300_RS_ROUTE_SOURCE_INTERP_3 3 3347 # define R300_RS_ROUTE_SOURCE_INTERP_4 4 3348 # define R300_RS_ROUTE_SOURCE_INTERP_5 5 /* GUESS */ 3349 # define R300_RS_ROUTE_SOURCE_INTERP_6 6 /* GUESS */ 3350 # define R300_RS_ROUTE_SOURCE_INTERP_7 7 /* GUESS */ 3351 # define R300_RS_ROUTE_ENABLE (1 << 3) /* GUESS */ 3352 # define R300_RS_ROUTE_DEST_SHIFT 6 3353 # define R300_RS_ROUTE_DEST_MASK (31 << 6) /* GUESS */ 3354 3355 /* Special handling for color: When the fragment program uses color, 3356 // the ROUTE_0_COLOR bit is set and ROUTE_0_COLOR_DEST contains the 3357 // color register index. */ 3358 # define R300_RS_ROUTE_0_COLOR (1 << 14) 3359 # define R300_RS_ROUTE_0_COLOR_DEST_SHIFT 17 3360 # define R300_RS_ROUTE_0_COLOR_DEST_MASK (31 << 17) /* GUESS */ 3361 /* As above, but for secondary color */ 3362 # define R300_RS_ROUTE_1_COLOR1 (1 << 14) 3363 # define R300_RS_ROUTE_1_COLOR1_DEST_SHIFT 17 3364 # define R300_RS_ROUTE_1_COLOR1_DEST_MASK (31 << 17) 3365 # define R300_RS_ROUTE_1_UNKNOWN11 (1 << 11) 3366 /* END */ 3367 3368 /* BEGIN: Scissors and cliprects 3369 // There are four clipping rectangles. Their corner coordinates are inclusive. 3370 // Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending 3371 // on whether the pixel is inside cliprects 0-3, respectively. For example, 3372 // if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned 3373 // the number 3 (binary 0011). 3374 // Iff the bit corresponding to the pixel's number in RE_CLIPRECT_CNTL is set, 3375 // the pixel is rasterized. 3376 // 3377 // In addition to this, there is a scissors rectangle. Only pixels inside the 3378 // scissors rectangle are drawn. (coordinates are inclusive) 3379 // 3380 // For some reason, the top-left corner of the framebuffer is at (1440, 1440) 3381 // for the purpose of clipping and scissors. */ 3382 #define R300_RE_CLIPRECT_TL_0 0x43B0 3383 #define R300_RE_CLIPRECT_BR_0 0x43B4 3384 #define R300_RE_CLIPRECT_TL_1 0x43B8 3385 #define R300_RE_CLIPRECT_BR_1 0x43BC 3386 #define R300_RE_CLIPRECT_TL_2 0x43C0 3387 #define R300_RE_CLIPRECT_BR_2 0x43C4 3388 #define R300_RE_CLIPRECT_TL_3 0x43C8 3389 #define R300_RE_CLIPRECT_BR_3 0x43CC 3390 # define R300_CLIPRECT_OFFSET 1440 3391 # define R300_CLIPRECT_MASK 0x1FFF 3392 # define R300_CLIPRECT_X_SHIFT 0 3393 # define R300_CLIPRECT_X_MASK (0x1FFF << 0) 3394 # define R300_CLIPRECT_Y_SHIFT 13 3395 # define R300_CLIPRECT_Y_MASK (0x1FFF << 13) 3396 #define R300_RE_CLIPRECT_CNTL 0x43D0 3397 # define R300_CLIP_OUT (1 << 0) 3398 # define R300_CLIP_0 (1 << 1) 3399 # define R300_CLIP_1 (1 << 2) 3400 # define R300_CLIP_10 (1 << 3) 3401 # define R300_CLIP_2 (1 << 4) 3402 # define R300_CLIP_20 (1 << 5) 3403 # define R300_CLIP_21 (1 << 6) 3404 # define R300_CLIP_210 (1 << 7) 3405 # define R300_CLIP_3 (1 << 8) 3406 # define R300_CLIP_30 (1 << 9) 3407 # define R300_CLIP_31 (1 << 10) 3408 # define R300_CLIP_310 (1 << 11) 3409 # define R300_CLIP_32 (1 << 12) 3410 # define R300_CLIP_320 (1 << 13) 3411 # define R300_CLIP_321 (1 << 14) 3412 # define R300_CLIP_3210 (1 << 15) 3413 3414 /* gap */ 3415 #define R300_RE_SCISSORS_TL 0x43E0 3416 #define R300_RE_SCISSORS_BR 0x43E4 3417 # define R300_SCISSORS_OFFSET 1440 3418 # define R300_SCISSORS_X_SHIFT 0 3419 # define R300_SCISSORS_X_MASK (0x1FFF << 0) 3420 # define R300_SCISSORS_Y_SHIFT 13 3421 # define R300_SCISSORS_Y_MASK (0x1FFF << 13) 3422 /* END */ 3423 3424 /* BEGIN: Texture specification 3425 // The texture specification dwords are grouped by meaning and not by texture unit. 3426 // This means that e.g. the offset for texture image unit N is found in register 3427 // TX_OFFSET_0 + (4*N) */ 3428 #define R300_TX_FILTER_0 0x4400 3429 #define R300_TX_FILTER_1 0x4404 3430 # define R300_TX_REPEAT 0 3431 # define R300_TX_MIRRORED 1 3432 # define R300_TX_CLAMP 4 3433 # define R300_TX_CLAMP_TO_EDGE 2 3434 # define R300_TX_CLAMP_TO_BORDER 6 3435 # define R300_TX_WRAP_S_SHIFT 0 3436 # define R300_TX_WRAP_S_MASK (7 << 0) 3437 # define R300_TX_WRAP_T_SHIFT 3 3438 # define R300_TX_WRAP_T_MASK (7 << 3) 3439 # define R300_TX_WRAP_Q_SHIFT 6 3440 # define R300_TX_WRAP_Q_MASK (7 << 6) 3441 # define R300_TX_MAG_FILTER_NEAREST (1 << 9) 3442 # define R300_TX_MAG_FILTER_LINEAR (2 << 9) 3443 # define R300_TX_MAG_FILTER_MASK (3 << 9) 3444 # define R300_TX_MIN_FILTER_NEAREST (1 << 11) 3445 # define R300_TX_MIN_FILTER_LINEAR (2 << 11) 3446 # define R300_TX_MIN_FILTER_NEAREST_MIP_NEAREST (5 << 11) 3447 # define R300_TX_MIN_FILTER_NEAREST_MIP_LINEAR (9 << 11) 3448 # define R300_TX_MIN_FILTER_LINEAR_MIP_NEAREST (6 << 11) 3449 # define R300_TX_MIN_FILTER_LINEAR_MIP_LINEAR (10 << 11) 3450 /* NOTE: NEAREST doesnt seem to exist. 3451 Im not seting MAG_FILTER_MASK and (3 << 11) on for all 3452 anisotropy modes because that would void selected mag filter */ 3453 # define R300_TX_MIN_FILTER_ANISO_NEAREST ((0 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) 3454 # define R300_TX_MIN_FILTER_ANISO_LINEAR ((0 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) 3455 # define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_NEAREST ((1 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) 3456 # define R300_TX_MIN_FILTER_ANISO_NEAREST_MIP_LINEAR ((2 << 13) /*|R300_TX_MAG_FILTER_MASK|(3<<11)*/) 3457 # define R300_TX_MIN_FILTER_MASK ( (15 << 11) | (3 << 13) ) 3458 # define R300_TX_MAX_ANISO_1_TO_1 (0 << 21) 3459 # define R300_TX_MAX_ANISO_2_TO_1 (2 << 21) 3460 # define R300_TX_MAX_ANISO_4_TO_1 (4 << 21) 3461 # define R300_TX_MAX_ANISO_8_TO_1 (6 << 21) 3462 # define R300_TX_MAX_ANISO_16_TO_1 (8 << 21) 3463 # define R300_TX_MAX_ANISO_MASK (14 << 21) 3464 3465 #define R300_TX_FILTER1_0 0x4440 3466 #define R300_TX_FILTER1_1 0x4444 3467 # define R300_CHROMA_KEY_MODE_DISABLE 0 3468 # define R300_CHROMA_KEY_FORCE 1 3469 # define R300_CHROMA_KEY_BLEND 2 3470 # define R300_MC_ROUND_NORMAL (0<<2) 3471 # define R300_MC_ROUND_MPEG4 (1<<2) 3472 # define R300_LOD_BIAS_MASK 0x1fff 3473 # define R300_EDGE_ANISO_EDGE_DIAG (0<<13) 3474 # define R300_EDGE_ANISO_EDGE_ONLY (1<<13) 3475 # define R300_MC_COORD_TRUNCATE_DISABLE (0<<14) 3476 # define R300_MC_COORD_TRUNCATE_MPEG (1<<14) 3477 # define R300_TX_TRI_PERF_0_8 (0<<15) 3478 # define R300_TX_TRI_PERF_1_8 (1<<15) 3479 # define R300_TX_TRI_PERF_1_4 (2<<15) 3480 # define R300_TX_TRI_PERF_3_8 (3<<15) 3481 # define R300_ANISO_THRESHOLD_MASK (7<<17) 3482 3483 #define R300_TX_SIZE_0 0x4480 3484 #define R300_TX_SIZE_1 0x4484 3485 # define R300_TX_WIDTH_SHIFT 0 3486 # define R300_TX_WIDTH_MASK (2047 << 0) 3487 # define R300_TX_HEIGHT_SHIFT 11 3488 # define R300_TX_HEIGHT_MASK (2047 << 11) 3489 # define R300_TX_UNK23 (1 << 23) 3490 # define R300_TX_SIZE_SHIFT 26 /* largest of width, height */ 3491 # define R300_TX_SIZE_MASK (15 << 26) 3492 # define R300_TX_SIZE_PROJECTED (1<<30) 3493 # define R300_TX_SIZE_TXPITCH_EN (1<<31) 3494 3495 #define R300_TX_FORMAT_0 0x44C0 3496 #define R300_TX_FORMAT_1 0x44C4 3497 /* The interpretation of the format word by Wladimir van der Laan */ 3498 /* The X, Y, Z and W refer to the layout of the components. 3499 They are given meanings as R, G, B and Alpha by the swizzle 3500 specification */ 3501 # define R300_TX_FORMAT_X8 0x0 3502 # define R300_TX_FORMAT_X16 0x1 3503 # define R300_TX_FORMAT_Y4X4 0x2 3504 # define R300_TX_FORMAT_Y8X8 0x3 3505 # define R300_TX_FORMAT_Y16X16 0x4 3506 # define R300_TX_FORMAT_Z3Y3X2 0x5 3507 # define R300_TX_FORMAT_Z5Y6X5 0x6 3508 # define R300_TX_FORMAT_Z6Y5X5 0x7 3509 # define R300_TX_FORMAT_Z11Y11X10 0x8 3510 # define R300_TX_FORMAT_Z10Y11X11 0x9 3511 # define R300_TX_FORMAT_W4Z4Y4X4 0xA 3512 # define R300_TX_FORMAT_W1Z5Y5X5 0xB 3513 # define R300_TX_FORMAT_W8Z8Y8X8 0xC 3514 # define R300_TX_FORMAT_W2Z10Y10X10 0xD 3515 # define R300_TX_FORMAT_W16Z16Y16X16 0xE 3516 # define R300_TX_FORMAT_DXT1 0xF 3517 # define R300_TX_FORMAT_DXT3 0x10 3518 # define R300_TX_FORMAT_DXT5 0x11 3519 # define R300_TX_FORMAT_D3DMFT_CxV8U8 0x12 /* no swizzle */ 3520 # define R300_TX_FORMAT_A8R8G8B8 0x13 /* no swizzle */ 3521 # define R300_TX_FORMAT_B8G8_B8G8 0x14 /* no swizzle */ 3522 # define R300_TX_FORMAT_G8R8_G8B8 0x15 /* no swizzle */ 3523 /* 0x16 - some 16 bit green format.. ?? */ 3524 # define R300_TX_FORMAT_UNK25 (1 << 25) /* no swizzle */ 3525 # define R300_TX_FORMAT_CUBIC_MAP (1 << 26) 3526 /* gap */ 3527 /* Floating point formats */ 3528 /* Note - hardware supports both 16 and 32 bit floating point */ 3529 # define R300_TX_FORMAT_FL_I16 0x18 3530 # define R300_TX_FORMAT_FL_I16A16 0x19 3531 # define R300_TX_FORMAT_FL_R16G16B16A16 0x1A 3532 # define R300_TX_FORMAT_FL_I32 0x1B 3533 # define R300_TX_FORMAT_FL_I32A32 0x1C 3534 # define R300_TX_FORMAT_FL_R32G32B32A32 0x1D 3535 /* alpha modes, convenience mostly */ 3536 /* if you have alpha, pick constant appropriate to the 3537 number of channels (1 for I8, 2 for I8A8, 4 for R8G8B8A8, etc */ 3538 # define R300_TX_FORMAT_ALPHA_1CH 0x000 3539 # define R300_TX_FORMAT_ALPHA_2CH 0x200 3540 # define R300_TX_FORMAT_ALPHA_4CH 0x600 3541 # define R300_TX_FORMAT_ALPHA_NONE 0xA00 3542 /* Swizzling */ 3543 /* constants */ 3544 # define R300_TX_FORMAT_X 0 3545 # define R300_TX_FORMAT_Y 1 3546 # define R300_TX_FORMAT_Z 2 3547 # define R300_TX_FORMAT_W 3 3548 # define R300_TX_FORMAT_ZERO 4 3549 # define R300_TX_FORMAT_ONE 5 3550 # define R300_TX_FORMAT_CUT_Z 6 /* 2.0*Z, everything above 1.0 is set to 0.0 */ 3551 # define R300_TX_FORMAT_CUT_W 7 /* 2.0*W, everything above 1.0 is set to 0.0 */ 3552 # define R300_TX_FORMAT_B_SHIFT 18 3553 # define R300_TX_FORMAT_G_SHIFT 15 3554 # define R300_TX_FORMAT_R_SHIFT 12 3555 # define R300_TX_FORMAT_A_SHIFT 9 3556 /* Convenience macro to take care of layout and swizzling */ 3557 # define R300_EASY_TXFORMAT(B, G, R, A, FMT) (\ 3558 ((R300_TX_FORMAT_##B)<<R300_TX_FORMAT_B_SHIFT) \ 3559 | ((R300_TX_FORMAT_##G)<<R300_TX_FORMAT_G_SHIFT) \ 3560 | ((R300_TX_FORMAT_##R)<<R300_TX_FORMAT_R_SHIFT) \ 3561 | ((R300_TX_FORMAT_##A)<<R300_TX_FORMAT_A_SHIFT) \ 3562 | (R300_TX_FORMAT_##FMT) \ 3563 ) 3564 /* These can be ORed with result of R300_EASY_TX_FORMAT() */ 3565 /* We don't really know what they do. Take values from a constant color ? */ 3566 # define R300_TX_FORMAT_CONST_X (1<<5) 3567 # define R300_TX_FORMAT_CONST_Y (2<<5) 3568 # define R300_TX_FORMAT_CONST_Z (4<<5) 3569 # define R300_TX_FORMAT_CONST_W (8<<5) 3570 # define R300_TX_FORMAT_YUV_MODE 0x00800000 3571 /* Precalculated formats */ 3572 # define R300_TXFORMAT_ARGB8888 R300_EASY_TXFORMAT(X, Y, Z, W, W8Z8Y8X8) 3573 # define R300_TXFORMAT_XRGB8888 R300_EASY_TXFORMAT(X, Y, Z, ONE, W8Z8Y8X8) 3574 # define R300_TXFORMAT_RGB565 R300_EASY_TXFORMAT(X, Y, Z, ONE, Z5Y6X5) 3575 # define R300_TXFORMAT_ARGB4444 R300_EASY_TXFORMAT(X, Y, Z, W, W4Z4Y4X4) 3576 # define R300_TXFORMAT_ARGB1555 R300_EASY_TXFORMAT(X, Y, Z, W, W1Z5Y5X5) 3577 # define R300_TXFORMAT_RGB444 R300_EASY_TXFORMAT(X, Y, Z, ONE, W4Z4Y4X4) 3578 # define R300_TXFORMAT_RGB555 R300_EASY_TXFORMAT(X, Y, Z, ONE, W1Z5Y5X5) 3579 # define R300_TXFORMAT_RGB332 R300_EASY_TXFORMAT(X, Y, Z, ONE, Z3Y3X2) 3580 # define R300_TXFORMAT_A8 R300_EASY_TXFORMAT(ONE, ONE, ONE, X, X8) 3581 # define R300_TXFORMAT_I8 R300_EASY_TXFORMAT(X, X, X, X, X8) 3582 # define R300_TXFORMAT_VYUY422 R300_EASY_TXFORMAT(X, Y, Z, ONE, G8R8_G8B8)|R300_TX_FORMAT_YUV_MODE 3583 # define R300_TXFORMAT_YVYU422 R300_EASY_TXFORMAT(X, Y, Z, ONE, B8G8_B8G8)|R300_TX_FORMAT_YUV_MODE 3584 3585 3586 #define R300_TX_PITCH_0 0x4500 /* obvious missing in gap */ 3587 #define R300_TX_PITCH_1 0x4504 3588 3589 #define R300_TX_OFFSET_0 0x4540 3590 #define R300_TX_OFFSET_1 0x4544 3591 /* BEGIN: Guess from R200 */ 3592 # define R300_TXO_ENDIAN_NO_SWAP (0 << 0) 3593 # define R300_TXO_ENDIAN_BYTE_SWAP (1 << 0) 3594 # define R300_TXO_ENDIAN_WORD_SWAP (2 << 0) 3595 # define R300_TXO_ENDIAN_HALFDW_SWAP (3 << 0) 3596 # define R300_TXO_MACRO_TILE (1 << 2) 3597 # define R300_TXO_MICRO_TILE (1 << 3) 3598 # define R300_TXO_OFFSET_MASK 0xffffffe0 3599 /* END */ 3600 3601 #define R300_TX_CHROMA_KEY_0 0x4580 /* pixel value */ 3602 3603 #define R300_TX_BORDER_COLOR_0 0x45C0 //ff00ff00 == { 0, 1.0, 0, 1.0 } 3604 3605 /* END */ 3606 3607 /* BEGIN: Fragment program instruction set 3608 // Fragment programs are written directly into register space. 3609 // There are separate instruction streams for texture instructions and ALU 3610 // instructions. 3611 // In order to synchronize these streams, the program is divided into up 3612 // to 4 nodes. Each node begins with a number of TEX operations, followed 3613 // by a number of ALU operations. 3614 // The first node can have zero TEX ops, all subsequent nodes must have at least 3615 // one TEX ops. 3616 // All nodes must have at least one ALU op. 3617 // 3618 // The index of the last node is stored in PFS_CNTL_0: A value of 0 means 3619 // 1 node, a value of 3 means 4 nodes. 3620 // The total amount of instructions is defined in PFS_CNTL_2. The offsets are 3621 // offsets into the respective instruction streams, while *_END points to the 3622 // last instruction relative to this offset. */ 3623 #define R300_PFS_CNTL_0 0x4600 3624 # define R300_PFS_CNTL_LAST_NODES_SHIFT 0 3625 # define R300_PFS_CNTL_LAST_NODES_MASK (3 << 0) 3626 # define R300_PFS_CNTL_FIRST_NODE_HAS_TEX (1 << 3) 3627 #define R300_PFS_CNTL_1 0x4604 3628 /* There is an unshifted value here which has so far always been equal to the 3629 // index of the highest used temporary register. */ 3630 #define R300_PFS_CNTL_2 0x4608 3631 # define R300_PFS_CNTL_ALU_OFFSET_SHIFT 0 3632 # define R300_PFS_CNTL_ALU_OFFSET_MASK (63 << 0) 3633 # define R300_PFS_CNTL_ALU_END_SHIFT 6 3634 # define R300_PFS_CNTL_ALU_END_MASK (63 << 0) 3635 # define R300_PFS_CNTL_TEX_OFFSET_SHIFT 12 3636 # define R300_PFS_CNTL_TEX_OFFSET_MASK (31 << 12) /* GUESS */ 3637 # define R300_PFS_CNTL_TEX_END_SHIFT 18 3638 # define R300_PFS_CNTL_TEX_END_MASK (31 << 18) /* GUESS */ 3639 3640 /* gap */ 3641 /* Nodes are stored backwards. The last active node is always stored in 3642 // PFS_NODE_3. 3643 // Example: In a 2-node program, NODE_0 and NODE_1 are set to 0. The 3644 // first node is stored in NODE_2, the second node is stored in NODE_3. 3645 // 3646 // Offsets are relative to the master offset from PFS_CNTL_2. 3647 // LAST_NODE is set for the last node, and only for the last node. */ 3648 #define R300_PFS_NODE_0 0x4610 3649 #define R300_PFS_NODE_1 0x4614 3650 #define R300_PFS_NODE_2 0x4618 3651 #define R300_PFS_NODE_3 0x461C 3652 # define R300_PFS_NODE_ALU_OFFSET_SHIFT 0 3653 # define R300_PFS_NODE_ALU_OFFSET_MASK (63 << 0) 3654 # define R300_PFS_NODE_ALU_END_SHIFT 6 3655 # define R300_PFS_NODE_ALU_END_MASK (63 << 6) 3656 # define R300_PFS_NODE_TEX_OFFSET_SHIFT 12 3657 # define R300_PFS_NODE_TEX_OFFSET_MASK (31 << 12) 3658 # define R300_PFS_NODE_TEX_END_SHIFT 17 3659 # define R300_PFS_NODE_TEX_END_MASK (31 << 17) 3660 /*# define R300_PFS_NODE_LAST_NODE (1 << 22) */ 3661 # define R300_PFS_NODE_OUTPUT_COLOR (1 << 22) 3662 # define R300_PFS_NODE_OUTPUT_DEPTH (1 << 23) 3663 3664 /* TEX 3665 // As far as I can tell, texture instructions cannot write into output 3666 // registers directly. A subsequent ALU instruction is always necessary, 3667 // even if it's just MAD o0, r0, 1, 0 */ 3668 #define R300_PFS_TEXI_0 0x4620 3669 #define R300_PFS_TEXI_1 0x4624 3670 # define R300_FPITX_SRC_SHIFT 0 3671 # define R300_FPITX_SRC_MASK (31 << 0) 3672 # define R300_FPITX_SRC_CONST (1 << 5) /* GUESS */ 3673 # define R300_FPITX_DST_SHIFT 6 3674 # define R300_FPITX_DST_MASK (31 << 6) 3675 # define R300_FPITX_IMAGE_SHIFT 11 3676 # define R300_FPITX_IMAGE_MASK (15 << 11) /* GUESS based on layout and native limits */ 3677 /* Unsure if these are opcodes, or some kind of bitfield, but this is how 3678 * they were set when I checked 3679 */ 3680 # define R300_FPITX_OPCODE_SHIFT 15 3681 # define R300_FPITX_OP_TEX (1 << 15) 3682 # define R300_FPITX_OP_KIL (2 << 15) 3683 # define R300_FPITX_OP_TXP (3 << 15) 3684 # define R300_FPITX_OP_TXB (4 << 15) 3685 3686 /* ALU 3687 // The ALU instructions register blocks are enumerated according to the order 3688 // in which fglrx. I assume there is space for 64 instructions, since 3689 // each block has space for a maximum of 64 DWORDs, and this matches reported 3690 // native limits. 3691 // 3692 // The basic functional block seems to be one MAD for each color and alpha, 3693 // and an adder that adds all components after the MUL. 3694 // - ADD, MUL, MAD etc.: use MAD with appropriate neutral operands 3695 // - DP4: Use OUTC_DP4, OUTA_DP4 3696 // - DP3: Use OUTC_DP3, OUTA_DP4, appropriate alpha operands 3697 // - DPH: Use OUTC_DP4, OUTA_DP4, appropriate alpha operands 3698 // - CMP: If ARG2 < 0, return ARG1, else return ARG0 3699 // - FLR: use FRC+MAD 3700 // - XPD: use MAD+MAD 3701 // - SGE, SLT: use MAD+CMP 3702 // - RSQ: use ABS modifier for argument 3703 // - Use OUTC_REPL_ALPHA to write results of an alpha-only operation (e.g. RCP) 3704 // into color register 3705 // - apparently, there's no quick DST operation 3706 // - fglrx set FPI2_UNKNOWN_31 on a "MAD fragment.color, tmp0, tmp1, tmp2" 3707 // - fglrx set FPI2_UNKNOWN_31 on a "MAX r2, r1, c0" 3708 // - fglrx once set FPI0_UNKNOWN_31 on a "FRC r1, r1" 3709 // 3710 // Operand selection 3711 // First stage selects three sources from the available registers and 3712 // constant parameters. This is defined in INSTR1 (color) and INSTR3 (alpha). 3713 // fglrx sorts the three source fields: Registers before constants, 3714 // lower indices before higher indices; I do not know whether this is necessary. 3715 // fglrx fills unused sources with "read constant 0" 3716 // According to specs, you cannot select more than two different constants. 3717 // 3718 // Second stage selects the operands from the sources. This is defined in 3719 // INSTR0 (color) and INSTR2 (alpha). You can also select the special constants 3720 // zero and one. 3721 // Swizzling and negation happens in this stage, as well. 3722 // 3723 // Important: Color and alpha seem to be mostly separate, i.e. their sources 3724 // selection appears to be fully independent (the register storage is probably 3725 // physically split into a color and an alpha section). 3726 // However (because of the apparent physical split), there is some interaction 3727 // WRT swizzling. If, for example, you want to load an R component into an 3728 // Alpha operand, this R component is taken from a *color* source, not from 3729 // an alpha source. The corresponding register doesn't even have to appear in 3730 // the alpha sources list. (I hope this alll makes sense to you) 3731 // 3732 // Destination selection 3733 // The destination register index is in FPI1 (color) and FPI3 (alpha) together 3734 // with enable bits. 3735 // There are separate enable bits for writing into temporary registers 3736 // (DSTC_REG_* /DSTA_REG) and and program output registers (DSTC_OUTPUT_* /DSTA_OUTPUT). 3737 // You can write to both at once, or not write at all (the same index 3738 // must be used for both). 3739 // 3740 // Note: There is a special form for LRP 3741 // - Argument order is the same as in ARB_fragment_program. 3742 // - Operation is MAD 3743 // - ARG1 is set to ARGC_SRC1C_LRP/ARGC_SRC1A_LRP 3744 // - Set FPI0/FPI2_SPECIAL_LRP 3745 // Arbitrary LRP (including support for swizzling) requires vanilla MAD+MAD */ 3746 #define R300_PFS_INSTR1_0 0x46C0 3747 # define R300_FPI1_SRC0C_SHIFT 0 3748 # define R300_FPI1_SRC0C_MASK (31 << 0) 3749 # define R300_FPI1_SRC0C_CONST (1 << 5) 3750 # define R300_FPI1_SRC1C_SHIFT 6 3751 # define R300_FPI1_SRC1C_MASK (31 << 6) 3752 # define R300_FPI1_SRC1C_CONST (1 << 11) 3753 # define R300_FPI1_SRC2C_SHIFT 12 3754 # define R300_FPI1_SRC2C_MASK (31 << 12) 3755 # define R300_FPI1_SRC2C_CONST (1 << 17) 3756 # define R300_FPI1_DSTC_SHIFT 18 3757 # define R300_FPI1_DSTC_MASK (31 << 18) 3758 # define R300_FPI1_DSTC_REG_MASK_SHIFT 23 3759 # define R300_FPI1_DSTC_REG_X (1 << 23) 3760 # define R300_FPI1_DSTC_REG_Y (1 << 24) 3761 # define R300_FPI1_DSTC_REG_Z (1 << 25) 3762 # define R300_FPI1_DSTC_OUTPUT_MASK_SHIFT 26 3763 # define R300_FPI1_DSTC_OUTPUT_X (1 << 26) 3764 # define R300_FPI1_DSTC_OUTPUT_Y (1 << 27) 3765 # define R300_FPI1_DSTC_OUTPUT_Z (1 << 28) 3766 3767 #define R300_PFS_INSTR3_0 0x47C0 3768 # define R300_FPI3_SRC0A_SHIFT 0 3769 # define R300_FPI3_SRC0A_MASK (31 << 0) 3770 # define R300_FPI3_SRC0A_CONST (1 << 5) 3771 # define R300_FPI3_SRC1A_SHIFT 6 3772 # define R300_FPI3_SRC1A_MASK (31 << 6) 3773 # define R300_FPI3_SRC1A_CONST (1 << 11) 3774 # define R300_FPI3_SRC2A_SHIFT 12 3775 # define R300_FPI3_SRC2A_MASK (31 << 12) 3776 # define R300_FPI3_SRC2A_CONST (1 << 17) 3777 # define R300_FPI3_DSTA_SHIFT 18 3778 # define R300_FPI3_DSTA_MASK (31 << 18) 3779 # define R300_FPI3_DSTA_REG (1 << 23) 3780 # define R300_FPI3_DSTA_OUTPUT (1 << 24) 3781 # define R300_FPI3_DSTA_DEPTH (1 << 27) 3782 3783 #define R300_PFS_INSTR0_0 0x48C0 3784 # define R300_FPI0_ARGC_SRC0C_XYZ 0 3785 # define R300_FPI0_ARGC_SRC0C_XXX 1 3786 # define R300_FPI0_ARGC_SRC0C_YYY 2 3787 # define R300_FPI0_ARGC_SRC0C_ZZZ 3 3788 # define R300_FPI0_ARGC_SRC1C_XYZ 4 3789 # define R300_FPI0_ARGC_SRC1C_XXX 5 3790 # define R300_FPI0_ARGC_SRC1C_YYY 6 3791 # define R300_FPI0_ARGC_SRC1C_ZZZ 7 3792 # define R300_FPI0_ARGC_SRC2C_XYZ 8 3793 # define R300_FPI0_ARGC_SRC2C_XXX 9 3794 # define R300_FPI0_ARGC_SRC2C_YYY 10 3795 # define R300_FPI0_ARGC_SRC2C_ZZZ 11 3796 # define R300_FPI0_ARGC_SRC0A 12 3797 # define R300_FPI0_ARGC_SRC1A 13 3798 # define R300_FPI0_ARGC_SRC2A 14 3799 # define R300_FPI0_ARGC_SRC1C_LRP 15 3800 # define R300_FPI0_ARGC_ZERO 20 3801 # define R300_FPI0_ARGC_ONE 21 3802 # define R300_FPI0_ARGC_HALF 22 /* GUESS */ 3803 # define R300_FPI0_ARGC_SRC0C_YZX 23 3804 # define R300_FPI0_ARGC_SRC1C_YZX 24 3805 # define R300_FPI0_ARGC_SRC2C_YZX 25 3806 # define R300_FPI0_ARGC_SRC0C_ZXY 26 3807 # define R300_FPI0_ARGC_SRC1C_ZXY 27 3808 # define R300_FPI0_ARGC_SRC2C_ZXY 28 3809 # define R300_FPI0_ARGC_SRC0CA_WZY 29 3810 # define R300_FPI0_ARGC_SRC1CA_WZY 30 3811 # define R300_FPI0_ARGC_SRC2CA_WZY 31 3812 3813 # define R300_FPI0_ARG0C_SHIFT 0 3814 # define R300_FPI0_ARG0C_MASK (31 << 0) 3815 # define R300_FPI0_ARG0C_NEG (1 << 5) 3816 # define R300_FPI0_ARG0C_ABS (1 << 6) 3817 # define R300_FPI0_ARG1C_SHIFT 7 3818 # define R300_FPI0_ARG1C_MASK (31 << 7) 3819 # define R300_FPI0_ARG1C_NEG (1 << 12) 3820 # define R300_FPI0_ARG1C_ABS (1 << 13) 3821 # define R300_FPI0_ARG2C_SHIFT 14 3822 # define R300_FPI0_ARG2C_MASK (31 << 14) 3823 # define R300_FPI0_ARG2C_NEG (1 << 19) 3824 # define R300_FPI0_ARG2C_ABS (1 << 20) 3825 # define R300_FPI0_SPECIAL_LRP (1 << 21) 3826 # define R300_FPI0_OUTC_MAD (0 << 23) 3827 # define R300_FPI0_OUTC_DP3 (1 << 23) 3828 # define R300_FPI0_OUTC_DP4 (2 << 23) 3829 # define R300_FPI0_OUTC_MIN (4 << 23) 3830 # define R300_FPI0_OUTC_MAX (5 << 23) 3831 # define R300_FPI0_OUTC_CMP (8 << 23) 3832 # define R300_FPI0_OUTC_FRC (9 << 23) 3833 # define R300_FPI0_OUTC_REPL_ALPHA (10 << 23) 3834 # define R300_FPI0_OUTC_SAT (1 << 30) 3835 # define R300_FPI0_INSERT_NOP (1 << 31) 3836 3837 #define R300_PFS_INSTR2_0 0x49C0 3838 # define R300_FPI2_ARGA_SRC0C_X 0 3839 # define R300_FPI2_ARGA_SRC0C_Y 1 3840 # define R300_FPI2_ARGA_SRC0C_Z 2 3841 # define R300_FPI2_ARGA_SRC1C_X 3 3842 # define R300_FPI2_ARGA_SRC1C_Y 4 3843 # define R300_FPI2_ARGA_SRC1C_Z 5 3844 # define R300_FPI2_ARGA_SRC2C_X 6 3845 # define R300_FPI2_ARGA_SRC2C_Y 7 3846 # define R300_FPI2_ARGA_SRC2C_Z 8 3847 # define R300_FPI2_ARGA_SRC0A 9 3848 # define R300_FPI2_ARGA_SRC1A 10 3849 # define R300_FPI2_ARGA_SRC2A 11 3850 # define R300_FPI2_ARGA_SRC1A_LRP 15 3851 # define R300_FPI2_ARGA_ZERO 16 3852 # define R300_FPI2_ARGA_ONE 17 3853 # define R300_FPI2_ARGA_HALF 18 /* GUESS */ 3854 3855 # define R300_FPI2_ARG0A_SHIFT 0 3856 # define R300_FPI2_ARG0A_MASK (31 << 0) 3857 # define R300_FPI2_ARG0A_NEG (1 << 5) 3858 # define R300_FPI2_ARG0A_ABS (1 << 6) /* GUESS */ 3859 # define R300_FPI2_ARG1A_SHIFT 7 3860 # define R300_FPI2_ARG1A_MASK (31 << 7) 3861 # define R300_FPI2_ARG1A_NEG (1 << 12) 3862 # define R300_FPI2_ARG1A_ABS (1 << 13) /* GUESS */ 3863 # define R300_FPI2_ARG2A_SHIFT 14 3864 # define R300_FPI2_ARG2A_MASK (31 << 14) 3865 # define R300_FPI2_ARG2A_NEG (1 << 19) 3866 # define R300_FPI2_ARG2A_ABS (1 << 20) /* GUESS */ 3867 # define R300_FPI2_SPECIAL_LRP (1 << 21) 3868 # define R300_FPI2_OUTA_MAD (0 << 23) 3869 # define R300_FPI2_OUTA_DP4 (1 << 23) 3870 # define R300_FPI2_OUTA_MIN (2 << 23) 3871 # define R300_FPI2_OUTA_MAX (3 << 23) 3872 # define R300_FPI2_OUTA_CMP (6 << 23) 3873 # define R300_FPI2_OUTA_FRC (7 << 23) 3874 # define R300_FPI2_OUTA_EX2 (8 << 23) 3875 # define R300_FPI2_OUTA_LG2 (9 << 23) 3876 # define R300_FPI2_OUTA_RCP (10 << 23) 3877 # define R300_FPI2_OUTA_RSQ (11 << 23) 3878 # define R300_FPI2_OUTA_SAT (1 << 30) 3879 # define R300_FPI2_UNKNOWN_31 (1 << 31) 3880 /* END */ 3881 3882 /* gap */ 3883 #define R300_PP_ALPHA_TEST 0x4BD4 3884 # define R300_REF_ALPHA_MASK 0x000000ff 3885 # define R300_ALPHA_TEST_FAIL (0 << 8) 3886 # define R300_ALPHA_TEST_LESS (1 << 8) 3887 # define R300_ALPHA_TEST_LEQUAL (3 << 8) 3888 # define R300_ALPHA_TEST_EQUAL (2 << 8) 3889 # define R300_ALPHA_TEST_GEQUAL (6 << 8) 3890 # define R300_ALPHA_TEST_GREATER (4 << 8) 3891 # define R300_ALPHA_TEST_NEQUAL (5 << 8) 3892 # define R300_ALPHA_TEST_PASS (7 << 8) 3893 # define R300_ALPHA_TEST_OP_MASK (7 << 8) 3894 # define R300_ALPHA_TEST_ENABLE (1 << 11) 3895 3896 /* gap */ 3897 /* Fragment program parameters in 7.16 floating point */ 3898 #define R300_PFS_PARAM_0_X 0x4C00 3899 #define R300_PFS_PARAM_0_Y 0x4C04 3900 #define R300_PFS_PARAM_0_Z 0x4C08 3901 #define R300_PFS_PARAM_0_W 0x4C0C 3902 /* GUESS: PARAM_31 is last, based on native limits reported by fglrx */ 3903 #define R300_PFS_PARAM_31_X 0x4DF0 3904 #define R300_PFS_PARAM_31_Y 0x4DF4 3905 #define R300_PFS_PARAM_31_Z 0x4DF8 3906 #define R300_PFS_PARAM_31_W 0x4DFC 3907 3908 /* Notes: 3909 // - AFAIK fglrx always sets BLEND_UNKNOWN when blending is used in the application 3910 // - AFAIK fglrx always sets BLEND_NO_SEPARATE when CBLEND and ABLEND are set to the same 3911 // function (both registers are always set up completely in any case) 3912 // - Most blend flags are simply copied from R200 and not tested yet */ 3913 #define R300_RB3D_CBLEND 0x4E04 3914 #define R300_RB3D_ABLEND 0x4E08 3915 /* the following only appear in CBLEND */ 3916 # define R300_BLEND_ENABLE (1 << 0) 3917 # define R300_BLEND_UNKNOWN (3 << 1) 3918 # define R300_BLEND_NO_SEPARATE (1 << 3) 3919 /* the following are shared between CBLEND and ABLEND */ 3920 # define R300_FCN_MASK (3 << 12) 3921 # define R300_COMB_FCN_ADD_CLAMP (0 << 12) 3922 # define R300_COMB_FCN_ADD_NOCLAMP (1 << 12) 3923 # define R300_COMB_FCN_SUB_CLAMP (2 << 12) 3924 # define R300_COMB_FCN_SUB_NOCLAMP (3 << 12) 3925 # define R300_SRC_BLEND_GL_ZERO (32 << 16) 3926 # define R300_SRC_BLEND_GL_ONE (33 << 16) 3927 # define R300_SRC_BLEND_GL_SRC_COLOR (34 << 16) 3928 # define R300_SRC_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 16) 3929 # define R300_SRC_BLEND_GL_DST_COLOR (36 << 16) 3930 # define R300_SRC_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 16) 3931 # define R300_SRC_BLEND_GL_SRC_ALPHA (38 << 16) 3932 # define R300_SRC_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 16) 3933 # define R300_SRC_BLEND_GL_DST_ALPHA (40 << 16) 3934 # define R300_SRC_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 16) 3935 # define R300_SRC_BLEND_GL_SRC_ALPHA_SATURATE (42 << 16) 3936 # define R300_SRC_BLEND_GL_CONST_COLOR (43 << 16) 3937 # define R300_SRC_BLEND_GL_ONE_MINUS_CONST_COLOR (44 << 16) 3938 # define R300_SRC_BLEND_GL_CONST_ALPHA (45 << 16) 3939 # define R300_SRC_BLEND_GL_ONE_MINUS_CONST_ALPHA (46 << 16) 3940 # define R300_SRC_BLEND_MASK (63 << 16) 3941 # define R300_DST_BLEND_GL_ZERO (32 << 24) 3942 # define R300_DST_BLEND_GL_ONE (33 << 24) 3943 # define R300_DST_BLEND_GL_SRC_COLOR (34 << 24) 3944 # define R300_DST_BLEND_GL_ONE_MINUS_SRC_COLOR (35 << 24) 3945 # define R300_DST_BLEND_GL_DST_COLOR (36 << 24) 3946 # define R300_DST_BLEND_GL_ONE_MINUS_DST_COLOR (37 << 24) 3947 # define R300_DST_BLEND_GL_SRC_ALPHA (38 << 24) 3948 # define R300_DST_BLEND_GL_ONE_MINUS_SRC_ALPHA (39 << 24) 3949 # define R300_DST_BLEND_GL_DST_ALPHA (40 << 24) 3950 # define R300_DST_BLEND_GL_ONE_MINUS_DST_ALPHA (41 << 24) 3951 # define R300_DST_BLEND_GL_CONST_COLOR (43 << 24) 3952 # define R300_DST_BLEND_GL_ONE_MINUS_CONST_COLOR (44 << 24) 3953 # define R300_DST_BLEND_GL_CONST_ALPHA (45 << 24) 3954 # define R300_DST_BLEND_GL_ONE_MINUS_CONST_ALPHA (46 << 24) 3955 # define R300_DST_BLEND_MASK (63 << 24) 3956 #define R300_RB3D_COLORMASK 0x4E0C 3957 # define R300_COLORMASK0_B (1<<0) 3958 # define R300_COLORMASK0_G (1<<1) 3959 # define R300_COLORMASK0_R (1<<2) 3960 # define R300_COLORMASK0_A (1<<3) 3961 3962 #define R300_RB3D_BLENDCOLOR 0x4E10 /* ARGB */ 3963 3964 /* gap */ 3965 #define R300_RB3D_COLOROFFSET0 0x4E28 3966 # define R300_COLOROFFSET_MASK 0xFFFFFFF0 /* GUESS */ 3967 #define R300_RB3D_COLOROFFSET1 0x4E2C /* GUESS */ 3968 #define R300_RB3D_COLOROFFSET2 0x4E30 /* GUESS */ 3969 #define R300_RB3D_COLOROFFSET3 0x4E34 /* GUESS */ 3970 /* gap */ 3971 /* Bit 16: Larger tiles 3972 // Bit 17: 4x2 tiles 3973 // Bit 18: Extremely weird tile like, but some pixels duplicated? */ 3974 #define R300_RB3D_COLORPITCH0 0x4E38 3975 # define R300_COLORPITCH_MASK 0x00001FF8 /* GUESS */ 3976 # define R300_COLOR_TILE_ENABLE (1 << 16) /* GUESS */ 3977 # define R300_COLOR_MICROTILE_ENABLE (1 << 17) /* GUESS */ 3978 # define R300_COLOR_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ 3979 # define R300_COLOR_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ 3980 # define R300_COLOR_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ 3981 # define R300_COLOR_FORMAT_RGB565 (2 << 22) 3982 # define R300_COLOR_FORMAT_ARGB8888 (3 << 22) 3983 # define R300_COLOR_FORMAT_RGB8 (4 << 22) 3984 # define R300_COLOR_FORMAT_MASK (7 << 22) 3985 #define R300_RB3D_COLORPITCH1 0x4E3C /* GUESS */ 3986 #define R300_RB3D_COLORPITCH2 0x4E40 /* GUESS */ 3987 #define R300_RB3D_COLORPITCH3 0x4E44 /* GUESS */ 3988 3989 #define R300_RB3D_DSTCACHE_MODE 0x4E48 3990 /* gap */ 3991 /* Guess by Vladimir. 3992 // Set to 0A before 3D operations, set to 02 afterwards. */ 3993 #define R300_RB3D_DSTCACHE_CTLSTAT 0x4E4C 3994 # define R300_RB3D_DSTCACHE_02 0x00000002 3995 # define R300_RB3D_DSTCACHE_0A 0x0000000A 3996 3997 /* gap */ 3998 /* There seems to be no "write only" setting, so use Z-test = ALWAYS for this. */ 3999 /* Bit (1<<8) is the "test" bit. so plain write is 6 - vd */ 4000 #define R300_RB3D_ZSTENCIL_CNTL_0 0x4F00 4001 # define R300_RB3D_Z_DISABLED_1 0x00000010 /* GUESS */ 4002 # define R300_RB3D_Z_DISABLED_2 0x00000014 /* GUESS */ 4003 # define R300_RB3D_Z_TEST 0x00000012 4004 # define R300_RB3D_Z_TEST_AND_WRITE 0x00000016 4005 # define R300_RB3D_Z_WRITE_ONLY 0x00000006 4006 # define R300_RB3D_STENCIL_ENABLE 0x00000001 4007 4008 #define R300_RB3D_ZSTENCIL_CNTL_1 0x4F04 4009 /* functions */ 4010 # define R300_ZS_NEVER 0 4011 # define R300_ZS_LESS 1 4012 # define R300_ZS_LEQUAL 2 4013 # define R300_ZS_EQUAL 3 4014 # define R300_ZS_GEQUAL 4 4015 # define R300_ZS_GREATER 5 4016 # define R300_ZS_NOTEQUAL 6 4017 # define R300_ZS_ALWAYS 7 4018 # define R300_ZS_MASK 7 4019 /* operations */ 4020 # define R300_ZS_KEEP 0 4021 # define R300_ZS_ZERO 1 4022 # define R300_ZS_REPLACE 2 4023 # define R300_ZS_INCR 3 4024 # define R300_ZS_DECR 4 4025 # define R300_ZS_INVERT 5 4026 # define R300_ZS_INCR_WRAP 6 4027 # define R300_ZS_DECR_WRAP 7 4028 4029 /* front and back refer to operations done for front 4030 and back faces, i.e. separate stencil function support */ 4031 # define R300_RB3D_ZS1_DEPTH_FUNC_SHIFT 0 4032 # define R300_RB3D_ZS1_FRONT_FUNC_SHIFT 3 4033 # define R300_RB3D_ZS1_FRONT_FAIL_OP_SHIFT 6 4034 # define R300_RB3D_ZS1_FRONT_ZPASS_OP_SHIFT 9 4035 # define R300_RB3D_ZS1_FRONT_ZFAIL_OP_SHIFT 12 4036 # define R300_RB3D_ZS1_BACK_FUNC_SHIFT 15 4037 # define R300_RB3D_ZS1_BACK_FAIL_OP_SHIFT 18 4038 # define R300_RB3D_ZS1_BACK_ZPASS_OP_SHIFT 21 4039 # define R300_RB3D_ZS1_BACK_ZFAIL_OP_SHIFT 24 4040 4041 4042 4043 #define R300_RB3D_ZSTENCIL_CNTL_2 0x4F08 4044 # define R300_RB3D_ZS2_STENCIL_REF_SHIFT 0 4045 # define R300_RB3D_ZS2_STENCIL_MASK 0xFF 4046 # define R300_RB3D_ZS2_STENCIL_MASK_SHIFT 8 4047 # define R300_RB3D_ZS2_STENCIL_WRITE_MASK_SHIFT 16 4048 4049 /* gap */ 4050 4051 #define R300_RB3D_ZSTENCIL_FORMAT 0x4F10 4052 # define R300_DEPTH_FORMAT_16BIT_INT_Z (0 << 0) 4053 # define R300_DEPTH_FORMAT_24BIT_INT_Z (2 << 0) 4054 /* 16 bit format or some aditional bit ? */ 4055 # define R300_DEPTH_FORMAT_UNK32 (32 << 0) 4056 4057 /* gap */ 4058 #define R300_RB3D_DEPTHOFFSET 0x4F20 4059 #define R300_RB3D_DEPTHPITCH 0x4F24 4060 # define R300_DEPTHPITCH_MASK 0x00001FF8 /* GUESS */ 4061 # define R300_DEPTH_TILE_ENABLE (1 << 16) /* GUESS */ 4062 # define R300_DEPTH_MICROTILE_ENABLE (1 << 17) /* GUESS */ 4063 # define R300_DEPTH_ENDIAN_NO_SWAP (0 << 18) /* GUESS */ 4064 # define R300_DEPTH_ENDIAN_WORD_SWAP (1 << 18) /* GUESS */ 4065 # define R300_DEPTH_ENDIAN_DWORD_SWAP (2 << 18) /* GUESS */ 4066 4067 /* BEGIN: Vertex program instruction set 4068 // Every instruction is four dwords long: 4069 // DWORD 0: output and opcode 4070 // DWORD 1: first argument 4071 // DWORD 2: second argument 4072 // DWORD 3: third argument 4073 // 4074 // Notes: 4075 // - ABS r, a is implemented as MAX r, a, -a 4076 // - MOV is implemented as ADD to zero 4077 // - XPD is implemented as MUL + MAD 4078 // - FLR is implemented as FRC + ADD 4079 // - apparently, fglrx tries to schedule instructions so that there is at least 4080 // one instruction between the write to a temporary and the first read 4081 // from said temporary; however, violations of this scheduling are allowed 4082 // - register indices seem to be unrelated with OpenGL aliasing to conventional state 4083 // - only one attribute and one parameter can be loaded at a time; however, the 4084 // same attribute/parameter can be used for more than one argument 4085 // - the second software argument for POW is the third hardware argument (no idea why) 4086 // - MAD with only temporaries as input seems to use VPI_OUT_SELECT_MAD_2 4087 // 4088 // There is some magic surrounding LIT: 4089 // The single argument is replicated across all three inputs, but swizzled: 4090 // First argument: xyzy 4091 // Second argument: xyzx 4092 // Third argument: xyzw 4093 // Whenever the result is used later in the fragment program, fglrx forces x and w 4094 // to be 1.0 in the input selection; I don't know whether this is strictly necessary */ 4095 #define R300_VPI_OUT_OP_DOT (1 << 0) 4096 #define R300_VPI_OUT_OP_MUL (2 << 0) 4097 #define R300_VPI_OUT_OP_ADD (3 << 0) 4098 #define R300_VPI_OUT_OP_MAD (4 << 0) 4099 #define R300_VPI_OUT_OP_DST (5 << 0) 4100 #define R300_VPI_OUT_OP_FRC (6 << 0) 4101 #define R300_VPI_OUT_OP_MAX (7 << 0) 4102 #define R300_VPI_OUT_OP_MIN (8 << 0) 4103 #define R300_VPI_OUT_OP_SGE (9 << 0) 4104 #define R300_VPI_OUT_OP_SLT (10 << 0) 4105 #define R300_VPI_OUT_OP_UNK12 (12 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, vector(scalar, vector) */ 4106 #define R300_VPI_OUT_OP_EXP (65 << 0) 4107 #define R300_VPI_OUT_OP_LOG (66 << 0) 4108 #define R300_VPI_OUT_OP_UNK67 (67 << 0) /* Used in fog computations, scalar(scalar) */ 4109 #define R300_VPI_OUT_OP_LIT (68 << 0) 4110 #define R300_VPI_OUT_OP_POW (69 << 0) 4111 #define R300_VPI_OUT_OP_RCP (70 << 0) 4112 #define R300_VPI_OUT_OP_RSQ (72 << 0) 4113 #define R300_VPI_OUT_OP_UNK73 (73 << 0) /* Used in GL_POINT_DISTANCE_ATTENUATION_ARB, scalar(scalar) */ 4114 #define R300_VPI_OUT_OP_EX2 (75 << 0) 4115 #define R300_VPI_OUT_OP_LG2 (76 << 0) 4116 #define R300_VPI_OUT_OP_MAD_2 (128 << 0) 4117 #define R300_VPI_OUT_OP_UNK129 (129 << 0) /* all temps, vector(scalar, vector, vector) */ 4118 4119 #define R300_VPI_OUT_REG_CLASS_TEMPORARY (0 << 8) 4120 #define R300_VPI_OUT_REG_CLASS_RESULT (2 << 8) 4121 #define R300_VPI_OUT_REG_CLASS_MASK (31 << 8) 4122 4123 #define R300_VPI_OUT_REG_INDEX_SHIFT 13 4124 #define R300_VPI_OUT_REG_INDEX_MASK (31 << 13) /* GUESS based on fglrx native limits */ 4125 4126 #define R300_VPI_OUT_WRITE_X (1 << 20) 4127 #define R300_VPI_OUT_WRITE_Y (1 << 21) 4128 #define R300_VPI_OUT_WRITE_Z (1 << 22) 4129 #define R300_VPI_OUT_WRITE_W (1 << 23) 4130 4131 #define R300_VPI_IN_REG_CLASS_TEMPORARY (0 << 0) 4132 #define R300_VPI_IN_REG_CLASS_ATTRIBUTE (1 << 0) 4133 #define R300_VPI_IN_REG_CLASS_PARAMETER (2 << 0) 4134 #define R300_VPI_IN_REG_CLASS_NONE (9 << 0) 4135 #define R300_VPI_IN_REG_CLASS_MASK (31 << 0) /* GUESS */ 4136 4137 #define R300_VPI_IN_REG_INDEX_SHIFT 5 4138 #define R300_VPI_IN_REG_INDEX_MASK (255 << 5) /* GUESS based on fglrx native limits */ 4139 4140 /* The R300 can select components from the input register arbitrarily. 4141 // Use the following constants, shifted by the component shift you 4142 // want to select */ 4143 #define R300_VPI_IN_SELECT_X 0 4144 #define R300_VPI_IN_SELECT_Y 1 4145 #define R300_VPI_IN_SELECT_Z 2 4146 #define R300_VPI_IN_SELECT_W 3 4147 #define R300_VPI_IN_SELECT_ZERO 4 4148 #define R300_VPI_IN_SELECT_ONE 5 4149 #define R300_VPI_IN_SELECT_MASK 7 4150 4151 #define R300_VPI_IN_X_SHIFT 13 4152 #define R300_VPI_IN_Y_SHIFT 16 4153 #define R300_VPI_IN_Z_SHIFT 19 4154 #define R300_VPI_IN_W_SHIFT 22 4155 4156 #define R300_VPI_IN_NEG_X (1 << 25) 4157 #define R300_VPI_IN_NEG_Y (1 << 26) 4158 #define R300_VPI_IN_NEG_Z (1 << 27) 4159 #define R300_VPI_IN_NEG_W (1 << 28) 4160 /* END */ 4161 4162 //BEGIN: Packet 3 commands 4163 4164 // A primitive emission dword. 4165 #define R300_PRIM_TYPE_NONE (0 << 0) 4166 #define R300_PRIM_TYPE_POINT (1 << 0) 4167 #define R300_PRIM_TYPE_LINE (2 << 0) 4168 #define R300_PRIM_TYPE_LINE_STRIP (3 << 0) 4169 #define R300_PRIM_TYPE_TRI_LIST (4 << 0) 4170 #define R300_PRIM_TYPE_TRI_FAN (5 << 0) 4171 #define R300_PRIM_TYPE_TRI_STRIP (6 << 0) 4172 #define R300_PRIM_TYPE_TRI_TYPE2 (7 << 0) 4173 #define R300_PRIM_TYPE_RECT_LIST (8 << 0) 4174 #define R300_PRIM_TYPE_3VRT_POINT_LIST (9 << 0) 4175 #define R300_PRIM_TYPE_3VRT_LINE_LIST (10 << 0) 4176 #define R300_PRIM_TYPE_POINT_SPRITES (11 << 0) // GUESS (based on r200) 4177 #define R300_PRIM_TYPE_LINE_LOOP (12 << 0) 4178 #define R300_PRIM_TYPE_QUADS (13 << 0) 4179 #define R300_PRIM_TYPE_QUAD_STRIP (14 << 0) 4180 #define R300_PRIM_TYPE_POLYGON (15 << 0) 4181 #define R300_PRIM_TYPE_MASK 0xF 4182 #define R300_PRIM_WALK_IND (1 << 4) 4183 #define R300_PRIM_WALK_LIST (2 << 4) 4184 #define R300_PRIM_WALK_RING (3 << 4) 4185 #define R300_PRIM_WALK_MASK (3 << 4) 4186 #define R300_PRIM_COLOR_ORDER_BGRA (0 << 6) // GUESS (based on r200) 4187 #define R300_PRIM_COLOR_ORDER_RGBA (1 << 6) // GUESS 4188 #define R300_PRIM_NUM_VERTICES_SHIFT 16 4189 4190 /* Registers for CP and Microcode Engine */ 4191 #define CP_ME_RAM_ADDR 0x07d4 4192 #define CP_ME_RAM_RADDR 0x07d8 4193 #define CP_ME_RAM_DATAH 0x07dc 4194 #define CP_ME_RAM_DATAL 0x07e0 4195 4196 #define CP_RB_BASE 0x0700 4197 #define CP_RB_CNTL 0x0704 4198 #define CP_RB_RPTR_ADDR 0x070c 4199 #define CP_RB_RPTR 0x0710 4200 #define CP_RB_WPTR 0x0714 4201 4202 #define CP_IB_BASE 0x0738 4203 #define CP_IB_BUFSZ 0x073c 4204 4205 #define CP_CSQ_CNTL 0x0740 4206 # define CSQ_CNT_PRIMARY_MASK (0xff << 0) 4207 # define CSQ_PRIDIS_INDDIS (0 << 28) 4208 # define CSQ_PRIPIO_INDDIS (1 << 28) 4209 # define CSQ_PRIBM_INDDIS (2 << 28) 4210 # define CSQ_PRIPIO_INDBM (3 << 28) 4211 # define CSQ_PRIBM_INDBM (4 << 28) 4212 # define CSQ_PRIPIO_INDPIO (15 << 28) 4213 #define CP_CSQ_STAT 0x07f8 4214 # define CSQ_RPTR_PRIMARY_MASK (0xff << 0) 4215 # define CSQ_WPTR_PRIMARY_MASK (0xff << 8) 4216 # define CSQ_RPTR_INDIRECT_MASK (0xff << 16) 4217 # define CSQ_WPTR_INDIRECT_MASK (0xff << 24) 4218 #define CP_CSQ_ADDR 0x07f0 4219 #define CP_CSQ_DATA 0x07f4 4220 #define CP_CSQ_APER_PRIMARY 0x1000 4221 #define CP_CSQ_APER_INDIRECT 0x1300 4222 4223 #define CP_RB_WPTR_DELAY 0x0718 4224 # define PRE_WRITE_TIMER_SHIFT 0 4225 # define PRE_WRITE_LIMIT_SHIFT 23 4226 4227 #define AIC_CNTL 0x01d0 4228 # define PCIGART_TRANSLATE_EN (1 << 0) 4229 #define AIC_LO_ADDR 0x01dc 4230 4231 4232 4233 /* Constants */ 4234 #define LAST_FRAME_REG GUI_SCRATCH_REG0 4235 #define LAST_CLEAR_REG GUI_SCRATCH_REG2 4236 4237 4238 4239 /* CP packet types */ 4240 #define CP_PACKET0 0x00000000 4241 #define CP_PACKET1 0x40000000 4242 #define CP_PACKET2 0x80000000 4243 #define CP_PACKET3 0xC0000000 4244 # define CP_PACKET_MASK 0xC0000000 4245 # define CP_PACKET_COUNT_MASK 0x3fff0000 4246 # define CP_PACKET_MAX_DWORDS (1 << 12) 4247 # define CP_PACKET0_REG_MASK 0x000007ff 4248 # define CP_PACKET1_REG0_MASK 0x000007ff 4249 # define CP_PACKET1_REG1_MASK 0x003ff800 4250 4251 #define CP_PACKET0_ONE_REG_WR 0x00008000 4252 4253 #define CP_PACKET3_NOP 0xC0001000 4254 #define CP_PACKET3_NEXT_CHAR 0xC0001900 4255 #define CP_PACKET3_PLY_NEXTSCAN 0xC0001D00 4256 #define CP_PACKET3_SET_SCISSORS 0xC0001E00 4257 #define CP_PACKET3_3D_RNDR_GEN_INDX_PRIM 0xC0002300 4258 #define CP_PACKET3_LOAD_MICROCODE 0xC0002400 4259 #define CP_PACKET3_WAIT_FOR_IDLE 0xC0002600 4260 #define CP_PACKET3_3D_DRAW_VBUF 0xC0002800 4261 #define CP_PACKET3_3D_DRAW_IMMD 0xC0002900 4262 #define CP_PACKET3_3D_DRAW_INDX 0xC0002A00 4263 #define CP_PACKET3_LOAD_PALETTE 0xC0002C00 4264 #define R200_CP_PACKET3_3D_DRAW_IMMD_2 0xc0003500 4265 #define CP_PACKET3_3D_LOAD_VBPNTR 0xC0002F00 4266 #define CP_PACKET3_CNTL_PAINT 0xC0009100 4267 #define CP_PACKET3_CNTL_BITBLT 0xC0009200 4268 #define CP_PACKET3_CNTL_SMALLTEXT 0xC0009300 4269 #define CP_PACKET3_CNTL_HOSTDATA_BLT 0xC0009400 4270 #define CP_PACKET3_CNTL_POLYLINE 0xC0009500 4271 #define CP_PACKET3_CNTL_POLYSCANLINES 0xC0009800 4272 #define CP_PACKET3_CNTL_PAINT_MULTI 0xC0009A00 4273 #define CP_PACKET3_CNTL_BITBLT_MULTI 0xC0009B00 4274 #define CP_PACKET3_CNTL_TRANS_BITBLT 0xC0009C00 4275 4276 4277 #define CP_VC_FRMT_XY 0x00000000 4278 #define CP_VC_FRMT_W0 0x00000001 4279 #define CP_VC_FRMT_FPCOLOR 0x00000002 4280 #define CP_VC_FRMT_FPALPHA 0x00000004 4281 #define CP_VC_FRMT_PKCOLOR 0x00000008 4282 #define CP_VC_FRMT_FPSPEC 0x00000010 4283 #define CP_VC_FRMT_FPFOG 0x00000020 4284 #define CP_VC_FRMT_PKSPEC 0x00000040 4285 #define CP_VC_FRMT_ST0 0x00000080 4286 #define CP_VC_FRMT_ST1 0x00000100 4287 #define CP_VC_FRMT_Q1 0x00000200 4288 #define CP_VC_FRMT_ST2 0x00000400 4289 #define CP_VC_FRMT_Q2 0x00000800 4290 #define CP_VC_FRMT_ST3 0x00001000 4291 #define CP_VC_FRMT_Q3 0x00002000 4292 #define CP_VC_FRMT_Q0 0x00004000 4293 #define CP_VC_FRMT_BLND_WEIGHT_CNT_MASK 0x00038000 4294 #define CP_VC_FRMT_N0 0x00040000 4295 #define CP_VC_FRMT_XY1 0x08000000 4296 #define CP_VC_FRMT_Z1 0x10000000 4297 #define CP_VC_FRMT_W1 0x20000000 4298 #define CP_VC_FRMT_N1 0x40000000 4299 #define CP_VC_FRMT_Z 0x80000000 4300 4301 #define CP_VC_CNTL_PRIM_TYPE_NONE 0x00000000 4302 #define CP_VC_CNTL_PRIM_TYPE_POINT 0x00000001 4303 #define CP_VC_CNTL_PRIM_TYPE_LINE 0x00000002 4304 #define CP_VC_CNTL_PRIM_TYPE_LINE_STRIP 0x00000003 4305 #define CP_VC_CNTL_PRIM_TYPE_TRI_LIST 0x00000004 4306 #define CP_VC_CNTL_PRIM_TYPE_TRI_FAN 0x00000005 4307 #define CP_VC_CNTL_PRIM_TYPE_TRI_STRIP 0x00000006 4308 #define CP_VC_CNTL_PRIM_TYPE_TRI_TYPE_2 0x00000007 4309 #define CP_VC_CNTL_PRIM_TYPE_RECT_LIST 0x00000008 4310 #define CP_VC_CNTL_PRIM_TYPE_3VRT_POINT_LIST 0x00000009 4311 #define CP_VC_CNTL_PRIM_TYPE_3VRT_LINE_LIST 0x0000000a 4312 #define CP_VC_CNTL_PRIM_WALK_IND 0x00000010 4313 #define CP_VC_CNTL_PRIM_WALK_LIST 0x00000020 4314 #define CP_VC_CNTL_PRIM_WALK_RING 0x00000030 4315 #define CP_VC_CNTL_COLOR_ORDER_BGRA 0x00000000 4316 #define CP_VC_CNTL_COLOR_ORDER_RGBA 0x00000040 4317 #define CP_VC_CNTL_MAOS_ENABLE 0x00000080 4318 #define CP_VC_CNTL_VTX_FMT_NON_MODE 0x00000000 4319 #define CP_VC_CNTL_VTX_FMT_MODE 0x00000100 4320 #define CP_VC_CNTL_TCL_DISABLE 0x00000000 4321 #define CP_VC_CNTL_TCL_ENABLE 0x00000200 4322 #define CP_VC_CNTL_NUM_SHIFT 16 4323 4324 #define VS_MATRIX_0_ADDR 0 4325 #define VS_MATRIX_1_ADDR 4 4326 #define VS_MATRIX_2_ADDR 8 4327 #define VS_MATRIX_3_ADDR 12 4328 #define VS_MATRIX_4_ADDR 16 4329 #define VS_MATRIX_5_ADDR 20 4330 #define VS_MATRIX_6_ADDR 24 4331 #define VS_MATRIX_7_ADDR 28 4332 #define VS_MATRIX_8_ADDR 32 4333 #define VS_MATRIX_9_ADDR 36 4334 #define VS_MATRIX_10_ADDR 40 4335 #define VS_MATRIX_11_ADDR 44 4336 #define VS_MATRIX_12_ADDR 48 4337 #define VS_MATRIX_13_ADDR 52 4338 #define VS_MATRIX_14_ADDR 56 4339 #define VS_MATRIX_15_ADDR 60 4340 #define VS_LIGHT_AMBIENT_ADDR 64 4341 #define VS_LIGHT_DIFFUSE_ADDR 72 4342 #define VS_LIGHT_SPECULAR_ADDR 80 4343 #define VS_LIGHT_DIRPOS_ADDR 88 4344 #define VS_LIGHT_HWVSPOT_ADDR 96 4345 #define VS_LIGHT_ATTENUATION_ADDR 104 4346 #define VS_MATRIX_EYE2CLIP_ADDR 112 4347 #define VS_UCP_ADDR 116 4348 #define VS_GLOBAL_AMBIENT_ADDR 122 4349 #define VS_FOG_PARAM_ADDR 123 4350 #define VS_EYE_VECTOR_ADDR 124 4351 4352 #define SS_LIGHT_DCD_ADDR 0 4353 #define SS_LIGHT_SPOT_EXPONENT_ADDR 8 4354 #define SS_LIGHT_SPOT_CUTOFF_ADDR 16 4355 #define SS_LIGHT_SPECULAR_THRESH_ADDR 24 4356 #define SS_LIGHT_RANGE_CUTOFF_ADDR 32 4357 #define SS_VERT_GUARD_CLIP_ADJ_ADDR 48 4358 #define SS_VERT_GUARD_DISCARD_ADJ_ADDR 49 4359 #define SS_HORZ_GUARD_CLIP_ADJ_ADDR 50 4360 #define SS_HORZ_GUARD_DISCARD_ADJ_ADDR 51 4361 #define SS_SHININESS 60 4362 4363 4364 #endif /* __RADEON_REGS_H__ */ 4365