1 /* $OpenBSD: fpu.h,v 1.2 2012/12/04 05:00:40 deraadt Exp $ */ 2 3 /* 4 * Copyright (c) 2010 Miodrag Vallat. 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 /* 20 * Layout of the floating-point control/status register (FCR31) 21 */ 22 23 /* flush denormalized results to zero instead of causing FPCSR_C_E */ 24 #define FPCSR_FS 0x01000000 25 26 /* compare condition bits: one bit for MIPS I/II/III, eight bits for MIPS IV */ 27 #define FPCSR_CONDBIT(c) ((c) == 0 ? 23 : 24 + (c)) 28 #define FPCSR_CONDVAL(c) (1U << FPCSR_CONDBIT(c)) 29 30 /* cause bits */ 31 #define FPCSR_C_E 0x00020000 /* unimplemented operation */ 32 #define FPCSR_C_V 0x00010000 /* invalid operation */ 33 #define FPCSR_C_Z 0x00008000 /* division by zero */ 34 #define FPCSR_C_O 0x00004000 /* overflow */ 35 #define FPCSR_C_U 0x00002000 /* underflow */ 36 #define FPCSR_C_I 0x00001000 /* inexact */ 37 38 /* enable bits */ 39 #define FPCSR_E_V 0x00000800 /* invalid operation */ 40 #define FPCSR_E_Z 0x00000400 /* division by zero */ 41 #define FPCSR_E_O 0x00000200 /* overflow */ 42 #define FPCSR_E_U 0x00000100 /* underflow */ 43 #define FPCSR_E_I 0x00000080 /* inexact */ 44 45 /* flags bits */ 46 #define FPCSR_F_V 0x00000040 /* invalid operation */ 47 #define FPCSR_F_Z 0x00000020 /* division by zero */ 48 #define FPCSR_F_O 0x00000010 /* overflow */ 49 #define FPCSR_F_U 0x00000008 /* underflow */ 50 #define FPCSR_F_I 0x00000004 /* inexact */ 51 52 #define FPCSR_C_MASK 0x0003f000 53 #define FPCSR_C_SHIFT 12 54 #define FPCSR_E_MASK 0x00000f80 55 #define FPCSR_E_SHIFT 7 56 #define FPCSR_F_MASK 0x0000007c 57 #define FPCSR_F_SHIFT 2 58 #define FPCSR_RM_MASK 0x00000003 /* rounding mode */ 59 60 #ifndef _KERNEL 61 62 /* 63 * IRIX-compatible interfaces allowing userland to control the state 64 * of the floating-point control/status register. These are intended 65 * to let userland control the state of the FS bit. 66 */ 67 #include <sys/cdefs.h> 68 69 __BEGIN_DECLS 70 int get_fpc_csr(void); 71 int set_fpc_csr(int); 72 __END_DECLS 73 #endif /* _KERNEL */ 74