1 /*
2 * QEMU Malta board support
3 *
4 * Copyright (c) 2006 Aurelien Jarno
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qemu/units.h"
27 #include "qemu/bitops.h"
28 #include "qemu/datadir.h"
29 #include "qemu/guest-random.h"
30 #include "hw/clock.h"
31 #include "hw/southbridge/piix.h"
32 #include "hw/isa/superio.h"
33 #include "hw/char/serial.h"
34 #include "net/net.h"
35 #include "hw/boards.h"
36 #include "hw/i2c/smbus_eeprom.h"
37 #include "hw/block/flash.h"
38 #include "hw/mips/mips.h"
39 #include "hw/mips/bootloader.h"
40 #include "hw/pci/pci.h"
41 #include "hw/pci/pci_bus.h"
42 #include "qemu/log.h"
43 #include "hw/ide/pci.h"
44 #include "hw/irq.h"
45 #include "hw/loader.h"
46 #include "elf.h"
47 #include "qom/object.h"
48 #include "hw/sysbus.h" /* SysBusDevice */
49 #include "qemu/host-utils.h"
50 #include "sysemu/qtest.h"
51 #include "sysemu/reset.h"
52 #include "sysemu/runstate.h"
53 #include "qapi/error.h"
54 #include "qemu/error-report.h"
55 #include "sysemu/kvm.h"
56 #include "semihosting/semihost.h"
57 #include "hw/mips/cps.h"
58 #include "hw/qdev-clock.h"
59 #include "target/mips/internal.h"
60 #include "trace.h"
61 #include "cpu.h"
62
63 #define ENVP_PADDR 0x2000
64 #define ENVP_VADDR cpu_mips_phys_to_kseg0(NULL, ENVP_PADDR)
65 #define ENVP_NB_ENTRIES 16
66 #define ENVP_ENTRY_SIZE 256
67
68 /* Hardware addresses */
69 #define FLASH_ADDRESS 0x1e000000ULL
70 #define FPGA_ADDRESS 0x1f000000ULL
71 #define RESET_ADDRESS 0x1fc00000ULL
72
73 #define FLASH_SIZE 0x400000
74 #define BIOS_SIZE (4 * MiB)
75
76 #define PIIX4_PCI_DEVFN PCI_DEVFN(10, 0)
77
78 typedef struct {
79 MemoryRegion iomem;
80 MemoryRegion iomem_lo; /* 0 - 0x900 */
81 MemoryRegion iomem_hi; /* 0xa00 - 0x100000 */
82 uint32_t leds;
83 uint32_t brk;
84 uint32_t gpout;
85 uint32_t i2cin;
86 uint32_t i2coe;
87 uint32_t i2cout;
88 uint32_t i2csel;
89 CharBackend display;
90 char display_text[9];
91 SerialMM *uart;
92 bool display_inited;
93 } MaltaFPGAState;
94
95 #if TARGET_BIG_ENDIAN
96 #define BIOS_FILENAME "mips_bios.bin"
97 #else
98 #define BIOS_FILENAME "mipsel_bios.bin"
99 #endif
100
101 #define TYPE_MIPS_MALTA "mips-malta"
102 OBJECT_DECLARE_SIMPLE_TYPE(MaltaState, MIPS_MALTA)
103
104 struct MaltaState {
105 SysBusDevice parent_obj;
106
107 Clock *cpuclk;
108 MIPSCPSState cps;
109 };
110
111 static struct _loaderparams {
112 int ram_size, ram_low_size;
113 const char *kernel_filename;
114 const char *kernel_cmdline;
115 const char *initrd_filename;
116 } loaderparams;
117
118 /* Malta FPGA */
malta_fpga_update_display_leds(MaltaFPGAState * s)119 static void malta_fpga_update_display_leds(MaltaFPGAState *s)
120 {
121 char leds_text[9];
122 int i;
123
124 for (i = 7 ; i >= 0 ; i--) {
125 if (s->leds & (1 << i)) {
126 leds_text[i] = '#';
127 } else {
128 leds_text[i] = ' ';
129 }
130 }
131 leds_text[8] = '\0';
132
133 trace_malta_fpga_leds(leds_text);
134 qemu_chr_fe_printf(&s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n",
135 leds_text);
136 }
137
malta_fpga_update_display_ascii(MaltaFPGAState * s)138 static void malta_fpga_update_display_ascii(MaltaFPGAState *s)
139 {
140 trace_malta_fpga_display(s->display_text);
141 qemu_chr_fe_printf(&s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|",
142 s->display_text);
143 }
144
145 /*
146 * EEPROM 24C01 / 24C02 emulation.
147 *
148 * Emulation for serial EEPROMs:
149 * 24C01 - 1024 bit (128 x 8)
150 * 24C02 - 2048 bit (256 x 8)
151 *
152 * Typical device names include Microchip 24C02SC or SGS Thomson ST24C02.
153 */
154
155 #if defined(DEBUG)
156 # define logout(fmt, ...) \
157 fprintf(stderr, "MALTA\t%-24s" fmt, __func__, ## __VA_ARGS__)
158 #else
159 # define logout(fmt, ...) ((void)0)
160 #endif
161
162 struct _eeprom24c0x_t {
163 uint8_t tick;
164 uint8_t address;
165 uint8_t command;
166 uint8_t ack;
167 uint8_t scl;
168 uint8_t sda;
169 uint8_t data;
170 /* uint16_t size; */
171 uint8_t contents[256];
172 };
173
174 typedef struct _eeprom24c0x_t eeprom24c0x_t;
175
176 static eeprom24c0x_t spd_eeprom = {
177 .contents = {
178 /* 00000000: */
179 0x80, 0x08, 0xFF, 0x0D, 0x0A, 0xFF, 0x40, 0x00,
180 /* 00000008: */
181 0x01, 0x75, 0x54, 0x00, 0x82, 0x08, 0x00, 0x01,
182 /* 00000010: */
183 0x8F, 0x04, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00,
184 /* 00000018: */
185 0x00, 0x00, 0x00, 0x14, 0x0F, 0x14, 0x2D, 0xFF,
186 /* 00000020: */
187 0x15, 0x08, 0x15, 0x08, 0x00, 0x00, 0x00, 0x00,
188 /* 00000028: */
189 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
190 /* 00000030: */
191 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
192 /* 00000038: */
193 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x12, 0xD0,
194 /* 00000040: */
195 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
196 /* 00000048: */
197 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
198 /* 00000050: */
199 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
200 /* 00000058: */
201 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
202 /* 00000060: */
203 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
204 /* 00000068: */
205 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
206 /* 00000070: */
207 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
208 /* 00000078: */
209 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64, 0xF4,
210 },
211 };
212
generate_eeprom_spd(uint8_t * eeprom,ram_addr_t ram_size)213 static void generate_eeprom_spd(uint8_t *eeprom, ram_addr_t ram_size)
214 {
215 enum sdram_type type;
216 uint8_t *spd = spd_eeprom.contents;
217 uint8_t nbanks = 0;
218 uint16_t density = 0;
219 int i;
220
221 /* work in terms of MB */
222 ram_size /= MiB;
223
224 while ((ram_size >= 4) && (nbanks <= 2)) {
225 int sz_log2 = MIN(31 - clz32(ram_size), 14);
226 nbanks++;
227 density |= 1 << (sz_log2 - 2);
228 ram_size -= 1 << sz_log2;
229 }
230
231 /* split to 2 banks if possible */
232 if ((nbanks == 1) && (density > 1)) {
233 nbanks++;
234 density >>= 1;
235 }
236
237 if (density & 0xff00) {
238 density = (density & 0xe0) | ((density >> 8) & 0x1f);
239 type = DDR2;
240 } else if (!(density & 0x1f)) {
241 type = DDR2;
242 } else {
243 type = SDR;
244 }
245
246 if (ram_size) {
247 warn_report("SPD cannot represent final " RAM_ADDR_FMT "MB"
248 " of SDRAM", ram_size);
249 }
250
251 /* fill in SPD memory information */
252 spd[2] = type;
253 spd[5] = nbanks;
254 spd[31] = density;
255
256 /* checksum */
257 spd[63] = 0;
258 for (i = 0; i < 63; i++) {
259 spd[63] += spd[i];
260 }
261
262 /* copy for SMBUS */
263 memcpy(eeprom, spd, sizeof(spd_eeprom.contents));
264 }
265
generate_eeprom_serial(uint8_t * eeprom)266 static void generate_eeprom_serial(uint8_t *eeprom)
267 {
268 int i, pos = 0;
269 uint8_t mac[6] = { 0x00 };
270 uint8_t sn[5] = { 0x01, 0x23, 0x45, 0x67, 0x89 };
271
272 /* version */
273 eeprom[pos++] = 0x01;
274
275 /* count */
276 eeprom[pos++] = 0x02;
277
278 /* MAC address */
279 eeprom[pos++] = 0x01; /* MAC */
280 eeprom[pos++] = 0x06; /* length */
281 memcpy(&eeprom[pos], mac, sizeof(mac));
282 pos += sizeof(mac);
283
284 /* serial number */
285 eeprom[pos++] = 0x02; /* serial */
286 eeprom[pos++] = 0x05; /* length */
287 memcpy(&eeprom[pos], sn, sizeof(sn));
288 pos += sizeof(sn);
289
290 /* checksum */
291 eeprom[pos] = 0;
292 for (i = 0; i < pos; i++) {
293 eeprom[pos] += eeprom[i];
294 }
295 }
296
eeprom24c0x_read(eeprom24c0x_t * eeprom)297 static uint8_t eeprom24c0x_read(eeprom24c0x_t *eeprom)
298 {
299 logout("%u: scl = %u, sda = %u, data = 0x%02x\n",
300 eeprom->tick, eeprom->scl, eeprom->sda, eeprom->data);
301 return eeprom->sda;
302 }
303
eeprom24c0x_write(eeprom24c0x_t * eeprom,int scl,int sda)304 static void eeprom24c0x_write(eeprom24c0x_t *eeprom, int scl, int sda)
305 {
306 if (eeprom->scl && scl && (eeprom->sda != sda)) {
307 logout("%u: scl = %u->%u, sda = %u->%u i2c %s\n",
308 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda,
309 sda ? "stop" : "start");
310 if (!sda) {
311 eeprom->tick = 1;
312 eeprom->command = 0;
313 }
314 } else if (eeprom->tick == 0 && !eeprom->ack) {
315 /* Waiting for start. */
316 logout("%u: scl = %u->%u, sda = %u->%u wait for i2c start\n",
317 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
318 } else if (!eeprom->scl && scl) {
319 logout("%u: scl = %u->%u, sda = %u->%u trigger bit\n",
320 eeprom->tick, eeprom->scl, scl, eeprom->sda, sda);
321 if (eeprom->ack) {
322 logout("\ti2c ack bit = 0\n");
323 sda = 0;
324 eeprom->ack = 0;
325 } else if (eeprom->sda == sda) {
326 uint8_t bit = (sda != 0);
327 logout("\ti2c bit = %d\n", bit);
328 if (eeprom->tick < 9) {
329 eeprom->command <<= 1;
330 eeprom->command += bit;
331 eeprom->tick++;
332 if (eeprom->tick == 9) {
333 logout("\tcommand 0x%04x, %s\n", eeprom->command,
334 bit ? "read" : "write");
335 eeprom->ack = 1;
336 }
337 } else if (eeprom->tick < 17) {
338 if (eeprom->command & 1) {
339 sda = ((eeprom->data & 0x80) != 0);
340 }
341 eeprom->address <<= 1;
342 eeprom->address += bit;
343 eeprom->tick++;
344 eeprom->data <<= 1;
345 if (eeprom->tick == 17) {
346 eeprom->data = eeprom->contents[eeprom->address];
347 logout("\taddress 0x%04x, data 0x%02x\n",
348 eeprom->address, eeprom->data);
349 eeprom->ack = 1;
350 eeprom->tick = 0;
351 }
352 } else if (eeprom->tick >= 17) {
353 sda = 0;
354 }
355 } else {
356 logout("\tsda changed with raising scl\n");
357 }
358 } else {
359 logout("%u: scl = %u->%u, sda = %u->%u\n", eeprom->tick, eeprom->scl,
360 scl, eeprom->sda, sda);
361 }
362 eeprom->scl = scl;
363 eeprom->sda = sda;
364 }
365
malta_fpga_read(void * opaque,hwaddr addr,unsigned size)366 static uint64_t malta_fpga_read(void *opaque, hwaddr addr,
367 unsigned size)
368 {
369 MaltaFPGAState *s = opaque;
370 uint32_t val = 0;
371 uint32_t saddr;
372
373 saddr = (addr & 0xfffff);
374
375 switch (saddr) {
376
377 /* SWITCH Register */
378 case 0x00200:
379 val = 0x00000000;
380 break;
381
382 /* STATUS Register */
383 case 0x00208:
384 #if TARGET_BIG_ENDIAN
385 val = 0x00000012;
386 #else
387 val = 0x00000010;
388 #endif
389 break;
390
391 /* JMPRS Register */
392 case 0x00210:
393 val = 0x00;
394 break;
395
396 /* LEDBAR Register */
397 case 0x00408:
398 val = s->leds;
399 break;
400
401 /* BRKRES Register */
402 case 0x00508:
403 val = s->brk;
404 break;
405
406 /* UART Registers are handled directly by the serial device */
407
408 /* GPOUT Register */
409 case 0x00a00:
410 val = s->gpout;
411 break;
412
413 /* XXX: implement a real I2C controller */
414
415 /* GPINP Register */
416 case 0x00a08:
417 /* IN = OUT until a real I2C control is implemented */
418 if (s->i2csel) {
419 val = s->i2cout;
420 } else {
421 val = 0x00;
422 }
423 break;
424
425 /* I2CINP Register */
426 case 0x00b00:
427 val = ((s->i2cin & ~1) | eeprom24c0x_read(&spd_eeprom));
428 break;
429
430 /* I2COE Register */
431 case 0x00b08:
432 val = s->i2coe;
433 break;
434
435 /* I2COUT Register */
436 case 0x00b10:
437 val = s->i2cout;
438 break;
439
440 /* I2CSEL Register */
441 case 0x00b18:
442 val = s->i2csel;
443 break;
444
445 default:
446 qemu_log_mask(LOG_GUEST_ERROR,
447 "malta_fpga_read: Bad register addr 0x%"HWADDR_PRIX"\n",
448 addr);
449 break;
450 }
451 return val;
452 }
453
malta_fpga_write(void * opaque,hwaddr addr,uint64_t val,unsigned size)454 static void malta_fpga_write(void *opaque, hwaddr addr,
455 uint64_t val, unsigned size)
456 {
457 MaltaFPGAState *s = opaque;
458 uint32_t saddr;
459
460 saddr = (addr & 0xfffff);
461
462 switch (saddr) {
463
464 /* SWITCH Register */
465 case 0x00200:
466 break;
467
468 /* JMPRS Register */
469 case 0x00210:
470 break;
471
472 /* LEDBAR Register */
473 case 0x00408:
474 s->leds = val & 0xff;
475 malta_fpga_update_display_leds(s);
476 break;
477
478 /* ASCIIWORD Register */
479 case 0x00410:
480 snprintf(s->display_text, 9, "%08X", (uint32_t)val);
481 malta_fpga_update_display_ascii(s);
482 break;
483
484 /* ASCIIPOS0 to ASCIIPOS7 Registers */
485 case 0x00418:
486 case 0x00420:
487 case 0x00428:
488 case 0x00430:
489 case 0x00438:
490 case 0x00440:
491 case 0x00448:
492 case 0x00450:
493 s->display_text[(saddr - 0x00418) >> 3] = (char) val;
494 malta_fpga_update_display_ascii(s);
495 break;
496
497 /* SOFTRES Register */
498 case 0x00500:
499 if (val == 0x42) {
500 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
501 }
502 break;
503
504 /* BRKRES Register */
505 case 0x00508:
506 s->brk = val & 0xff;
507 break;
508
509 /* UART Registers are handled directly by the serial device */
510
511 /* GPOUT Register */
512 case 0x00a00:
513 s->gpout = val & 0xff;
514 break;
515
516 /* I2COE Register */
517 case 0x00b08:
518 s->i2coe = val & 0x03;
519 break;
520
521 /* I2COUT Register */
522 case 0x00b10:
523 eeprom24c0x_write(&spd_eeprom, val & 0x02, val & 0x01);
524 s->i2cout = val;
525 break;
526
527 /* I2CSEL Register */
528 case 0x00b18:
529 s->i2csel = val & 0x01;
530 break;
531
532 default:
533 qemu_log_mask(LOG_GUEST_ERROR,
534 "malta_fpga_write: Bad register addr 0x%"HWADDR_PRIX"\n",
535 addr);
536 break;
537 }
538 }
539
540 static const MemoryRegionOps malta_fpga_ops = {
541 .read = malta_fpga_read,
542 .write = malta_fpga_write,
543 .endianness = DEVICE_NATIVE_ENDIAN,
544 };
545
malta_fpga_reset(void * opaque)546 static void malta_fpga_reset(void *opaque)
547 {
548 MaltaFPGAState *s = opaque;
549
550 s->leds = 0x00;
551 s->brk = 0x0a;
552 s->gpout = 0x00;
553 s->i2cin = 0x3;
554 s->i2coe = 0x0;
555 s->i2cout = 0x3;
556 s->i2csel = 0x1;
557
558 s->display_text[8] = '\0';
559 snprintf(s->display_text, 9, " ");
560 }
561
malta_fgpa_display_event(void * opaque,QEMUChrEvent event)562 static void malta_fgpa_display_event(void *opaque, QEMUChrEvent event)
563 {
564 MaltaFPGAState *s = opaque;
565
566 if (event == CHR_EVENT_OPENED && !s->display_inited) {
567 qemu_chr_fe_printf(&s->display, "\e[HMalta LEDBAR\r\n");
568 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
569 qemu_chr_fe_printf(&s->display, "+ +\r\n");
570 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
571 qemu_chr_fe_printf(&s->display, "\n");
572 qemu_chr_fe_printf(&s->display, "Malta ASCII\r\n");
573 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
574 qemu_chr_fe_printf(&s->display, "+ +\r\n");
575 qemu_chr_fe_printf(&s->display, "+--------+\r\n");
576 s->display_inited = true;
577 }
578 }
579
malta_fpga_init(MemoryRegion * address_space,hwaddr base,qemu_irq uart_irq,Chardev * uart_chr)580 static MaltaFPGAState *malta_fpga_init(MemoryRegion *address_space,
581 hwaddr base, qemu_irq uart_irq, Chardev *uart_chr)
582 {
583 MaltaFPGAState *s;
584 Chardev *chr;
585
586 s = g_new0(MaltaFPGAState, 1);
587
588 memory_region_init_io(&s->iomem, NULL, &malta_fpga_ops, s,
589 "malta-fpga", 0x100000);
590 memory_region_init_alias(&s->iomem_lo, NULL, "malta-fpga",
591 &s->iomem, 0, 0x900);
592 memory_region_init_alias(&s->iomem_hi, NULL, "malta-fpga",
593 &s->iomem, 0xa00, 0x100000 - 0xa00);
594
595 memory_region_add_subregion(address_space, base, &s->iomem_lo);
596 memory_region_add_subregion(address_space, base + 0xa00, &s->iomem_hi);
597
598 chr = qemu_chr_new("fpga", "vc:320x200", NULL);
599 qemu_chr_fe_init(&s->display, chr, NULL);
600 qemu_chr_fe_set_handlers(&s->display, NULL, NULL,
601 malta_fgpa_display_event, NULL, s, NULL, true);
602
603 s->uart = serial_mm_init(address_space, base + 0x900, 3, uart_irq,
604 230400, uart_chr, DEVICE_NATIVE_ENDIAN);
605
606 malta_fpga_reset(s);
607 qemu_register_reset(malta_fpga_reset, s);
608
609 return s;
610 }
611
612 /* Network support */
network_init(PCIBus * pci_bus)613 static void network_init(PCIBus *pci_bus)
614 {
615 /* The malta board has a PCNet card using PCI SLOT 11 */
616 pci_init_nic_in_slot(pci_bus, "pcnet", NULL, "0b");
617 pci_init_nic_devices(pci_bus, "pcnet");
618 }
619
bl_setup_gt64120_jump_kernel(void ** p,uint64_t run_addr,uint64_t kernel_entry)620 static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr,
621 uint64_t kernel_entry)
622 {
623 static const char pci_pins_cfg[PCI_NUM_PINS] = {
624 10, 10, 11, 11 /* PIIX IRQRC[A:D] */
625 };
626
627 /* Bus endianness is always reversed */
628 #if TARGET_BIG_ENDIAN
629 #define cpu_to_gt32(x) (x)
630 #else
631 #define cpu_to_gt32(x) bswap32(x)
632 #endif
633
634 /* setup MEM-to-PCI0 mapping as done by YAMON */
635
636 /* move GT64120 registers from 0x14000000 to 0x1be00000 */
637 bl_gen_write_u32(p, /* GT_ISD */
638 cpu_mips_phys_to_kseg1(NULL, 0x14000000 + 0x68),
639 cpu_to_gt32(0x1be00000 << 3));
640
641 /* setup PCI0 io window to 0x18000000-0x181fffff */
642 bl_gen_write_u32(p, /* GT_PCI0IOLD */
643 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48),
644 cpu_to_gt32(0x18000000 << 3));
645 bl_gen_write_u32(p, /* GT_PCI0IOHD */
646 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50),
647 cpu_to_gt32(0x08000000 << 3));
648
649 /* setup PCI0 mem windows */
650 bl_gen_write_u32(p, /* GT_PCI0M0LD */
651 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),
652 cpu_to_gt32(0x10000000 << 3));
653 bl_gen_write_u32(p, /* GT_PCI0M0HD */
654 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x60),
655 cpu_to_gt32(0x07e00000 << 3));
656 bl_gen_write_u32(p, /* GT_PCI0M1LD */
657 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x80),
658 cpu_to_gt32(0x18200000 << 3));
659 bl_gen_write_u32(p, /* GT_PCI0M1HD */
660 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x88),
661 cpu_to_gt32(0x0bc00000 << 3));
662
663 #undef cpu_to_gt32
664
665 /*
666 * The PIIX ISA bridge is on PCI bus 0 dev 10 func 0.
667 * Load the PIIX IRQC[A:D] routing config address, then
668 * write routing configuration to the config data register.
669 */
670 bl_gen_write_u32(p, /* GT_PCI0_CFGADDR */
671 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcf8),
672 tswap32((1 << 31) /* ConfigEn */
673 | PCI_BUILD_BDF(0, PIIX4_PCI_DEVFN) << 8
674 | PIIX_PIRQCA));
675 bl_gen_write_u32(p, /* GT_PCI0_CFGDATA */
676 cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0xcfc),
677 tswap32(ldl_be_p(pci_pins_cfg)));
678
679 bl_gen_jump_kernel(p,
680 true, ENVP_VADDR - 64,
681 /*
682 * If semihosting is used, arguments have already
683 * been passed, so we preserve $a0.
684 */
685 !semihosting_get_argc(), 2,
686 true, ENVP_VADDR,
687 true, ENVP_VADDR + 8,
688 true, loaderparams.ram_low_size,
689 kernel_entry);
690 }
691
write_bootloader_nanomips(uint8_t * base,uint64_t run_addr,uint64_t kernel_entry)692 static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr,
693 uint64_t kernel_entry)
694 {
695 uint16_t *p;
696
697 /* Small bootloader */
698 p = (uint16_t *)base;
699
700 stw_p(p++, 0x2800); stw_p(p++, 0x001c);
701 /* bc to_here */
702 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
703 /* nop */
704 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
705 /* nop */
706 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
707 /* nop */
708 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
709 /* nop */
710 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
711 /* nop */
712 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
713 /* nop */
714 stw_p(p++, 0x8000); stw_p(p++, 0xc000);
715 /* nop */
716
717 /* to_here: */
718
719 bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
720 }
721
722 /*
723 * ROM and pseudo bootloader
724 *
725 * The following code implements a very very simple bootloader. It first
726 * loads the registers a0 to a3 to the values expected by the OS, and
727 * then jump at the kernel address.
728 *
729 * The bootloader should pass the locations of the kernel arguments and
730 * environment variables tables. Those tables contain the 32-bit address
731 * of NULL terminated strings. The environment variables table should be
732 * terminated by a NULL address.
733 *
734 * For a simpler implementation, the number of kernel arguments is fixed
735 * to two (the name of the kernel and the command line), and the two
736 * tables are actually the same one.
737 *
738 * The registers a0 to a3 should contain the following values:
739 * a0 - number of kernel arguments
740 * a1 - 32-bit address of the kernel arguments table
741 * a2 - 32-bit address of the environment variables table
742 * a3 - RAM size in bytes
743 */
write_bootloader(uint8_t * base,uint64_t run_addr,uint64_t kernel_entry)744 static void write_bootloader(uint8_t *base, uint64_t run_addr,
745 uint64_t kernel_entry)
746 {
747 uint32_t *p;
748
749 /* Small bootloader */
750 p = (uint32_t *)base;
751
752 stl_p(p++, 0x08000000 | /* j 0x1fc00580 */
753 ((run_addr + 0x580) & 0x0fffffff) >> 2);
754 stl_p(p++, 0x00000000); /* nop */
755
756 /* YAMON service vector */
757 stl_p(base + 0x500, run_addr + 0x0580); /* start: */
758 stl_p(base + 0x504, run_addr + 0x083c); /* print_count: */
759 stl_p(base + 0x520, run_addr + 0x0580); /* start: */
760 stl_p(base + 0x52c, run_addr + 0x0800); /* flush_cache: */
761 stl_p(base + 0x534, run_addr + 0x0808); /* print: */
762 stl_p(base + 0x538, run_addr + 0x0800); /* reg_cpu_isr: */
763 stl_p(base + 0x53c, run_addr + 0x0800); /* unred_cpu_isr: */
764 stl_p(base + 0x540, run_addr + 0x0800); /* reg_ic_isr: */
765 stl_p(base + 0x544, run_addr + 0x0800); /* unred_ic_isr: */
766 stl_p(base + 0x548, run_addr + 0x0800); /* reg_esr: */
767 stl_p(base + 0x54c, run_addr + 0x0800); /* unreg_esr: */
768 stl_p(base + 0x550, run_addr + 0x0800); /* getchar: */
769 stl_p(base + 0x554, run_addr + 0x0800); /* syscon_read: */
770
771
772 /* Second part of the bootloader */
773 p = (uint32_t *) (base + 0x580);
774
775 /*
776 * Load BAR registers as done by YAMON:
777 *
778 * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff
779 * - set up PCI0 MEM0 at 0x10000000, size 0x7e00000
780 * - set up PCI0 MEM1 at 0x18200000, size 0xbc00000
781 *
782 */
783
784 bl_setup_gt64120_jump_kernel((void **)&p, run_addr, kernel_entry);
785
786 /* YAMON subroutines */
787 p = (uint32_t *) (base + 0x800);
788 stl_p(p++, 0x03e00009); /* jalr ra */
789 stl_p(p++, 0x24020000); /* li v0,0 */
790 /* 808 YAMON print */
791 stl_p(p++, 0x03e06821); /* move t5,ra */
792 stl_p(p++, 0x00805821); /* move t3,a0 */
793 stl_p(p++, 0x00a05021); /* move t2,a1 */
794 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */
795 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */
796 stl_p(p++, 0x10800005); /* beqz a0,834 */
797 stl_p(p++, 0x00000000); /* nop */
798 stl_p(p++, 0x0ff0021c); /* jal 870 */
799 stl_p(p++, 0x00000000); /* nop */
800 stl_p(p++, 0x1000fff9); /* b 814 */
801 stl_p(p++, 0x00000000); /* nop */
802 stl_p(p++, 0x01a00009); /* jalr t5 */
803 stl_p(p++, 0x01602021); /* move a0,t3 */
804 /* 0x83c YAMON print_count */
805 stl_p(p++, 0x03e06821); /* move t5,ra */
806 stl_p(p++, 0x00805821); /* move t3,a0 */
807 stl_p(p++, 0x00a05021); /* move t2,a1 */
808 stl_p(p++, 0x00c06021); /* move t4,a2 */
809 stl_p(p++, 0x91440000); /* lbu a0,0(t2) */
810 stl_p(p++, 0x0ff0021c); /* jal 870 */
811 stl_p(p++, 0x00000000); /* nop */
812 stl_p(p++, 0x254a0001); /* addiu t2,t2,1 */
813 stl_p(p++, 0x258cffff); /* addiu t4,t4,-1 */
814 stl_p(p++, 0x1580fffa); /* bnez t4,84c */
815 stl_p(p++, 0x00000000); /* nop */
816 stl_p(p++, 0x01a00009); /* jalr t5 */
817 stl_p(p++, 0x01602021); /* move a0,t3 */
818 /* 0x870 */
819 stl_p(p++, 0x3c08b800); /* lui t0,0xb400 */
820 stl_p(p++, 0x350803f8); /* ori t0,t0,0x3f8 */
821 stl_p(p++, 0x91090005); /* lbu t1,5(t0) */
822 stl_p(p++, 0x00000000); /* nop */
823 stl_p(p++, 0x31290040); /* andi t1,t1,0x40 */
824 stl_p(p++, 0x1120fffc); /* beqz t1,878 <outch+0x8> */
825 stl_p(p++, 0x00000000); /* nop */
826 stl_p(p++, 0x03e00009); /* jalr ra */
827 stl_p(p++, 0xa1040000); /* sb a0,0(t0) */
828 }
829
prom_set(uint32_t * prom_buf,int index,const char * string,...)830 static void G_GNUC_PRINTF(3, 4) prom_set(uint32_t *prom_buf, int index,
831 const char *string, ...)
832 {
833 va_list ap;
834 uint32_t table_addr;
835
836 if (index >= ENVP_NB_ENTRIES) {
837 return;
838 }
839
840 if (string == NULL) {
841 prom_buf[index] = 0;
842 return;
843 }
844
845 table_addr = sizeof(uint32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
846 prom_buf[index] = tswap32(ENVP_VADDR + table_addr);
847
848 va_start(ap, string);
849 vsnprintf((char *)prom_buf + table_addr, ENVP_ENTRY_SIZE, string, ap);
850 va_end(ap);
851 }
852
reinitialize_rng_seed(void * opaque)853 static void reinitialize_rng_seed(void *opaque)
854 {
855 char *rng_seed_hex = opaque;
856 uint8_t rng_seed[32];
857
858 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
859 for (size_t i = 0; i < sizeof(rng_seed); ++i) {
860 sprintf(rng_seed_hex + i * 2, "%02x", rng_seed[i]);
861 }
862 }
863
864 /* Kernel */
load_kernel(void)865 static uint64_t load_kernel(void)
866 {
867 uint64_t kernel_entry, kernel_high, initrd_size;
868 long kernel_size;
869 ram_addr_t initrd_offset;
870 uint32_t *prom_buf;
871 long prom_size;
872 int prom_index = 0;
873 uint8_t rng_seed[32];
874 char rng_seed_hex[sizeof(rng_seed) * 2 + 1];
875 size_t rng_seed_prom_offset;
876
877 kernel_size = load_elf(loaderparams.kernel_filename, NULL,
878 cpu_mips_kseg0_to_phys, NULL,
879 &kernel_entry, NULL,
880 &kernel_high, NULL, TARGET_BIG_ENDIAN, EM_MIPS,
881 1, 0);
882 if (kernel_size < 0) {
883 error_report("could not load kernel '%s': %s",
884 loaderparams.kernel_filename,
885 load_elf_strerror(kernel_size));
886 exit(1);
887 }
888
889 /* Check where the kernel has been linked */
890 if (kernel_entry <= USEG_LIMIT) {
891 error_report("Trap-and-Emul kernels (Linux CONFIG_KVM_GUEST)"
892 " are not supported");
893 exit(1);
894 }
895
896 /* load initrd */
897 initrd_size = 0;
898 initrd_offset = 0;
899 if (loaderparams.initrd_filename) {
900 initrd_size = get_image_size(loaderparams.initrd_filename);
901 if (initrd_size > 0) {
902 /*
903 * The kernel allocates the bootmap memory in the low memory after
904 * the initrd. It takes at most 128kiB for 2GB RAM and 4kiB
905 * pages.
906 */
907 initrd_offset = ROUND_UP(loaderparams.ram_low_size
908 - (initrd_size + 128 * KiB),
909 INITRD_PAGE_SIZE);
910 if (kernel_high >= initrd_offset) {
911 error_report("memory too small for initial ram disk '%s'",
912 loaderparams.initrd_filename);
913 exit(1);
914 }
915 initrd_size = load_image_targphys(loaderparams.initrd_filename,
916 initrd_offset,
917 loaderparams.ram_size - initrd_offset);
918 }
919 if (initrd_size == (target_ulong) -1) {
920 error_report("could not load initial ram disk '%s'",
921 loaderparams.initrd_filename);
922 exit(1);
923 }
924 }
925
926 /* Setup prom parameters. */
927 prom_size = ENVP_NB_ENTRIES * (sizeof(int32_t) + ENVP_ENTRY_SIZE);
928 prom_buf = g_malloc(prom_size);
929
930 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_filename);
931 if (initrd_size > 0) {
932 prom_set(prom_buf, prom_index++,
933 "rd_start=0x%" PRIx64 " rd_size=%" PRId64 " %s",
934 cpu_mips_phys_to_kseg0(NULL, initrd_offset),
935 initrd_size, loaderparams.kernel_cmdline);
936 } else {
937 prom_set(prom_buf, prom_index++, "%s", loaderparams.kernel_cmdline);
938 }
939
940 prom_set(prom_buf, prom_index++, "memsize");
941 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_low_size);
942
943 prom_set(prom_buf, prom_index++, "ememsize");
944 prom_set(prom_buf, prom_index++, "%u", loaderparams.ram_size);
945
946 prom_set(prom_buf, prom_index++, "modetty0");
947 prom_set(prom_buf, prom_index++, "38400n8r");
948
949 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
950 for (size_t i = 0; i < sizeof(rng_seed); ++i) {
951 sprintf(rng_seed_hex + i * 2, "%02x", rng_seed[i]);
952 }
953 prom_set(prom_buf, prom_index++, "rngseed");
954 rng_seed_prom_offset = prom_index * ENVP_ENTRY_SIZE +
955 sizeof(uint32_t) * ENVP_NB_ENTRIES;
956 prom_set(prom_buf, prom_index++, "%s", rng_seed_hex);
957
958 prom_set(prom_buf, prom_index++, NULL);
959
960 rom_add_blob_fixed("prom", prom_buf, prom_size, ENVP_PADDR);
961 qemu_register_reset_nosnapshotload(reinitialize_rng_seed,
962 rom_ptr(ENVP_PADDR, prom_size) + rng_seed_prom_offset);
963
964 g_free(prom_buf);
965 return kernel_entry;
966 }
967
malta_mips_config(MIPSCPU * cpu)968 static void malta_mips_config(MIPSCPU *cpu)
969 {
970 MachineState *ms = MACHINE(qdev_get_machine());
971 unsigned int smp_cpus = ms->smp.cpus;
972 CPUMIPSState *env = &cpu->env;
973 CPUState *cs = CPU(cpu);
974
975 if (ase_mt_available(env)) {
976 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
977 CP0MVPC0_PTC, 8,
978 smp_cpus * cs->nr_threads - 1);
979 env->mvp->CP0_MVPConf0 = deposit32(env->mvp->CP0_MVPConf0,
980 CP0MVPC0_PVPE, 4, smp_cpus - 1);
981 }
982 }
983
malta_pci_slot_get_pirq(PCIDevice * pci_dev,int irq_num)984 static int malta_pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
985 {
986 int slot;
987
988 slot = PCI_SLOT(pci_dev->devfn);
989
990 switch (slot) {
991 /* PIIX4 USB */
992 case 10:
993 return 3;
994 /* AMD 79C973 Ethernet */
995 case 11:
996 return 1;
997 /* Crystal 4281 Sound */
998 case 12:
999 return 2;
1000 /* PCI slot 1 to 4 */
1001 case 18 ... 21:
1002 return ((slot - 18) + irq_num) & 0x03;
1003 /* Unknown device, don't do any translation */
1004 default:
1005 return irq_num;
1006 }
1007 }
1008
main_cpu_reset(void * opaque)1009 static void main_cpu_reset(void *opaque)
1010 {
1011 MIPSCPU *cpu = opaque;
1012 CPUMIPSState *env = &cpu->env;
1013
1014 cpu_reset(CPU(cpu));
1015
1016 /*
1017 * The bootloader does not need to be rewritten as it is located in a
1018 * read only location. The kernel location and the arguments table
1019 * location does not change.
1020 */
1021 if (loaderparams.kernel_filename) {
1022 env->CP0_Status &= ~(1 << CP0St_ERL);
1023 }
1024
1025 malta_mips_config(cpu);
1026 }
1027
create_cpu_without_cps(MachineState * ms,MaltaState * s,qemu_irq * cbus_irq,qemu_irq * i8259_irq)1028 static void create_cpu_without_cps(MachineState *ms, MaltaState *s,
1029 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
1030 {
1031 CPUMIPSState *env;
1032 MIPSCPU *cpu;
1033 int i;
1034
1035 for (i = 0; i < ms->smp.cpus; i++) {
1036 cpu = mips_cpu_create_with_clock(ms->cpu_type, s->cpuclk);
1037
1038 /* Init internal devices */
1039 cpu_mips_irq_init_cpu(cpu);
1040 cpu_mips_clock_init(cpu);
1041 qemu_register_reset(main_cpu_reset, cpu);
1042 }
1043
1044 cpu = MIPS_CPU(first_cpu);
1045 env = &cpu->env;
1046 *i8259_irq = env->irq[2];
1047 *cbus_irq = env->irq[4];
1048 }
1049
create_cps(MachineState * ms,MaltaState * s,qemu_irq * cbus_irq,qemu_irq * i8259_irq)1050 static void create_cps(MachineState *ms, MaltaState *s,
1051 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
1052 {
1053 object_initialize_child(OBJECT(s), "cps", &s->cps, TYPE_MIPS_CPS);
1054 object_property_set_str(OBJECT(&s->cps), "cpu-type", ms->cpu_type,
1055 &error_fatal);
1056 object_property_set_uint(OBJECT(&s->cps), "num-vp", ms->smp.cpus,
1057 &error_fatal);
1058 qdev_connect_clock_in(DEVICE(&s->cps), "clk-in", s->cpuclk);
1059 sysbus_realize(SYS_BUS_DEVICE(&s->cps), &error_fatal);
1060
1061 sysbus_mmio_map_overlap(SYS_BUS_DEVICE(&s->cps), 0, 0, 1);
1062
1063 *i8259_irq = get_cps_irq(&s->cps, 3);
1064 *cbus_irq = NULL;
1065 }
1066
mips_create_cpu(MachineState * ms,MaltaState * s,qemu_irq * cbus_irq,qemu_irq * i8259_irq)1067 static void mips_create_cpu(MachineState *ms, MaltaState *s,
1068 qemu_irq *cbus_irq, qemu_irq *i8259_irq)
1069 {
1070 if ((ms->smp.cpus > 1) && cpu_type_supports_cps_smp(ms->cpu_type)) {
1071 create_cps(ms, s, cbus_irq, i8259_irq);
1072 } else {
1073 create_cpu_without_cps(ms, s, cbus_irq, i8259_irq);
1074 }
1075 }
1076
1077 static
mips_malta_init(MachineState * machine)1078 void mips_malta_init(MachineState *machine)
1079 {
1080 ram_addr_t ram_size = machine->ram_size;
1081 ram_addr_t ram_low_size;
1082 const char *kernel_filename = machine->kernel_filename;
1083 const char *kernel_cmdline = machine->kernel_cmdline;
1084 const char *initrd_filename = machine->initrd_filename;
1085 char *filename;
1086 PFlashCFI01 *fl;
1087 MemoryRegion *system_memory = get_system_memory();
1088 MemoryRegion *ram_low_preio = g_new(MemoryRegion, 1);
1089 MemoryRegion *ram_low_postio;
1090 MemoryRegion *bios, *bios_copy = g_new(MemoryRegion, 1);
1091 const size_t smbus_eeprom_size = 8 * 256;
1092 uint8_t *smbus_eeprom_buf = g_malloc0(smbus_eeprom_size);
1093 uint64_t kernel_entry, bootloader_run_addr;
1094 PCIBus *pci_bus;
1095 ISABus *isa_bus;
1096 qemu_irq cbus_irq, i8259_irq;
1097 I2CBus *smbus;
1098 DriveInfo *dinfo;
1099 int fl_idx = 0;
1100 MaltaState *s;
1101 PCIDevice *piix4;
1102 DeviceState *dev;
1103
1104 s = MIPS_MALTA(qdev_new(TYPE_MIPS_MALTA));
1105 sysbus_realize_and_unref(SYS_BUS_DEVICE(s), &error_fatal);
1106
1107 /* create CPU */
1108 mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);
1109
1110 /* allocate RAM */
1111 if (ram_size > 2 * GiB) {
1112 error_report("Too much memory for this machine: %" PRId64 "MB,"
1113 " maximum 2048MB", ram_size / MiB);
1114 exit(1);
1115 }
1116
1117 /* register RAM at high address where it is undisturbed by IO */
1118 memory_region_add_subregion(system_memory, 0x80000000, machine->ram);
1119
1120 /* alias for pre IO hole access */
1121 memory_region_init_alias(ram_low_preio, NULL, "mips_malta_low_preio.ram",
1122 machine->ram, 0, MIN(ram_size, 256 * MiB));
1123 memory_region_add_subregion(system_memory, 0, ram_low_preio);
1124
1125 /* alias for post IO hole access, if there is enough RAM */
1126 if (ram_size > 512 * MiB) {
1127 ram_low_postio = g_new(MemoryRegion, 1);
1128 memory_region_init_alias(ram_low_postio, NULL,
1129 "mips_malta_low_postio.ram",
1130 machine->ram, 512 * MiB,
1131 ram_size - 512 * MiB);
1132 memory_region_add_subregion(system_memory, 512 * MiB,
1133 ram_low_postio);
1134 }
1135
1136 /* FPGA */
1137
1138 /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */
1139 malta_fpga_init(system_memory, FPGA_ADDRESS, cbus_irq, serial_hd(2));
1140
1141 /* Load firmware in flash / BIOS. */
1142 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
1143 fl = pflash_cfi01_register(FLASH_ADDRESS, "mips_malta.bios",
1144 FLASH_SIZE,
1145 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL,
1146 65536,
1147 4, 0x0000, 0x0000, 0x0000, 0x0000,
1148 TARGET_BIG_ENDIAN);
1149 bios = pflash_cfi01_get_memory(fl);
1150 fl_idx++;
1151 if (kernel_filename) {
1152 ram_low_size = MIN(ram_size, 256 * MiB);
1153 bootloader_run_addr = cpu_mips_phys_to_kseg0(NULL, RESET_ADDRESS);
1154
1155 /* Write a small bootloader to the flash location. */
1156 loaderparams.ram_size = ram_size;
1157 loaderparams.ram_low_size = ram_low_size;
1158 loaderparams.kernel_filename = kernel_filename;
1159 loaderparams.kernel_cmdline = kernel_cmdline;
1160 loaderparams.initrd_filename = initrd_filename;
1161 kernel_entry = load_kernel();
1162
1163 if (!cpu_type_supports_isa(machine->cpu_type, ISA_NANOMIPS32)) {
1164 write_bootloader(memory_region_get_ram_ptr(bios),
1165 bootloader_run_addr, kernel_entry);
1166 } else {
1167 write_bootloader_nanomips(memory_region_get_ram_ptr(bios),
1168 bootloader_run_addr, kernel_entry);
1169 }
1170 } else {
1171 target_long bios_size = FLASH_SIZE;
1172 /* Load firmware from flash. */
1173 if (!dinfo) {
1174 /* Load a BIOS image. */
1175 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS,
1176 machine->firmware ?: BIOS_FILENAME);
1177 if (filename) {
1178 bios_size = load_image_targphys(filename, FLASH_ADDRESS,
1179 BIOS_SIZE);
1180 g_free(filename);
1181 } else {
1182 bios_size = -1;
1183 }
1184 if ((bios_size < 0 || bios_size > BIOS_SIZE) &&
1185 machine->firmware && !qtest_enabled()) {
1186 error_report("Could not load MIPS bios '%s'", machine->firmware);
1187 exit(1);
1188 }
1189 }
1190 /*
1191 * In little endian mode the 32bit words in the bios are swapped,
1192 * a neat trick which allows bi-endian firmware.
1193 */
1194 #if !TARGET_BIG_ENDIAN
1195 {
1196 uint32_t *end, *addr;
1197 const size_t swapsize = MIN(bios_size, 0x3e0000);
1198 addr = rom_ptr(FLASH_ADDRESS, swapsize);
1199 if (!addr) {
1200 addr = memory_region_get_ram_ptr(bios);
1201 }
1202 end = (void *)addr + swapsize;
1203 while (addr < end) {
1204 bswap32s(addr);
1205 addr++;
1206 }
1207 }
1208 #endif
1209 }
1210
1211 /*
1212 * Map the BIOS at a 2nd physical location, as on the real board.
1213 * Copy it so that we can patch in the MIPS revision, which cannot be
1214 * handled by an overlapping region as the resulting ROM code subpage
1215 * regions are not executable.
1216 */
1217 memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE,
1218 &error_fatal);
1219 if (!rom_copy(memory_region_get_ram_ptr(bios_copy),
1220 FLASH_ADDRESS, BIOS_SIZE)) {
1221 memcpy(memory_region_get_ram_ptr(bios_copy),
1222 memory_region_get_ram_ptr(bios), BIOS_SIZE);
1223 }
1224 memory_region_set_readonly(bios_copy, true);
1225 memory_region_add_subregion(system_memory, RESET_ADDRESS, bios_copy);
1226
1227 /* Board ID = 0x420 (Malta Board with CoreLV) */
1228 stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
1229
1230 /* Northbridge */
1231 dev = qdev_new("gt64120");
1232 qdev_prop_set_bit(dev, "cpu-little-endian", !TARGET_BIG_ENDIAN);
1233 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
1234 pci_bus = PCI_BUS(qdev_get_child_bus(dev, "pci"));
1235 pci_bus_map_irqs(pci_bus, malta_pci_slot_get_pirq);
1236
1237 /* Southbridge */
1238 piix4 = pci_new_multifunction(PIIX4_PCI_DEVFN, TYPE_PIIX4_PCI_DEVICE);
1239 qdev_prop_set_uint32(DEVICE(piix4), "smb_io_base", 0x1100);
1240 pci_realize_and_unref(piix4, pci_bus, &error_fatal);
1241 isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix4), "isa.0"));
1242
1243 dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "ide"));
1244 pci_ide_create_devs(PCI_DEVICE(dev));
1245
1246 /* Interrupt controller */
1247 qdev_connect_gpio_out_named(DEVICE(piix4), "intr", 0, i8259_irq);
1248
1249 /* generate SPD EEPROM data */
1250 dev = DEVICE(object_resolve_path_component(OBJECT(piix4), "pm"));
1251 smbus = I2C_BUS(qdev_get_child_bus(dev, "i2c"));
1252 generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
1253 generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
1254 smbus_eeprom_init(smbus, 8, smbus_eeprom_buf, smbus_eeprom_size);
1255 g_free(smbus_eeprom_buf);
1256
1257 /* Super I/O: SMS FDC37M817 */
1258 isa_create_simple(isa_bus, TYPE_FDC37M81X_SUPERIO);
1259
1260 /* Network card */
1261 network_init(pci_bus);
1262
1263 /* Optional PCI video card */
1264 pci_vga_init(pci_bus);
1265 }
1266
mips_malta_instance_init(Object * obj)1267 static void mips_malta_instance_init(Object *obj)
1268 {
1269 MaltaState *s = MIPS_MALTA(obj);
1270
1271 s->cpuclk = qdev_init_clock_out(DEVICE(obj), "cpu-refclk");
1272 clock_set_hz(s->cpuclk, 320000000); /* 320 MHz */
1273 }
1274
1275 static const TypeInfo mips_malta_device = {
1276 .name = TYPE_MIPS_MALTA,
1277 .parent = TYPE_SYS_BUS_DEVICE,
1278 .instance_size = sizeof(MaltaState),
1279 .instance_init = mips_malta_instance_init,
1280 };
1281
1282 GlobalProperty malta_compat[] = {
1283 { "PIIX4_PM", "memory-hotplug-support", "off" },
1284 { "PIIX4_PM", "acpi-pci-hotplug-with-bridge-support", "off" },
1285 { "PIIX4_PM", "acpi-root-pci-hotplug", "off" },
1286 { "PIIX4_PM", "x-not-migrate-acpi-index", "true" },
1287 };
1288 const size_t malta_compat_len = G_N_ELEMENTS(malta_compat);
1289
mips_malta_machine_init(MachineClass * mc)1290 static void mips_malta_machine_init(MachineClass *mc)
1291 {
1292 mc->desc = "MIPS Malta Core LV";
1293 mc->init = mips_malta_init;
1294 mc->block_default_type = IF_IDE;
1295 mc->max_cpus = 16;
1296 mc->is_default = true;
1297 #ifdef TARGET_MIPS64
1298 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("20Kc");
1299 #else
1300 mc->default_cpu_type = MIPS_CPU_TYPE_NAME("24Kf");
1301 #endif
1302 mc->default_ram_id = "mips_malta.ram";
1303 compat_props_add(mc->compat_props, malta_compat, malta_compat_len);
1304 }
1305
1306 DEFINE_MACHINE("malta", mips_malta_machine_init)
1307
mips_malta_register_types(void)1308 static void mips_malta_register_types(void)
1309 {
1310 type_register_static(&mips_malta_device);
1311 }
1312
1313 type_init(mips_malta_register_types)
1314