1// DO NOT EDIT 2// generated by: ppc64map -fmt=decoder ../pp64.csv 3 4package ppc64asm 5 6const ( 7 _ Op = iota 8 CNTLZW 9 CNTLZW_ 10 B 11 BA 12 BL 13 BLA 14 BC 15 BCA 16 BCL 17 BCLA 18 BCLR 19 BCLRL 20 BCCTR 21 BCCTRL 22 BCTAR 23 BCTARL 24 CRAND 25 CROR 26 CRNAND 27 CRXOR 28 CRNOR 29 CRANDC 30 MCRF 31 CREQV 32 CRORC 33 SC 34 CLRBHRB 35 MFBHRBE 36 LBZ 37 LBZU 38 LBZX 39 LBZUX 40 LHZ 41 LHZU 42 LHZX 43 LHZUX 44 LHA 45 LHAU 46 LHAX 47 LHAUX 48 LWZ 49 LWZU 50 LWZX 51 LWZUX 52 LWA 53 LWAX 54 LWAUX 55 LD 56 LDU 57 LDX 58 LDUX 59 STB 60 STBU 61 STBX 62 STBUX 63 STH 64 STHU 65 STHX 66 STHUX 67 STW 68 STWU 69 STWX 70 STWUX 71 STD 72 STDU 73 STDX 74 STDUX 75 LQ 76 STQ 77 LHBRX 78 LWBRX 79 STHBRX 80 STWBRX 81 LDBRX 82 STDBRX 83 LMW 84 STMW 85 LSWI 86 LSWX 87 STSWI 88 STSWX 89 LI 90 ADDI 91 LIS 92 ADDIS 93 ADD 94 ADD_ 95 ADDO 96 ADDO_ 97 ADDIC 98 SUBF 99 SUBF_ 100 SUBFO 101 SUBFO_ 102 ADDIC_ 103 SUBFIC 104 ADDC 105 ADDC_ 106 ADDCO 107 ADDCO_ 108 SUBFC 109 SUBFC_ 110 SUBFCO 111 SUBFCO_ 112 ADDE 113 ADDE_ 114 ADDEO 115 ADDEO_ 116 ADDME 117 ADDME_ 118 ADDMEO 119 ADDMEO_ 120 SUBFE 121 SUBFE_ 122 SUBFEO 123 SUBFEO_ 124 SUBFME 125 SUBFME_ 126 SUBFMEO 127 SUBFMEO_ 128 ADDZE 129 ADDZE_ 130 ADDZEO 131 ADDZEO_ 132 SUBFZE 133 SUBFZE_ 134 SUBFZEO 135 SUBFZEO_ 136 NEG 137 NEG_ 138 NEGO 139 NEGO_ 140 MULLI 141 MULLW 142 MULLW_ 143 MULLWO 144 MULLWO_ 145 MULHW 146 MULHW_ 147 MULHWU 148 MULHWU_ 149 DIVW 150 DIVW_ 151 DIVWO 152 DIVWO_ 153 DIVWU 154 DIVWU_ 155 DIVWUO 156 DIVWUO_ 157 DIVWE 158 DIVWE_ 159 DIVWEO 160 DIVWEO_ 161 DIVWEU 162 DIVWEU_ 163 DIVWEUO 164 DIVWEUO_ 165 MULLD 166 MULLD_ 167 MULLDO 168 MULLDO_ 169 MULHDU 170 MULHDU_ 171 MULHD 172 MULHD_ 173 DIVD 174 DIVD_ 175 DIVDO 176 DIVDO_ 177 DIVDU 178 DIVDU_ 179 DIVDUO 180 DIVDUO_ 181 DIVDE 182 DIVDE_ 183 DIVDEO 184 DIVDEO_ 185 DIVDEU 186 DIVDEU_ 187 DIVDEUO 188 DIVDEUO_ 189 CMPWI 190 CMPDI 191 CMPW 192 CMPD 193 CMPLWI 194 CMPLDI 195 CMPLW 196 CMPLD 197 TWI 198 TW 199 TDI 200 ISEL 201 TD 202 ANDI_ 203 ANDIS_ 204 ORI 205 ORIS 206 XORI 207 XORIS 208 AND 209 AND_ 210 XOR 211 XOR_ 212 NAND 213 NAND_ 214 OR 215 OR_ 216 NOR 217 NOR_ 218 ANDC 219 ANDC_ 220 EXTSB 221 EXTSB_ 222 EQV 223 EQV_ 224 ORC 225 ORC_ 226 EXTSH 227 EXTSH_ 228 CMPB 229 POPCNTB 230 POPCNTW 231 PRTYD 232 PRTYW 233 EXTSW 234 EXTSW_ 235 CNTLZD 236 CNTLZD_ 237 POPCNTD 238 BPERMD 239 RLWINM 240 RLWINM_ 241 RLWNM 242 RLWNM_ 243 RLWIMI 244 RLWIMI_ 245 RLDICL 246 RLDICL_ 247 RLDICR 248 RLDICR_ 249 RLDIC 250 RLDIC_ 251 RLDCL 252 RLDCL_ 253 RLDCR 254 RLDCR_ 255 RLDIMI 256 RLDIMI_ 257 SLW 258 SLW_ 259 SRW 260 SRW_ 261 SRAWI 262 SRAWI_ 263 SRAW 264 SRAW_ 265 SLD 266 SLD_ 267 SRD 268 SRD_ 269 SRADI 270 SRADI_ 271 SRAD 272 SRAD_ 273 CDTBCD 274 CBCDTD 275 ADDG6S 276 MTSPR 277 MFSPR 278 MTCRF 279 MFCR 280 MTSLE 281 MFVSRD 282 MFVSRWZ 283 MTVSRD 284 MTVSRWA 285 MTVSRWZ 286 MTOCRF 287 MFOCRF 288 MCRXR 289 MTDCRUX 290 MFDCRUX 291 LFS 292 LFSU 293 LFSX 294 LFSUX 295 LFD 296 LFDU 297 LFDX 298 LFDUX 299 LFIWAX 300 LFIWZX 301 STFS 302 STFSU 303 STFSX 304 STFSUX 305 STFD 306 STFDU 307 STFDX 308 STFDUX 309 STFIWX 310 LFDP 311 LFDPX 312 STFDP 313 STFDPX 314 FMR 315 FMR_ 316 FABS 317 FABS_ 318 FNABS 319 FNABS_ 320 FNEG 321 FNEG_ 322 FCPSGN 323 FCPSGN_ 324 FMRGEW 325 FMRGOW 326 FADD 327 FADD_ 328 FADDS 329 FADDS_ 330 FSUB 331 FSUB_ 332 FSUBS 333 FSUBS_ 334 FMUL 335 FMUL_ 336 FMULS 337 FMULS_ 338 FDIV 339 FDIV_ 340 FDIVS 341 FDIVS_ 342 FSQRT 343 FSQRT_ 344 FSQRTS 345 FSQRTS_ 346 FRE 347 FRE_ 348 FRES 349 FRES_ 350 FRSQRTE 351 FRSQRTE_ 352 FRSQRTES 353 FRSQRTES_ 354 FTDIV 355 FTSQRT 356 FMADD 357 FMADD_ 358 FMADDS 359 FMADDS_ 360 FMSUB 361 FMSUB_ 362 FMSUBS 363 FMSUBS_ 364 FNMADD 365 FNMADD_ 366 FNMADDS 367 FNMADDS_ 368 FNMSUB 369 FNMSUB_ 370 FNMSUBS 371 FNMSUBS_ 372 FRSP 373 FRSP_ 374 FCTID 375 FCTID_ 376 FCTIDZ 377 FCTIDZ_ 378 FCTIDU 379 FCTIDU_ 380 FCTIDUZ 381 FCTIDUZ_ 382 FCTIW 383 FCTIW_ 384 FCTIWZ 385 FCTIWZ_ 386 FCTIWU 387 FCTIWU_ 388 FCTIWUZ 389 FCTIWUZ_ 390 FCFID 391 FCFID_ 392 FCFIDU 393 FCFIDU_ 394 FCFIDS 395 FCFIDS_ 396 FCFIDUS 397 FCFIDUS_ 398 FRIN 399 FRIN_ 400 FRIZ 401 FRIZ_ 402 FRIP 403 FRIP_ 404 FRIM 405 FRIM_ 406 FCMPU 407 FCMPO 408 FSEL 409 FSEL_ 410 MFFS 411 MFFS_ 412 MCRFS 413 MTFSFI 414 MTFSFI_ 415 MTFSF 416 MTFSF_ 417 MTFSB0 418 MTFSB0_ 419 MTFSB1 420 MTFSB1_ 421 LVEBX 422 LVEHX 423 LVEWX 424 LVX 425 LVXL 426 STVEBX 427 STVEHX 428 STVEWX 429 STVX 430 STVXL 431 LVSL 432 LVSR 433 VPKPX 434 VPKSDSS 435 VPKSDUS 436 VPKSHSS 437 VPKSHUS 438 VPKSWSS 439 VPKSWUS 440 VPKUDUM 441 VPKUDUS 442 VPKUHUM 443 VPKUHUS 444 VPKUWUM 445 VPKUWUS 446 VUPKHPX 447 VUPKLPX 448 VUPKHSB 449 VUPKHSH 450 VUPKHSW 451 VUPKLSB 452 VUPKLSH 453 VUPKLSW 454 VMRGHB 455 VMRGHH 456 VMRGLB 457 VMRGLH 458 VMRGHW 459 VMRGLW 460 VMRGEW 461 VMRGOW 462 VSPLTB 463 VSPLTH 464 VSPLTW 465 VSPLTISB 466 VSPLTISH 467 VSPLTISW 468 VPERM 469 VSEL 470 VSL 471 VSLDOI 472 VSLO 473 VSR 474 VSRO 475 VADDCUW 476 VADDSBS 477 VADDSHS 478 VADDSWS 479 VADDUBM 480 VADDUDM 481 VADDUHM 482 VADDUWM 483 VADDUBS 484 VADDUHS 485 VADDUWS 486 VADDUQM 487 VADDEUQM 488 VADDCUQ 489 VADDECUQ 490 VSUBCUW 491 VSUBSBS 492 VSUBSHS 493 VSUBSWS 494 VSUBUBM 495 VSUBUDM 496 VSUBUHM 497 VSUBUWM 498 VSUBUBS 499 VSUBUHS 500 VSUBUWS 501 VSUBUQM 502 VSUBEUQM 503 VSUBCUQ 504 VSUBECUQ 505 VMULESB 506 VMULEUB 507 VMULOSB 508 VMULOUB 509 VMULESH 510 VMULEUH 511 VMULOSH 512 VMULOUH 513 VMULESW 514 VMULEUW 515 VMULOSW 516 VMULOUW 517 VMULUWM 518 VMHADDSHS 519 VMHRADDSHS 520 VMLADDUHM 521 VMSUMUBM 522 VMSUMMBM 523 VMSUMSHM 524 VMSUMSHS 525 VMSUMUHM 526 VMSUMUHS 527 VSUMSWS 528 VSUM2SWS 529 VSUM4SBS 530 VSUM4SHS 531 VSUM4UBS 532 VAVGSB 533 VAVGSH 534 VAVGSW 535 VAVGUB 536 VAVGUW 537 VAVGUH 538 VMAXSB 539 VMAXSD 540 VMAXUB 541 VMAXUD 542 VMAXSH 543 VMAXSW 544 VMAXUH 545 VMAXUW 546 VMINSB 547 VMINSD 548 VMINUB 549 VMINUD 550 VMINSH 551 VMINSW 552 VMINUH 553 VMINUW 554 VCMPEQUB 555 VCMPEQUB_ 556 VCMPEQUH 557 VCMPEQUH_ 558 VCMPEQUW 559 VCMPEQUW_ 560 VCMPEQUD 561 VCMPEQUD_ 562 VCMPGTSB 563 VCMPGTSB_ 564 VCMPGTSD 565 VCMPGTSD_ 566 VCMPGTSH 567 VCMPGTSH_ 568 VCMPGTSW 569 VCMPGTSW_ 570 VCMPGTUB 571 VCMPGTUB_ 572 VCMPGTUD 573 VCMPGTUD_ 574 VCMPGTUH 575 VCMPGTUH_ 576 VCMPGTUW 577 VCMPGTUW_ 578 VAND 579 VANDC 580 VEQV 581 VNAND 582 VORC 583 VNOR 584 VOR 585 VXOR 586 VRLB 587 VRLH 588 VRLW 589 VRLD 590 VSLB 591 VSLH 592 VSLW 593 VSLD 594 VSRB 595 VSRH 596 VSRW 597 VSRD 598 VSRAB 599 VSRAH 600 VSRAW 601 VSRAD 602 VADDFP 603 VSUBFP 604 VMADDFP 605 VNMSUBFP 606 VMAXFP 607 VMINFP 608 VCTSXS 609 VCTUXS 610 VCFSX 611 VCFUX 612 VRFIM 613 VRFIN 614 VRFIP 615 VRFIZ 616 VCMPBFP 617 VCMPBFP_ 618 VCMPEQFP 619 VCMPEQFP_ 620 VCMPGEFP 621 VCMPGEFP_ 622 VCMPGTFP 623 VCMPGTFP_ 624 VEXPTEFP 625 VLOGEFP 626 VREFP 627 VRSQRTEFP 628 VCIPHER 629 VCIPHERLAST 630 VNCIPHER 631 VNCIPHERLAST 632 VSBOX 633 VSHASIGMAD 634 VSHASIGMAW 635 VPMSUMB 636 VPMSUMD 637 VPMSUMH 638 VPMSUMW 639 VPERMXOR 640 VGBBD 641 VCLZB 642 VCLZH 643 VCLZW 644 VCLZD 645 VPOPCNTB 646 VPOPCNTD 647 VPOPCNTH 648 VPOPCNTW 649 VBPERMQ 650 BCDADD_ 651 BCDSUB_ 652 MTVSCR 653 MFVSCR 654 DADD 655 DADD_ 656 DSUB 657 DSUB_ 658 DMUL 659 DMUL_ 660 DDIV 661 DDIV_ 662 DCMPU 663 DCMPO 664 DTSTDC 665 DTSTDG 666 DTSTEX 667 DTSTSF 668 DQUAI 669 DQUAI_ 670 DQUA 671 DQUA_ 672 DRRND 673 DRRND_ 674 DRINTX 675 DRINTX_ 676 DRINTN 677 DRINTN_ 678 DCTDP 679 DCTDP_ 680 DCTQPQ 681 DCTQPQ_ 682 DRSP 683 DRSP_ 684 DRDPQ 685 DRDPQ_ 686 DCFFIX 687 DCFFIX_ 688 DCFFIXQ 689 DCFFIXQ_ 690 DCTFIX 691 DCTFIX_ 692 DDEDPD 693 DDEDPD_ 694 DENBCD 695 DENBCD_ 696 DXEX 697 DXEX_ 698 DIEX 699 DIEX_ 700 DSCLI 701 DSCLI_ 702 DSCRI 703 DSCRI_ 704 LXSDX 705 LXSIWAX 706 LXSIWZX 707 LXSSPX 708 LXVD2X 709 LXVDSX 710 LXVW4X 711 STXSDX 712 STXSIWX 713 STXSSPX 714 STXVD2X 715 STXVW4X 716 XSABSDP 717 XSADDDP 718 XSADDSP 719 XSCMPODP 720 XSCMPUDP 721 XSCPSGNDP 722 XSCVDPSP 723 XSCVDPSPN 724 XSCVDPSXDS 725 XSCVDPSXWS 726 XSCVDPUXDS 727 XSCVDPUXWS 728 XSCVSPDP 729 XSCVSPDPN 730 XSCVSXDDP 731 XSCVSXDSP 732 XSCVUXDDP 733 XSCVUXDSP 734 XSDIVDP 735 XSDIVSP 736 XSMADDADP 737 XSMADDASP 738 XSMAXDP 739 XSMINDP 740 XSMSUBADP 741 XSMSUBASP 742 XSMULDP 743 XSMULSP 744 XSNABSDP 745 XSNEGDP 746 XSNMADDADP 747 XSNMADDASP 748 XSNMSUBADP 749 XSNMSUBASP 750 XSRDPI 751 XSRDPIC 752 XSRDPIM 753 XSRDPIP 754 XSRDPIZ 755 XSREDP 756 XSRESP 757 XSRSP 758 XSRSQRTEDP 759 XSRSQRTESP 760 XSSQRTDP 761 XSSQRTSP 762 XSSUBDP 763 XSSUBSP 764 XSTDIVDP 765 XSTSQRTDP 766 XVABSDP 767 XVABSSP 768 XVADDDP 769 XVADDSP 770 XVCMPEQDP 771 XVCMPEQDP_ 772 XVCMPEQSP 773 XVCMPEQSP_ 774 XVCMPGEDP 775 XVCMPGEDP_ 776 XVCMPGESP 777 XVCMPGESP_ 778 XVCMPGTDP 779 XVCMPGTDP_ 780 XVCMPGTSP 781 XVCMPGTSP_ 782 XVCPSGNDP 783 XVCPSGNSP 784 XVCVDPSP 785 XVCVDPSXDS 786 XVCVDPSXWS 787 XVCVDPUXDS 788 XVCVDPUXWS 789 XVCVSPDP 790 XVCVSPSXDS 791 XVCVSPSXWS 792 XVCVSPUXDS 793 XVCVSPUXWS 794 XVCVSXDDP 795 XVCVSXDSP 796 XVCVSXWDP 797 XVCVSXWSP 798 XVCVUXDDP 799 XVCVUXDSP 800 XVCVUXWDP 801 XVCVUXWSP 802 XVDIVDP 803 XVDIVSP 804 XVMADDADP 805 XVMADDASP 806 XVMAXDP 807 XVMAXSP 808 XVMINDP 809 XVMINSP 810 XVMSUBADP 811 XVMSUBASP 812 XVMULDP 813 XVMULSP 814 XVNABSDP 815 XVNABSSP 816 XVNEGDP 817 XVNEGSP 818 XVNMADDADP 819 XVNMADDASP 820 XVNMSUBADP 821 XVNMSUBASP 822 XVRDPI 823 XVRDPIC 824 XVRDPIM 825 XVRDPIP 826 XVRDPIZ 827 XVREDP 828 XVRESP 829 XVRSPI 830 XVRSPIC 831 XVRSPIM 832 XVRSPIP 833 XVRSPIZ 834 XVRSQRTEDP 835 XVRSQRTESP 836 XVSQRTDP 837 XVSQRTSP 838 XVSUBDP 839 XVSUBSP 840 XVTDIVDP 841 XVTDIVSP 842 XVTSQRTDP 843 XVTSQRTSP 844 XXLAND 845 XXLANDC 846 XXLEQV 847 XXLNAND 848 XXLORC 849 XXLNOR 850 XXLOR 851 XXLXOR 852 XXMRGHW 853 XXMRGLW 854 XXPERMDI 855 XXSEL 856 XXSLDWI 857 XXSPLTW 858 BRINC 859 EVABS 860 EVADDIW 861 EVADDSMIAAW 862 EVADDSSIAAW 863 EVADDUMIAAW 864 EVADDUSIAAW 865 EVADDW 866 EVAND 867 EVCMPEQ 868 EVANDC 869 EVCMPGTS 870 EVCMPGTU 871 EVCMPLTU 872 EVCMPLTS 873 EVCNTLSW 874 EVCNTLZW 875 EVDIVWS 876 EVDIVWU 877 EVEQV 878 EVEXTSB 879 EVEXTSH 880 EVLDD 881 EVLDH 882 EVLDDX 883 EVLDHX 884 EVLDW 885 EVLHHESPLAT 886 EVLDWX 887 EVLHHESPLATX 888 EVLHHOSSPLAT 889 EVLHHOUSPLAT 890 EVLHHOSSPLATX 891 EVLHHOUSPLATX 892 EVLWHE 893 EVLWHOS 894 EVLWHEX 895 EVLWHOSX 896 EVLWHOU 897 EVLWHSPLAT 898 EVLWHOUX 899 EVLWHSPLATX 900 EVLWWSPLAT 901 EVMERGEHI 902 EVLWWSPLATX 903 EVMERGELO 904 EVMERGEHILO 905 EVMHEGSMFAA 906 EVMERGELOHI 907 EVMHEGSMFAN 908 EVMHEGSMIAA 909 EVMHEGUMIAA 910 EVMHEGSMIAN 911 EVMHEGUMIAN 912 EVMHESMF 913 EVMHESMFAAW 914 EVMHESMFA 915 EVMHESMFANW 916 EVMHESMI 917 EVMHESMIAAW 918 EVMHESMIA 919 EVMHESMIANW 920 EVMHESSF 921 EVMHESSFA 922 EVMHESSFAAW 923 EVMHESSFANW 924 EVMHESSIAAW 925 EVMHESSIANW 926 EVMHEUMI 927 EVMHEUMIAAW 928 EVMHEUMIA 929 EVMHEUMIANW 930 EVMHEUSIAAW 931 EVMHEUSIANW 932 EVMHOGSMFAA 933 EVMHOGSMIAA 934 EVMHOGSMFAN 935 EVMHOGSMIAN 936 EVMHOGUMIAA 937 EVMHOSMF 938 EVMHOGUMIAN 939 EVMHOSMFA 940 EVMHOSMFAAW 941 EVMHOSMI 942 EVMHOSMFANW 943 EVMHOSMIA 944 EVMHOSMIAAW 945 EVMHOSMIANW 946 EVMHOSSF 947 EVMHOSSFA 948 EVMHOSSFAAW 949 EVMHOSSFANW 950 EVMHOSSIAAW 951 EVMHOUMI 952 EVMHOSSIANW 953 EVMHOUMIA 954 EVMHOUMIAAW 955 EVMHOUSIAAW 956 EVMHOUMIANW 957 EVMHOUSIANW 958 EVMRA 959 EVMWHSMF 960 EVMWHSMI 961 EVMWHSMFA 962 EVMWHSMIA 963 EVMWHSSF 964 EVMWHUMI 965 EVMWHSSFA 966 EVMWHUMIA 967 EVMWLSMIAAW 968 EVMWLSSIAAW 969 EVMWLSMIANW 970 EVMWLSSIANW 971 EVMWLUMI 972 EVMWLUMIAAW 973 EVMWLUMIA 974 EVMWLUMIANW 975 EVMWLUSIAAW 976 EVMWSMF 977 EVMWLUSIANW 978 EVMWSMFA 979 EVMWSMFAA 980 EVMWSMI 981 EVMWSMIAA 982 EVMWSMFAN 983 EVMWSMIA 984 EVMWSMIAN 985 EVMWSSF 986 EVMWSSFA 987 EVMWSSFAA 988 EVMWUMI 989 EVMWSSFAN 990 EVMWUMIA 991 EVMWUMIAA 992 EVNAND 993 EVMWUMIAN 994 EVNEG 995 EVNOR 996 EVORC 997 EVOR 998 EVRLW 999 EVRLWI 1000 EVSEL 1001 EVRNDW 1002 EVSLW 1003 EVSPLATFI 1004 EVSRWIS 1005 EVSLWI 1006 EVSPLATI 1007 EVSRWIU 1008 EVSRWS 1009 EVSTDD 1010 EVSRWU 1011 EVSTDDX 1012 EVSTDH 1013 EVSTDW 1014 EVSTDHX 1015 EVSTDWX 1016 EVSTWHE 1017 EVSTWHO 1018 EVSTWWE 1019 EVSTWHEX 1020 EVSTWHOX 1021 EVSTWWEX 1022 EVSTWWO 1023 EVSUBFSMIAAW 1024 EVSTWWOX 1025 EVSUBFSSIAAW 1026 EVSUBFUMIAAW 1027 EVSUBFUSIAAW 1028 EVSUBFW 1029 EVSUBIFW 1030 EVXOR 1031 EVFSABS 1032 EVFSNABS 1033 EVFSNEG 1034 EVFSADD 1035 EVFSMUL 1036 EVFSSUB 1037 EVFSDIV 1038 EVFSCMPGT 1039 EVFSCMPLT 1040 EVFSCMPEQ 1041 EVFSTSTGT 1042 EVFSTSTLT 1043 EVFSTSTEQ 1044 EVFSCFSI 1045 EVFSCFSF 1046 EVFSCFUI 1047 EVFSCFUF 1048 EVFSCTSI 1049 EVFSCTUI 1050 EVFSCTSIZ 1051 EVFSCTUIZ 1052 EVFSCTSF 1053 EVFSCTUF 1054 EFSABS 1055 EFSNEG 1056 EFSNABS 1057 EFSADD 1058 EFSMUL 1059 EFSSUB 1060 EFSDIV 1061 EFSCMPGT 1062 EFSCMPLT 1063 EFSCMPEQ 1064 EFSTSTGT 1065 EFSTSTLT 1066 EFSTSTEQ 1067 EFSCFSI 1068 EFSCFSF 1069 EFSCTSI 1070 EFSCFUI 1071 EFSCFUF 1072 EFSCTUI 1073 EFSCTSIZ 1074 EFSCTSF 1075 EFSCTUIZ 1076 EFSCTUF 1077 EFDABS 1078 EFDNEG 1079 EFDNABS 1080 EFDADD 1081 EFDMUL 1082 EFDSUB 1083 EFDDIV 1084 EFDCMPGT 1085 EFDCMPEQ 1086 EFDCMPLT 1087 EFDTSTGT 1088 EFDTSTLT 1089 EFDCFSI 1090 EFDTSTEQ 1091 EFDCFUI 1092 EFDCFSID 1093 EFDCFSF 1094 EFDCFUF 1095 EFDCFUID 1096 EFDCTSI 1097 EFDCTUI 1098 EFDCTSIDZ 1099 EFDCTUIDZ 1100 EFDCTSIZ 1101 EFDCTSF 1102 EFDCTUF 1103 EFDCTUIZ 1104 EFDCFS 1105 EFSCFD 1106 DLMZB 1107 DLMZB_ 1108 MACCHW 1109 MACCHW_ 1110 MACCHWO 1111 MACCHWO_ 1112 MACCHWS 1113 MACCHWS_ 1114 MACCHWSO 1115 MACCHWSO_ 1116 MACCHWU 1117 MACCHWU_ 1118 MACCHWUO 1119 MACCHWUO_ 1120 MACCHWSU 1121 MACCHWSU_ 1122 MACCHWSUO 1123 MACCHWSUO_ 1124 MACHHW 1125 MACHHW_ 1126 MACHHWO 1127 MACHHWO_ 1128 MACHHWS 1129 MACHHWS_ 1130 MACHHWSO 1131 MACHHWSO_ 1132 MACHHWU 1133 MACHHWU_ 1134 MACHHWUO 1135 MACHHWUO_ 1136 MACHHWSU 1137 MACHHWSU_ 1138 MACHHWSUO 1139 MACHHWSUO_ 1140 MACLHW 1141 MACLHW_ 1142 MACLHWO 1143 MACLHWO_ 1144 MACLHWS 1145 MACLHWS_ 1146 MACLHWSO 1147 MACLHWSO_ 1148 MACLHWU 1149 MACLHWU_ 1150 MACLHWUO 1151 MACLHWUO_ 1152 MULCHW 1153 MULCHW_ 1154 MACLHWSU 1155 MACLHWSU_ 1156 MACLHWSUO 1157 MACLHWSUO_ 1158 MULCHWU 1159 MULCHWU_ 1160 MULHHW 1161 MULHHW_ 1162 MULLHW 1163 MULLHW_ 1164 MULHHWU 1165 MULHHWU_ 1166 MULLHWU 1167 MULLHWU_ 1168 NMACCHW 1169 NMACCHW_ 1170 NMACCHWO 1171 NMACCHWO_ 1172 NMACCHWS 1173 NMACCHWS_ 1174 NMACCHWSO 1175 NMACCHWSO_ 1176 NMACHHW 1177 NMACHHW_ 1178 NMACHHWO 1179 NMACHHWO_ 1180 NMACHHWS 1181 NMACHHWS_ 1182 NMACHHWSO 1183 NMACHHWSO_ 1184 NMACLHW 1185 NMACLHW_ 1186 NMACLHWO 1187 NMACLHWO_ 1188 NMACLHWS 1189 NMACLHWS_ 1190 NMACLHWSO 1191 NMACLHWSO_ 1192 ICBI 1193 ICBT 1194 DCBA 1195 DCBT 1196 DCBTST 1197 DCBZ 1198 DCBST 1199 DCBF 1200 ISYNC 1201 LBARX 1202 LHARX 1203 LWARX 1204 STBCX_ 1205 STHCX_ 1206 STWCX_ 1207 LDARX 1208 STDCX_ 1209 LQARX 1210 STQCX_ 1211 SYNC 1212 EIEIO 1213 MBAR 1214 WAIT 1215 TBEGIN_ 1216 TEND_ 1217 TABORT_ 1218 TABORTWC_ 1219 TABORTWCI_ 1220 TABORTDC_ 1221 TABORTDCI_ 1222 TSR_ 1223 TCHECK 1224 MFTB 1225 RFEBB 1226 LBDX 1227 LHDX 1228 LWDX 1229 LDDX 1230 LFDDX 1231 STBDX 1232 STHDX 1233 STWDX 1234 STDDX 1235 STFDDX 1236 DSN 1237 ECIWX 1238 ECOWX 1239 RFID 1240 HRFID 1241 DOZE 1242 NAP 1243 SLEEP 1244 RVWINKLE 1245 LBZCIX 1246 LWZCIX 1247 LHZCIX 1248 LDCIX 1249 STBCIX 1250 STWCIX 1251 STHCIX 1252 STDCIX 1253 TRECLAIM_ 1254 TRECHKPT_ 1255 MTMSR 1256 MTMSRD 1257 MFMSR 1258 SLBIE 1259 SLBIA 1260 SLBMTE 1261 SLBMFEV 1262 SLBMFEE 1263 SLBFEE_ 1264 MTSR 1265 MTSRIN 1266 MFSR 1267 MFSRIN 1268 TLBIE 1269 TLBIEL 1270 TLBIA 1271 TLBSYNC 1272 MSGSND 1273 MSGCLR 1274 MSGSNDP 1275 MSGCLRP 1276 MTTMR 1277 RFI 1278 RFCI 1279 RFDI 1280 RFMCI 1281 RFGI 1282 EHPRIV 1283 MTDCR 1284 MTDCRX 1285 MFDCR 1286 MFDCRX 1287 WRTEE 1288 WRTEEI 1289 LBEPX 1290 LHEPX 1291 LWEPX 1292 LDEPX 1293 STBEPX 1294 STHEPX 1295 STWEPX 1296 STDEPX 1297 DCBSTEP 1298 DCBTEP 1299 DCBFEP 1300 DCBTSTEP 1301 ICBIEP 1302 DCBZEP 1303 LFDEPX 1304 STFDEPX 1305 EVLDDEPX 1306 EVSTDDEPX 1307 LVEPX 1308 LVEPXL 1309 STVEPX 1310 STVEPXL 1311 DCBI 1312 DCBLQ_ 1313 ICBLQ_ 1314 DCBTLS 1315 DCBTSTLS 1316 ICBTLS 1317 ICBLC 1318 DCBLC 1319 TLBIVAX 1320 TLBILX 1321 TLBSX 1322 TLBSRX_ 1323 TLBRE 1324 TLBWE 1325 DNH 1326 DCI 1327 ICI 1328 DCREAD 1329 ICREAD 1330 MFPMR 1331 MTPMR 1332) 1333 1334var opstr = [...]string{ 1335 CNTLZW: "cntlzw", 1336 CNTLZW_: "cntlzw.", 1337 B: "b", 1338 BA: "ba", 1339 BL: "bl", 1340 BLA: "bla", 1341 BC: "bc", 1342 BCA: "bca", 1343 BCL: "bcl", 1344 BCLA: "bcla", 1345 BCLR: "bclr", 1346 BCLRL: "bclrl", 1347 BCCTR: "bcctr", 1348 BCCTRL: "bcctrl", 1349 BCTAR: "bctar", 1350 BCTARL: "bctarl", 1351 CRAND: "crand", 1352 CROR: "cror", 1353 CRNAND: "crnand", 1354 CRXOR: "crxor", 1355 CRNOR: "crnor", 1356 CRANDC: "crandc", 1357 MCRF: "mcrf", 1358 CREQV: "creqv", 1359 CRORC: "crorc", 1360 SC: "sc", 1361 CLRBHRB: "clrbhrb", 1362 MFBHRBE: "mfbhrbe", 1363 LBZ: "lbz", 1364 LBZU: "lbzu", 1365 LBZX: "lbzx", 1366 LBZUX: "lbzux", 1367 LHZ: "lhz", 1368 LHZU: "lhzu", 1369 LHZX: "lhzx", 1370 LHZUX: "lhzux", 1371 LHA: "lha", 1372 LHAU: "lhau", 1373 LHAX: "lhax", 1374 LHAUX: "lhaux", 1375 LWZ: "lwz", 1376 LWZU: "lwzu", 1377 LWZX: "lwzx", 1378 LWZUX: "lwzux", 1379 LWA: "lwa", 1380 LWAX: "lwax", 1381 LWAUX: "lwaux", 1382 LD: "ld", 1383 LDU: "ldu", 1384 LDX: "ldx", 1385 LDUX: "ldux", 1386 STB: "stb", 1387 STBU: "stbu", 1388 STBX: "stbx", 1389 STBUX: "stbux", 1390 STH: "sth", 1391 STHU: "sthu", 1392 STHX: "sthx", 1393 STHUX: "sthux", 1394 STW: "stw", 1395 STWU: "stwu", 1396 STWX: "stwx", 1397 STWUX: "stwux", 1398 STD: "std", 1399 STDU: "stdu", 1400 STDX: "stdx", 1401 STDUX: "stdux", 1402 LQ: "lq", 1403 STQ: "stq", 1404 LHBRX: "lhbrx", 1405 LWBRX: "lwbrx", 1406 STHBRX: "sthbrx", 1407 STWBRX: "stwbrx", 1408 LDBRX: "ldbrx", 1409 STDBRX: "stdbrx", 1410 LMW: "lmw", 1411 STMW: "stmw", 1412 LSWI: "lswi", 1413 LSWX: "lswx", 1414 STSWI: "stswi", 1415 STSWX: "stswx", 1416 LI: "li", 1417 ADDI: "addi", 1418 LIS: "lis", 1419 ADDIS: "addis", 1420 ADD: "add", 1421 ADD_: "add.", 1422 ADDO: "addo", 1423 ADDO_: "addo.", 1424 ADDIC: "addic", 1425 SUBF: "subf", 1426 SUBF_: "subf.", 1427 SUBFO: "subfo", 1428 SUBFO_: "subfo.", 1429 ADDIC_: "addic.", 1430 SUBFIC: "subfic", 1431 ADDC: "addc", 1432 ADDC_: "addc.", 1433 ADDCO: "addco", 1434 ADDCO_: "addco.", 1435 SUBFC: "subfc", 1436 SUBFC_: "subfc.", 1437 SUBFCO: "subfco", 1438 SUBFCO_: "subfco.", 1439 ADDE: "adde", 1440 ADDE_: "adde.", 1441 ADDEO: "addeo", 1442 ADDEO_: "addeo.", 1443 ADDME: "addme", 1444 ADDME_: "addme.", 1445 ADDMEO: "addmeo", 1446 ADDMEO_: "addmeo.", 1447 SUBFE: "subfe", 1448 SUBFE_: "subfe.", 1449 SUBFEO: "subfeo", 1450 SUBFEO_: "subfeo.", 1451 SUBFME: "subfme", 1452 SUBFME_: "subfme.", 1453 SUBFMEO: "subfmeo", 1454 SUBFMEO_: "subfmeo.", 1455 ADDZE: "addze", 1456 ADDZE_: "addze.", 1457 ADDZEO: "addzeo", 1458 ADDZEO_: "addzeo.", 1459 SUBFZE: "subfze", 1460 SUBFZE_: "subfze.", 1461 SUBFZEO: "subfzeo", 1462 SUBFZEO_: "subfzeo.", 1463 NEG: "neg", 1464 NEG_: "neg.", 1465 NEGO: "nego", 1466 NEGO_: "nego.", 1467 MULLI: "mulli", 1468 MULLW: "mullw", 1469 MULLW_: "mullw.", 1470 MULLWO: "mullwo", 1471 MULLWO_: "mullwo.", 1472 MULHW: "mulhw", 1473 MULHW_: "mulhw.", 1474 MULHWU: "mulhwu", 1475 MULHWU_: "mulhwu.", 1476 DIVW: "divw", 1477 DIVW_: "divw.", 1478 DIVWO: "divwo", 1479 DIVWO_: "divwo.", 1480 DIVWU: "divwu", 1481 DIVWU_: "divwu.", 1482 DIVWUO: "divwuo", 1483 DIVWUO_: "divwuo.", 1484 DIVWE: "divwe", 1485 DIVWE_: "divwe.", 1486 DIVWEO: "divweo", 1487 DIVWEO_: "divweo.", 1488 DIVWEU: "divweu", 1489 DIVWEU_: "divweu.", 1490 DIVWEUO: "divweuo", 1491 DIVWEUO_: "divweuo.", 1492 MULLD: "mulld", 1493 MULLD_: "mulld.", 1494 MULLDO: "mulldo", 1495 MULLDO_: "mulldo.", 1496 MULHDU: "mulhdu", 1497 MULHDU_: "mulhdu.", 1498 MULHD: "mulhd", 1499 MULHD_: "mulhd.", 1500 DIVD: "divd", 1501 DIVD_: "divd.", 1502 DIVDO: "divdo", 1503 DIVDO_: "divdo.", 1504 DIVDU: "divdu", 1505 DIVDU_: "divdu.", 1506 DIVDUO: "divduo", 1507 DIVDUO_: "divduo.", 1508 DIVDE: "divde", 1509 DIVDE_: "divde.", 1510 DIVDEO: "divdeo", 1511 DIVDEO_: "divdeo.", 1512 DIVDEU: "divdeu", 1513 DIVDEU_: "divdeu.", 1514 DIVDEUO: "divdeuo", 1515 DIVDEUO_: "divdeuo.", 1516 CMPWI: "cmpwi", 1517 CMPDI: "cmpdi", 1518 CMPW: "cmpw", 1519 CMPD: "cmpd", 1520 CMPLWI: "cmplwi", 1521 CMPLDI: "cmpldi", 1522 CMPLW: "cmplw", 1523 CMPLD: "cmpld", 1524 TWI: "twi", 1525 TW: "tw", 1526 TDI: "tdi", 1527 ISEL: "isel", 1528 TD: "td", 1529 ANDI_: "andi.", 1530 ANDIS_: "andis.", 1531 ORI: "ori", 1532 ORIS: "oris", 1533 XORI: "xori", 1534 XORIS: "xoris", 1535 AND: "and", 1536 AND_: "and.", 1537 XOR: "xor", 1538 XOR_: "xor.", 1539 NAND: "nand", 1540 NAND_: "nand.", 1541 OR: "or", 1542 OR_: "or.", 1543 NOR: "nor", 1544 NOR_: "nor.", 1545 ANDC: "andc", 1546 ANDC_: "andc.", 1547 EXTSB: "extsb", 1548 EXTSB_: "extsb.", 1549 EQV: "eqv", 1550 EQV_: "eqv.", 1551 ORC: "orc", 1552 ORC_: "orc.", 1553 EXTSH: "extsh", 1554 EXTSH_: "extsh.", 1555 CMPB: "cmpb", 1556 POPCNTB: "popcntb", 1557 POPCNTW: "popcntw", 1558 PRTYD: "prtyd", 1559 PRTYW: "prtyw", 1560 EXTSW: "extsw", 1561 EXTSW_: "extsw.", 1562 CNTLZD: "cntlzd", 1563 CNTLZD_: "cntlzd.", 1564 POPCNTD: "popcntd", 1565 BPERMD: "bpermd", 1566 RLWINM: "rlwinm", 1567 RLWINM_: "rlwinm.", 1568 RLWNM: "rlwnm", 1569 RLWNM_: "rlwnm.", 1570 RLWIMI: "rlwimi", 1571 RLWIMI_: "rlwimi.", 1572 RLDICL: "rldicl", 1573 RLDICL_: "rldicl.", 1574 RLDICR: "rldicr", 1575 RLDICR_: "rldicr.", 1576 RLDIC: "rldic", 1577 RLDIC_: "rldic.", 1578 RLDCL: "rldcl", 1579 RLDCL_: "rldcl.", 1580 RLDCR: "rldcr", 1581 RLDCR_: "rldcr.", 1582 RLDIMI: "rldimi", 1583 RLDIMI_: "rldimi.", 1584 SLW: "slw", 1585 SLW_: "slw.", 1586 SRW: "srw", 1587 SRW_: "srw.", 1588 SRAWI: "srawi", 1589 SRAWI_: "srawi.", 1590 SRAW: "sraw", 1591 SRAW_: "sraw.", 1592 SLD: "sld", 1593 SLD_: "sld.", 1594 SRD: "srd", 1595 SRD_: "srd.", 1596 SRADI: "sradi", 1597 SRADI_: "sradi.", 1598 SRAD: "srad", 1599 SRAD_: "srad.", 1600 CDTBCD: "cdtbcd", 1601 CBCDTD: "cbcdtd", 1602 ADDG6S: "addg6s", 1603 MTSPR: "mtspr", 1604 MFSPR: "mfspr", 1605 MTCRF: "mtcrf", 1606 MFCR: "mfcr", 1607 MTSLE: "mtsle", 1608 MFVSRD: "mfvsrd", 1609 MFVSRWZ: "mfvsrwz", 1610 MTVSRD: "mtvsrd", 1611 MTVSRWA: "mtvsrwa", 1612 MTVSRWZ: "mtvsrwz", 1613 MTOCRF: "mtocrf", 1614 MFOCRF: "mfocrf", 1615 MCRXR: "mcrxr", 1616 MTDCRUX: "mtdcrux", 1617 MFDCRUX: "mfdcrux", 1618 LFS: "lfs", 1619 LFSU: "lfsu", 1620 LFSX: "lfsx", 1621 LFSUX: "lfsux", 1622 LFD: "lfd", 1623 LFDU: "lfdu", 1624 LFDX: "lfdx", 1625 LFDUX: "lfdux", 1626 LFIWAX: "lfiwax", 1627 LFIWZX: "lfiwzx", 1628 STFS: "stfs", 1629 STFSU: "stfsu", 1630 STFSX: "stfsx", 1631 STFSUX: "stfsux", 1632 STFD: "stfd", 1633 STFDU: "stfdu", 1634 STFDX: "stfdx", 1635 STFDUX: "stfdux", 1636 STFIWX: "stfiwx", 1637 LFDP: "lfdp", 1638 LFDPX: "lfdpx", 1639 STFDP: "stfdp", 1640 STFDPX: "stfdpx", 1641 FMR: "fmr", 1642 FMR_: "fmr.", 1643 FABS: "fabs", 1644 FABS_: "fabs.", 1645 FNABS: "fnabs", 1646 FNABS_: "fnabs.", 1647 FNEG: "fneg", 1648 FNEG_: "fneg.", 1649 FCPSGN: "fcpsgn", 1650 FCPSGN_: "fcpsgn.", 1651 FMRGEW: "fmrgew", 1652 FMRGOW: "fmrgow", 1653 FADD: "fadd", 1654 FADD_: "fadd.", 1655 FADDS: "fadds", 1656 FADDS_: "fadds.", 1657 FSUB: "fsub", 1658 FSUB_: "fsub.", 1659 FSUBS: "fsubs", 1660 FSUBS_: "fsubs.", 1661 FMUL: "fmul", 1662 FMUL_: "fmul.", 1663 FMULS: "fmuls", 1664 FMULS_: "fmuls.", 1665 FDIV: "fdiv", 1666 FDIV_: "fdiv.", 1667 FDIVS: "fdivs", 1668 FDIVS_: "fdivs.", 1669 FSQRT: "fsqrt", 1670 FSQRT_: "fsqrt.", 1671 FSQRTS: "fsqrts", 1672 FSQRTS_: "fsqrts.", 1673 FRE: "fre", 1674 FRE_: "fre.", 1675 FRES: "fres", 1676 FRES_: "fres.", 1677 FRSQRTE: "frsqrte", 1678 FRSQRTE_: "frsqrte.", 1679 FRSQRTES: "frsqrtes", 1680 FRSQRTES_: "frsqrtes.", 1681 FTDIV: "ftdiv", 1682 FTSQRT: "ftsqrt", 1683 FMADD: "fmadd", 1684 FMADD_: "fmadd.", 1685 FMADDS: "fmadds", 1686 FMADDS_: "fmadds.", 1687 FMSUB: "fmsub", 1688 FMSUB_: "fmsub.", 1689 FMSUBS: "fmsubs", 1690 FMSUBS_: "fmsubs.", 1691 FNMADD: "fnmadd", 1692 FNMADD_: "fnmadd.", 1693 FNMADDS: "fnmadds", 1694 FNMADDS_: "fnmadds.", 1695 FNMSUB: "fnmsub", 1696 FNMSUB_: "fnmsub.", 1697 FNMSUBS: "fnmsubs", 1698 FNMSUBS_: "fnmsubs.", 1699 FRSP: "frsp", 1700 FRSP_: "frsp.", 1701 FCTID: "fctid", 1702 FCTID_: "fctid.", 1703 FCTIDZ: "fctidz", 1704 FCTIDZ_: "fctidz.", 1705 FCTIDU: "fctidu", 1706 FCTIDU_: "fctidu.", 1707 FCTIDUZ: "fctiduz", 1708 FCTIDUZ_: "fctiduz.", 1709 FCTIW: "fctiw", 1710 FCTIW_: "fctiw.", 1711 FCTIWZ: "fctiwz", 1712 FCTIWZ_: "fctiwz.", 1713 FCTIWU: "fctiwu", 1714 FCTIWU_: "fctiwu.", 1715 FCTIWUZ: "fctiwuz", 1716 FCTIWUZ_: "fctiwuz.", 1717 FCFID: "fcfid", 1718 FCFID_: "fcfid.", 1719 FCFIDU: "fcfidu", 1720 FCFIDU_: "fcfidu.", 1721 FCFIDS: "fcfids", 1722 FCFIDS_: "fcfids.", 1723 FCFIDUS: "fcfidus", 1724 FCFIDUS_: "fcfidus.", 1725 FRIN: "frin", 1726 FRIN_: "frin.", 1727 FRIZ: "friz", 1728 FRIZ_: "friz.", 1729 FRIP: "frip", 1730 FRIP_: "frip.", 1731 FRIM: "frim", 1732 FRIM_: "frim.", 1733 FCMPU: "fcmpu", 1734 FCMPO: "fcmpo", 1735 FSEL: "fsel", 1736 FSEL_: "fsel.", 1737 MFFS: "mffs", 1738 MFFS_: "mffs.", 1739 MCRFS: "mcrfs", 1740 MTFSFI: "mtfsfi", 1741 MTFSFI_: "mtfsfi.", 1742 MTFSF: "mtfsf", 1743 MTFSF_: "mtfsf.", 1744 MTFSB0: "mtfsb0", 1745 MTFSB0_: "mtfsb0.", 1746 MTFSB1: "mtfsb1", 1747 MTFSB1_: "mtfsb1.", 1748 LVEBX: "lvebx", 1749 LVEHX: "lvehx", 1750 LVEWX: "lvewx", 1751 LVX: "lvx", 1752 LVXL: "lvxl", 1753 STVEBX: "stvebx", 1754 STVEHX: "stvehx", 1755 STVEWX: "stvewx", 1756 STVX: "stvx", 1757 STVXL: "stvxl", 1758 LVSL: "lvsl", 1759 LVSR: "lvsr", 1760 VPKPX: "vpkpx", 1761 VPKSDSS: "vpksdss", 1762 VPKSDUS: "vpksdus", 1763 VPKSHSS: "vpkshss", 1764 VPKSHUS: "vpkshus", 1765 VPKSWSS: "vpkswss", 1766 VPKSWUS: "vpkswus", 1767 VPKUDUM: "vpkudum", 1768 VPKUDUS: "vpkudus", 1769 VPKUHUM: "vpkuhum", 1770 VPKUHUS: "vpkuhus", 1771 VPKUWUM: "vpkuwum", 1772 VPKUWUS: "vpkuwus", 1773 VUPKHPX: "vupkhpx", 1774 VUPKLPX: "vupklpx", 1775 VUPKHSB: "vupkhsb", 1776 VUPKHSH: "vupkhsh", 1777 VUPKHSW: "vupkhsw", 1778 VUPKLSB: "vupklsb", 1779 VUPKLSH: "vupklsh", 1780 VUPKLSW: "vupklsw", 1781 VMRGHB: "vmrghb", 1782 VMRGHH: "vmrghh", 1783 VMRGLB: "vmrglb", 1784 VMRGLH: "vmrglh", 1785 VMRGHW: "vmrghw", 1786 VMRGLW: "vmrglw", 1787 VMRGEW: "vmrgew", 1788 VMRGOW: "vmrgow", 1789 VSPLTB: "vspltb", 1790 VSPLTH: "vsplth", 1791 VSPLTW: "vspltw", 1792 VSPLTISB: "vspltisb", 1793 VSPLTISH: "vspltish", 1794 VSPLTISW: "vspltisw", 1795 VPERM: "vperm", 1796 VSEL: "vsel", 1797 VSL: "vsl", 1798 VSLDOI: "vsldoi", 1799 VSLO: "vslo", 1800 VSR: "vsr", 1801 VSRO: "vsro", 1802 VADDCUW: "vaddcuw", 1803 VADDSBS: "vaddsbs", 1804 VADDSHS: "vaddshs", 1805 VADDSWS: "vaddsws", 1806 VADDUBM: "vaddubm", 1807 VADDUDM: "vaddudm", 1808 VADDUHM: "vadduhm", 1809 VADDUWM: "vadduwm", 1810 VADDUBS: "vaddubs", 1811 VADDUHS: "vadduhs", 1812 VADDUWS: "vadduws", 1813 VADDUQM: "vadduqm", 1814 VADDEUQM: "vaddeuqm", 1815 VADDCUQ: "vaddcuq", 1816 VADDECUQ: "vaddecuq", 1817 VSUBCUW: "vsubcuw", 1818 VSUBSBS: "vsubsbs", 1819 VSUBSHS: "vsubshs", 1820 VSUBSWS: "vsubsws", 1821 VSUBUBM: "vsububm", 1822 VSUBUDM: "vsubudm", 1823 VSUBUHM: "vsubuhm", 1824 VSUBUWM: "vsubuwm", 1825 VSUBUBS: "vsububs", 1826 VSUBUHS: "vsubuhs", 1827 VSUBUWS: "vsubuws", 1828 VSUBUQM: "vsubuqm", 1829 VSUBEUQM: "vsubeuqm", 1830 VSUBCUQ: "vsubcuq", 1831 VSUBECUQ: "vsubecuq", 1832 VMULESB: "vmulesb", 1833 VMULEUB: "vmuleub", 1834 VMULOSB: "vmulosb", 1835 VMULOUB: "vmuloub", 1836 VMULESH: "vmulesh", 1837 VMULEUH: "vmuleuh", 1838 VMULOSH: "vmulosh", 1839 VMULOUH: "vmulouh", 1840 VMULESW: "vmulesw", 1841 VMULEUW: "vmuleuw", 1842 VMULOSW: "vmulosw", 1843 VMULOUW: "vmulouw", 1844 VMULUWM: "vmuluwm", 1845 VMHADDSHS: "vmhaddshs", 1846 VMHRADDSHS: "vmhraddshs", 1847 VMLADDUHM: "vmladduhm", 1848 VMSUMUBM: "vmsumubm", 1849 VMSUMMBM: "vmsummbm", 1850 VMSUMSHM: "vmsumshm", 1851 VMSUMSHS: "vmsumshs", 1852 VMSUMUHM: "vmsumuhm", 1853 VMSUMUHS: "vmsumuhs", 1854 VSUMSWS: "vsumsws", 1855 VSUM2SWS: "vsum2sws", 1856 VSUM4SBS: "vsum4sbs", 1857 VSUM4SHS: "vsum4shs", 1858 VSUM4UBS: "vsum4ubs", 1859 VAVGSB: "vavgsb", 1860 VAVGSH: "vavgsh", 1861 VAVGSW: "vavgsw", 1862 VAVGUB: "vavgub", 1863 VAVGUW: "vavguw", 1864 VAVGUH: "vavguh", 1865 VMAXSB: "vmaxsb", 1866 VMAXSD: "vmaxsd", 1867 VMAXUB: "vmaxub", 1868 VMAXUD: "vmaxud", 1869 VMAXSH: "vmaxsh", 1870 VMAXSW: "vmaxsw", 1871 VMAXUH: "vmaxuh", 1872 VMAXUW: "vmaxuw", 1873 VMINSB: "vminsb", 1874 VMINSD: "vminsd", 1875 VMINUB: "vminub", 1876 VMINUD: "vminud", 1877 VMINSH: "vminsh", 1878 VMINSW: "vminsw", 1879 VMINUH: "vminuh", 1880 VMINUW: "vminuw", 1881 VCMPEQUB: "vcmpequb", 1882 VCMPEQUB_: "vcmpequb.", 1883 VCMPEQUH: "vcmpequh", 1884 VCMPEQUH_: "vcmpequh.", 1885 VCMPEQUW: "vcmpequw", 1886 VCMPEQUW_: "vcmpequw.", 1887 VCMPEQUD: "vcmpequd", 1888 VCMPEQUD_: "vcmpequd.", 1889 VCMPGTSB: "vcmpgtsb", 1890 VCMPGTSB_: "vcmpgtsb.", 1891 VCMPGTSD: "vcmpgtsd", 1892 VCMPGTSD_: "vcmpgtsd.", 1893 VCMPGTSH: "vcmpgtsh", 1894 VCMPGTSH_: "vcmpgtsh.", 1895 VCMPGTSW: "vcmpgtsw", 1896 VCMPGTSW_: "vcmpgtsw.", 1897 VCMPGTUB: "vcmpgtub", 1898 VCMPGTUB_: "vcmpgtub.", 1899 VCMPGTUD: "vcmpgtud", 1900 VCMPGTUD_: "vcmpgtud.", 1901 VCMPGTUH: "vcmpgtuh", 1902 VCMPGTUH_: "vcmpgtuh.", 1903 VCMPGTUW: "vcmpgtuw", 1904 VCMPGTUW_: "vcmpgtuw.", 1905 VAND: "vand", 1906 VANDC: "vandc", 1907 VEQV: "veqv", 1908 VNAND: "vnand", 1909 VORC: "vorc", 1910 VNOR: "vnor", 1911 VOR: "vor", 1912 VXOR: "vxor", 1913 VRLB: "vrlb", 1914 VRLH: "vrlh", 1915 VRLW: "vrlw", 1916 VRLD: "vrld", 1917 VSLB: "vslb", 1918 VSLH: "vslh", 1919 VSLW: "vslw", 1920 VSLD: "vsld", 1921 VSRB: "vsrb", 1922 VSRH: "vsrh", 1923 VSRW: "vsrw", 1924 VSRD: "vsrd", 1925 VSRAB: "vsrab", 1926 VSRAH: "vsrah", 1927 VSRAW: "vsraw", 1928 VSRAD: "vsrad", 1929 VADDFP: "vaddfp", 1930 VSUBFP: "vsubfp", 1931 VMADDFP: "vmaddfp", 1932 VNMSUBFP: "vnmsubfp", 1933 VMAXFP: "vmaxfp", 1934 VMINFP: "vminfp", 1935 VCTSXS: "vctsxs", 1936 VCTUXS: "vctuxs", 1937 VCFSX: "vcfsx", 1938 VCFUX: "vcfux", 1939 VRFIM: "vrfim", 1940 VRFIN: "vrfin", 1941 VRFIP: "vrfip", 1942 VRFIZ: "vrfiz", 1943 VCMPBFP: "vcmpbfp", 1944 VCMPBFP_: "vcmpbfp.", 1945 VCMPEQFP: "vcmpeqfp", 1946 VCMPEQFP_: "vcmpeqfp.", 1947 VCMPGEFP: "vcmpgefp", 1948 VCMPGEFP_: "vcmpgefp.", 1949 VCMPGTFP: "vcmpgtfp", 1950 VCMPGTFP_: "vcmpgtfp.", 1951 VEXPTEFP: "vexptefp", 1952 VLOGEFP: "vlogefp", 1953 VREFP: "vrefp", 1954 VRSQRTEFP: "vrsqrtefp", 1955 VCIPHER: "vcipher", 1956 VCIPHERLAST: "vcipherlast", 1957 VNCIPHER: "vncipher", 1958 VNCIPHERLAST: "vncipherlast", 1959 VSBOX: "vsbox", 1960 VSHASIGMAD: "vshasigmad", 1961 VSHASIGMAW: "vshasigmaw", 1962 VPMSUMB: "vpmsumb", 1963 VPMSUMD: "vpmsumd", 1964 VPMSUMH: "vpmsumh", 1965 VPMSUMW: "vpmsumw", 1966 VPERMXOR: "vpermxor", 1967 VGBBD: "vgbbd", 1968 VCLZB: "vclzb", 1969 VCLZH: "vclzh", 1970 VCLZW: "vclzw", 1971 VCLZD: "vclzd", 1972 VPOPCNTB: "vpopcntb", 1973 VPOPCNTD: "vpopcntd", 1974 VPOPCNTH: "vpopcnth", 1975 VPOPCNTW: "vpopcntw", 1976 VBPERMQ: "vbpermq", 1977 BCDADD_: "bcdadd.", 1978 BCDSUB_: "bcdsub.", 1979 MTVSCR: "mtvscr", 1980 MFVSCR: "mfvscr", 1981 DADD: "dadd", 1982 DADD_: "dadd.", 1983 DSUB: "dsub", 1984 DSUB_: "dsub.", 1985 DMUL: "dmul", 1986 DMUL_: "dmul.", 1987 DDIV: "ddiv", 1988 DDIV_: "ddiv.", 1989 DCMPU: "dcmpu", 1990 DCMPO: "dcmpo", 1991 DTSTDC: "dtstdc", 1992 DTSTDG: "dtstdg", 1993 DTSTEX: "dtstex", 1994 DTSTSF: "dtstsf", 1995 DQUAI: "dquai", 1996 DQUAI_: "dquai.", 1997 DQUA: "dqua", 1998 DQUA_: "dqua.", 1999 DRRND: "drrnd", 2000 DRRND_: "drrnd.", 2001 DRINTX: "drintx", 2002 DRINTX_: "drintx.", 2003 DRINTN: "drintn", 2004 DRINTN_: "drintn.", 2005 DCTDP: "dctdp", 2006 DCTDP_: "dctdp.", 2007 DCTQPQ: "dctqpq", 2008 DCTQPQ_: "dctqpq.", 2009 DRSP: "drsp", 2010 DRSP_: "drsp.", 2011 DRDPQ: "drdpq", 2012 DRDPQ_: "drdpq.", 2013 DCFFIX: "dcffix", 2014 DCFFIX_: "dcffix.", 2015 DCFFIXQ: "dcffixq", 2016 DCFFIXQ_: "dcffixq.", 2017 DCTFIX: "dctfix", 2018 DCTFIX_: "dctfix.", 2019 DDEDPD: "ddedpd", 2020 DDEDPD_: "ddedpd.", 2021 DENBCD: "denbcd", 2022 DENBCD_: "denbcd.", 2023 DXEX: "dxex", 2024 DXEX_: "dxex.", 2025 DIEX: "diex", 2026 DIEX_: "diex.", 2027 DSCLI: "dscli", 2028 DSCLI_: "dscli.", 2029 DSCRI: "dscri", 2030 DSCRI_: "dscri.", 2031 LXSDX: "lxsdx", 2032 LXSIWAX: "lxsiwax", 2033 LXSIWZX: "lxsiwzx", 2034 LXSSPX: "lxsspx", 2035 LXVD2X: "lxvd2x", 2036 LXVDSX: "lxvdsx", 2037 LXVW4X: "lxvw4x", 2038 STXSDX: "stxsdx", 2039 STXSIWX: "stxsiwx", 2040 STXSSPX: "stxsspx", 2041 STXVD2X: "stxvd2x", 2042 STXVW4X: "stxvw4x", 2043 XSABSDP: "xsabsdp", 2044 XSADDDP: "xsadddp", 2045 XSADDSP: "xsaddsp", 2046 XSCMPODP: "xscmpodp", 2047 XSCMPUDP: "xscmpudp", 2048 XSCPSGNDP: "xscpsgndp", 2049 XSCVDPSP: "xscvdpsp", 2050 XSCVDPSPN: "xscvdpspn", 2051 XSCVDPSXDS: "xscvdpsxds", 2052 XSCVDPSXWS: "xscvdpsxws", 2053 XSCVDPUXDS: "xscvdpuxds", 2054 XSCVDPUXWS: "xscvdpuxws", 2055 XSCVSPDP: "xscvspdp", 2056 XSCVSPDPN: "xscvspdpn", 2057 XSCVSXDDP: "xscvsxddp", 2058 XSCVSXDSP: "xscvsxdsp", 2059 XSCVUXDDP: "xscvuxddp", 2060 XSCVUXDSP: "xscvuxdsp", 2061 XSDIVDP: "xsdivdp", 2062 XSDIVSP: "xsdivsp", 2063 XSMADDADP: "xsmaddadp", 2064 XSMADDASP: "xsmaddasp", 2065 XSMAXDP: "xsmaxdp", 2066 XSMINDP: "xsmindp", 2067 XSMSUBADP: "xsmsubadp", 2068 XSMSUBASP: "xsmsubasp", 2069 XSMULDP: "xsmuldp", 2070 XSMULSP: "xsmulsp", 2071 XSNABSDP: "xsnabsdp", 2072 XSNEGDP: "xsnegdp", 2073 XSNMADDADP: "xsnmaddadp", 2074 XSNMADDASP: "xsnmaddasp", 2075 XSNMSUBADP: "xsnmsubadp", 2076 XSNMSUBASP: "xsnmsubasp", 2077 XSRDPI: "xsrdpi", 2078 XSRDPIC: "xsrdpic", 2079 XSRDPIM: "xsrdpim", 2080 XSRDPIP: "xsrdpip", 2081 XSRDPIZ: "xsrdpiz", 2082 XSREDP: "xsredp", 2083 XSRESP: "xsresp", 2084 XSRSP: "xsrsp", 2085 XSRSQRTEDP: "xsrsqrtedp", 2086 XSRSQRTESP: "xsrsqrtesp", 2087 XSSQRTDP: "xssqrtdp", 2088 XSSQRTSP: "xssqrtsp", 2089 XSSUBDP: "xssubdp", 2090 XSSUBSP: "xssubsp", 2091 XSTDIVDP: "xstdivdp", 2092 XSTSQRTDP: "xstsqrtdp", 2093 XVABSDP: "xvabsdp", 2094 XVABSSP: "xvabssp", 2095 XVADDDP: "xvadddp", 2096 XVADDSP: "xvaddsp", 2097 XVCMPEQDP: "xvcmpeqdp", 2098 XVCMPEQDP_: "xvcmpeqdp.", 2099 XVCMPEQSP: "xvcmpeqsp", 2100 XVCMPEQSP_: "xvcmpeqsp.", 2101 XVCMPGEDP: "xvcmpgedp", 2102 XVCMPGEDP_: "xvcmpgedp.", 2103 XVCMPGESP: "xvcmpgesp", 2104 XVCMPGESP_: "xvcmpgesp.", 2105 XVCMPGTDP: "xvcmpgtdp", 2106 XVCMPGTDP_: "xvcmpgtdp.", 2107 XVCMPGTSP: "xvcmpgtsp", 2108 XVCMPGTSP_: "xvcmpgtsp.", 2109 XVCPSGNDP: "xvcpsgndp", 2110 XVCPSGNSP: "xvcpsgnsp", 2111 XVCVDPSP: "xvcvdpsp", 2112 XVCVDPSXDS: "xvcvdpsxds", 2113 XVCVDPSXWS: "xvcvdpsxws", 2114 XVCVDPUXDS: "xvcvdpuxds", 2115 XVCVDPUXWS: "xvcvdpuxws", 2116 XVCVSPDP: "xvcvspdp", 2117 XVCVSPSXDS: "xvcvspsxds", 2118 XVCVSPSXWS: "xvcvspsxws", 2119 XVCVSPUXDS: "xvcvspuxds", 2120 XVCVSPUXWS: "xvcvspuxws", 2121 XVCVSXDDP: "xvcvsxddp", 2122 XVCVSXDSP: "xvcvsxdsp", 2123 XVCVSXWDP: "xvcvsxwdp", 2124 XVCVSXWSP: "xvcvsxwsp", 2125 XVCVUXDDP: "xvcvuxddp", 2126 XVCVUXDSP: "xvcvuxdsp", 2127 XVCVUXWDP: "xvcvuxwdp", 2128 XVCVUXWSP: "xvcvuxwsp", 2129 XVDIVDP: "xvdivdp", 2130 XVDIVSP: "xvdivsp", 2131 XVMADDADP: "xvmaddadp", 2132 XVMADDASP: "xvmaddasp", 2133 XVMAXDP: "xvmaxdp", 2134 XVMAXSP: "xvmaxsp", 2135 XVMINDP: "xvmindp", 2136 XVMINSP: "xvminsp", 2137 XVMSUBADP: "xvmsubadp", 2138 XVMSUBASP: "xvmsubasp", 2139 XVMULDP: "xvmuldp", 2140 XVMULSP: "xvmulsp", 2141 XVNABSDP: "xvnabsdp", 2142 XVNABSSP: "xvnabssp", 2143 XVNEGDP: "xvnegdp", 2144 XVNEGSP: "xvnegsp", 2145 XVNMADDADP: "xvnmaddadp", 2146 XVNMADDASP: "xvnmaddasp", 2147 XVNMSUBADP: "xvnmsubadp", 2148 XVNMSUBASP: "xvnmsubasp", 2149 XVRDPI: "xvrdpi", 2150 XVRDPIC: "xvrdpic", 2151 XVRDPIM: "xvrdpim", 2152 XVRDPIP: "xvrdpip", 2153 XVRDPIZ: "xvrdpiz", 2154 XVREDP: "xvredp", 2155 XVRESP: "xvresp", 2156 XVRSPI: "xvrspi", 2157 XVRSPIC: "xvrspic", 2158 XVRSPIM: "xvrspim", 2159 XVRSPIP: "xvrspip", 2160 XVRSPIZ: "xvrspiz", 2161 XVRSQRTEDP: "xvrsqrtedp", 2162 XVRSQRTESP: "xvrsqrtesp", 2163 XVSQRTDP: "xvsqrtdp", 2164 XVSQRTSP: "xvsqrtsp", 2165 XVSUBDP: "xvsubdp", 2166 XVSUBSP: "xvsubsp", 2167 XVTDIVDP: "xvtdivdp", 2168 XVTDIVSP: "xvtdivsp", 2169 XVTSQRTDP: "xvtsqrtdp", 2170 XVTSQRTSP: "xvtsqrtsp", 2171 XXLAND: "xxland", 2172 XXLANDC: "xxlandc", 2173 XXLEQV: "xxleqv", 2174 XXLNAND: "xxlnand", 2175 XXLORC: "xxlorc", 2176 XXLNOR: "xxlnor", 2177 XXLOR: "xxlor", 2178 XXLXOR: "xxlxor", 2179 XXMRGHW: "xxmrghw", 2180 XXMRGLW: "xxmrglw", 2181 XXPERMDI: "xxpermdi", 2182 XXSEL: "xxsel", 2183 XXSLDWI: "xxsldwi", 2184 XXSPLTW: "xxspltw", 2185 BRINC: "brinc", 2186 EVABS: "evabs", 2187 EVADDIW: "evaddiw", 2188 EVADDSMIAAW: "evaddsmiaaw", 2189 EVADDSSIAAW: "evaddssiaaw", 2190 EVADDUMIAAW: "evaddumiaaw", 2191 EVADDUSIAAW: "evaddusiaaw", 2192 EVADDW: "evaddw", 2193 EVAND: "evand", 2194 EVCMPEQ: "evcmpeq", 2195 EVANDC: "evandc", 2196 EVCMPGTS: "evcmpgts", 2197 EVCMPGTU: "evcmpgtu", 2198 EVCMPLTU: "evcmpltu", 2199 EVCMPLTS: "evcmplts", 2200 EVCNTLSW: "evcntlsw", 2201 EVCNTLZW: "evcntlzw", 2202 EVDIVWS: "evdivws", 2203 EVDIVWU: "evdivwu", 2204 EVEQV: "eveqv", 2205 EVEXTSB: "evextsb", 2206 EVEXTSH: "evextsh", 2207 EVLDD: "evldd", 2208 EVLDH: "evldh", 2209 EVLDDX: "evlddx", 2210 EVLDHX: "evldhx", 2211 EVLDW: "evldw", 2212 EVLHHESPLAT: "evlhhesplat", 2213 EVLDWX: "evldwx", 2214 EVLHHESPLATX: "evlhhesplatx", 2215 EVLHHOSSPLAT: "evlhhossplat", 2216 EVLHHOUSPLAT: "evlhhousplat", 2217 EVLHHOSSPLATX: "evlhhossplatx", 2218 EVLHHOUSPLATX: "evlhhousplatx", 2219 EVLWHE: "evlwhe", 2220 EVLWHOS: "evlwhos", 2221 EVLWHEX: "evlwhex", 2222 EVLWHOSX: "evlwhosx", 2223 EVLWHOU: "evlwhou", 2224 EVLWHSPLAT: "evlwhsplat", 2225 EVLWHOUX: "evlwhoux", 2226 EVLWHSPLATX: "evlwhsplatx", 2227 EVLWWSPLAT: "evlwwsplat", 2228 EVMERGEHI: "evmergehi", 2229 EVLWWSPLATX: "evlwwsplatx", 2230 EVMERGELO: "evmergelo", 2231 EVMERGEHILO: "evmergehilo", 2232 EVMHEGSMFAA: "evmhegsmfaa", 2233 EVMERGELOHI: "evmergelohi", 2234 EVMHEGSMFAN: "evmhegsmfan", 2235 EVMHEGSMIAA: "evmhegsmiaa", 2236 EVMHEGUMIAA: "evmhegumiaa", 2237 EVMHEGSMIAN: "evmhegsmian", 2238 EVMHEGUMIAN: "evmhegumian", 2239 EVMHESMF: "evmhesmf", 2240 EVMHESMFAAW: "evmhesmfaaw", 2241 EVMHESMFA: "evmhesmfa", 2242 EVMHESMFANW: "evmhesmfanw", 2243 EVMHESMI: "evmhesmi", 2244 EVMHESMIAAW: "evmhesmiaaw", 2245 EVMHESMIA: "evmhesmia", 2246 EVMHESMIANW: "evmhesmianw", 2247 EVMHESSF: "evmhessf", 2248 EVMHESSFA: "evmhessfa", 2249 EVMHESSFAAW: "evmhessfaaw", 2250 EVMHESSFANW: "evmhessfanw", 2251 EVMHESSIAAW: "evmhessiaaw", 2252 EVMHESSIANW: "evmhessianw", 2253 EVMHEUMI: "evmheumi", 2254 EVMHEUMIAAW: "evmheumiaaw", 2255 EVMHEUMIA: "evmheumia", 2256 EVMHEUMIANW: "evmheumianw", 2257 EVMHEUSIAAW: "evmheusiaaw", 2258 EVMHEUSIANW: "evmheusianw", 2259 EVMHOGSMFAA: "evmhogsmfaa", 2260 EVMHOGSMIAA: "evmhogsmiaa", 2261 EVMHOGSMFAN: "evmhogsmfan", 2262 EVMHOGSMIAN: "evmhogsmian", 2263 EVMHOGUMIAA: "evmhogumiaa", 2264 EVMHOSMF: "evmhosmf", 2265 EVMHOGUMIAN: "evmhogumian", 2266 EVMHOSMFA: "evmhosmfa", 2267 EVMHOSMFAAW: "evmhosmfaaw", 2268 EVMHOSMI: "evmhosmi", 2269 EVMHOSMFANW: "evmhosmfanw", 2270 EVMHOSMIA: "evmhosmia", 2271 EVMHOSMIAAW: "evmhosmiaaw", 2272 EVMHOSMIANW: "evmhosmianw", 2273 EVMHOSSF: "evmhossf", 2274 EVMHOSSFA: "evmhossfa", 2275 EVMHOSSFAAW: "evmhossfaaw", 2276 EVMHOSSFANW: "evmhossfanw", 2277 EVMHOSSIAAW: "evmhossiaaw", 2278 EVMHOUMI: "evmhoumi", 2279 EVMHOSSIANW: "evmhossianw", 2280 EVMHOUMIA: "evmhoumia", 2281 EVMHOUMIAAW: "evmhoumiaaw", 2282 EVMHOUSIAAW: "evmhousiaaw", 2283 EVMHOUMIANW: "evmhoumianw", 2284 EVMHOUSIANW: "evmhousianw", 2285 EVMRA: "evmra", 2286 EVMWHSMF: "evmwhsmf", 2287 EVMWHSMI: "evmwhsmi", 2288 EVMWHSMFA: "evmwhsmfa", 2289 EVMWHSMIA: "evmwhsmia", 2290 EVMWHSSF: "evmwhssf", 2291 EVMWHUMI: "evmwhumi", 2292 EVMWHSSFA: "evmwhssfa", 2293 EVMWHUMIA: "evmwhumia", 2294 EVMWLSMIAAW: "evmwlsmiaaw", 2295 EVMWLSSIAAW: "evmwlssiaaw", 2296 EVMWLSMIANW: "evmwlsmianw", 2297 EVMWLSSIANW: "evmwlssianw", 2298 EVMWLUMI: "evmwlumi", 2299 EVMWLUMIAAW: "evmwlumiaaw", 2300 EVMWLUMIA: "evmwlumia", 2301 EVMWLUMIANW: "evmwlumianw", 2302 EVMWLUSIAAW: "evmwlusiaaw", 2303 EVMWSMF: "evmwsmf", 2304 EVMWLUSIANW: "evmwlusianw", 2305 EVMWSMFA: "evmwsmfa", 2306 EVMWSMFAA: "evmwsmfaa", 2307 EVMWSMI: "evmwsmi", 2308 EVMWSMIAA: "evmwsmiaa", 2309 EVMWSMFAN: "evmwsmfan", 2310 EVMWSMIA: "evmwsmia", 2311 EVMWSMIAN: "evmwsmian", 2312 EVMWSSF: "evmwssf", 2313 EVMWSSFA: "evmwssfa", 2314 EVMWSSFAA: "evmwssfaa", 2315 EVMWUMI: "evmwumi", 2316 EVMWSSFAN: "evmwssfan", 2317 EVMWUMIA: "evmwumia", 2318 EVMWUMIAA: "evmwumiaa", 2319 EVNAND: "evnand", 2320 EVMWUMIAN: "evmwumian", 2321 EVNEG: "evneg", 2322 EVNOR: "evnor", 2323 EVORC: "evorc", 2324 EVOR: "evor", 2325 EVRLW: "evrlw", 2326 EVRLWI: "evrlwi", 2327 EVSEL: "evsel", 2328 EVRNDW: "evrndw", 2329 EVSLW: "evslw", 2330 EVSPLATFI: "evsplatfi", 2331 EVSRWIS: "evsrwis", 2332 EVSLWI: "evslwi", 2333 EVSPLATI: "evsplati", 2334 EVSRWIU: "evsrwiu", 2335 EVSRWS: "evsrws", 2336 EVSTDD: "evstdd", 2337 EVSRWU: "evsrwu", 2338 EVSTDDX: "evstddx", 2339 EVSTDH: "evstdh", 2340 EVSTDW: "evstdw", 2341 EVSTDHX: "evstdhx", 2342 EVSTDWX: "evstdwx", 2343 EVSTWHE: "evstwhe", 2344 EVSTWHO: "evstwho", 2345 EVSTWWE: "evstwwe", 2346 EVSTWHEX: "evstwhex", 2347 EVSTWHOX: "evstwhox", 2348 EVSTWWEX: "evstwwex", 2349 EVSTWWO: "evstwwo", 2350 EVSUBFSMIAAW: "evsubfsmiaaw", 2351 EVSTWWOX: "evstwwox", 2352 EVSUBFSSIAAW: "evsubfssiaaw", 2353 EVSUBFUMIAAW: "evsubfumiaaw", 2354 EVSUBFUSIAAW: "evsubfusiaaw", 2355 EVSUBFW: "evsubfw", 2356 EVSUBIFW: "evsubifw", 2357 EVXOR: "evxor", 2358 EVFSABS: "evfsabs", 2359 EVFSNABS: "evfsnabs", 2360 EVFSNEG: "evfsneg", 2361 EVFSADD: "evfsadd", 2362 EVFSMUL: "evfsmul", 2363 EVFSSUB: "evfssub", 2364 EVFSDIV: "evfsdiv", 2365 EVFSCMPGT: "evfscmpgt", 2366 EVFSCMPLT: "evfscmplt", 2367 EVFSCMPEQ: "evfscmpeq", 2368 EVFSTSTGT: "evfststgt", 2369 EVFSTSTLT: "evfststlt", 2370 EVFSTSTEQ: "evfststeq", 2371 EVFSCFSI: "evfscfsi", 2372 EVFSCFSF: "evfscfsf", 2373 EVFSCFUI: "evfscfui", 2374 EVFSCFUF: "evfscfuf", 2375 EVFSCTSI: "evfsctsi", 2376 EVFSCTUI: "evfsctui", 2377 EVFSCTSIZ: "evfsctsiz", 2378 EVFSCTUIZ: "evfsctuiz", 2379 EVFSCTSF: "evfsctsf", 2380 EVFSCTUF: "evfsctuf", 2381 EFSABS: "efsabs", 2382 EFSNEG: "efsneg", 2383 EFSNABS: "efsnabs", 2384 EFSADD: "efsadd", 2385 EFSMUL: "efsmul", 2386 EFSSUB: "efssub", 2387 EFSDIV: "efsdiv", 2388 EFSCMPGT: "efscmpgt", 2389 EFSCMPLT: "efscmplt", 2390 EFSCMPEQ: "efscmpeq", 2391 EFSTSTGT: "efststgt", 2392 EFSTSTLT: "efststlt", 2393 EFSTSTEQ: "efststeq", 2394 EFSCFSI: "efscfsi", 2395 EFSCFSF: "efscfsf", 2396 EFSCTSI: "efsctsi", 2397 EFSCFUI: "efscfui", 2398 EFSCFUF: "efscfuf", 2399 EFSCTUI: "efsctui", 2400 EFSCTSIZ: "efsctsiz", 2401 EFSCTSF: "efsctsf", 2402 EFSCTUIZ: "efsctuiz", 2403 EFSCTUF: "efsctuf", 2404 EFDABS: "efdabs", 2405 EFDNEG: "efdneg", 2406 EFDNABS: "efdnabs", 2407 EFDADD: "efdadd", 2408 EFDMUL: "efdmul", 2409 EFDSUB: "efdsub", 2410 EFDDIV: "efddiv", 2411 EFDCMPGT: "efdcmpgt", 2412 EFDCMPEQ: "efdcmpeq", 2413 EFDCMPLT: "efdcmplt", 2414 EFDTSTGT: "efdtstgt", 2415 EFDTSTLT: "efdtstlt", 2416 EFDCFSI: "efdcfsi", 2417 EFDTSTEQ: "efdtsteq", 2418 EFDCFUI: "efdcfui", 2419 EFDCFSID: "efdcfsid", 2420 EFDCFSF: "efdcfsf", 2421 EFDCFUF: "efdcfuf", 2422 EFDCFUID: "efdcfuid", 2423 EFDCTSI: "efdctsi", 2424 EFDCTUI: "efdctui", 2425 EFDCTSIDZ: "efdctsidz", 2426 EFDCTUIDZ: "efdctuidz", 2427 EFDCTSIZ: "efdctsiz", 2428 EFDCTSF: "efdctsf", 2429 EFDCTUF: "efdctuf", 2430 EFDCTUIZ: "efdctuiz", 2431 EFDCFS: "efdcfs", 2432 EFSCFD: "efscfd", 2433 DLMZB: "dlmzb", 2434 DLMZB_: "dlmzb.", 2435 MACCHW: "macchw", 2436 MACCHW_: "macchw.", 2437 MACCHWO: "macchwo", 2438 MACCHWO_: "macchwo.", 2439 MACCHWS: "macchws", 2440 MACCHWS_: "macchws.", 2441 MACCHWSO: "macchwso", 2442 MACCHWSO_: "macchwso.", 2443 MACCHWU: "macchwu", 2444 MACCHWU_: "macchwu.", 2445 MACCHWUO: "macchwuo", 2446 MACCHWUO_: "macchwuo.", 2447 MACCHWSU: "macchwsu", 2448 MACCHWSU_: "macchwsu.", 2449 MACCHWSUO: "macchwsuo", 2450 MACCHWSUO_: "macchwsuo.", 2451 MACHHW: "machhw", 2452 MACHHW_: "machhw.", 2453 MACHHWO: "machhwo", 2454 MACHHWO_: "machhwo.", 2455 MACHHWS: "machhws", 2456 MACHHWS_: "machhws.", 2457 MACHHWSO: "machhwso", 2458 MACHHWSO_: "machhwso.", 2459 MACHHWU: "machhwu", 2460 MACHHWU_: "machhwu.", 2461 MACHHWUO: "machhwuo", 2462 MACHHWUO_: "machhwuo.", 2463 MACHHWSU: "machhwsu", 2464 MACHHWSU_: "machhwsu.", 2465 MACHHWSUO: "machhwsuo", 2466 MACHHWSUO_: "machhwsuo.", 2467 MACLHW: "maclhw", 2468 MACLHW_: "maclhw.", 2469 MACLHWO: "maclhwo", 2470 MACLHWO_: "maclhwo.", 2471 MACLHWS: "maclhws", 2472 MACLHWS_: "maclhws.", 2473 MACLHWSO: "maclhwso", 2474 MACLHWSO_: "maclhwso.", 2475 MACLHWU: "maclhwu", 2476 MACLHWU_: "maclhwu.", 2477 MACLHWUO: "maclhwuo", 2478 MACLHWUO_: "maclhwuo.", 2479 MULCHW: "mulchw", 2480 MULCHW_: "mulchw.", 2481 MACLHWSU: "maclhwsu", 2482 MACLHWSU_: "maclhwsu.", 2483 MACLHWSUO: "maclhwsuo", 2484 MACLHWSUO_: "maclhwsuo.", 2485 MULCHWU: "mulchwu", 2486 MULCHWU_: "mulchwu.", 2487 MULHHW: "mulhhw", 2488 MULHHW_: "mulhhw.", 2489 MULLHW: "mullhw", 2490 MULLHW_: "mullhw.", 2491 MULHHWU: "mulhhwu", 2492 MULHHWU_: "mulhhwu.", 2493 MULLHWU: "mullhwu", 2494 MULLHWU_: "mullhwu.", 2495 NMACCHW: "nmacchw", 2496 NMACCHW_: "nmacchw.", 2497 NMACCHWO: "nmacchwo", 2498 NMACCHWO_: "nmacchwo.", 2499 NMACCHWS: "nmacchws", 2500 NMACCHWS_: "nmacchws.", 2501 NMACCHWSO: "nmacchwso", 2502 NMACCHWSO_: "nmacchwso.", 2503 NMACHHW: "nmachhw", 2504 NMACHHW_: "nmachhw.", 2505 NMACHHWO: "nmachhwo", 2506 NMACHHWO_: "nmachhwo.", 2507 NMACHHWS: "nmachhws", 2508 NMACHHWS_: "nmachhws.", 2509 NMACHHWSO: "nmachhwso", 2510 NMACHHWSO_: "nmachhwso.", 2511 NMACLHW: "nmaclhw", 2512 NMACLHW_: "nmaclhw.", 2513 NMACLHWO: "nmaclhwo", 2514 NMACLHWO_: "nmaclhwo.", 2515 NMACLHWS: "nmaclhws", 2516 NMACLHWS_: "nmaclhws.", 2517 NMACLHWSO: "nmaclhwso", 2518 NMACLHWSO_: "nmaclhwso.", 2519 ICBI: "icbi", 2520 ICBT: "icbt", 2521 DCBA: "dcba", 2522 DCBT: "dcbt", 2523 DCBTST: "dcbtst", 2524 DCBZ: "dcbz", 2525 DCBST: "dcbst", 2526 DCBF: "dcbf", 2527 ISYNC: "isync", 2528 LBARX: "lbarx", 2529 LHARX: "lharx", 2530 LWARX: "lwarx", 2531 STBCX_: "stbcx.", 2532 STHCX_: "sthcx.", 2533 STWCX_: "stwcx.", 2534 LDARX: "ldarx", 2535 STDCX_: "stdcx.", 2536 LQARX: "lqarx", 2537 STQCX_: "stqcx.", 2538 SYNC: "sync", 2539 EIEIO: "eieio", 2540 MBAR: "mbar", 2541 WAIT: "wait", 2542 TBEGIN_: "tbegin.", 2543 TEND_: "tend.", 2544 TABORT_: "tabort.", 2545 TABORTWC_: "tabortwc.", 2546 TABORTWCI_: "tabortwci.", 2547 TABORTDC_: "tabortdc.", 2548 TABORTDCI_: "tabortdci.", 2549 TSR_: "tsr.", 2550 TCHECK: "tcheck", 2551 MFTB: "mftb", 2552 RFEBB: "rfebb", 2553 LBDX: "lbdx", 2554 LHDX: "lhdx", 2555 LWDX: "lwdx", 2556 LDDX: "lddx", 2557 LFDDX: "lfddx", 2558 STBDX: "stbdx", 2559 STHDX: "sthdx", 2560 STWDX: "stwdx", 2561 STDDX: "stddx", 2562 STFDDX: "stfddx", 2563 DSN: "dsn", 2564 ECIWX: "eciwx", 2565 ECOWX: "ecowx", 2566 RFID: "rfid", 2567 HRFID: "hrfid", 2568 DOZE: "doze", 2569 NAP: "nap", 2570 SLEEP: "sleep", 2571 RVWINKLE: "rvwinkle", 2572 LBZCIX: "lbzcix", 2573 LWZCIX: "lwzcix", 2574 LHZCIX: "lhzcix", 2575 LDCIX: "ldcix", 2576 STBCIX: "stbcix", 2577 STWCIX: "stwcix", 2578 STHCIX: "sthcix", 2579 STDCIX: "stdcix", 2580 TRECLAIM_: "treclaim.", 2581 TRECHKPT_: "trechkpt.", 2582 MTMSR: "mtmsr", 2583 MTMSRD: "mtmsrd", 2584 MFMSR: "mfmsr", 2585 SLBIE: "slbie", 2586 SLBIA: "slbia", 2587 SLBMTE: "slbmte", 2588 SLBMFEV: "slbmfev", 2589 SLBMFEE: "slbmfee", 2590 SLBFEE_: "slbfee.", 2591 MTSR: "mtsr", 2592 MTSRIN: "mtsrin", 2593 MFSR: "mfsr", 2594 MFSRIN: "mfsrin", 2595 TLBIE: "tlbie", 2596 TLBIEL: "tlbiel", 2597 TLBIA: "tlbia", 2598 TLBSYNC: "tlbsync", 2599 MSGSND: "msgsnd", 2600 MSGCLR: "msgclr", 2601 MSGSNDP: "msgsndp", 2602 MSGCLRP: "msgclrp", 2603 MTTMR: "mttmr", 2604 RFI: "rfi", 2605 RFCI: "rfci", 2606 RFDI: "rfdi", 2607 RFMCI: "rfmci", 2608 RFGI: "rfgi", 2609 EHPRIV: "ehpriv", 2610 MTDCR: "mtdcr", 2611 MTDCRX: "mtdcrx", 2612 MFDCR: "mfdcr", 2613 MFDCRX: "mfdcrx", 2614 WRTEE: "wrtee", 2615 WRTEEI: "wrteei", 2616 LBEPX: "lbepx", 2617 LHEPX: "lhepx", 2618 LWEPX: "lwepx", 2619 LDEPX: "ldepx", 2620 STBEPX: "stbepx", 2621 STHEPX: "sthepx", 2622 STWEPX: "stwepx", 2623 STDEPX: "stdepx", 2624 DCBSTEP: "dcbstep", 2625 DCBTEP: "dcbtep", 2626 DCBFEP: "dcbfep", 2627 DCBTSTEP: "dcbtstep", 2628 ICBIEP: "icbiep", 2629 DCBZEP: "dcbzep", 2630 LFDEPX: "lfdepx", 2631 STFDEPX: "stfdepx", 2632 EVLDDEPX: "evlddepx", 2633 EVSTDDEPX: "evstddepx", 2634 LVEPX: "lvepx", 2635 LVEPXL: "lvepxl", 2636 STVEPX: "stvepx", 2637 STVEPXL: "stvepxl", 2638 DCBI: "dcbi", 2639 DCBLQ_: "dcblq.", 2640 ICBLQ_: "icblq.", 2641 DCBTLS: "dcbtls", 2642 DCBTSTLS: "dcbtstls", 2643 ICBTLS: "icbtls", 2644 ICBLC: "icblc", 2645 DCBLC: "dcblc", 2646 TLBIVAX: "tlbivax", 2647 TLBILX: "tlbilx", 2648 TLBSX: "tlbsx", 2649 TLBSRX_: "tlbsrx.", 2650 TLBRE: "tlbre", 2651 TLBWE: "tlbwe", 2652 DNH: "dnh", 2653 DCI: "dci", 2654 ICI: "ici", 2655 DCREAD: "dcread", 2656 ICREAD: "icread", 2657 MFPMR: "mfpmr", 2658 MTPMR: "mtpmr", 2659} 2660 2661var ( 2662 ap_Reg_11_15 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{11, 5}}} 2663 ap_Reg_6_10 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{6, 5}}} 2664 ap_PCRel_6_29_shift2 = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{6, 24}}} 2665 ap_Label_6_29_shift2 = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{6, 24}}} 2666 ap_ImmUnsigned_6_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 5}}} 2667 ap_CondRegBit_11_15 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{11, 5}}} 2668 ap_PCRel_16_29_shift2 = &argField{Type: TypePCRel, Shift: 2, BitFields: BitFields{{16, 14}}} 2669 ap_Label_16_29_shift2 = &argField{Type: TypeLabel, Shift: 2, BitFields: BitFields{{16, 14}}} 2670 ap_ImmUnsigned_19_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{19, 2}}} 2671 ap_CondRegBit_6_10 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{6, 5}}} 2672 ap_CondRegBit_16_20 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{16, 5}}} 2673 ap_CondRegField_6_8 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{6, 3}}} 2674 ap_CondRegField_11_13 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{11, 3}}} 2675 ap_ImmUnsigned_20_26 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 7}}} 2676 ap_SpReg_11_20 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{11, 10}}} 2677 ap_Offset_16_31 = &argField{Type: TypeOffset, Shift: 0, BitFields: BitFields{{16, 16}}} 2678 ap_Reg_16_20 = &argField{Type: TypeReg, Shift: 0, BitFields: BitFields{{16, 5}}} 2679 ap_Offset_16_29_shift2 = &argField{Type: TypeOffset, Shift: 2, BitFields: BitFields{{16, 14}}} 2680 ap_Offset_16_27_shift4 = &argField{Type: TypeOffset, Shift: 4, BitFields: BitFields{{16, 12}}} 2681 ap_ImmUnsigned_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 5}}} 2682 ap_ImmSigned_16_31 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 16}}} 2683 ap_ImmUnsigned_16_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 16}}} 2684 ap_CondRegBit_21_25 = &argField{Type: TypeCondRegBit, Shift: 0, BitFields: BitFields{{21, 5}}} 2685 ap_ImmUnsigned_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 5}}} 2686 ap_ImmUnsigned_26_30 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 5}}} 2687 ap_ImmUnsigned_30_30_16_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}} 2688 ap_ImmUnsigned_26_26_21_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{26, 1}, {21, 5}}} 2689 ap_SpReg_16_20_11_15 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{16, 5}, {11, 5}}} 2690 ap_ImmUnsigned_12_19 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 8}}} 2691 ap_ImmUnsigned_10_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{10, 1}}} 2692 ap_VecSReg_31_31_6_10 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{31, 1}, {6, 5}}} 2693 ap_FPReg_6_10 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{6, 5}}} 2694 ap_FPReg_16_20 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{16, 5}}} 2695 ap_FPReg_11_15 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{11, 5}}} 2696 ap_FPReg_21_25 = &argField{Type: TypeFPReg, Shift: 0, BitFields: BitFields{{21, 5}}} 2697 ap_ImmUnsigned_16_19 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 4}}} 2698 ap_ImmUnsigned_15_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{15, 1}}} 2699 ap_ImmUnsigned_7_14 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 8}}} 2700 ap_ImmUnsigned_6_6 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 1}}} 2701 ap_VecReg_6_10 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{6, 5}}} 2702 ap_VecReg_11_15 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{11, 5}}} 2703 ap_VecReg_16_20 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{16, 5}}} 2704 ap_ImmUnsigned_12_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{12, 4}}} 2705 ap_ImmUnsigned_13_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{13, 3}}} 2706 ap_ImmUnsigned_14_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{14, 2}}} 2707 ap_ImmSigned_11_15 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{11, 5}}} 2708 ap_VecReg_21_25 = &argField{Type: TypeVecReg, Shift: 0, BitFields: BitFields{{21, 5}}} 2709 ap_ImmUnsigned_22_25 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 4}}} 2710 ap_ImmUnsigned_11_15 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 5}}} 2711 ap_ImmUnsigned_16_16 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 1}}} 2712 ap_ImmUnsigned_17_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{17, 4}}} 2713 ap_ImmUnsigned_22_22 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 1}}} 2714 ap_ImmUnsigned_16_21 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{16, 6}}} 2715 ap_ImmUnsigned_21_22 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{21, 2}}} 2716 ap_ImmUnsigned_11_12 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 2}}} 2717 ap_ImmUnsigned_11_11 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 1}}} 2718 ap_VecSReg_30_30_16_20 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{30, 1}, {16, 5}}} 2719 ap_VecSReg_29_29_11_15 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{29, 1}, {11, 5}}} 2720 ap_ImmUnsigned_22_23 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{22, 2}}} 2721 ap_VecSReg_28_28_21_25 = &argField{Type: TypeVecSReg, Shift: 0, BitFields: BitFields{{28, 1}, {21, 5}}} 2722 ap_CondRegField_29_31 = &argField{Type: TypeCondRegField, Shift: 0, BitFields: BitFields{{29, 3}}} 2723 ap_ImmUnsigned_7_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{7, 4}}} 2724 ap_ImmUnsigned_9_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{9, 2}}} 2725 ap_ImmUnsigned_31_31 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{31, 1}}} 2726 ap_ImmSigned_16_20 = &argField{Type: TypeImmSigned, Shift: 0, BitFields: BitFields{{16, 5}}} 2727 ap_ImmUnsigned_20_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{20, 1}}} 2728 ap_ImmUnsigned_8_10 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{8, 3}}} 2729 ap_SpReg_12_15 = &argField{Type: TypeSpReg, Shift: 0, BitFields: BitFields{{12, 4}}} 2730 ap_ImmUnsigned_6_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{6, 15}}} 2731 ap_ImmUnsigned_11_20 = &argField{Type: TypeImmUnsigned, Shift: 0, BitFields: BitFields{{11, 10}}} 2732) 2733 2734var instFormats = [...]instFormat{ 2735 {CNTLZW, 0xfc0007ff, 0x7c000034, 0xf800, // Count Leading Zeros Word X-form (cntlzw RA, RS) 2736 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 2737 {CNTLZW_, 0xfc0007ff, 0x7c000035, 0xf800, // Count Leading Zeros Word X-form (cntlzw. RA, RS) 2738 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 2739 {B, 0xfc000003, 0x48000000, 0x0, // Branch I-form (b target_addr) 2740 [5]*argField{ap_PCRel_6_29_shift2}}, 2741 {BA, 0xfc000003, 0x48000002, 0x0, // Branch I-form (ba target_addr) 2742 [5]*argField{ap_Label_6_29_shift2}}, 2743 {BL, 0xfc000003, 0x48000001, 0x0, // Branch I-form (bl target_addr) 2744 [5]*argField{ap_PCRel_6_29_shift2}}, 2745 {BLA, 0xfc000003, 0x48000003, 0x0, // Branch I-form (bla target_addr) 2746 [5]*argField{ap_Label_6_29_shift2}}, 2747 {BC, 0xfc000003, 0x40000000, 0x0, // Branch Conditional B-form (bc BO,BI,target_addr) 2748 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}}, 2749 {BCA, 0xfc000003, 0x40000002, 0x0, // Branch Conditional B-form (bca BO,BI,target_addr) 2750 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}}, 2751 {BCL, 0xfc000003, 0x40000001, 0x0, // Branch Conditional B-form (bcl BO,BI,target_addr) 2752 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_PCRel_16_29_shift2}}, 2753 {BCLA, 0xfc000003, 0x40000003, 0x0, // Branch Conditional B-form (bcla BO,BI,target_addr) 2754 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_Label_16_29_shift2}}, 2755 {BCLR, 0xfc0007ff, 0x4c000020, 0xe000, // Branch Conditional to Link Register XL-form (bclr BO,BI,BH) 2756 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, 2757 {BCLRL, 0xfc0007ff, 0x4c000021, 0xe000, // Branch Conditional to Link Register XL-form (bclrl BO,BI,BH) 2758 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, 2759 {BCCTR, 0xfc0007ff, 0x4c000420, 0xe000, // Branch Conditional to Count Register XL-form (bcctr BO,BI,BH) 2760 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, 2761 {BCCTRL, 0xfc0007ff, 0x4c000421, 0xe000, // Branch Conditional to Count Register XL-form (bcctrl BO,BI,BH) 2762 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, 2763 {BCTAR, 0xfc0007ff, 0x4c000460, 0xe000, // Branch Conditional to Branch Target Address Register XL-form (bctar BO,BI,BH) 2764 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, 2765 {BCTARL, 0xfc0007ff, 0x4c000461, 0xe000, // Branch Conditional to Branch Target Address Register XL-form (bctarl BO,BI,BH) 2766 [5]*argField{ap_ImmUnsigned_6_10, ap_CondRegBit_11_15, ap_ImmUnsigned_19_20}}, 2767 {CRAND, 0xfc0007fe, 0x4c000202, 0x1, // Condition Register AND XL-form (crand BT,BA,BB) 2768 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 2769 {CROR, 0xfc0007fe, 0x4c000382, 0x1, // Condition Register OR XL-form (cror BT,BA,BB) 2770 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 2771 {CRNAND, 0xfc0007fe, 0x4c0001c2, 0x1, // Condition Register NAND XL-form (crnand BT,BA,BB) 2772 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 2773 {CRXOR, 0xfc0007fe, 0x4c000182, 0x1, // Condition Register XOR XL-form (crxor BT,BA,BB) 2774 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 2775 {CRNOR, 0xfc0007fe, 0x4c000042, 0x1, // Condition Register NOR XL-form (crnor BT,BA,BB) 2776 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 2777 {CRANDC, 0xfc0007fe, 0x4c000102, 0x1, // Condition Register AND with Complement XL-form (crandc BT,BA,BB) 2778 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 2779 {MCRF, 0xfc0007fe, 0x4c000000, 0x63f801, // Move Condition Register Field XL-form (mcrf BF,BFA) 2780 [5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}}, 2781 {CREQV, 0xfc0007fe, 0x4c000242, 0x1, // Condition Register Equivalent XL-form (creqv BT,BA,BB) 2782 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 2783 {CRORC, 0xfc0007fe, 0x4c000342, 0x1, // Condition Register OR with Complement XL-form (crorc BT,BA,BB) 2784 [5]*argField{ap_CondRegBit_6_10, ap_CondRegBit_11_15, ap_CondRegBit_16_20}}, 2785 {SC, 0xfc000002, 0x44000002, 0x3fff01d, // System Call SC-form (sc LEV) 2786 [5]*argField{ap_ImmUnsigned_20_26}}, 2787 {CLRBHRB, 0xfc0007fe, 0x7c00035c, 0x3fff801, // Clear BHRB X-form (clrbhrb) 2788 [5]*argField{}}, 2789 {MFBHRBE, 0xfc0007fe, 0x7c00025c, 0x1, // Move From Branch History Rolling Buffer XFX-form (mfbhrbe RT,BHRBE) 2790 [5]*argField{ap_Reg_6_10, ap_SpReg_11_20}}, 2791 {LBZ, 0xfc000000, 0x88000000, 0x0, // Load Byte and Zero D-form (lbz RT,D(RA)) 2792 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2793 {LBZU, 0xfc000000, 0x8c000000, 0x0, // Load Byte and Zero with Update D-form (lbzu RT,D(RA)) 2794 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2795 {LBZX, 0xfc0007fe, 0x7c0000ae, 0x1, // Load Byte and Zero Indexed X-form (lbzx RT,RA,RB) 2796 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2797 {LBZUX, 0xfc0007fe, 0x7c0000ee, 0x1, // Load Byte and Zero with Update Indexed X-form (lbzux RT,RA,RB) 2798 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2799 {LHZ, 0xfc000000, 0xa0000000, 0x0, // Load Halfword and Zero D-form (lhz RT,D(RA)) 2800 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2801 {LHZU, 0xfc000000, 0xa4000000, 0x0, // Load Halfword and Zero with Update D-form (lhzu RT,D(RA)) 2802 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2803 {LHZX, 0xfc0007fe, 0x7c00022e, 0x1, // Load Halfword and Zero Indexed X-form (lhzx RT,RA,RB) 2804 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2805 {LHZUX, 0xfc0007fe, 0x7c00026e, 0x1, // Load Halfword and Zero with Update Indexed X-form (lhzux RT,RA,RB) 2806 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2807 {LHA, 0xfc000000, 0xa8000000, 0x0, // Load Halfword Algebraic D-form (lha RT,D(RA)) 2808 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2809 {LHAU, 0xfc000000, 0xac000000, 0x0, // Load Halfword Algebraic with Update D-form (lhau RT,D(RA)) 2810 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2811 {LHAX, 0xfc0007fe, 0x7c0002ae, 0x1, // Load Halfword Algebraic Indexed X-form (lhax RT,RA,RB) 2812 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2813 {LHAUX, 0xfc0007fe, 0x7c0002ee, 0x1, // Load Halfword Algebraic with Update Indexed X-form (lhaux RT,RA,RB) 2814 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2815 {LWZ, 0xfc000000, 0x80000000, 0x0, // Load Word and Zero D-form (lwz RT,D(RA)) 2816 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2817 {LWZU, 0xfc000000, 0x84000000, 0x0, // Load Word and Zero with Update D-form (lwzu RT,D(RA)) 2818 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2819 {LWZX, 0xfc0007fe, 0x7c00002e, 0x1, // Load Word and Zero Indexed X-form (lwzx RT,RA,RB) 2820 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2821 {LWZUX, 0xfc0007fe, 0x7c00006e, 0x1, // Load Word and Zero with Update Indexed X-form (lwzux RT,RA,RB) 2822 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2823 {LWA, 0xfc000003, 0xe8000002, 0x0, // Load Word Algebraic DS-form (lwa RT,DS(RA)) 2824 [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 2825 {LWAX, 0xfc0007fe, 0x7c0002aa, 0x1, // Load Word Algebraic Indexed X-form (lwax RT,RA,RB) 2826 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2827 {LWAUX, 0xfc0007fe, 0x7c0002ea, 0x1, // Load Word Algebraic with Update Indexed X-form (lwaux RT,RA,RB) 2828 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2829 {LD, 0xfc000003, 0xe8000000, 0x0, // Load Doubleword DS-form (ld RT,DS(RA)) 2830 [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 2831 {LDU, 0xfc000003, 0xe8000001, 0x0, // Load Doubleword with Update DS-form (ldu RT,DS(RA)) 2832 [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 2833 {LDX, 0xfc0007fe, 0x7c00002a, 0x1, // Load Doubleword Indexed X-form (ldx RT,RA,RB) 2834 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2835 {LDUX, 0xfc0007fe, 0x7c00006a, 0x1, // Load Doubleword with Update Indexed X-form (ldux RT,RA,RB) 2836 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2837 {STB, 0xfc000000, 0x98000000, 0x0, // Store Byte D-form (stb RS,D(RA)) 2838 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2839 {STBU, 0xfc000000, 0x9c000000, 0x0, // Store Byte with Update D-form (stbu RS,D(RA)) 2840 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2841 {STBX, 0xfc0007fe, 0x7c0001ae, 0x1, // Store Byte Indexed X-form (stbx RS,RA,RB) 2842 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2843 {STBUX, 0xfc0007fe, 0x7c0001ee, 0x1, // Store Byte with Update Indexed X-form (stbux RS,RA,RB) 2844 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2845 {STH, 0xfc000000, 0xb0000000, 0x0, // Store Halfword D-form (sth RS,D(RA)) 2846 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2847 {STHU, 0xfc000000, 0xb4000000, 0x0, // Store Halfword with Update D-form (sthu RS,D(RA)) 2848 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2849 {STHX, 0xfc0007fe, 0x7c00032e, 0x1, // Store Halfword Indexed X-form (sthx RS,RA,RB) 2850 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2851 {STHUX, 0xfc0007fe, 0x7c00036e, 0x1, // Store Halfword with Update Indexed X-form (sthux RS,RA,RB) 2852 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2853 {STW, 0xfc000000, 0x90000000, 0x0, // Store Word D-form (stw RS,D(RA)) 2854 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2855 {STWU, 0xfc000000, 0x94000000, 0x0, // Store Word with Update D-form (stwu RS,D(RA)) 2856 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2857 {STWX, 0xfc0007fe, 0x7c00012e, 0x1, // Store Word Indexed X-form (stwx RS,RA,RB) 2858 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2859 {STWUX, 0xfc0007fe, 0x7c00016e, 0x1, // Store Word with Update Indexed X-form (stwux RS,RA,RB) 2860 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2861 {STD, 0xfc000003, 0xf8000000, 0x0, // Store Doubleword DS-form (std RS,DS(RA)) 2862 [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 2863 {STDU, 0xfc000003, 0xf8000001, 0x0, // Store Doubleword with Update DS-form (stdu RS,DS(RA)) 2864 [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 2865 {STDX, 0xfc0007fe, 0x7c00012a, 0x1, // Store Doubleword Indexed X-form (stdx RS,RA,RB) 2866 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2867 {STDUX, 0xfc0007fe, 0x7c00016a, 0x1, // Store Doubleword with Update Indexed X-form (stdux RS,RA,RB) 2868 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2869 {LQ, 0xfc000000, 0xe0000000, 0xf, // Load Quadword DQ-form (lq RTp,DQ(RA)) 2870 [5]*argField{ap_Reg_6_10, ap_Offset_16_27_shift4, ap_Reg_11_15}}, 2871 {STQ, 0xfc000003, 0xf8000002, 0x0, // Store Quadword DS-form (stq RSp,DS(RA)) 2872 [5]*argField{ap_Reg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 2873 {LHBRX, 0xfc0007fe, 0x7c00062c, 0x1, // Load Halfword Byte-Reverse Indexed X-form (lhbrx RT,RA,RB) 2874 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2875 {LWBRX, 0xfc0007fe, 0x7c00042c, 0x1, // Load Word Byte-Reverse Indexed X-form (lwbrx RT,RA,RB) 2876 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2877 {STHBRX, 0xfc0007fe, 0x7c00072c, 0x1, // Store Halfword Byte-Reverse Indexed X-form (sthbrx RS,RA,RB) 2878 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2879 {STWBRX, 0xfc0007fe, 0x7c00052c, 0x1, // Store Word Byte-Reverse Indexed X-form (stwbrx RS,RA,RB) 2880 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2881 {LDBRX, 0xfc0007fe, 0x7c000428, 0x1, // Load Doubleword Byte-Reverse Indexed X-form (ldbrx RT,RA,RB) 2882 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2883 {STDBRX, 0xfc0007fe, 0x7c000528, 0x1, // Store Doubleword Byte-Reverse Indexed X-form (stdbrx RS,RA,RB) 2884 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2885 {LMW, 0xfc000000, 0xb8000000, 0x0, // Load Multiple Word D-form (lmw RT,D(RA)) 2886 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2887 {STMW, 0xfc000000, 0xbc000000, 0x0, // Store Multiple Word D-form (stmw RS,D(RA)) 2888 [5]*argField{ap_Reg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 2889 {LSWI, 0xfc0007fe, 0x7c0004aa, 0x1, // Load String Word Immediate X-form (lswi RT,RA,NB) 2890 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, 2891 {LSWX, 0xfc0007fe, 0x7c00042a, 0x1, // Load String Word Indexed X-form (lswx RT,RA,RB) 2892 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2893 {STSWI, 0xfc0007fe, 0x7c0005aa, 0x1, // Store String Word Immediate X-form (stswi RS,RA,NB) 2894 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, 2895 {STSWX, 0xfc0007fe, 0x7c00052a, 0x1, // Store String Word Indexed X-form (stswx RS,RA,RB) 2896 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2897 {LI, 0xfc1f0000, 0x38000000, 0x0, // Add Immediate D-form (li RT,SI) 2898 [5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}}, 2899 {ADDI, 0xfc000000, 0x38000000, 0x0, // Add Immediate D-form (addi RT,RA,SI) 2900 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 2901 {LIS, 0xfc1f0000, 0x3c000000, 0x0, // Add Immediate Shifted D-form (lis RT, SI) 2902 [5]*argField{ap_Reg_6_10, ap_ImmSigned_16_31}}, 2903 {ADDIS, 0xfc000000, 0x3c000000, 0x0, // Add Immediate Shifted D-form (addis RT,RA,SI) 2904 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 2905 {ADD, 0xfc0007ff, 0x7c000214, 0x0, // Add XO-form (add RT,RA,RB) 2906 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2907 {ADD_, 0xfc0007ff, 0x7c000215, 0x0, // Add XO-form (add. RT,RA,RB) 2908 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2909 {ADDO, 0xfc0007ff, 0x7c000614, 0x0, // Add XO-form (addo RT,RA,RB) 2910 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2911 {ADDO_, 0xfc0007ff, 0x7c000615, 0x0, // Add XO-form (addo. RT,RA,RB) 2912 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2913 {ADDIC, 0xfc000000, 0x30000000, 0x0, // Add Immediate Carrying D-form (addic RT,RA,SI) 2914 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 2915 {SUBF, 0xfc0007ff, 0x7c000050, 0x0, // Subtract From XO-form (subf RT,RA,RB) 2916 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2917 {SUBF_, 0xfc0007ff, 0x7c000051, 0x0, // Subtract From XO-form (subf. RT,RA,RB) 2918 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2919 {SUBFO, 0xfc0007ff, 0x7c000450, 0x0, // Subtract From XO-form (subfo RT,RA,RB) 2920 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2921 {SUBFO_, 0xfc0007ff, 0x7c000451, 0x0, // Subtract From XO-form (subfo. RT,RA,RB) 2922 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2923 {ADDIC_, 0xfc000000, 0x34000000, 0x0, // Add Immediate Carrying and Record D-form (addic. RT,RA,SI) 2924 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 2925 {SUBFIC, 0xfc000000, 0x20000000, 0x0, // Subtract From Immediate Carrying D-form (subfic RT,RA,SI) 2926 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 2927 {ADDC, 0xfc0007ff, 0x7c000014, 0x0, // Add Carrying XO-form (addc RT,RA,RB) 2928 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2929 {ADDC_, 0xfc0007ff, 0x7c000015, 0x0, // Add Carrying XO-form (addc. RT,RA,RB) 2930 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2931 {ADDCO, 0xfc0007ff, 0x7c000414, 0x0, // Add Carrying XO-form (addco RT,RA,RB) 2932 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2933 {ADDCO_, 0xfc0007ff, 0x7c000415, 0x0, // Add Carrying XO-form (addco. RT,RA,RB) 2934 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2935 {SUBFC, 0xfc0007ff, 0x7c000010, 0x0, // Subtract From Carrying XO-form (subfc RT,RA,RB) 2936 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2937 {SUBFC_, 0xfc0007ff, 0x7c000011, 0x0, // Subtract From Carrying XO-form (subfc. RT,RA,RB) 2938 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2939 {SUBFCO, 0xfc0007ff, 0x7c000410, 0x0, // Subtract From Carrying XO-form (subfco RT,RA,RB) 2940 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2941 {SUBFCO_, 0xfc0007ff, 0x7c000411, 0x0, // Subtract From Carrying XO-form (subfco. RT,RA,RB) 2942 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2943 {ADDE, 0xfc0007ff, 0x7c000114, 0x0, // Add Extended XO-form (adde RT,RA,RB) 2944 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2945 {ADDE_, 0xfc0007ff, 0x7c000115, 0x0, // Add Extended XO-form (adde. RT,RA,RB) 2946 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2947 {ADDEO, 0xfc0007ff, 0x7c000514, 0x0, // Add Extended XO-form (addeo RT,RA,RB) 2948 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2949 {ADDEO_, 0xfc0007ff, 0x7c000515, 0x0, // Add Extended XO-form (addeo. RT,RA,RB) 2950 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2951 {ADDME, 0xfc0007ff, 0x7c0001d4, 0xf800, // Add to Minus One Extended XO-form (addme RT,RA) 2952 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2953 {ADDME_, 0xfc0007ff, 0x7c0001d5, 0xf800, // Add to Minus One Extended XO-form (addme. RT,RA) 2954 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2955 {ADDMEO, 0xfc0007ff, 0x7c0005d4, 0xf800, // Add to Minus One Extended XO-form (addmeo RT,RA) 2956 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2957 {ADDMEO_, 0xfc0007ff, 0x7c0005d5, 0xf800, // Add to Minus One Extended XO-form (addmeo. RT,RA) 2958 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2959 {SUBFE, 0xfc0007ff, 0x7c000110, 0x0, // Subtract From Extended XO-form (subfe RT,RA,RB) 2960 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2961 {SUBFE_, 0xfc0007ff, 0x7c000111, 0x0, // Subtract From Extended XO-form (subfe. RT,RA,RB) 2962 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2963 {SUBFEO, 0xfc0007ff, 0x7c000510, 0x0, // Subtract From Extended XO-form (subfeo RT,RA,RB) 2964 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2965 {SUBFEO_, 0xfc0007ff, 0x7c000511, 0x0, // Subtract From Extended XO-form (subfeo. RT,RA,RB) 2966 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 2967 {SUBFME, 0xfc0007ff, 0x7c0001d0, 0xf800, // Subtract From Minus One Extended XO-form (subfme RT,RA) 2968 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2969 {SUBFME_, 0xfc0007ff, 0x7c0001d1, 0xf800, // Subtract From Minus One Extended XO-form (subfme. RT,RA) 2970 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2971 {SUBFMEO, 0xfc0007ff, 0x7c0005d0, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo RT,RA) 2972 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2973 {SUBFMEO_, 0xfc0007ff, 0x7c0005d1, 0xf800, // Subtract From Minus One Extended XO-form (subfmeo. RT,RA) 2974 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2975 {ADDZE, 0xfc0007ff, 0x7c000194, 0xf800, // Add to Zero Extended XO-form (addze RT,RA) 2976 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2977 {ADDZE_, 0xfc0007ff, 0x7c000195, 0xf800, // Add to Zero Extended XO-form (addze. RT,RA) 2978 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2979 {ADDZEO, 0xfc0007ff, 0x7c000594, 0xf800, // Add to Zero Extended XO-form (addzeo RT,RA) 2980 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2981 {ADDZEO_, 0xfc0007ff, 0x7c000595, 0xf800, // Add to Zero Extended XO-form (addzeo. RT,RA) 2982 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2983 {SUBFZE, 0xfc0007ff, 0x7c000190, 0xf800, // Subtract From Zero Extended XO-form (subfze RT,RA) 2984 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2985 {SUBFZE_, 0xfc0007ff, 0x7c000191, 0xf800, // Subtract From Zero Extended XO-form (subfze. RT,RA) 2986 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2987 {SUBFZEO, 0xfc0007ff, 0x7c000590, 0xf800, // Subtract From Zero Extended XO-form (subfzeo RT,RA) 2988 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2989 {SUBFZEO_, 0xfc0007ff, 0x7c000591, 0xf800, // Subtract From Zero Extended XO-form (subfzeo. RT,RA) 2990 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2991 {NEG, 0xfc0007ff, 0x7c0000d0, 0xf800, // Negate XO-form (neg RT,RA) 2992 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2993 {NEG_, 0xfc0007ff, 0x7c0000d1, 0xf800, // Negate XO-form (neg. RT,RA) 2994 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2995 {NEGO, 0xfc0007ff, 0x7c0004d0, 0xf800, // Negate XO-form (nego RT,RA) 2996 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2997 {NEGO_, 0xfc0007ff, 0x7c0004d1, 0xf800, // Negate XO-form (nego. RT,RA) 2998 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 2999 {MULLI, 0xfc000000, 0x1c000000, 0x0, // Multiply Low Immediate D-form (mulli RT,RA,SI) 3000 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 3001 {MULLW, 0xfc0007ff, 0x7c0001d6, 0x0, // Multiply Low Word XO-form (mullw RT,RA,RB) 3002 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3003 {MULLW_, 0xfc0007ff, 0x7c0001d7, 0x0, // Multiply Low Word XO-form (mullw. RT,RA,RB) 3004 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3005 {MULLWO, 0xfc0007ff, 0x7c0005d6, 0x0, // Multiply Low Word XO-form (mullwo RT,RA,RB) 3006 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3007 {MULLWO_, 0xfc0007ff, 0x7c0005d7, 0x0, // Multiply Low Word XO-form (mullwo. RT,RA,RB) 3008 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3009 {MULHW, 0xfc0003ff, 0x7c000096, 0x400, // Multiply High Word XO-form (mulhw RT,RA,RB) 3010 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3011 {MULHW_, 0xfc0003ff, 0x7c000097, 0x400, // Multiply High Word XO-form (mulhw. RT,RA,RB) 3012 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3013 {MULHWU, 0xfc0003ff, 0x7c000016, 0x400, // Multiply High Word Unsigned XO-form (mulhwu RT,RA,RB) 3014 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3015 {MULHWU_, 0xfc0003ff, 0x7c000017, 0x400, // Multiply High Word Unsigned XO-form (mulhwu. RT,RA,RB) 3016 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3017 {DIVW, 0xfc0007ff, 0x7c0003d6, 0x0, // Divide Word XO-form (divw RT,RA,RB) 3018 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3019 {DIVW_, 0xfc0007ff, 0x7c0003d7, 0x0, // Divide Word XO-form (divw. RT,RA,RB) 3020 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3021 {DIVWO, 0xfc0007ff, 0x7c0007d6, 0x0, // Divide Word XO-form (divwo RT,RA,RB) 3022 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3023 {DIVWO_, 0xfc0007ff, 0x7c0007d7, 0x0, // Divide Word XO-form (divwo. RT,RA,RB) 3024 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3025 {DIVWU, 0xfc0007ff, 0x7c000396, 0x0, // Divide Word Unsigned XO-form (divwu RT,RA,RB) 3026 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3027 {DIVWU_, 0xfc0007ff, 0x7c000397, 0x0, // Divide Word Unsigned XO-form (divwu. RT,RA,RB) 3028 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3029 {DIVWUO, 0xfc0007ff, 0x7c000796, 0x0, // Divide Word Unsigned XO-form (divwuo RT,RA,RB) 3030 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3031 {DIVWUO_, 0xfc0007ff, 0x7c000797, 0x0, // Divide Word Unsigned XO-form (divwuo. RT,RA,RB) 3032 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3033 {DIVWE, 0xfc0007ff, 0x7c000356, 0x0, // Divide Word Extended XO-form (divwe RT,RA,RB) 3034 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3035 {DIVWE_, 0xfc0007ff, 0x7c000357, 0x0, // Divide Word Extended XO-form (divwe. RT,RA,RB) 3036 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3037 {DIVWEO, 0xfc0007ff, 0x7c000756, 0x0, // Divide Word Extended XO-form (divweo RT,RA,RB) 3038 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3039 {DIVWEO_, 0xfc0007ff, 0x7c000757, 0x0, // Divide Word Extended XO-form (divweo. RT,RA,RB) 3040 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3041 {DIVWEU, 0xfc0007ff, 0x7c000316, 0x0, // Divide Word Extended Unsigned XO-form (divweu RT,RA,RB) 3042 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3043 {DIVWEU_, 0xfc0007ff, 0x7c000317, 0x0, // Divide Word Extended Unsigned XO-form (divweu. RT,RA,RB) 3044 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3045 {DIVWEUO, 0xfc0007ff, 0x7c000716, 0x0, // Divide Word Extended Unsigned XO-form (divweuo RT,RA,RB) 3046 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3047 {DIVWEUO_, 0xfc0007ff, 0x7c000717, 0x0, // Divide Word Extended Unsigned XO-form (divweuo. RT,RA,RB) 3048 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3049 {MULLD, 0xfc0007ff, 0x7c0001d2, 0x0, // Multiply Low Doubleword XO-form (mulld RT,RA,RB) 3050 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3051 {MULLD_, 0xfc0007ff, 0x7c0001d3, 0x0, // Multiply Low Doubleword XO-form (mulld. RT,RA,RB) 3052 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3053 {MULLDO, 0xfc0007ff, 0x7c0005d2, 0x0, // Multiply Low Doubleword XO-form (mulldo RT,RA,RB) 3054 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3055 {MULLDO_, 0xfc0007ff, 0x7c0005d3, 0x0, // Multiply Low Doubleword XO-form (mulldo. RT,RA,RB) 3056 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3057 {MULHDU, 0xfc0003ff, 0x7c000012, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu RT,RA,RB) 3058 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3059 {MULHDU_, 0xfc0003ff, 0x7c000013, 0x400, // Multiply High Doubleword Unsigned XO-form (mulhdu. RT,RA,RB) 3060 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3061 {MULHD, 0xfc0003ff, 0x7c000092, 0x400, // Multiply High Doubleword XO-form (mulhd RT,RA,RB) 3062 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3063 {MULHD_, 0xfc0003ff, 0x7c000093, 0x400, // Multiply High Doubleword XO-form (mulhd. RT,RA,RB) 3064 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3065 {DIVD, 0xfc0007ff, 0x7c0003d2, 0x0, // Divide Doubleword XO-form (divd RT,RA,RB) 3066 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3067 {DIVD_, 0xfc0007ff, 0x7c0003d3, 0x0, // Divide Doubleword XO-form (divd. RT,RA,RB) 3068 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3069 {DIVDO, 0xfc0007ff, 0x7c0007d2, 0x0, // Divide Doubleword XO-form (divdo RT,RA,RB) 3070 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3071 {DIVDO_, 0xfc0007ff, 0x7c0007d3, 0x0, // Divide Doubleword XO-form (divdo. RT,RA,RB) 3072 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3073 {DIVDU, 0xfc0007ff, 0x7c000392, 0x0, // Divide Doubleword Unsigned XO-form (divdu RT,RA,RB) 3074 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3075 {DIVDU_, 0xfc0007ff, 0x7c000393, 0x0, // Divide Doubleword Unsigned XO-form (divdu. RT,RA,RB) 3076 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3077 {DIVDUO, 0xfc0007ff, 0x7c000792, 0x0, // Divide Doubleword Unsigned XO-form (divduo RT,RA,RB) 3078 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3079 {DIVDUO_, 0xfc0007ff, 0x7c000793, 0x0, // Divide Doubleword Unsigned XO-form (divduo. RT,RA,RB) 3080 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3081 {DIVDE, 0xfc0007ff, 0x7c000352, 0x0, // Divide Doubleword Extended XO-form (divde RT,RA,RB) 3082 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3083 {DIVDE_, 0xfc0007ff, 0x7c000353, 0x0, // Divide Doubleword Extended XO-form (divde. RT,RA,RB) 3084 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3085 {DIVDEO, 0xfc0007ff, 0x7c000752, 0x0, // Divide Doubleword Extended XO-form (divdeo RT,RA,RB) 3086 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3087 {DIVDEO_, 0xfc0007ff, 0x7c000753, 0x0, // Divide Doubleword Extended XO-form (divdeo. RT,RA,RB) 3088 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3089 {DIVDEU, 0xfc0007ff, 0x7c000312, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu RT,RA,RB) 3090 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3091 {DIVDEU_, 0xfc0007ff, 0x7c000313, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeu. RT,RA,RB) 3092 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3093 {DIVDEUO, 0xfc0007ff, 0x7c000712, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo RT,RA,RB) 3094 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3095 {DIVDEUO_, 0xfc0007ff, 0x7c000713, 0x0, // Divide Doubleword Extended Unsigned XO-form (divdeuo. RT,RA,RB) 3096 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3097 {CMPWI, 0xfc200000, 0x2c000000, 0x400000, // Compare Immediate D-form (cmpwi BF,RA,SI) 3098 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}}, 3099 {CMPDI, 0xfc200000, 0x2c200000, 0x400000, // Compare Immediate D-form (cmpdi BF,RA,SI) 3100 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmSigned_16_31}}, 3101 {CMPW, 0xfc2007fe, 0x7c000000, 0x400001, // Compare X-form (cmpw BF,RA,RB) 3102 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 3103 {CMPD, 0xfc2007fe, 0x7c200000, 0x400001, // Compare X-form (cmpd BF,RA,RB) 3104 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 3105 {CMPLWI, 0xfc200000, 0x28000000, 0x400000, // Compare Logical Immediate D-form (cmplwi BF,RA,UI) 3106 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}}, 3107 {CMPLDI, 0xfc200000, 0x28200000, 0x400000, // Compare Logical Immediate D-form (cmpldi BF,RA,UI) 3108 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_ImmUnsigned_16_31}}, 3109 {CMPLW, 0xfc2007fe, 0x7c000040, 0x400001, // Compare Logical X-form (cmplw BF,RA,RB) 3110 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 3111 {CMPLD, 0xfc2007fe, 0x7c200040, 0x400001, // Compare Logical X-form (cmpld BF,RA,RB) 3112 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 3113 {TWI, 0xfc000000, 0xc000000, 0x0, // Trap Word Immediate D-form (twi TO,RA,SI) 3114 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 3115 {TW, 0xfc0007fe, 0x7c000008, 0x1, // Trap Word X-form (tw TO,RA,RB) 3116 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3117 {TDI, 0xfc000000, 0x8000000, 0x0, // Trap Doubleword Immediate D-form (tdi TO,RA,SI) 3118 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_31}}, 3119 {ISEL, 0xfc00003e, 0x7c00001e, 0x1, // Integer Select A-form (isel RT,RA,RB,BC) 3120 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegBit_21_25}}, 3121 {TD, 0xfc0007fe, 0x7c000088, 0x1, // Trap Doubleword X-form (td TO,RA,RB) 3122 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3123 {ANDI_, 0xfc000000, 0x70000000, 0x0, // AND Immediate D-form (andi. RA,RS,UI) 3124 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, 3125 {ANDIS_, 0xfc000000, 0x74000000, 0x0, // AND Immediate Shifted D-form (andis. RA,RS,UI) 3126 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, 3127 {ORI, 0xfc000000, 0x60000000, 0x0, // OR Immediate D-form (ori RA,RS,UI) 3128 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, 3129 {ORIS, 0xfc000000, 0x64000000, 0x0, // OR Immediate Shifted D-form (oris RA,RS,UI) 3130 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, 3131 {XORI, 0xfc000000, 0x68000000, 0x0, // XOR Immediate D-form (xori RA,RS,UI) 3132 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, 3133 {XORIS, 0xfc000000, 0x6c000000, 0x0, // XOR Immediate Shifted D-form (xoris RA,RS,UI) 3134 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_31}}, 3135 {AND, 0xfc0007ff, 0x7c000038, 0x0, // AND X-form (and RA,RS,RB) 3136 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3137 {AND_, 0xfc0007ff, 0x7c000039, 0x0, // AND X-form (and. RA,RS,RB) 3138 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3139 {XOR, 0xfc0007ff, 0x7c000278, 0x0, // XOR X-form (xor RA,RS,RB) 3140 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3141 {XOR_, 0xfc0007ff, 0x7c000279, 0x0, // XOR X-form (xor. RA,RS,RB) 3142 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3143 {NAND, 0xfc0007ff, 0x7c0003b8, 0x0, // NAND X-form (nand RA,RS,RB) 3144 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3145 {NAND_, 0xfc0007ff, 0x7c0003b9, 0x0, // NAND X-form (nand. RA,RS,RB) 3146 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3147 {OR, 0xfc0007ff, 0x7c000378, 0x0, // OR X-form (or RA,RS,RB) 3148 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3149 {OR_, 0xfc0007ff, 0x7c000379, 0x0, // OR X-form (or. RA,RS,RB) 3150 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3151 {NOR, 0xfc0007ff, 0x7c0000f8, 0x0, // NOR X-form (nor RA,RS,RB) 3152 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3153 {NOR_, 0xfc0007ff, 0x7c0000f9, 0x0, // NOR X-form (nor. RA,RS,RB) 3154 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3155 {ANDC, 0xfc0007ff, 0x7c000078, 0x0, // AND with Complement X-form (andc RA,RS,RB) 3156 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3157 {ANDC_, 0xfc0007ff, 0x7c000079, 0x0, // AND with Complement X-form (andc. RA,RS,RB) 3158 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3159 {EXTSB, 0xfc0007ff, 0x7c000774, 0xf800, // Extend Sign Byte X-form (extsb RA,RS) 3160 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3161 {EXTSB_, 0xfc0007ff, 0x7c000775, 0xf800, // Extend Sign Byte X-form (extsb. RA,RS) 3162 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3163 {EQV, 0xfc0007ff, 0x7c000238, 0x0, // Equivalent X-form (eqv RA,RS,RB) 3164 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3165 {EQV_, 0xfc0007ff, 0x7c000239, 0x0, // Equivalent X-form (eqv. RA,RS,RB) 3166 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3167 {ORC, 0xfc0007ff, 0x7c000338, 0x0, // OR with Complement X-form (orc RA,RS,RB) 3168 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3169 {ORC_, 0xfc0007ff, 0x7c000339, 0x0, // OR with Complement X-form (orc. RA,RS,RB) 3170 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3171 {EXTSH, 0xfc0007ff, 0x7c000734, 0xf800, // Extend Sign Halfword X-form (extsh RA,RS) 3172 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3173 {EXTSH_, 0xfc0007ff, 0x7c000735, 0xf800, // Extend Sign Halfword X-form (extsh. RA,RS) 3174 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3175 {CMPB, 0xfc0007fe, 0x7c0003f8, 0x1, // Compare Bytes X-form (cmpb RA,RS,RB) 3176 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3177 {POPCNTB, 0xfc0007fe, 0x7c0000f4, 0xf801, // Population Count Bytes X-form (popcntb RA, RS) 3178 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3179 {POPCNTW, 0xfc0007fe, 0x7c0002f4, 0xf801, // Population Count Words X-form (popcntw RA, RS) 3180 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3181 {PRTYD, 0xfc0007fe, 0x7c000174, 0xf801, // Parity Doubleword X-form (prtyd RA,RS) 3182 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3183 {PRTYW, 0xfc0007fe, 0x7c000134, 0xf801, // Parity Word X-form (prtyw RA,RS) 3184 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3185 {EXTSW, 0xfc0007ff, 0x7c0007b4, 0xf800, // Extend Sign Word X-form (extsw RA,RS) 3186 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3187 {EXTSW_, 0xfc0007ff, 0x7c0007b5, 0xf800, // Extend Sign Word X-form (extsw. RA,RS) 3188 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3189 {CNTLZD, 0xfc0007ff, 0x7c000074, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd RA,RS) 3190 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3191 {CNTLZD_, 0xfc0007ff, 0x7c000075, 0xf800, // Count Leading Zeros Doubleword X-form (cntlzd. RA,RS) 3192 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3193 {POPCNTD, 0xfc0007fe, 0x7c0003f4, 0xf801, // Population Count Doubleword X-form (popcntd RA, RS) 3194 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3195 {BPERMD, 0xfc0007fe, 0x7c0001f8, 0x1, // Bit Permute Doubleword X-form (bpermd RA,RS,RB) 3196 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3197 {RLWINM, 0xfc000001, 0x54000000, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm RA,RS,SH,MB,ME) 3198 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, 3199 {RLWINM_, 0xfc000001, 0x54000001, 0x0, // Rotate Left Word Immediate then AND with Mask M-form (rlwinm. RA,RS,SH,MB,ME) 3200 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, 3201 {RLWNM, 0xfc000001, 0x5c000000, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm RA,RS,RB,MB,ME) 3202 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, 3203 {RLWNM_, 0xfc000001, 0x5c000001, 0x0, // Rotate Left Word then AND with Mask M-form (rlwnm. RA,RS,RB,MB,ME) 3204 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, 3205 {RLWIMI, 0xfc000001, 0x50000000, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi RA,RS,SH,MB,ME) 3206 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, 3207 {RLWIMI_, 0xfc000001, 0x50000001, 0x0, // Rotate Left Word Immediate then Mask Insert M-form (rlwimi. RA,RS,SH,MB,ME) 3208 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_ImmUnsigned_21_25, ap_ImmUnsigned_26_30}}, 3209 {RLDICL, 0xfc00001d, 0x78000000, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl RA,RS,SH,MB) 3210 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 3211 {RLDICL_, 0xfc00001d, 0x78000001, 0x0, // Rotate Left Doubleword Immediate then Clear Left MD-form (rldicl. RA,RS,SH,MB) 3212 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 3213 {RLDICR, 0xfc00001d, 0x78000004, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr RA,RS,SH,ME) 3214 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 3215 {RLDICR_, 0xfc00001d, 0x78000005, 0x0, // Rotate Left Doubleword Immediate then Clear Right MD-form (rldicr. RA,RS,SH,ME) 3216 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 3217 {RLDIC, 0xfc00001d, 0x78000008, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic RA,RS,SH,MB) 3218 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 3219 {RLDIC_, 0xfc00001d, 0x78000009, 0x0, // Rotate Left Doubleword Immediate then Clear MD-form (rldic. RA,RS,SH,MB) 3220 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 3221 {RLDCL, 0xfc00001f, 0x78000010, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl RA,RS,RB,MB) 3222 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, 3223 {RLDCL_, 0xfc00001f, 0x78000011, 0x0, // Rotate Left Doubleword then Clear Left MDS-form (rldcl. RA,RS,RB,MB) 3224 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, 3225 {RLDCR, 0xfc00001f, 0x78000012, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr RA,RS,RB,ME) 3226 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, 3227 {RLDCR_, 0xfc00001f, 0x78000013, 0x0, // Rotate Left Doubleword then Clear Right MDS-form (rldcr. RA,RS,RB,ME) 3228 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_26_26_21_25}}, 3229 {RLDIMI, 0xfc00001d, 0x7800000c, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi RA,RS,SH,MB) 3230 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 3231 {RLDIMI_, 0xfc00001d, 0x7800000d, 0x0, // Rotate Left Doubleword Immediate then Mask Insert MD-form (rldimi. RA,RS,SH,MB) 3232 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20, ap_ImmUnsigned_26_26_21_25}}, 3233 {SLW, 0xfc0007ff, 0x7c000030, 0x0, // Shift Left Word X-form (slw RA,RS,RB) 3234 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3235 {SLW_, 0xfc0007ff, 0x7c000031, 0x0, // Shift Left Word X-form (slw. RA,RS,RB) 3236 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3237 {SRW, 0xfc0007ff, 0x7c000430, 0x0, // Shift Right Word X-form (srw RA,RS,RB) 3238 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3239 {SRW_, 0xfc0007ff, 0x7c000431, 0x0, // Shift Right Word X-form (srw. RA,RS,RB) 3240 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3241 {SRAWI, 0xfc0007ff, 0x7c000670, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi RA,RS,SH) 3242 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}}, 3243 {SRAWI_, 0xfc0007ff, 0x7c000671, 0x0, // Shift Right Algebraic Word Immediate X-form (srawi. RA,RS,SH) 3244 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_16_20}}, 3245 {SRAW, 0xfc0007ff, 0x7c000630, 0x0, // Shift Right Algebraic Word X-form (sraw RA,RS,RB) 3246 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3247 {SRAW_, 0xfc0007ff, 0x7c000631, 0x0, // Shift Right Algebraic Word X-form (sraw. RA,RS,RB) 3248 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3249 {SLD, 0xfc0007ff, 0x7c000036, 0x0, // Shift Left Doubleword X-form (sld RA,RS,RB) 3250 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3251 {SLD_, 0xfc0007ff, 0x7c000037, 0x0, // Shift Left Doubleword X-form (sld. RA,RS,RB) 3252 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3253 {SRD, 0xfc0007ff, 0x7c000436, 0x0, // Shift Right Doubleword X-form (srd RA,RS,RB) 3254 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3255 {SRD_, 0xfc0007ff, 0x7c000437, 0x0, // Shift Right Doubleword X-form (srd. RA,RS,RB) 3256 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3257 {SRADI, 0xfc0007fd, 0x7c000674, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi RA,RS,SH) 3258 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}}, 3259 {SRADI_, 0xfc0007fd, 0x7c000675, 0x0, // Shift Right Algebraic Doubleword Immediate XS-form (sradi. RA,RS,SH) 3260 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_ImmUnsigned_30_30_16_20}}, 3261 {SRAD, 0xfc0007ff, 0x7c000634, 0x0, // Shift Right Algebraic Doubleword X-form (srad RA,RS,RB) 3262 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3263 {SRAD_, 0xfc0007ff, 0x7c000635, 0x0, // Shift Right Algebraic Doubleword X-form (srad. RA,RS,RB) 3264 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 3265 {CDTBCD, 0xfc0007fe, 0x7c000234, 0xf801, // Convert Declets To Binary Coded Decimal X-form (cdtbcd RA, RS) 3266 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3267 {CBCDTD, 0xfc0007fe, 0x7c000274, 0xf801, // Convert Binary Coded Decimal To Declets X-form (cbcdtd RA, RS) 3268 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 3269 {ADDG6S, 0xfc0003fe, 0x7c000094, 0x401, // Add and Generate Sixes XO-form (addg6s RT,RA,RB) 3270 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3271 {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS) 3272 [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, 3273 {MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR) 3274 [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, 3275 {MTCRF, 0xfc1007fe, 0x7c000120, 0x801, // Move To Condition Register Fields XFX-form (mtcrf FXM,RS) 3276 [5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}}, 3277 {MFCR, 0xfc1007fe, 0x7c000026, 0xff801, // Move From Condition Register XFX-form (mfcr RT) 3278 [5]*argField{ap_Reg_6_10}}, 3279 {MTSLE, 0xfc0007fe, 0x7c000126, 0x3dff801, // Move To Split Little Endian X-form (mtsle L) 3280 [5]*argField{ap_ImmUnsigned_10_10}}, 3281 {MFVSRD, 0xfc0007fe, 0x7c000066, 0xf800, // Move From VSR Doubleword XX1-form (mfvsrd RA,XS) 3282 [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}}, 3283 {MFVSRWZ, 0xfc0007fe, 0x7c0000e6, 0xf800, // Move From VSR Word and Zero XX1-form (mfvsrwz RA,XS) 3284 [5]*argField{ap_Reg_11_15, ap_VecSReg_31_31_6_10}}, 3285 {MTVSRD, 0xfc0007fe, 0x7c000166, 0xf800, // Move To VSR Doubleword XX1-form (mtvsrd XT,RA) 3286 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, 3287 {MTVSRWA, 0xfc0007fe, 0x7c0001a6, 0xf800, // Move To VSR Word Algebraic XX1-form (mtvsrwa XT,RA) 3288 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, 3289 {MTVSRWZ, 0xfc0007fe, 0x7c0001e6, 0xf800, // Move To VSR Word and Zero XX1-form (mtvsrwz XT,RA) 3290 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15}}, 3291 {MTOCRF, 0xfc1007fe, 0x7c100120, 0x801, // Move To One Condition Register Field XFX-form (mtocrf FXM,RS) 3292 [5]*argField{ap_ImmUnsigned_12_19, ap_Reg_6_10}}, 3293 {MFOCRF, 0xfc1007fe, 0x7c100026, 0x801, // Move From One Condition Register Field XFX-form (mfocrf RT,FXM) 3294 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_12_19}}, 3295 {MCRXR, 0xfc0007fe, 0x7c000400, 0x7ff801, // Move to Condition Register from XER X-form (mcrxr BF) 3296 [5]*argField{ap_CondRegField_6_8}}, 3297 {MTDCRUX, 0xfc0007fe, 0x7c000346, 0xf801, // Move To Device Control Register User-mode Indexed X-form (mtdcrux RS,RA) 3298 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 3299 {MFDCRUX, 0xfc0007fe, 0x7c000246, 0xf801, // Move From Device Control Register User-mode Indexed X-form (mfdcrux RT,RA) 3300 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 3301 {LFS, 0xfc000000, 0xc0000000, 0x0, // Load Floating-Point Single D-form (lfs FRT,D(RA)) 3302 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 3303 {LFSU, 0xfc000000, 0xc4000000, 0x0, // Load Floating-Point Single with Update D-form (lfsu FRT,D(RA)) 3304 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 3305 {LFSX, 0xfc0007fe, 0x7c00042e, 0x1, // Load Floating-Point Single Indexed X-form (lfsx FRT,RA,RB) 3306 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3307 {LFSUX, 0xfc0007fe, 0x7c00046e, 0x1, // Load Floating-Point Single with Update Indexed X-form (lfsux FRT,RA,RB) 3308 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3309 {LFD, 0xfc000000, 0xc8000000, 0x0, // Load Floating-Point Double D-form (lfd FRT,D(RA)) 3310 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 3311 {LFDU, 0xfc000000, 0xcc000000, 0x0, // Load Floating-Point Double with Update D-form (lfdu FRT,D(RA)) 3312 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 3313 {LFDX, 0xfc0007fe, 0x7c0004ae, 0x1, // Load Floating-Point Double Indexed X-form (lfdx FRT,RA,RB) 3314 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3315 {LFDUX, 0xfc0007fe, 0x7c0004ee, 0x1, // Load Floating-Point Double with Update Indexed X-form (lfdux FRT,RA,RB) 3316 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3317 {LFIWAX, 0xfc0007fe, 0x7c0006ae, 0x1, // Load Floating-Point as Integer Word Algebraic Indexed X-form (lfiwax FRT,RA,RB) 3318 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3319 {LFIWZX, 0xfc0007fe, 0x7c0006ee, 0x1, // Load Floating-Point as Integer Word and Zero Indexed X-form (lfiwzx FRT,RA,RB) 3320 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3321 {STFS, 0xfc000000, 0xd0000000, 0x0, // Store Floating-Point Single D-form (stfs FRS,D(RA)) 3322 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 3323 {STFSU, 0xfc000000, 0xd4000000, 0x0, // Store Floating-Point Single with Update D-form (stfsu FRS,D(RA)) 3324 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 3325 {STFSX, 0xfc0007fe, 0x7c00052e, 0x1, // Store Floating-Point Single Indexed X-form (stfsx FRS,RA,RB) 3326 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3327 {STFSUX, 0xfc0007fe, 0x7c00056e, 0x1, // Store Floating-Point Single with Update Indexed X-form (stfsux FRS,RA,RB) 3328 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3329 {STFD, 0xfc000000, 0xd8000000, 0x0, // Store Floating-Point Double D-form (stfd FRS,D(RA)) 3330 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 3331 {STFDU, 0xfc000000, 0xdc000000, 0x0, // Store Floating-Point Double with Update D-form (stfdu FRS,D(RA)) 3332 [5]*argField{ap_FPReg_6_10, ap_Offset_16_31, ap_Reg_11_15}}, 3333 {STFDX, 0xfc0007fe, 0x7c0005ae, 0x1, // Store Floating-Point Double Indexed X-form (stfdx FRS,RA,RB) 3334 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3335 {STFDUX, 0xfc0007fe, 0x7c0005ee, 0x1, // Store Floating-Point Double with Update Indexed X-form (stfdux FRS,RA,RB) 3336 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3337 {STFIWX, 0xfc0007fe, 0x7c0007ae, 0x1, // Store Floating-Point as Integer Word Indexed X-form (stfiwx FRS,RA,RB) 3338 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3339 {LFDP, 0xfc000003, 0xe4000000, 0x0, // Load Floating-Point Double Pair DS-form (lfdp FRTp,DS(RA)) 3340 [5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 3341 {LFDPX, 0xfc0007fe, 0x7c00062e, 0x1, // Load Floating-Point Double Pair Indexed X-form (lfdpx FRTp,RA,RB) 3342 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3343 {STFDP, 0xfc000003, 0xf4000000, 0x0, // Store Floating-Point Double Pair DS-form (stfdp FRSp,DS(RA)) 3344 [5]*argField{ap_FPReg_6_10, ap_Offset_16_29_shift2, ap_Reg_11_15}}, 3345 {STFDPX, 0xfc0007fe, 0x7c00072e, 0x1, // Store Floating-Point Double Pair Indexed X-form (stfdpx FRSp,RA,RB) 3346 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3347 {FMR, 0xfc0007ff, 0xfc000090, 0x1f0000, // Floating Move Register X-form (fmr FRT,FRB) 3348 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3349 {FMR_, 0xfc0007ff, 0xfc000091, 0x1f0000, // Floating Move Register X-form (fmr. FRT,FRB) 3350 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3351 {FABS, 0xfc0007ff, 0xfc000210, 0x1f0000, // Floating Absolute Value X-form (fabs FRT,FRB) 3352 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3353 {FABS_, 0xfc0007ff, 0xfc000211, 0x1f0000, // Floating Absolute Value X-form (fabs. FRT,FRB) 3354 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3355 {FNABS, 0xfc0007ff, 0xfc000110, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs FRT,FRB) 3356 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3357 {FNABS_, 0xfc0007ff, 0xfc000111, 0x1f0000, // Floating Negative Absolute Value X-form (fnabs. FRT,FRB) 3358 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3359 {FNEG, 0xfc0007ff, 0xfc000050, 0x1f0000, // Floating Negate X-form (fneg FRT,FRB) 3360 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3361 {FNEG_, 0xfc0007ff, 0xfc000051, 0x1f0000, // Floating Negate X-form (fneg. FRT,FRB) 3362 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3363 {FCPSGN, 0xfc0007ff, 0xfc000010, 0x0, // Floating Copy Sign X-form (fcpsgn FRT, FRA, FRB) 3364 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3365 {FCPSGN_, 0xfc0007ff, 0xfc000011, 0x0, // Floating Copy Sign X-form (fcpsgn. FRT, FRA, FRB) 3366 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3367 {FMRGEW, 0xfc0007fe, 0xfc00078c, 0x1, // Floating Merge Even Word X-form (fmrgew FRT,FRA,FRB) 3368 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3369 {FMRGOW, 0xfc0007fe, 0xfc00068c, 0x1, // Floating Merge Odd Word X-form (fmrgow FRT,FRA,FRB) 3370 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3371 {FADD, 0xfc00003f, 0xfc00002a, 0x7c0, // Floating Add [Single] A-form (fadd FRT,FRA,FRB) 3372 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3373 {FADD_, 0xfc00003f, 0xfc00002b, 0x7c0, // Floating Add [Single] A-form (fadd. FRT,FRA,FRB) 3374 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3375 {FADDS, 0xfc00003f, 0xec00002a, 0x7c0, // Floating Add [Single] A-form (fadds FRT,FRA,FRB) 3376 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3377 {FADDS_, 0xfc00003f, 0xec00002b, 0x7c0, // Floating Add [Single] A-form (fadds. FRT,FRA,FRB) 3378 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3379 {FSUB, 0xfc00003f, 0xfc000028, 0x7c0, // Floating Subtract [Single] A-form (fsub FRT,FRA,FRB) 3380 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3381 {FSUB_, 0xfc00003f, 0xfc000029, 0x7c0, // Floating Subtract [Single] A-form (fsub. FRT,FRA,FRB) 3382 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3383 {FSUBS, 0xfc00003f, 0xec000028, 0x7c0, // Floating Subtract [Single] A-form (fsubs FRT,FRA,FRB) 3384 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3385 {FSUBS_, 0xfc00003f, 0xec000029, 0x7c0, // Floating Subtract [Single] A-form (fsubs. FRT,FRA,FRB) 3386 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3387 {FMUL, 0xfc00003f, 0xfc000032, 0xf800, // Floating Multiply [Single] A-form (fmul FRT,FRA,FRC) 3388 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, 3389 {FMUL_, 0xfc00003f, 0xfc000033, 0xf800, // Floating Multiply [Single] A-form (fmul. FRT,FRA,FRC) 3390 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, 3391 {FMULS, 0xfc00003f, 0xec000032, 0xf800, // Floating Multiply [Single] A-form (fmuls FRT,FRA,FRC) 3392 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, 3393 {FMULS_, 0xfc00003f, 0xec000033, 0xf800, // Floating Multiply [Single] A-form (fmuls. FRT,FRA,FRC) 3394 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25}}, 3395 {FDIV, 0xfc00003f, 0xfc000024, 0x7c0, // Floating Divide [Single] A-form (fdiv FRT,FRA,FRB) 3396 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3397 {FDIV_, 0xfc00003f, 0xfc000025, 0x7c0, // Floating Divide [Single] A-form (fdiv. FRT,FRA,FRB) 3398 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3399 {FDIVS, 0xfc00003f, 0xec000024, 0x7c0, // Floating Divide [Single] A-form (fdivs FRT,FRA,FRB) 3400 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3401 {FDIVS_, 0xfc00003f, 0xec000025, 0x7c0, // Floating Divide [Single] A-form (fdivs. FRT,FRA,FRB) 3402 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 3403 {FSQRT, 0xfc00003f, 0xfc00002c, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrt FRT,FRB) 3404 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3405 {FSQRT_, 0xfc00003f, 0xfc00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrt. FRT,FRB) 3406 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3407 {FSQRTS, 0xfc00003f, 0xec00002c, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrts FRT,FRB) 3408 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3409 {FSQRTS_, 0xfc00003f, 0xec00002d, 0x1f07c0, // Floating Square Root [Single] A-form (fsqrts. FRT,FRB) 3410 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3411 {FRE, 0xfc00003f, 0xfc000030, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fre FRT,FRB) 3412 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3413 {FRE_, 0xfc00003f, 0xfc000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fre. FRT,FRB) 3414 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3415 {FRES, 0xfc00003f, 0xec000030, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fres FRT,FRB) 3416 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3417 {FRES_, 0xfc00003f, 0xec000031, 0x1f07c0, // Floating Reciprocal Estimate [Single] A-form (fres. FRT,FRB) 3418 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3419 {FRSQRTE, 0xfc00003f, 0xfc000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrte FRT,FRB) 3420 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3421 {FRSQRTE_, 0xfc00003f, 0xfc000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrte. FRT,FRB) 3422 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3423 {FRSQRTES, 0xfc00003f, 0xec000034, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrtes FRT,FRB) 3424 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3425 {FRSQRTES_, 0xfc00003f, 0xec000035, 0x1f07c0, // Floating Reciprocal Square Root Estimate [Single] A-form (frsqrtes. FRT,FRB) 3426 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3427 {FTDIV, 0xfc0007fe, 0xfc000100, 0x600001, // Floating Test for software Divide X-form (ftdiv BF,FRA,FRB) 3428 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 3429 {FTSQRT, 0xfc0007fe, 0xfc000140, 0x7f0001, // Floating Test for software Square Root X-form (ftsqrt BF,FRB) 3430 [5]*argField{ap_CondRegField_6_8, ap_FPReg_16_20}}, 3431 {FMADD, 0xfc00003f, 0xfc00003a, 0x0, // Floating Multiply-Add [Single] A-form (fmadd FRT,FRA,FRC,FRB) 3432 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3433 {FMADD_, 0xfc00003f, 0xfc00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadd. FRT,FRA,FRC,FRB) 3434 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3435 {FMADDS, 0xfc00003f, 0xec00003a, 0x0, // Floating Multiply-Add [Single] A-form (fmadds FRT,FRA,FRC,FRB) 3436 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3437 {FMADDS_, 0xfc00003f, 0xec00003b, 0x0, // Floating Multiply-Add [Single] A-form (fmadds. FRT,FRA,FRC,FRB) 3438 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3439 {FMSUB, 0xfc00003f, 0xfc000038, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsub FRT,FRA,FRC,FRB) 3440 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3441 {FMSUB_, 0xfc00003f, 0xfc000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsub. FRT,FRA,FRC,FRB) 3442 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3443 {FMSUBS, 0xfc00003f, 0xec000038, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsubs FRT,FRA,FRC,FRB) 3444 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3445 {FMSUBS_, 0xfc00003f, 0xec000039, 0x0, // Floating Multiply-Subtract [Single] A-form (fmsubs. FRT,FRA,FRC,FRB) 3446 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3447 {FNMADD, 0xfc00003f, 0xfc00003e, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadd FRT,FRA,FRC,FRB) 3448 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3449 {FNMADD_, 0xfc00003f, 0xfc00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadd. FRT,FRA,FRC,FRB) 3450 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3451 {FNMADDS, 0xfc00003f, 0xec00003e, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadds FRT,FRA,FRC,FRB) 3452 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3453 {FNMADDS_, 0xfc00003f, 0xec00003f, 0x0, // Floating Negative Multiply-Add [Single] A-form (fnmadds. FRT,FRA,FRC,FRB) 3454 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3455 {FNMSUB, 0xfc00003f, 0xfc00003c, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsub FRT,FRA,FRC,FRB) 3456 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3457 {FNMSUB_, 0xfc00003f, 0xfc00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsub. FRT,FRA,FRC,FRB) 3458 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3459 {FNMSUBS, 0xfc00003f, 0xec00003c, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsubs FRT,FRA,FRC,FRB) 3460 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3461 {FNMSUBS_, 0xfc00003f, 0xec00003d, 0x0, // Floating Negative Multiply-Subtract [Single] A-form (fnmsubs. FRT,FRA,FRC,FRB) 3462 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3463 {FRSP, 0xfc0007ff, 0xfc000018, 0x1f0000, // Floating Round to Single-Precision X-form (frsp FRT,FRB) 3464 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3465 {FRSP_, 0xfc0007ff, 0xfc000019, 0x1f0000, // Floating Round to Single-Precision X-form (frsp. FRT,FRB) 3466 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3467 {FCTID, 0xfc0007ff, 0xfc00065c, 0x1f0000, // Floating Convert To Integer Doubleword X-form (fctid FRT,FRB) 3468 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3469 {FCTID_, 0xfc0007ff, 0xfc00065d, 0x1f0000, // Floating Convert To Integer Doubleword X-form (fctid. FRT,FRB) 3470 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3471 {FCTIDZ, 0xfc0007ff, 0xfc00065e, 0x1f0000, // Floating Convert To Integer Doubleword with round toward Zero X-form (fctidz FRT,FRB) 3472 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3473 {FCTIDZ_, 0xfc0007ff, 0xfc00065f, 0x1f0000, // Floating Convert To Integer Doubleword with round toward Zero X-form (fctidz. FRT,FRB) 3474 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3475 {FCTIDU, 0xfc0007ff, 0xfc00075c, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned X-form (fctidu FRT,FRB) 3476 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3477 {FCTIDU_, 0xfc0007ff, 0xfc00075d, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned X-form (fctidu. FRT,FRB) 3478 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3479 {FCTIDUZ, 0xfc0007ff, 0xfc00075e, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form (fctiduz FRT,FRB) 3480 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3481 {FCTIDUZ_, 0xfc0007ff, 0xfc00075f, 0x1f0000, // Floating Convert To Integer Doubleword Unsigned with round toward Zero X-form (fctiduz. FRT,FRB) 3482 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3483 {FCTIW, 0xfc0007ff, 0xfc00001c, 0x1f0000, // Floating Convert To Integer Word X-form (fctiw FRT,FRB) 3484 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3485 {FCTIW_, 0xfc0007ff, 0xfc00001d, 0x1f0000, // Floating Convert To Integer Word X-form (fctiw. FRT,FRB) 3486 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3487 {FCTIWZ, 0xfc0007ff, 0xfc00001e, 0x1f0000, // Floating Convert To Integer Word with round toward Zero X-form (fctiwz FRT,FRB) 3488 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3489 {FCTIWZ_, 0xfc0007ff, 0xfc00001f, 0x1f0000, // Floating Convert To Integer Word with round toward Zero X-form (fctiwz. FRT,FRB) 3490 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3491 {FCTIWU, 0xfc0007ff, 0xfc00011c, 0x1f0000, // Floating Convert To Integer Word Unsigned X-form (fctiwu FRT,FRB) 3492 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3493 {FCTIWU_, 0xfc0007ff, 0xfc00011d, 0x1f0000, // Floating Convert To Integer Word Unsigned X-form (fctiwu. FRT,FRB) 3494 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3495 {FCTIWUZ, 0xfc0007ff, 0xfc00011e, 0x1f0000, // Floating Convert To Integer Word Unsigned with round toward Zero X-form (fctiwuz FRT,FRB) 3496 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3497 {FCTIWUZ_, 0xfc0007ff, 0xfc00011f, 0x1f0000, // Floating Convert To Integer Word Unsigned with round toward Zero X-form (fctiwuz. FRT,FRB) 3498 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3499 {FCFID, 0xfc0007ff, 0xfc00069c, 0x1f0000, // Floating Convert From Integer Doubleword X-form (fcfid FRT,FRB) 3500 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3501 {FCFID_, 0xfc0007ff, 0xfc00069d, 0x1f0000, // Floating Convert From Integer Doubleword X-form (fcfid. FRT,FRB) 3502 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3503 {FCFIDU, 0xfc0007ff, 0xfc00079c, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned X-form (fcfidu FRT,FRB) 3504 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3505 {FCFIDU_, 0xfc0007ff, 0xfc00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned X-form (fcfidu. FRT,FRB) 3506 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3507 {FCFIDS, 0xfc0007ff, 0xec00069c, 0x1f0000, // Floating Convert From Integer Doubleword Single X-form (fcfids FRT,FRB) 3508 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3509 {FCFIDS_, 0xfc0007ff, 0xec00069d, 0x1f0000, // Floating Convert From Integer Doubleword Single X-form (fcfids. FRT,FRB) 3510 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3511 {FCFIDUS, 0xfc0007ff, 0xec00079c, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned Single X-form (fcfidus FRT,FRB) 3512 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3513 {FCFIDUS_, 0xfc0007ff, 0xec00079d, 0x1f0000, // Floating Convert From Integer Doubleword Unsigned Single X-form (fcfidus. FRT,FRB) 3514 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3515 {FRIN, 0xfc0007ff, 0xfc000310, 0x1f0000, // Floating Round to Integer Nearest X-form (frin FRT,FRB) 3516 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3517 {FRIN_, 0xfc0007ff, 0xfc000311, 0x1f0000, // Floating Round to Integer Nearest X-form (frin. FRT,FRB) 3518 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3519 {FRIZ, 0xfc0007ff, 0xfc000350, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz FRT,FRB) 3520 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3521 {FRIZ_, 0xfc0007ff, 0xfc000351, 0x1f0000, // Floating Round to Integer Toward Zero X-form (friz. FRT,FRB) 3522 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3523 {FRIP, 0xfc0007ff, 0xfc000390, 0x1f0000, // Floating Round to Integer Plus X-form (frip FRT,FRB) 3524 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3525 {FRIP_, 0xfc0007ff, 0xfc000391, 0x1f0000, // Floating Round to Integer Plus X-form (frip. FRT,FRB) 3526 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3527 {FRIM, 0xfc0007ff, 0xfc0003d0, 0x1f0000, // Floating Round to Integer Minus X-form (frim FRT,FRB) 3528 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3529 {FRIM_, 0xfc0007ff, 0xfc0003d1, 0x1f0000, // Floating Round to Integer Minus X-form (frim. FRT,FRB) 3530 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 3531 {FCMPU, 0xfc0007fe, 0xfc000000, 0x600001, // Floating Compare Unordered X-form (fcmpu BF,FRA,FRB) 3532 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 3533 {FCMPO, 0xfc0007fe, 0xfc000040, 0x600001, // Floating Compare Ordered X-form (fcmpo BF,FRA,FRB) 3534 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 3535 {FSEL, 0xfc00003f, 0xfc00002e, 0x0, // Floating Select A-form (fsel FRT,FRA,FRC,FRB) 3536 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3537 {FSEL_, 0xfc00003f, 0xfc00002f, 0x0, // Floating Select A-form (fsel. FRT,FRA,FRC,FRB) 3538 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_21_25, ap_FPReg_16_20}}, 3539 {MFFS, 0xfc0007ff, 0xfc00048e, 0x1ff800, // Move From FPSCR X-form (mffs FRT) 3540 [5]*argField{ap_FPReg_6_10}}, 3541 {MFFS_, 0xfc0007ff, 0xfc00048f, 0x1ff800, // Move From FPSCR X-form (mffs. FRT) 3542 [5]*argField{ap_FPReg_6_10}}, 3543 {MCRFS, 0xfc0007fe, 0xfc000080, 0x63f801, // Move to Condition Register from FPSCR X-form (mcrfs BF,BFA) 3544 [5]*argField{ap_CondRegField_6_8, ap_CondRegField_11_13}}, 3545 {MTFSFI, 0xfc0007ff, 0xfc00010c, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi BF,U,W) 3546 [5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}}, 3547 {MTFSFI_, 0xfc0007ff, 0xfc00010d, 0x7e0800, // Move To FPSCR Field Immediate X-form (mtfsfi. BF,U,W) 3548 [5]*argField{ap_CondRegField_6_8, ap_ImmUnsigned_16_19, ap_ImmUnsigned_15_15}}, 3549 {MTFSF, 0xfc0007ff, 0xfc00058e, 0x0, // Move To FPSCR Fields XFL-form (mtfsf FLM,FRB,L,W) 3550 [5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}}, 3551 {MTFSF_, 0xfc0007ff, 0xfc00058f, 0x0, // Move To FPSCR Fields XFL-form (mtfsf. FLM,FRB,L,W) 3552 [5]*argField{ap_ImmUnsigned_7_14, ap_FPReg_16_20, ap_ImmUnsigned_6_6, ap_ImmUnsigned_15_15}}, 3553 {MTFSB0, 0xfc0007ff, 0xfc00008c, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0 BT) 3554 [5]*argField{ap_CondRegBit_6_10}}, 3555 {MTFSB0_, 0xfc0007ff, 0xfc00008d, 0x1ff800, // Move To FPSCR Bit 0 X-form (mtfsb0. BT) 3556 [5]*argField{ap_CondRegBit_6_10}}, 3557 {MTFSB1, 0xfc0007ff, 0xfc00004c, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1 BT) 3558 [5]*argField{ap_CondRegBit_6_10}}, 3559 {MTFSB1_, 0xfc0007ff, 0xfc00004d, 0x1ff800, // Move To FPSCR Bit 1 X-form (mtfsb1. BT) 3560 [5]*argField{ap_CondRegBit_6_10}}, 3561 {LVEBX, 0xfc0007fe, 0x7c00000e, 0x1, // Load Vector Element Byte Indexed X-form (lvebx VRT,RA,RB) 3562 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3563 {LVEHX, 0xfc0007fe, 0x7c00004e, 0x1, // Load Vector Element Halfword Indexed X-form (lvehx VRT,RA,RB) 3564 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3565 {LVEWX, 0xfc0007fe, 0x7c00008e, 0x1, // Load Vector Element Word Indexed X-form (lvewx VRT,RA,RB) 3566 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3567 {LVX, 0xfc0007fe, 0x7c0000ce, 0x1, // Load Vector Indexed X-form (lvx VRT,RA,RB) 3568 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3569 {LVXL, 0xfc0007fe, 0x7c0002ce, 0x1, // Load Vector Indexed LRU X-form (lvxl VRT,RA,RB) 3570 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3571 {STVEBX, 0xfc0007fe, 0x7c00010e, 0x1, // Store Vector Element Byte Indexed X-form (stvebx VRS,RA,RB) 3572 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3573 {STVEHX, 0xfc0007fe, 0x7c00014e, 0x1, // Store Vector Element Halfword Indexed X-form (stvehx VRS,RA,RB) 3574 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3575 {STVEWX, 0xfc0007fe, 0x7c00018e, 0x1, // Store Vector Element Word Indexed X-form (stvewx VRS,RA,RB) 3576 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3577 {STVX, 0xfc0007fe, 0x7c0001ce, 0x1, // Store Vector Indexed X-form (stvx VRS,RA,RB) 3578 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3579 {STVXL, 0xfc0007fe, 0x7c0003ce, 0x1, // Store Vector Indexed LRU X-form (stvxl VRS,RA,RB) 3580 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3581 {LVSL, 0xfc0007fe, 0x7c00000c, 0x1, // Load Vector for Shift Left Indexed X-form (lvsl VRT,RA,RB) 3582 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3583 {LVSR, 0xfc0007fe, 0x7c00004c, 0x1, // Load Vector for Shift Right Indexed X-form (lvsr VRT,RA,RB) 3584 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 3585 {VPKPX, 0xfc0007ff, 0x1000030e, 0x0, // Vector Pack Pixel VX-form (vpkpx VRT,VRA,VRB) 3586 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3587 {VPKSDSS, 0xfc0007ff, 0x100005ce, 0x0, // Vector Pack Signed Doubleword Signed Saturate VX-form (vpksdss VRT,VRA,VRB) 3588 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3589 {VPKSDUS, 0xfc0007ff, 0x1000054e, 0x0, // Vector Pack Signed Doubleword Unsigned Saturate VX-form (vpksdus VRT,VRA,VRB) 3590 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3591 {VPKSHSS, 0xfc0007ff, 0x1000018e, 0x0, // Vector Pack Signed Halfword Signed Saturate VX-form (vpkshss VRT,VRA,VRB) 3592 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3593 {VPKSHUS, 0xfc0007ff, 0x1000010e, 0x0, // Vector Pack Signed Halfword Unsigned Saturate VX-form (vpkshus VRT,VRA,VRB) 3594 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3595 {VPKSWSS, 0xfc0007ff, 0x100001ce, 0x0, // Vector Pack Signed Word Signed Saturate VX-form (vpkswss VRT,VRA,VRB) 3596 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3597 {VPKSWUS, 0xfc0007ff, 0x1000014e, 0x0, // Vector Pack Signed Word Unsigned Saturate VX-form (vpkswus VRT,VRA,VRB) 3598 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3599 {VPKUDUM, 0xfc0007ff, 0x1000044e, 0x0, // Vector Pack Unsigned Doubleword Unsigned Modulo VX-form (vpkudum VRT,VRA,VRB) 3600 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3601 {VPKUDUS, 0xfc0007ff, 0x100004ce, 0x0, // Vector Pack Unsigned Doubleword Unsigned Saturate VX-form (vpkudus VRT,VRA,VRB) 3602 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3603 {VPKUHUM, 0xfc0007ff, 0x1000000e, 0x0, // Vector Pack Unsigned Halfword Unsigned Modulo VX-form (vpkuhum VRT,VRA,VRB) 3604 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3605 {VPKUHUS, 0xfc0007ff, 0x1000008e, 0x0, // Vector Pack Unsigned Halfword Unsigned Saturate VX-form (vpkuhus VRT,VRA,VRB) 3606 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3607 {VPKUWUM, 0xfc0007ff, 0x1000004e, 0x0, // Vector Pack Unsigned Word Unsigned Modulo VX-form (vpkuwum VRT,VRA,VRB) 3608 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3609 {VPKUWUS, 0xfc0007ff, 0x100000ce, 0x0, // Vector Pack Unsigned Word Unsigned Saturate VX-form (vpkuwus VRT,VRA,VRB) 3610 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3611 {VUPKHPX, 0xfc0007ff, 0x1000034e, 0x1f0000, // Vector Unpack High Pixel VX-form (vupkhpx VRT,VRB) 3612 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3613 {VUPKLPX, 0xfc0007ff, 0x100003ce, 0x1f0000, // Vector Unpack Low Pixel VX-form (vupklpx VRT,VRB) 3614 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3615 {VUPKHSB, 0xfc0007ff, 0x1000020e, 0x1f0000, // Vector Unpack High Signed Byte VX-form (vupkhsb VRT,VRB) 3616 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3617 {VUPKHSH, 0xfc0007ff, 0x1000024e, 0x1f0000, // Vector Unpack High Signed Halfword VX-form (vupkhsh VRT,VRB) 3618 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3619 {VUPKHSW, 0xfc0007ff, 0x1000064e, 0x1f0000, // Vector Unpack High Signed Word VX-form (vupkhsw VRT,VRB) 3620 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3621 {VUPKLSB, 0xfc0007ff, 0x1000028e, 0x1f0000, // Vector Unpack Low Signed Byte VX-form (vupklsb VRT,VRB) 3622 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3623 {VUPKLSH, 0xfc0007ff, 0x100002ce, 0x1f0000, // Vector Unpack Low Signed Halfword VX-form (vupklsh VRT,VRB) 3624 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3625 {VUPKLSW, 0xfc0007ff, 0x100006ce, 0x1f0000, // Vector Unpack Low Signed Word VX-form (vupklsw VRT,VRB) 3626 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3627 {VMRGHB, 0xfc0007ff, 0x1000000c, 0x0, // Vector Merge High Byte VX-form (vmrghb VRT,VRA,VRB) 3628 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3629 {VMRGHH, 0xfc0007ff, 0x1000004c, 0x0, // Vector Merge High Halfword VX-form (vmrghh VRT,VRA,VRB) 3630 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3631 {VMRGLB, 0xfc0007ff, 0x1000010c, 0x0, // Vector Merge Low Byte VX-form (vmrglb VRT,VRA,VRB) 3632 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3633 {VMRGLH, 0xfc0007ff, 0x1000014c, 0x0, // Vector Merge Low Halfword VX-form (vmrglh VRT,VRA,VRB) 3634 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3635 {VMRGHW, 0xfc0007ff, 0x1000008c, 0x0, // Vector Merge High Word VX-form (vmrghw VRT,VRA,VRB) 3636 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3637 {VMRGLW, 0xfc0007ff, 0x1000018c, 0x0, // Vector Merge Low Word VX-form (vmrglw VRT,VRA,VRB) 3638 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3639 {VMRGEW, 0xfc0007ff, 0x1000078c, 0x0, // Vector Merge Even Word VX-form (vmrgew VRT,VRA,VRB) 3640 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3641 {VMRGOW, 0xfc0007ff, 0x1000068c, 0x0, // Vector Merge Odd Word VX-form (vmrgow VRT,VRA,VRB) 3642 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3643 {VSPLTB, 0xfc0007ff, 0x1000020c, 0x100000, // Vector Splat Byte VX-form (vspltb VRT,VRB,UIM) 3644 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_12_15}}, 3645 {VSPLTH, 0xfc0007ff, 0x1000024c, 0x180000, // Vector Splat Halfword VX-form (vsplth VRT,VRB,UIM) 3646 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_13_15}}, 3647 {VSPLTW, 0xfc0007ff, 0x1000028c, 0x1c0000, // Vector Splat Word VX-form (vspltw VRT,VRB,UIM) 3648 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_14_15}}, 3649 {VSPLTISB, 0xfc0007ff, 0x1000030c, 0xf800, // Vector Splat Immediate Signed Byte VX-form (vspltisb VRT,SIM) 3650 [5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}}, 3651 {VSPLTISH, 0xfc0007ff, 0x1000034c, 0xf800, // Vector Splat Immediate Signed Halfword VX-form (vspltish VRT,SIM) 3652 [5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}}, 3653 {VSPLTISW, 0xfc0007ff, 0x1000038c, 0xf800, // Vector Splat Immediate Signed Word VX-form (vspltisw VRT,SIM) 3654 [5]*argField{ap_VecReg_6_10, ap_ImmSigned_11_15}}, 3655 {VPERM, 0xfc00003f, 0x1000002b, 0x0, // Vector Permute VA-form (vperm VRT,VRA,VRB,VRC) 3656 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3657 {VSEL, 0xfc00003f, 0x1000002a, 0x0, // Vector Select VA-form (vsel VRT,VRA,VRB,VRC) 3658 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3659 {VSL, 0xfc0007ff, 0x100001c4, 0x0, // Vector Shift Left VX-form (vsl VRT,VRA,VRB) 3660 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3661 {VSLDOI, 0xfc00003f, 0x1000002c, 0x400, // Vector Shift Left Double by Octet Immediate VA-form (vsldoi VRT,VRA,VRB,SHB) 3662 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_25}}, 3663 {VSLO, 0xfc0007ff, 0x1000040c, 0x0, // Vector Shift Left by Octet VX-form (vslo VRT,VRA,VRB) 3664 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3665 {VSR, 0xfc0007ff, 0x100002c4, 0x0, // Vector Shift Right VX-form (vsr VRT,VRA,VRB) 3666 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3667 {VSRO, 0xfc0007ff, 0x1000044c, 0x0, // Vector Shift Right by Octet VX-form (vsro VRT,VRA,VRB) 3668 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3669 {VADDCUW, 0xfc0007ff, 0x10000180, 0x0, // Vector Add and Write Carry-Out Unsigned Word VX-form (vaddcuw VRT,VRA,VRB) 3670 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3671 {VADDSBS, 0xfc0007ff, 0x10000300, 0x0, // Vector Add Signed Byte Saturate VX-form (vaddsbs VRT,VRA,VRB) 3672 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3673 {VADDSHS, 0xfc0007ff, 0x10000340, 0x0, // Vector Add Signed Halfword Saturate VX-form (vaddshs VRT,VRA,VRB) 3674 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3675 {VADDSWS, 0xfc0007ff, 0x10000380, 0x0, // Vector Add Signed Word Saturate VX-form (vaddsws VRT,VRA,VRB) 3676 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3677 {VADDUBM, 0xfc0007ff, 0x10000000, 0x0, // Vector Add Unsigned Byte Modulo VX-form (vaddubm VRT,VRA,VRB) 3678 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3679 {VADDUDM, 0xfc0007ff, 0x100000c0, 0x0, // Vector Add Unsigned Doubleword Modulo VX-form (vaddudm VRT,VRA,VRB) 3680 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3681 {VADDUHM, 0xfc0007ff, 0x10000040, 0x0, // Vector Add Unsigned Halfword Modulo VX-form (vadduhm VRT,VRA,VRB) 3682 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3683 {VADDUWM, 0xfc0007ff, 0x10000080, 0x0, // Vector Add Unsigned Word Modulo VX-form (vadduwm VRT,VRA,VRB) 3684 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3685 {VADDUBS, 0xfc0007ff, 0x10000200, 0x0, // Vector Add Unsigned Byte Saturate VX-form (vaddubs VRT,VRA,VRB) 3686 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3687 {VADDUHS, 0xfc0007ff, 0x10000240, 0x0, // Vector Add Unsigned Halfword Saturate VX-form (vadduhs VRT,VRA,VRB) 3688 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3689 {VADDUWS, 0xfc0007ff, 0x10000280, 0x0, // Vector Add Unsigned Word Saturate VX-form (vadduws VRT,VRA,VRB) 3690 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3691 {VADDUQM, 0xfc0007ff, 0x10000100, 0x0, // Vector Add Unsigned Quadword Modulo VX-form (vadduqm VRT,VRA,VRB) 3692 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3693 {VADDEUQM, 0xfc00003f, 0x1000003c, 0x0, // Vector Add Extended Unsigned Quadword Modulo VA-form (vaddeuqm VRT,VRA,VRB,VRC) 3694 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3695 {VADDCUQ, 0xfc0007ff, 0x10000140, 0x0, // Vector Add & write Carry Unsigned Quadword VX-form (vaddcuq VRT,VRA,VRB) 3696 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3697 {VADDECUQ, 0xfc00003f, 0x1000003d, 0x0, // Vector Add Extended & write Carry Unsigned Quadword VA-form (vaddecuq VRT,VRA,VRB,VRC) 3698 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3699 {VSUBCUW, 0xfc0007ff, 0x10000580, 0x0, // Vector Subtract and Write Carry-Out Unsigned Word VX-form (vsubcuw VRT,VRA,VRB) 3700 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3701 {VSUBSBS, 0xfc0007ff, 0x10000700, 0x0, // Vector Subtract Signed Byte Saturate VX-form (vsubsbs VRT,VRA,VRB) 3702 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3703 {VSUBSHS, 0xfc0007ff, 0x10000740, 0x0, // Vector Subtract Signed Halfword Saturate VX-form (vsubshs VRT,VRA,VRB) 3704 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3705 {VSUBSWS, 0xfc0007ff, 0x10000780, 0x0, // Vector Subtract Signed Word Saturate VX-form (vsubsws VRT,VRA,VRB) 3706 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3707 {VSUBUBM, 0xfc0007ff, 0x10000400, 0x0, // Vector Subtract Unsigned Byte Modulo VX-form (vsububm VRT,VRA,VRB) 3708 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3709 {VSUBUDM, 0xfc0007ff, 0x100004c0, 0x0, // Vector Subtract Unsigned Doubleword Modulo VX-form (vsubudm VRT,VRA,VRB) 3710 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3711 {VSUBUHM, 0xfc0007ff, 0x10000440, 0x0, // Vector Subtract Unsigned Halfword Modulo VX-form (vsubuhm VRT,VRA,VRB) 3712 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3713 {VSUBUWM, 0xfc0007ff, 0x10000480, 0x0, // Vector Subtract Unsigned Word Modulo VX-form (vsubuwm VRT,VRA,VRB) 3714 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3715 {VSUBUBS, 0xfc0007ff, 0x10000600, 0x0, // Vector Subtract Unsigned Byte Saturate VX-form (vsububs VRT,VRA,VRB) 3716 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3717 {VSUBUHS, 0xfc0007ff, 0x10000640, 0x0, // Vector Subtract Unsigned Halfword Saturate VX-form (vsubuhs VRT,VRA,VRB) 3718 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3719 {VSUBUWS, 0xfc0007ff, 0x10000680, 0x0, // Vector Subtract Unsigned Word Saturate VX-form (vsubuws VRT,VRA,VRB) 3720 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3721 {VSUBUQM, 0xfc0007ff, 0x10000500, 0x0, // Vector Subtract Unsigned Quadword Modulo VX-form (vsubuqm VRT,VRA,VRB) 3722 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3723 {VSUBEUQM, 0xfc00003f, 0x1000003e, 0x0, // Vector Subtract Extended Unsigned Quadword Modulo VA-form (vsubeuqm VRT,VRA,VRB,VRC) 3724 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3725 {VSUBCUQ, 0xfc0007ff, 0x10000540, 0x0, // Vector Subtract & write Carry Unsigned Quadword VX-form (vsubcuq VRT,VRA,VRB) 3726 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3727 {VSUBECUQ, 0xfc00003f, 0x1000003f, 0x0, // Vector Subtract Extended & write Carry Unsigned Quadword VA-form (vsubecuq VRT,VRA,VRB,VRC) 3728 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3729 {VMULESB, 0xfc0007ff, 0x10000308, 0x0, // Vector Multiply Even Signed Byte VX-form (vmulesb VRT,VRA,VRB) 3730 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3731 {VMULEUB, 0xfc0007ff, 0x10000208, 0x0, // Vector Multiply Even Unsigned Byte VX-form (vmuleub VRT,VRA,VRB) 3732 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3733 {VMULOSB, 0xfc0007ff, 0x10000108, 0x0, // Vector Multiply Odd Signed Byte VX-form (vmulosb VRT,VRA,VRB) 3734 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3735 {VMULOUB, 0xfc0007ff, 0x10000008, 0x0, // Vector Multiply Odd Unsigned Byte VX-form (vmuloub VRT,VRA,VRB) 3736 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3737 {VMULESH, 0xfc0007ff, 0x10000348, 0x0, // Vector Multiply Even Signed Halfword VX-form (vmulesh VRT,VRA,VRB) 3738 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3739 {VMULEUH, 0xfc0007ff, 0x10000248, 0x0, // Vector Multiply Even Unsigned Halfword VX-form (vmuleuh VRT,VRA,VRB) 3740 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3741 {VMULOSH, 0xfc0007ff, 0x10000148, 0x0, // Vector Multiply Odd Signed Halfword VX-form (vmulosh VRT,VRA,VRB) 3742 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3743 {VMULOUH, 0xfc0007ff, 0x10000048, 0x0, // Vector Multiply Odd Unsigned Halfword VX-form (vmulouh VRT,VRA,VRB) 3744 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3745 {VMULESW, 0xfc0007ff, 0x10000388, 0x0, // Vector Multiply Even Signed Word VX-form (vmulesw VRT,VRA,VRB) 3746 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3747 {VMULEUW, 0xfc0007ff, 0x10000288, 0x0, // Vector Multiply Even Unsigned Word VX-form (vmuleuw VRT,VRA,VRB) 3748 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3749 {VMULOSW, 0xfc0007ff, 0x10000188, 0x0, // Vector Multiply Odd Signed Word VX-form (vmulosw VRT,VRA,VRB) 3750 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3751 {VMULOUW, 0xfc0007ff, 0x10000088, 0x0, // Vector Multiply Odd Unsigned Word VX-form (vmulouw VRT,VRA,VRB) 3752 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3753 {VMULUWM, 0xfc0007ff, 0x10000089, 0x0, // Vector Multiply Unsigned Word Modulo VX-form (vmuluwm VRT,VRA,VRB) 3754 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3755 {VMHADDSHS, 0xfc00003f, 0x10000020, 0x0, // Vector Multiply-High-Add Signed Halfword Saturate VA-form (vmhaddshs VRT,VRA,VRB,VRC) 3756 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3757 {VMHRADDSHS, 0xfc00003f, 0x10000021, 0x0, // Vector Multiply-High-Round-Add Signed Halfword Saturate VA-form (vmhraddshs VRT,VRA,VRB,VRC) 3758 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3759 {VMLADDUHM, 0xfc00003f, 0x10000022, 0x0, // Vector Multiply-Low-Add Unsigned Halfword Modulo VA-form (vmladduhm VRT,VRA,VRB,VRC) 3760 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3761 {VMSUMUBM, 0xfc00003f, 0x10000024, 0x0, // Vector Multiply-Sum Unsigned Byte Modulo VA-form (vmsumubm VRT,VRA,VRB,VRC) 3762 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3763 {VMSUMMBM, 0xfc00003f, 0x10000025, 0x0, // Vector Multiply-Sum Mixed Byte Modulo VA-form (vmsummbm VRT,VRA,VRB,VRC) 3764 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3765 {VMSUMSHM, 0xfc00003f, 0x10000028, 0x0, // Vector Multiply-Sum Signed Halfword Modulo VA-form (vmsumshm VRT,VRA,VRB,VRC) 3766 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3767 {VMSUMSHS, 0xfc00003f, 0x10000029, 0x0, // Vector Multiply-Sum Signed Halfword Saturate VA-form (vmsumshs VRT,VRA,VRB,VRC) 3768 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3769 {VMSUMUHM, 0xfc00003f, 0x10000026, 0x0, // Vector Multiply-Sum Unsigned Halfword Modulo VA-form (vmsumuhm VRT,VRA,VRB,VRC) 3770 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3771 {VMSUMUHS, 0xfc00003f, 0x10000027, 0x0, // Vector Multiply-Sum Unsigned Halfword Saturate VA-form (vmsumuhs VRT,VRA,VRB,VRC) 3772 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3773 {VSUMSWS, 0xfc0007ff, 0x10000788, 0x0, // Vector Sum across Signed Word Saturate VX-form (vsumsws VRT,VRA,VRB) 3774 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3775 {VSUM2SWS, 0xfc0007ff, 0x10000688, 0x0, // Vector Sum across Half Signed Word Saturate VX-form (vsum2sws VRT,VRA,VRB) 3776 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3777 {VSUM4SBS, 0xfc0007ff, 0x10000708, 0x0, // Vector Sum across Quarter Signed Byte Saturate VX-form (vsum4sbs VRT,VRA,VRB) 3778 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3779 {VSUM4SHS, 0xfc0007ff, 0x10000648, 0x0, // Vector Sum across Quarter Signed Halfword Saturate VX-form (vsum4shs VRT,VRA,VRB) 3780 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3781 {VSUM4UBS, 0xfc0007ff, 0x10000608, 0x0, // Vector Sum across Quarter Unsigned Byte Saturate VX-form (vsum4ubs VRT,VRA,VRB) 3782 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3783 {VAVGSB, 0xfc0007ff, 0x10000502, 0x0, // Vector Average Signed Byte VX-form (vavgsb VRT,VRA,VRB) 3784 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3785 {VAVGSH, 0xfc0007ff, 0x10000542, 0x0, // Vector Average Signed Halfword VX-form (vavgsh VRT,VRA,VRB) 3786 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3787 {VAVGSW, 0xfc0007ff, 0x10000582, 0x0, // Vector Average Signed Word VX-form (vavgsw VRT,VRA,VRB) 3788 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3789 {VAVGUB, 0xfc0007ff, 0x10000402, 0x0, // Vector Average Unsigned Byte VX-form (vavgub VRT,VRA,VRB) 3790 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3791 {VAVGUW, 0xfc0007ff, 0x10000482, 0x0, // Vector Average Unsigned Word VX-form (vavguw VRT,VRA,VRB) 3792 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3793 {VAVGUH, 0xfc0007ff, 0x10000442, 0x0, // Vector Average Unsigned Halfword VX-form (vavguh VRT,VRA,VRB) 3794 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3795 {VMAXSB, 0xfc0007ff, 0x10000102, 0x0, // Vector Maximum Signed Byte VX-form (vmaxsb VRT,VRA,VRB) 3796 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3797 {VMAXSD, 0xfc0007ff, 0x100001c2, 0x0, // Vector Maximum Signed Doubleword VX-form (vmaxsd VRT,VRA,VRB) 3798 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3799 {VMAXUB, 0xfc0007ff, 0x10000002, 0x0, // Vector Maximum Unsigned Byte VX-form (vmaxub VRT,VRA,VRB) 3800 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3801 {VMAXUD, 0xfc0007ff, 0x100000c2, 0x0, // Vector Maximum Unsigned Doubleword VX-form (vmaxud VRT,VRA,VRB) 3802 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3803 {VMAXSH, 0xfc0007ff, 0x10000142, 0x0, // Vector Maximum Signed Halfword VX-form (vmaxsh VRT,VRA,VRB) 3804 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3805 {VMAXSW, 0xfc0007ff, 0x10000182, 0x0, // Vector Maximum Signed Word VX-form (vmaxsw VRT,VRA,VRB) 3806 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3807 {VMAXUH, 0xfc0007ff, 0x10000042, 0x0, // Vector Maximum Unsigned Halfword VX-form (vmaxuh VRT,VRA,VRB) 3808 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3809 {VMAXUW, 0xfc0007ff, 0x10000082, 0x0, // Vector Maximum Unsigned Word VX-form (vmaxuw VRT,VRA,VRB) 3810 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3811 {VMINSB, 0xfc0007ff, 0x10000302, 0x0, // Vector Minimum Signed Byte VX-form (vminsb VRT,VRA,VRB) 3812 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3813 {VMINSD, 0xfc0007ff, 0x100003c2, 0x0, // Vector Minimum Signed Doubleword VX-form (vminsd VRT,VRA,VRB) 3814 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3815 {VMINUB, 0xfc0007ff, 0x10000202, 0x0, // Vector Minimum Unsigned Byte VX-form (vminub VRT,VRA,VRB) 3816 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3817 {VMINUD, 0xfc0007ff, 0x100002c2, 0x0, // Vector Minimum Unsigned Doubleword VX-form (vminud VRT,VRA,VRB) 3818 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3819 {VMINSH, 0xfc0007ff, 0x10000342, 0x0, // Vector Minimum Signed Halfword VX-form (vminsh VRT,VRA,VRB) 3820 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3821 {VMINSW, 0xfc0007ff, 0x10000382, 0x0, // Vector Minimum Signed Word VX-form (vminsw VRT,VRA,VRB) 3822 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3823 {VMINUH, 0xfc0007ff, 0x10000242, 0x0, // Vector Minimum Unsigned Halfword VX-form (vminuh VRT,VRA,VRB) 3824 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3825 {VMINUW, 0xfc0007ff, 0x10000282, 0x0, // Vector Minimum Unsigned Word VX-form (vminuw VRT,VRA,VRB) 3826 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3827 {VCMPEQUB, 0xfc0007ff, 0x10000006, 0x0, // Vector Compare Equal To Unsigned Byte VC-form (vcmpequb VRT,VRA,VRB) 3828 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3829 {VCMPEQUB_, 0xfc0007ff, 0x10000406, 0x0, // Vector Compare Equal To Unsigned Byte VC-form (vcmpequb. VRT,VRA,VRB) 3830 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3831 {VCMPEQUH, 0xfc0007ff, 0x10000046, 0x0, // Vector Compare Equal To Unsigned Halfword VC-form (vcmpequh VRT,VRA,VRB) 3832 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3833 {VCMPEQUH_, 0xfc0007ff, 0x10000446, 0x0, // Vector Compare Equal To Unsigned Halfword VC-form (vcmpequh. VRT,VRA,VRB) 3834 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3835 {VCMPEQUW, 0xfc0007ff, 0x10000086, 0x0, // Vector Compare Equal To Unsigned Word VC-form (vcmpequw VRT,VRA,VRB) 3836 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3837 {VCMPEQUW_, 0xfc0007ff, 0x10000486, 0x0, // Vector Compare Equal To Unsigned Word VC-form (vcmpequw. VRT,VRA,VRB) 3838 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3839 {VCMPEQUD, 0xfc0007ff, 0x100000c7, 0x0, // Vector Compare Equal To Unsigned Doubleword VX-form (vcmpequd VRT,VRA,VRB) 3840 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3841 {VCMPEQUD_, 0xfc0007ff, 0x100004c7, 0x0, // Vector Compare Equal To Unsigned Doubleword VX-form (vcmpequd. VRT,VRA,VRB) 3842 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3843 {VCMPGTSB, 0xfc0007ff, 0x10000306, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb VRT,VRA,VRB) 3844 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3845 {VCMPGTSB_, 0xfc0007ff, 0x10000706, 0x0, // Vector Compare Greater Than Signed Byte VC-form (vcmpgtsb. VRT,VRA,VRB) 3846 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3847 {VCMPGTSD, 0xfc0007ff, 0x100003c7, 0x0, // Vector Compare Greater Than Signed Doubleword VX-form (vcmpgtsd VRT,VRA,VRB) 3848 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3849 {VCMPGTSD_, 0xfc0007ff, 0x100007c7, 0x0, // Vector Compare Greater Than Signed Doubleword VX-form (vcmpgtsd. VRT,VRA,VRB) 3850 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3851 {VCMPGTSH, 0xfc0007ff, 0x10000346, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh VRT,VRA,VRB) 3852 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3853 {VCMPGTSH_, 0xfc0007ff, 0x10000746, 0x0, // Vector Compare Greater Than Signed Halfword VC-form (vcmpgtsh. VRT,VRA,VRB) 3854 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3855 {VCMPGTSW, 0xfc0007ff, 0x10000386, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw VRT,VRA,VRB) 3856 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3857 {VCMPGTSW_, 0xfc0007ff, 0x10000786, 0x0, // Vector Compare Greater Than Signed Word VC-form (vcmpgtsw. VRT,VRA,VRB) 3858 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3859 {VCMPGTUB, 0xfc0007ff, 0x10000206, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub VRT,VRA,VRB) 3860 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3861 {VCMPGTUB_, 0xfc0007ff, 0x10000606, 0x0, // Vector Compare Greater Than Unsigned Byte VC-form (vcmpgtub. VRT,VRA,VRB) 3862 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3863 {VCMPGTUD, 0xfc0007ff, 0x100002c7, 0x0, // Vector Compare Greater Than Unsigned Doubleword VX-form (vcmpgtud VRT,VRA,VRB) 3864 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3865 {VCMPGTUD_, 0xfc0007ff, 0x100006c7, 0x0, // Vector Compare Greater Than Unsigned Doubleword VX-form (vcmpgtud. VRT,VRA,VRB) 3866 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3867 {VCMPGTUH, 0xfc0007ff, 0x10000246, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh VRT,VRA,VRB) 3868 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3869 {VCMPGTUH_, 0xfc0007ff, 0x10000646, 0x0, // Vector Compare Greater Than Unsigned Halfword VC-form (vcmpgtuh. VRT,VRA,VRB) 3870 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3871 {VCMPGTUW, 0xfc0007ff, 0x10000286, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw VRT,VRA,VRB) 3872 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3873 {VCMPGTUW_, 0xfc0007ff, 0x10000686, 0x0, // Vector Compare Greater Than Unsigned Word VC-form (vcmpgtuw. VRT,VRA,VRB) 3874 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3875 {VAND, 0xfc0007ff, 0x10000404, 0x0, // Vector Logical AND VX-form (vand VRT,VRA,VRB) 3876 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3877 {VANDC, 0xfc0007ff, 0x10000444, 0x0, // Vector Logical AND with Complement VX-form (vandc VRT,VRA,VRB) 3878 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3879 {VEQV, 0xfc0007ff, 0x10000684, 0x0, // Vector Logical Equivalent VX-form (veqv VRT,VRA,VRB) 3880 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3881 {VNAND, 0xfc0007ff, 0x10000584, 0x0, // Vector Logical NAND VX-form (vnand VRT,VRA,VRB) 3882 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3883 {VORC, 0xfc0007ff, 0x10000544, 0x0, // Vector Logical OR with Complement VX-form (vorc VRT,VRA,VRB) 3884 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3885 {VNOR, 0xfc0007ff, 0x10000504, 0x0, // Vector Logical NOR VX-form (vnor VRT,VRA,VRB) 3886 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3887 {VOR, 0xfc0007ff, 0x10000484, 0x0, // Vector Logical OR VX-form (vor VRT,VRA,VRB) 3888 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3889 {VXOR, 0xfc0007ff, 0x100004c4, 0x0, // Vector Logical XOR VX-form (vxor VRT,VRA,VRB) 3890 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3891 {VRLB, 0xfc0007ff, 0x10000004, 0x0, // Vector Rotate Left Byte VX-form (vrlb VRT,VRA,VRB) 3892 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3893 {VRLH, 0xfc0007ff, 0x10000044, 0x0, // Vector Rotate Left Halfword VX-form (vrlh VRT,VRA,VRB) 3894 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3895 {VRLW, 0xfc0007ff, 0x10000084, 0x0, // Vector Rotate Left Word VX-form (vrlw VRT,VRA,VRB) 3896 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3897 {VRLD, 0xfc0007ff, 0x100000c4, 0x0, // Vector Rotate Left Doubleword VX-form (vrld VRT,VRA,VRB) 3898 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3899 {VSLB, 0xfc0007ff, 0x10000104, 0x0, // Vector Shift Left Byte VX-form (vslb VRT,VRA,VRB) 3900 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3901 {VSLH, 0xfc0007ff, 0x10000144, 0x0, // Vector Shift Left Halfword VX-form (vslh VRT,VRA,VRB) 3902 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3903 {VSLW, 0xfc0007ff, 0x10000184, 0x0, // Vector Shift Left Word VX-form (vslw VRT,VRA,VRB) 3904 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3905 {VSLD, 0xfc0007ff, 0x100005c4, 0x0, // Vector Shift Left Doubleword VX-form (vsld VRT,VRA,VRB) 3906 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3907 {VSRB, 0xfc0007ff, 0x10000204, 0x0, // Vector Shift Right Byte VX-form (vsrb VRT,VRA,VRB) 3908 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3909 {VSRH, 0xfc0007ff, 0x10000244, 0x0, // Vector Shift Right Halfword VX-form (vsrh VRT,VRA,VRB) 3910 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3911 {VSRW, 0xfc0007ff, 0x10000284, 0x0, // Vector Shift Right Word VX-form (vsrw VRT,VRA,VRB) 3912 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3913 {VSRD, 0xfc0007ff, 0x100006c4, 0x0, // Vector Shift Right Doubleword VX-form (vsrd VRT,VRA,VRB) 3914 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3915 {VSRAB, 0xfc0007ff, 0x10000304, 0x0, // Vector Shift Right Algebraic Byte VX-form (vsrab VRT,VRA,VRB) 3916 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3917 {VSRAH, 0xfc0007ff, 0x10000344, 0x0, // Vector Shift Right Algebraic Halfword VX-form (vsrah VRT,VRA,VRB) 3918 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3919 {VSRAW, 0xfc0007ff, 0x10000384, 0x0, // Vector Shift Right Algebraic Word VX-form (vsraw VRT,VRA,VRB) 3920 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3921 {VSRAD, 0xfc0007ff, 0x100003c4, 0x0, // Vector Shift Right Algebraic Doubleword VX-form (vsrad VRT,VRA,VRB) 3922 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3923 {VADDFP, 0xfc0007ff, 0x1000000a, 0x0, // Vector Add Single-Precision VX-form (vaddfp VRT,VRA,VRB) 3924 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3925 {VSUBFP, 0xfc0007ff, 0x1000004a, 0x0, // Vector Subtract Single-Precision VX-form (vsubfp VRT,VRA,VRB) 3926 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3927 {VMADDFP, 0xfc00003f, 0x1000002e, 0x0, // Vector Multiply-Add Single-Precision VA-form (vmaddfp VRT,VRA,VRC,VRB) 3928 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}}, 3929 {VNMSUBFP, 0xfc00003f, 0x1000002f, 0x0, // Vector Negative Multiply-Subtract Single-Precision VA-form (vnmsubfp VRT,VRA,VRC,VRB) 3930 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_21_25, ap_VecReg_16_20}}, 3931 {VMAXFP, 0xfc0007ff, 0x1000040a, 0x0, // Vector Maximum Single-Precision VX-form (vmaxfp VRT,VRA,VRB) 3932 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3933 {VMINFP, 0xfc0007ff, 0x1000044a, 0x0, // Vector Minimum Single-Precision VX-form (vminfp VRT,VRA,VRB) 3934 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3935 {VCTSXS, 0xfc0007ff, 0x100003ca, 0x0, // Vector Convert To Signed Fixed-Point Word Saturate VX-form (vctsxs VRT,VRB,UIM) 3936 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, 3937 {VCTUXS, 0xfc0007ff, 0x1000038a, 0x0, // Vector Convert To Unsigned Fixed-Point Word Saturate VX-form (vctuxs VRT,VRB,UIM) 3938 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, 3939 {VCFSX, 0xfc0007ff, 0x1000034a, 0x0, // Vector Convert From Signed Fixed-Point Word VX-form (vcfsx VRT,VRB,UIM) 3940 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, 3941 {VCFUX, 0xfc0007ff, 0x1000030a, 0x0, // Vector Convert From Unsigned Fixed-Point Word VX-form (vcfux VRT,VRB,UIM) 3942 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20, ap_ImmUnsigned_11_15}}, 3943 {VRFIM, 0xfc0007ff, 0x100002ca, 0x1f0000, // Vector Round to Single-Precision Integer toward -Infinity VX-form (vrfim VRT,VRB) 3944 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3945 {VRFIN, 0xfc0007ff, 0x1000020a, 0x1f0000, // Vector Round to Single-Precision Integer Nearest VX-form (vrfin VRT,VRB) 3946 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3947 {VRFIP, 0xfc0007ff, 0x1000028a, 0x1f0000, // Vector Round to Single-Precision Integer toward +Infinity VX-form (vrfip VRT,VRB) 3948 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3949 {VRFIZ, 0xfc0007ff, 0x1000024a, 0x1f0000, // Vector Round to Single-Precision Integer toward Zero VX-form (vrfiz VRT,VRB) 3950 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3951 {VCMPBFP, 0xfc0007ff, 0x100003c6, 0x0, // Vector Compare Bounds Single-Precision VC-form (vcmpbfp VRT,VRA,VRB) 3952 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3953 {VCMPBFP_, 0xfc0007ff, 0x100007c6, 0x0, // Vector Compare Bounds Single-Precision VC-form (vcmpbfp. VRT,VRA,VRB) 3954 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3955 {VCMPEQFP, 0xfc0007ff, 0x100000c6, 0x0, // Vector Compare Equal To Single-Precision VC-form (vcmpeqfp VRT,VRA,VRB) 3956 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3957 {VCMPEQFP_, 0xfc0007ff, 0x100004c6, 0x0, // Vector Compare Equal To Single-Precision VC-form (vcmpeqfp. VRT,VRA,VRB) 3958 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3959 {VCMPGEFP, 0xfc0007ff, 0x100001c6, 0x0, // Vector Compare Greater Than or Equal To Single-Precision VC-form (vcmpgefp VRT,VRA,VRB) 3960 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3961 {VCMPGEFP_, 0xfc0007ff, 0x100005c6, 0x0, // Vector Compare Greater Than or Equal To Single-Precision VC-form (vcmpgefp. VRT,VRA,VRB) 3962 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3963 {VCMPGTFP, 0xfc0007ff, 0x100002c6, 0x0, // Vector Compare Greater Than Single-Precision VC-form (vcmpgtfp VRT,VRA,VRB) 3964 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3965 {VCMPGTFP_, 0xfc0007ff, 0x100006c6, 0x0, // Vector Compare Greater Than Single-Precision VC-form (vcmpgtfp. VRT,VRA,VRB) 3966 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3967 {VEXPTEFP, 0xfc0007ff, 0x1000018a, 0x1f0000, // Vector 2 Raised to the Exponent Estimate Floating-Point VX-form (vexptefp VRT,VRB) 3968 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3969 {VLOGEFP, 0xfc0007ff, 0x100001ca, 0x1f0000, // Vector Log Base 2 Estimate Floating-Point VX-form (vlogefp VRT,VRB) 3970 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3971 {VREFP, 0xfc0007ff, 0x1000010a, 0x1f0000, // Vector Reciprocal Estimate Single-Precision VX-form (vrefp VRT,VRB) 3972 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3973 {VRSQRTEFP, 0xfc0007ff, 0x1000014a, 0x1f0000, // Vector Reciprocal Square Root Estimate Single-Precision VX-form (vrsqrtefp VRT,VRB) 3974 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 3975 {VCIPHER, 0xfc0007ff, 0x10000508, 0x0, // Vector AES Cipher VX-form (vcipher VRT,VRA,VRB) 3976 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3977 {VCIPHERLAST, 0xfc0007ff, 0x10000509, 0x0, // Vector AES Cipher Last VX-form (vcipherlast VRT,VRA,VRB) 3978 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3979 {VNCIPHER, 0xfc0007ff, 0x10000548, 0x0, // Vector AES Inverse Cipher VX-form (vncipher VRT,VRA,VRB) 3980 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3981 {VNCIPHERLAST, 0xfc0007ff, 0x10000549, 0x0, // Vector AES Inverse Cipher Last VX-form (vncipherlast VRT,VRA,VRB) 3982 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3983 {VSBOX, 0xfc0007ff, 0x100005c8, 0xf800, // Vector AES SubBytes VX-form (vsbox VRT,VRA) 3984 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15}}, 3985 {VSHASIGMAD, 0xfc0007ff, 0x100006c2, 0x0, // Vector SHA-512 Sigma Doubleword VX-form (vshasigmad VRT,VRA,ST,SIX) 3986 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}}, 3987 {VSHASIGMAW, 0xfc0007ff, 0x10000682, 0x0, // Vector SHA-256 Sigma Word VX-form (vshasigmaw VRT,VRA,ST,SIX) 3988 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_ImmUnsigned_16_16, ap_ImmUnsigned_17_20}}, 3989 {VPMSUMB, 0xfc0007ff, 0x10000408, 0x0, // Vector Polynomial Multiply-Sum Byte VX-form (vpmsumb VRT,VRA,VRB) 3990 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3991 {VPMSUMD, 0xfc0007ff, 0x100004c8, 0x0, // Vector Polynomial Multiply-Sum Doubleword VX-form (vpmsumd VRT,VRA,VRB) 3992 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3993 {VPMSUMH, 0xfc0007ff, 0x10000448, 0x0, // Vector Polynomial Multiply-Sum Halfword VX-form (vpmsumh VRT,VRA,VRB) 3994 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3995 {VPMSUMW, 0xfc0007ff, 0x10000488, 0x0, // Vector Polynomial Multiply-Sum Word VX-form (vpmsumw VRT,VRA,VRB) 3996 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 3997 {VPERMXOR, 0xfc00003f, 0x1000002d, 0x0, // Vector Permute and Exclusive-OR VA-form (vpermxor VRT,VRA,VRB,VRC) 3998 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_VecReg_21_25}}, 3999 {VGBBD, 0xfc0007ff, 0x1000050c, 0x1f0000, // Vector Gather Bits by Bytes by Doubleword VX-form (vgbbd VRT,VRB) 4000 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4001 {VCLZB, 0xfc0007ff, 0x10000702, 0x1f0000, // Vector Count Leading Zeros Byte VX-form (vclzb VRT,VRB) 4002 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4003 {VCLZH, 0xfc0007ff, 0x10000742, 0x1f0000, // Vector Count Leading Zeros Halfword VX-form (vclzh VRT,VRB) 4004 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4005 {VCLZW, 0xfc0007ff, 0x10000782, 0x1f0000, // Vector Count Leading Zeros Word VX-form (vclzw VRT,VRB) 4006 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4007 {VCLZD, 0xfc0007ff, 0x100007c2, 0x1f0000, // Vector Count Leading Zeros Doubleword (vclzd VRT,VRB) 4008 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4009 {VPOPCNTB, 0xfc0007ff, 0x10000703, 0x1f0000, // Vector Population Count Byte (vpopcntb VRT,VRB) 4010 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4011 {VPOPCNTD, 0xfc0007ff, 0x100007c3, 0x1f0000, // Vector Population Count Doubleword (vpopcntd VRT,VRB) 4012 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4013 {VPOPCNTH, 0xfc0007ff, 0x10000743, 0x1f0000, // Vector Population Count Halfword (vpopcnth VRT,VRB) 4014 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4015 {VPOPCNTW, 0xfc0007ff, 0x10000783, 0x1f0000, // Vector Population Count Word (vpopcntw VRT,VRB) 4016 [5]*argField{ap_VecReg_6_10, ap_VecReg_16_20}}, 4017 {VBPERMQ, 0xfc0007ff, 0x1000054c, 0x0, // Vector Bit Permute Quadword VX-form (vbpermq VRT,VRA,VRB) 4018 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20}}, 4019 {BCDADD_, 0xfc0005ff, 0x10000401, 0x0, // Decimal Add Modulo VX-form (bcdadd. VRT,VRA,VRB,PS) 4020 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, 4021 {BCDSUB_, 0xfc0005ff, 0x10000441, 0x0, // Decimal Subtract Modulo VX-form (bcdsub. VRT,VRA,VRB,PS) 4022 [5]*argField{ap_VecReg_6_10, ap_VecReg_11_15, ap_VecReg_16_20, ap_ImmUnsigned_22_22}}, 4023 {MTVSCR, 0xfc0007ff, 0x10000644, 0x3ff0000, // Move To Vector Status and Control Register VX-form (mtvscr VRB) 4024 [5]*argField{ap_VecReg_16_20}}, 4025 {MFVSCR, 0xfc0007ff, 0x10000604, 0x1ff800, // Move From Vector Status and Control Register VX-form (mfvscr VRT) 4026 [5]*argField{ap_VecReg_6_10}}, 4027 {DADD, 0xfc0007ff, 0xec000004, 0x0, // DFP Add [Quad] X-form (dadd FRT,FRA,FRB) 4028 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4029 {DADD_, 0xfc0007ff, 0xec000005, 0x0, // DFP Add [Quad] X-form (dadd. FRT,FRA,FRB) 4030 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4031 {DSUB, 0xfc0007ff, 0xec000404, 0x0, // DFP Subtract [Quad] X-form (dsub FRT,FRA,FRB) 4032 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4033 {DSUB_, 0xfc0007ff, 0xec000405, 0x0, // DFP Subtract [Quad] X-form (dsub. FRT,FRA,FRB) 4034 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4035 {DMUL, 0xfc0007ff, 0xec000044, 0x0, // DFP Multiply [Quad] X-form (dmul FRT,FRA,FRB) 4036 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4037 {DMUL_, 0xfc0007ff, 0xec000045, 0x0, // DFP Multiply [Quad] X-form (dmul. FRT,FRA,FRB) 4038 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4039 {DDIV, 0xfc0007ff, 0xec000444, 0x0, // DFP Divide [Quad] X-form (ddiv FRT,FRA,FRB) 4040 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4041 {DDIV_, 0xfc0007ff, 0xec000445, 0x0, // DFP Divide [Quad] X-form (ddiv. FRT,FRA,FRB) 4042 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4043 {DCMPU, 0xfc0007fe, 0xec000504, 0x600001, // DFP Compare Unordered [Quad] X-form (dcmpu BF,FRA,FRB) 4044 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 4045 {DCMPO, 0xfc0007fe, 0xec000104, 0x600001, // DFP Compare Ordered [Quad] X-form (dcmpo BF,FRA,FRB) 4046 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 4047 {DTSTDC, 0xfc0003fe, 0xec000184, 0x600001, // DFP Test Data Class [Quad] Z22-form (dtstdc BF,FRA,DCM) 4048 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4049 {DTSTDG, 0xfc0003fe, 0xec0001c4, 0x600001, // DFP Test Data Group [Quad] Z22-form (dtstdg BF,FRA,DGM) 4050 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4051 {DTSTEX, 0xfc0007fe, 0xec000144, 0x600001, // DFP Test Exponent [Quad] X-form (dtstex BF,FRA,FRB) 4052 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 4053 {DTSTSF, 0xfc0007fe, 0xec000544, 0x600001, // DFP Test Significance [Quad] X-form (dtstsf BF,FRA,FRB) 4054 [5]*argField{ap_CondRegField_6_8, ap_FPReg_11_15, ap_FPReg_16_20}}, 4055 {DQUAI, 0xfc0001ff, 0xec000086, 0x0, // DFP Quantize Immediate [Quad] Z23-form (dquai TE,FRT,FRB,RMC) 4056 [5]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4057 {DQUAI_, 0xfc0001ff, 0xec000087, 0x0, // DFP Quantize Immediate [Quad] Z23-form (dquai. TE,FRT,FRB,RMC) 4058 [5]*argField{ap_ImmSigned_11_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4059 {DQUA, 0xfc0001ff, 0xec000006, 0x0, // DFP Quantize [Quad] Z23-form (dqua FRT,FRA,FRB,RMC) 4060 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4061 {DQUA_, 0xfc0001ff, 0xec000007, 0x0, // DFP Quantize [Quad] Z23-form (dqua. FRT,FRA,FRB,RMC) 4062 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4063 {DRRND, 0xfc0001ff, 0xec000046, 0x0, // DFP Reround [Quad] Z23-form (drrnd FRT,FRA,FRB,RMC) 4064 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4065 {DRRND_, 0xfc0001ff, 0xec000047, 0x0, // DFP Reround [Quad] Z23-form (drrnd. FRT,FRA,FRB,RMC) 4066 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4067 {DRINTX, 0xfc0001ff, 0xec0000c6, 0x1e0000, // DFP Round To FP Integer With Inexact [Quad] Z23-form (drintx R,FRT,FRB,RMC) 4068 [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4069 {DRINTX_, 0xfc0001ff, 0xec0000c7, 0x1e0000, // DFP Round To FP Integer With Inexact [Quad] Z23-form (drintx. R,FRT,FRB,RMC) 4070 [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4071 {DRINTN, 0xfc0001ff, 0xec0001c6, 0x1e0000, // DFP Round To FP Integer Without Inexact [Quad] Z23-form (drintn R,FRT,FRB,RMC) 4072 [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4073 {DRINTN_, 0xfc0001ff, 0xec0001c7, 0x1e0000, // DFP Round To FP Integer Without Inexact [Quad] Z23-form (drintn. R,FRT,FRB,RMC) 4074 [5]*argField{ap_ImmUnsigned_15_15, ap_FPReg_6_10, ap_FPReg_16_20, ap_ImmUnsigned_21_22}}, 4075 {DCTDP, 0xfc0007ff, 0xec000204, 0x1f0000, // DFP Convert To DFP Long X-form (dctdp FRT,FRB) 4076 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4077 {DCTDP_, 0xfc0007ff, 0xec000205, 0x1f0000, // DFP Convert To DFP Long X-form (dctdp. FRT,FRB) 4078 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4079 {DCTQPQ, 0xfc0007ff, 0xfc000204, 0x1f0000, // DFP Convert To DFP Extended X-form (dctqpq FRTp,FRB) 4080 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4081 {DCTQPQ_, 0xfc0007ff, 0xfc000205, 0x1f0000, // DFP Convert To DFP Extended X-form (dctqpq. FRTp,FRB) 4082 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4083 {DRSP, 0xfc0007ff, 0xec000604, 0x1f0000, // DFP Round To DFP Short X-form (drsp FRT,FRB) 4084 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4085 {DRSP_, 0xfc0007ff, 0xec000605, 0x1f0000, // DFP Round To DFP Short X-form (drsp. FRT,FRB) 4086 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4087 {DRDPQ, 0xfc0007ff, 0xfc000604, 0x1f0000, // DFP Round To DFP Long X-form (drdpq FRTp,FRBp) 4088 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4089 {DRDPQ_, 0xfc0007ff, 0xfc000605, 0x1f0000, // DFP Round To DFP Long X-form (drdpq. FRTp,FRBp) 4090 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4091 {DCFFIX, 0xfc0007ff, 0xec000644, 0x1f0000, // DFP Convert From Fixed X-form (dcffix FRT,FRB) 4092 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4093 {DCFFIX_, 0xfc0007ff, 0xec000645, 0x1f0000, // DFP Convert From Fixed X-form (dcffix. FRT,FRB) 4094 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4095 {DCFFIXQ, 0xfc0007ff, 0xfc000644, 0x1f0000, // DFP Convert From Fixed Quad X-form (dcffixq FRTp,FRB) 4096 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4097 {DCFFIXQ_, 0xfc0007ff, 0xfc000645, 0x1f0000, // DFP Convert From Fixed Quad X-form (dcffixq. FRTp,FRB) 4098 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4099 {DCTFIX, 0xfc0007ff, 0xec000244, 0x1f0000, // DFP Convert To Fixed [Quad] X-form (dctfix FRT,FRB) 4100 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4101 {DCTFIX_, 0xfc0007ff, 0xec000245, 0x1f0000, // DFP Convert To Fixed [Quad] X-form (dctfix. FRT,FRB) 4102 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4103 {DDEDPD, 0xfc0007ff, 0xec000284, 0x70000, // DFP Decode DPD To BCD [Quad] X-form (ddedpd SP,FRT,FRB) 4104 [5]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}}, 4105 {DDEDPD_, 0xfc0007ff, 0xec000285, 0x70000, // DFP Decode DPD To BCD [Quad] X-form (ddedpd. SP,FRT,FRB) 4106 [5]*argField{ap_ImmUnsigned_11_12, ap_FPReg_6_10, ap_FPReg_16_20}}, 4107 {DENBCD, 0xfc0007ff, 0xec000684, 0xf0000, // DFP Encode BCD To DPD [Quad] X-form (denbcd S,FRT,FRB) 4108 [5]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}}, 4109 {DENBCD_, 0xfc0007ff, 0xec000685, 0xf0000, // DFP Encode BCD To DPD [Quad] X-form (denbcd. S,FRT,FRB) 4110 [5]*argField{ap_ImmUnsigned_11_11, ap_FPReg_6_10, ap_FPReg_16_20}}, 4111 {DXEX, 0xfc0007ff, 0xec0002c4, 0x1f0000, // DFP Extract Biased Exponent [Quad] X-form (dxex FRT,FRB) 4112 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4113 {DXEX_, 0xfc0007ff, 0xec0002c5, 0x1f0000, // DFP Extract Biased Exponent [Quad] X-form (dxex. FRT,FRB) 4114 [5]*argField{ap_FPReg_6_10, ap_FPReg_16_20}}, 4115 {DIEX, 0xfc0007ff, 0xec0006c4, 0x0, // DFP Insert Biased Exponent [Quad] X-form (diex FRT,FRA,FRB) 4116 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4117 {DIEX_, 0xfc0007ff, 0xec0006c5, 0x0, // DFP Insert Biased Exponent [Quad] X-form (diex. FRT,FRA,FRB) 4118 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_FPReg_16_20}}, 4119 {DSCLI, 0xfc0003ff, 0xec000084, 0x0, // DFP Shift Significand Left Immediate [Quad] Z22-form (dscli FRT,FRA,SH) 4120 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4121 {DSCLI_, 0xfc0003ff, 0xec000085, 0x0, // DFP Shift Significand Left Immediate [Quad] Z22-form (dscli. FRT,FRA,SH) 4122 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4123 {DSCRI, 0xfc0003ff, 0xec0000c4, 0x0, // DFP Shift Significand Right Immediate [Quad] Z22-form (dscri FRT,FRA,SH) 4124 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4125 {DSCRI_, 0xfc0003ff, 0xec0000c5, 0x0, // DFP Shift Significand Right Immediate [Quad] Z22-form (dscri. FRT,FRA,SH) 4126 [5]*argField{ap_FPReg_6_10, ap_FPReg_11_15, ap_ImmUnsigned_16_21}}, 4127 {LXSDX, 0xfc0007fe, 0x7c000498, 0x0, // Load VSX Scalar Doubleword Indexed XX1-form (lxsdx XT,RA,RB) 4128 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4129 {LXSIWAX, 0xfc0007fe, 0x7c000098, 0x0, // Load VSX Scalar as Integer Word Algebraic Indexed XX1-form (lxsiwax XT,RA,RB) 4130 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4131 {LXSIWZX, 0xfc0007fe, 0x7c000018, 0x0, // Load VSX Scalar as Integer Word and Zero Indexed XX1-form (lxsiwzx XT,RA,RB) 4132 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4133 {LXSSPX, 0xfc0007fe, 0x7c000418, 0x0, // Load VSX Scalar Single-Precision Indexed XX1-form (lxsspx XT,RA,RB) 4134 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4135 {LXVD2X, 0xfc0007fe, 0x7c000698, 0x0, // Load VSX Vector Doubleword*2 Indexed XX1-form (lxvd2x XT,RA,RB) 4136 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4137 {LXVDSX, 0xfc0007fe, 0x7c000298, 0x0, // Load VSX Vector Doubleword & Splat Indexed XX1-form (lxvdsx XT,RA,RB) 4138 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4139 {LXVW4X, 0xfc0007fe, 0x7c000618, 0x0, // Load VSX Vector Word*4 Indexed XX1-form (lxvw4x XT,RA,RB) 4140 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4141 {STXSDX, 0xfc0007fe, 0x7c000598, 0x0, // Store VSX Scalar Doubleword Indexed XX1-form (stxsdx XS,RA,RB) 4142 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4143 {STXSIWX, 0xfc0007fe, 0x7c000118, 0x0, // Store VSX Scalar as Integer Word Indexed XX1-form (stxsiwx XS,RA,RB) 4144 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4145 {STXSSPX, 0xfc0007fe, 0x7c000518, 0x0, // Store VSX Scalar Single-Precision Indexed XX1-form (stxsspx XS,RA,RB) 4146 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4147 {STXVD2X, 0xfc0007fe, 0x7c000798, 0x0, // Store VSX Vector Doubleword*2 Indexed XX1-form (stxvd2x XS,RA,RB) 4148 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4149 {STXVW4X, 0xfc0007fe, 0x7c000718, 0x0, // Store VSX Vector Word*4 Indexed XX1-form (stxvw4x XS,RA,RB) 4150 [5]*argField{ap_VecSReg_31_31_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4151 {XSABSDP, 0xfc0007fc, 0xf0000564, 0x1f0000, // VSX Scalar Absolute Value Double-Precision XX2-form (xsabsdp XT,XB) 4152 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4153 {XSADDDP, 0xfc0007f8, 0xf0000100, 0x0, // VSX Scalar Add Double-Precision XX3-form (xsadddp XT,XA,XB) 4154 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4155 {XSADDSP, 0xfc0007f8, 0xf0000000, 0x0, // VSX Scalar Add Single-Precision XX3-form (xsaddsp XT,XA,XB) 4156 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4157 {XSCMPODP, 0xfc0007f8, 0xf0000158, 0x600001, // VSX Scalar Compare Ordered Double-Precision XX3-form (xscmpodp BF,XA,XB) 4158 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4159 {XSCMPUDP, 0xfc0007f8, 0xf0000118, 0x600001, // VSX Scalar Compare Unordered Double-Precision XX3-form (xscmpudp BF,XA,XB) 4160 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4161 {XSCPSGNDP, 0xfc0007f8, 0xf0000580, 0x0, // VSX Scalar Copy Sign Double-Precision XX3-form (xscpsgndp XT,XA,XB) 4162 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4163 {XSCVDPSP, 0xfc0007fc, 0xf0000424, 0x1f0000, // VSX Scalar round Double-Precision to single-precision and Convert to Single-Precision format XX2-form (xscvdpsp XT,XB) 4164 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4165 {XSCVDPSPN, 0xfc0007fc, 0xf000042c, 0x1f0000, // VSX Scalar Convert Scalar Single-Precision to Vector Single-Precision format Non-signalling XX2-form (xscvdpspn XT,XB) 4166 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4167 {XSCVDPSXDS, 0xfc0007fc, 0xf0000560, 0x1f0000, // VSX Scalar truncate Double-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form (xscvdpsxds XT,XB) 4168 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4169 {XSCVDPSXWS, 0xfc0007fc, 0xf0000160, 0x1f0000, // VSX Scalar truncate Double-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form (xscvdpsxws XT,XB) 4170 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4171 {XSCVDPUXDS, 0xfc0007fc, 0xf0000520, 0x1f0000, // VSX Scalar truncate Double-Precision integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form (xscvdpuxds XT,XB) 4172 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4173 {XSCVDPUXWS, 0xfc0007fc, 0xf0000120, 0x1f0000, // VSX Scalar truncate Double-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form (xscvdpuxws XT,XB) 4174 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4175 {XSCVSPDP, 0xfc0007fc, 0xf0000524, 0x1f0000, // VSX Scalar Convert Single-Precision to Double-Precision format XX2-form (xscvspdp XT,XB) 4176 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4177 {XSCVSPDPN, 0xfc0007fc, 0xf000052c, 0x1f0000, // VSX Scalar Convert Single-Precision to Double-Precision format Non-signalling XX2-form (xscvspdpn XT,XB) 4178 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4179 {XSCVSXDDP, 0xfc0007fc, 0xf00005e0, 0x1f0000, // VSX Scalar Convert Signed Integer Doubleword to floating-point format and round to Double-Precision format XX2-form (xscvsxddp XT,XB) 4180 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4181 {XSCVSXDSP, 0xfc0007fc, 0xf00004e0, 0x1f0000, // VSX Scalar Convert Signed Integer Doubleword to floating-point format and round to Single-Precision XX2-form (xscvsxdsp XT,XB) 4182 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4183 {XSCVUXDDP, 0xfc0007fc, 0xf00005a0, 0x1f0000, // VSX Scalar Convert Unsigned Integer Doubleword to floating-point format and round to Double-Precision format XX2-form (xscvuxddp XT,XB) 4184 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4185 {XSCVUXDSP, 0xfc0007fc, 0xf00004a0, 0x1f0000, // VSX Scalar Convert Unsigned Integer Doubleword to floating-point format and round to Single-Precision XX2-form (xscvuxdsp XT,XB) 4186 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4187 {XSDIVDP, 0xfc0007f8, 0xf00001c0, 0x0, // VSX Scalar Divide Double-Precision XX3-form (xsdivdp XT,XA,XB) 4188 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4189 {XSDIVSP, 0xfc0007f8, 0xf00000c0, 0x0, // VSX Scalar Divide Single-Precision XX3-form (xsdivsp XT,XA,XB) 4190 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4191 {XSMADDADP, 0xfc0007f8, 0xf0000108, 0x0, // VSX Scalar Multiply-Add Double-Precision XX3-form (xsmaddadp XT,XA,XB) 4192 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4193 {XSMADDASP, 0xfc0007f8, 0xf0000008, 0x0, // VSX Scalar Multiply-Add Single-Precision XX3-form (xsmaddasp XT,XA,XB) 4194 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4195 {XSMAXDP, 0xfc0007f8, 0xf0000500, 0x0, // VSX Scalar Maximum Double-Precision XX3-form (xsmaxdp XT,XA,XB) 4196 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4197 {XSMINDP, 0xfc0007f8, 0xf0000540, 0x0, // VSX Scalar Minimum Double-Precision XX3-form (xsmindp XT,XA,XB) 4198 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4199 {XSMSUBADP, 0xfc0007f8, 0xf0000188, 0x0, // VSX Scalar Multiply-Subtract Double-Precision XX3-form (xsmsubadp XT,XA,XB) 4200 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4201 {XSMSUBASP, 0xfc0007f8, 0xf0000088, 0x0, // VSX Scalar Multiply-Subtract Single-Precision XX3-form (xsmsubasp XT,XA,XB) 4202 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4203 {XSMULDP, 0xfc0007f8, 0xf0000180, 0x0, // VSX Scalar Multiply Double-Precision XX3-form (xsmuldp XT,XA,XB) 4204 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4205 {XSMULSP, 0xfc0007f8, 0xf0000080, 0x0, // VSX Scalar Multiply Single-Precision XX3-form (xsmulsp XT,XA,XB) 4206 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4207 {XSNABSDP, 0xfc0007fc, 0xf00005a4, 0x1f0000, // VSX Scalar Negative Absolute Value Double-Precision XX2-form (xsnabsdp XT,XB) 4208 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4209 {XSNEGDP, 0xfc0007fc, 0xf00005e4, 0x1f0000, // VSX Scalar Negate Double-Precision XX2-form (xsnegdp XT,XB) 4210 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4211 {XSNMADDADP, 0xfc0007f8, 0xf0000508, 0x0, // VSX Scalar Negative Multiply-Add Double-Precision XX3-form (xsnmaddadp XT,XA,XB) 4212 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4213 {XSNMADDASP, 0xfc0007f8, 0xf0000408, 0x0, // VSX Scalar Negative Multiply-Add Single-Precision XX3-form (xsnmaddasp XT,XA,XB) 4214 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4215 {XSNMSUBADP, 0xfc0007f8, 0xf0000588, 0x0, // VSX Scalar Negative Multiply-Subtract Double-Precision XX3-form (xsnmsubadp XT,XA,XB) 4216 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4217 {XSNMSUBASP, 0xfc0007f8, 0xf0000488, 0x0, // VSX Scalar Negative Multiply-Subtract Single-Precision XX3-form (xsnmsubasp XT,XA,XB) 4218 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4219 {XSRDPI, 0xfc0007fc, 0xf0000124, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round to Nearest Away XX2-form (xsrdpi XT,XB) 4220 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4221 {XSRDPIC, 0xfc0007fc, 0xf00001ac, 0x1f0000, // VSX Scalar Round to Double-Precision Integer exact using Current rounding mode XX2-form (xsrdpic XT,XB) 4222 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4223 {XSRDPIM, 0xfc0007fc, 0xf00001e4, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round toward -Infinity XX2-form (xsrdpim XT,XB) 4224 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4225 {XSRDPIP, 0xfc0007fc, 0xf00001a4, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round toward +Infinity XX2-form (xsrdpip XT,XB) 4226 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4227 {XSRDPIZ, 0xfc0007fc, 0xf0000164, 0x1f0000, // VSX Scalar Round to Double-Precision Integer using round toward Zero XX2-form (xsrdpiz XT,XB) 4228 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4229 {XSREDP, 0xfc0007fc, 0xf0000168, 0x1f0000, // VSX Scalar Reciprocal Estimate Double-Precision XX2-form (xsredp XT,XB) 4230 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4231 {XSRESP, 0xfc0007fc, 0xf0000068, 0x1f0000, // VSX Scalar Reciprocal Estimate Single-Precision XX2-form (xsresp XT,XB) 4232 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4233 {XSRSP, 0xfc0007fc, 0xf0000464, 0x1f0000, // VSX Scalar Round to Single-Precision XX2-form (xsrsp XT,XB) 4234 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4235 {XSRSQRTEDP, 0xfc0007fc, 0xf0000128, 0x1f0000, // VSX Scalar Reciprocal Square Root Estimate Double-Precision XX2-form (xsrsqrtedp XT,XB) 4236 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4237 {XSRSQRTESP, 0xfc0007fc, 0xf0000028, 0x1f0000, // VSX Scalar Reciprocal Square Root Estimate Single-Precision XX2-form (xsrsqrtesp XT,XB) 4238 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4239 {XSSQRTDP, 0xfc0007fc, 0xf000012c, 0x1f0000, // VSX Scalar Square Root Double-Precision XX2-form (xssqrtdp XT,XB) 4240 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4241 {XSSQRTSP, 0xfc0007fc, 0xf000002c, 0x1f0000, // VSX Scalar Square Root Single-Precision XX-form (xssqrtsp XT,XB) 4242 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4243 {XSSUBDP, 0xfc0007f8, 0xf0000140, 0x0, // VSX Scalar Subtract Double-Precision XX3-form (xssubdp XT,XA,XB) 4244 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4245 {XSSUBSP, 0xfc0007f8, 0xf0000040, 0x0, // VSX Scalar Subtract Single-Precision XX3-form (xssubsp XT,XA,XB) 4246 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4247 {XSTDIVDP, 0xfc0007f8, 0xf00001e8, 0x600001, // VSX Scalar Test for software Divide Double-Precision XX3-form (xstdivdp BF,XA,XB) 4248 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4249 {XSTSQRTDP, 0xfc0007fc, 0xf00001a8, 0x7f0001, // VSX Scalar Test for software Square Root Double-Precision XX2-form (xstsqrtdp BF,XB) 4250 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}}, 4251 {XVABSDP, 0xfc0007fc, 0xf0000764, 0x1f0000, // VSX Vector Absolute Value Double-Precision XX2-form (xvabsdp XT,XB) 4252 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4253 {XVABSSP, 0xfc0007fc, 0xf0000664, 0x1f0000, // VSX Vector Absolute Value Single-Precision XX2-form (xvabssp XT,XB) 4254 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4255 {XVADDDP, 0xfc0007f8, 0xf0000300, 0x0, // VSX Vector Add Double-Precision XX3-form (xvadddp XT,XA,XB) 4256 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4257 {XVADDSP, 0xfc0007f8, 0xf0000200, 0x0, // VSX Vector Add Single-Precision XX3-form (xvaddsp XT,XA,XB) 4258 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4259 {XVCMPEQDP, 0xfc0007f8, 0xf0000318, 0x0, // VSX Vector Compare Equal To Double-Precision [ & Record ] XX3-form (xvcmpeqdp XT,XA,XB) 4260 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4261 {XVCMPEQDP_, 0xfc0007f8, 0xf0000718, 0x0, // VSX Vector Compare Equal To Double-Precision [ & Record ] XX3-form (xvcmpeqdp. XT,XA,XB) 4262 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4263 {XVCMPEQSP, 0xfc0007f8, 0xf0000218, 0x0, // VSX Vector Compare Equal To Single-Precision [ & Record ] XX3-form (xvcmpeqsp XT,XA,XB) 4264 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4265 {XVCMPEQSP_, 0xfc0007f8, 0xf0000618, 0x0, // VSX Vector Compare Equal To Single-Precision [ & Record ] XX3-form (xvcmpeqsp. XT,XA,XB) 4266 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4267 {XVCMPGEDP, 0xfc0007f8, 0xf0000398, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ] XX3-form (xvcmpgedp XT,XA,XB) 4268 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4269 {XVCMPGEDP_, 0xfc0007f8, 0xf0000798, 0x0, // VSX Vector Compare Greater Than or Equal To Double-Precision [ & Record ] XX3-form (xvcmpgedp. XT,XA,XB) 4270 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4271 {XVCMPGESP, 0xfc0007f8, 0xf0000298, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision [ & record CR6 ] XX3-form (xvcmpgesp XT,XA,XB) 4272 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4273 {XVCMPGESP_, 0xfc0007f8, 0xf0000698, 0x0, // VSX Vector Compare Greater Than or Equal To Single-Precision [ & record CR6 ] XX3-form (xvcmpgesp. XT,XA,XB) 4274 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4275 {XVCMPGTDP, 0xfc0007f8, 0xf0000358, 0x0, // VSX Vector Compare Greater Than Double-Precision [ & record CR6 ] XX3-form (xvcmpgtdp XT,XA,XB) 4276 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4277 {XVCMPGTDP_, 0xfc0007f8, 0xf0000758, 0x0, // VSX Vector Compare Greater Than Double-Precision [ & record CR6 ] XX3-form (xvcmpgtdp. XT,XA,XB) 4278 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4279 {XVCMPGTSP, 0xfc0007f8, 0xf0000258, 0x0, // VSX Vector Compare Greater Than Single-Precision [ & record CR6 ] XX3-form (xvcmpgtsp XT,XA,XB) 4280 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4281 {XVCMPGTSP_, 0xfc0007f8, 0xf0000658, 0x0, // VSX Vector Compare Greater Than Single-Precision [ & record CR6 ] XX3-form (xvcmpgtsp. XT,XA,XB) 4282 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4283 {XVCPSGNDP, 0xfc0007f8, 0xf0000780, 0x0, // VSX Vector Copy Sign Double-Precision XX3-form (xvcpsgndp XT,XA,XB) 4284 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4285 {XVCPSGNSP, 0xfc0007f8, 0xf0000680, 0x0, // VSX Vector Copy Sign Single-Precision XX3-form (xvcpsgnsp XT,XA,XB) 4286 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4287 {XVCVDPSP, 0xfc0007fc, 0xf0000624, 0x1f0000, // VSX Vector round Double-Precision to single-precision and Convert to Single-Precision format XX2-form (xvcvdpsp XT,XB) 4288 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4289 {XVCVDPSXDS, 0xfc0007fc, 0xf0000760, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form (xvcvdpsxds XT,XB) 4290 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4291 {XVCVDPSXWS, 0xfc0007fc, 0xf0000360, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form (xvcvdpsxws XT,XB) 4292 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4293 {XVCVDPUXDS, 0xfc0007fc, 0xf0000720, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form (xvcvdpuxds XT,XB) 4294 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4295 {XVCVDPUXWS, 0xfc0007fc, 0xf0000320, 0x1f0000, // VSX Vector truncate Double-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form (xvcvdpuxws XT,XB) 4296 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4297 {XVCVSPDP, 0xfc0007fc, 0xf0000724, 0x1f0000, // VSX Vector Convert Single-Precision to Double-Precision format XX2-form (xvcvspdp XT,XB) 4298 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4299 {XVCVSPSXDS, 0xfc0007fc, 0xf0000660, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Signed Integer Doubleword format with Saturate XX2-form (xvcvspsxds XT,XB) 4300 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4301 {XVCVSPSXWS, 0xfc0007fc, 0xf0000260, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Signed Integer Word format with Saturate XX2-form (xvcvspsxws XT,XB) 4302 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4303 {XVCVSPUXDS, 0xfc0007fc, 0xf0000620, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Unsigned Integer Doubleword format with Saturate XX2-form (xvcvspuxds XT,XB) 4304 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4305 {XVCVSPUXWS, 0xfc0007fc, 0xf0000220, 0x1f0000, // VSX Vector truncate Single-Precision to integer and Convert to Unsigned Integer Word format with Saturate XX2-form (xvcvspuxws XT,XB) 4306 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4307 {XVCVSXDDP, 0xfc0007fc, 0xf00007e0, 0x1f0000, // VSX Vector Convert and round Signed Integer Doubleword to Double-Precision format XX2-form (xvcvsxddp XT,XB) 4308 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4309 {XVCVSXDSP, 0xfc0007fc, 0xf00006e0, 0x1f0000, // VSX Vector Convert and round Signed Integer Doubleword to Single-Precision format XX2-form (xvcvsxdsp XT,XB) 4310 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4311 {XVCVSXWDP, 0xfc0007fc, 0xf00003e0, 0x1f0000, // VSX Vector Convert Signed Integer Word to Double-Precision format XX2-form (xvcvsxwdp XT,XB) 4312 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4313 {XVCVSXWSP, 0xfc0007fc, 0xf00002e0, 0x1f0000, // VSX Vector Convert and round Signed Integer Word to Single-Precision format XX2-form (xvcvsxwsp XT,XB) 4314 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4315 {XVCVUXDDP, 0xfc0007fc, 0xf00007a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Doubleword to Double-Precision format XX2-form (xvcvuxddp XT,XB) 4316 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4317 {XVCVUXDSP, 0xfc0007fc, 0xf00006a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Doubleword to Single-Precision format XX2-form (xvcvuxdsp XT,XB) 4318 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4319 {XVCVUXWDP, 0xfc0007fc, 0xf00003a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Word to Double-Precision format XX2-form (xvcvuxwdp XT,XB) 4320 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4321 {XVCVUXWSP, 0xfc0007fc, 0xf00002a0, 0x1f0000, // VSX Vector Convert and round Unsigned Integer Word to Single-Precision format XX2-form (xvcvuxwsp XT,XB) 4322 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4323 {XVDIVDP, 0xfc0007f8, 0xf00003c0, 0x0, // VSX Vector Divide Double-Precision XX3-form (xvdivdp XT,XA,XB) 4324 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4325 {XVDIVSP, 0xfc0007f8, 0xf00002c0, 0x0, // VSX Vector Divide Single-Precision XX3-form (xvdivsp XT,XA,XB) 4326 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4327 {XVMADDADP, 0xfc0007f8, 0xf0000308, 0x0, // VSX Vector Multiply-Add Double-Precision XX3-form (xvmaddadp XT,XA,XB) 4328 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4329 {XVMADDASP, 0xfc0007f8, 0xf0000208, 0x0, // VSX Vector Multiply-Add Single-Precision XX3-form (xvmaddasp XT,XA,XB) 4330 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4331 {XVMAXDP, 0xfc0007f8, 0xf0000700, 0x0, // VSX Vector Maximum Double-Precision XX3-form (xvmaxdp XT,XA,XB) 4332 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4333 {XVMAXSP, 0xfc0007f8, 0xf0000600, 0x0, // VSX Vector Maximum Single-Precision XX3-form (xvmaxsp XT,XA,XB) 4334 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4335 {XVMINDP, 0xfc0007f8, 0xf0000740, 0x0, // VSX Vector Minimum Double-Precision XX3-form (xvmindp XT,XA,XB) 4336 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4337 {XVMINSP, 0xfc0007f8, 0xf0000640, 0x0, // VSX Vector Minimum Single-Precision XX3-form (xvminsp XT,XA,XB) 4338 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4339 {XVMSUBADP, 0xfc0007f8, 0xf0000388, 0x0, // VSX Vector Multiply-Subtract Double-Precision XX3-form (xvmsubadp XT,XA,XB) 4340 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4341 {XVMSUBASP, 0xfc0007f8, 0xf0000288, 0x0, // VSX Vector Multiply-Subtract Single-Precision XX3-form (xvmsubasp XT,XA,XB) 4342 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4343 {XVMULDP, 0xfc0007f8, 0xf0000380, 0x0, // VSX Vector Multiply Double-Precision XX3-form (xvmuldp XT,XA,XB) 4344 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4345 {XVMULSP, 0xfc0007f8, 0xf0000280, 0x0, // VSX Vector Multiply Single-Precision XX3-form (xvmulsp XT,XA,XB) 4346 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4347 {XVNABSDP, 0xfc0007fc, 0xf00007a4, 0x1f0000, // VSX Vector Negative Absolute Value Double-Precision XX2-form (xvnabsdp XT,XB) 4348 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4349 {XVNABSSP, 0xfc0007fc, 0xf00006a4, 0x1f0000, // VSX Vector Negative Absolute Value Single-Precision XX2-form (xvnabssp XT,XB) 4350 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4351 {XVNEGDP, 0xfc0007fc, 0xf00007e4, 0x1f0000, // VSX Vector Negate Double-Precision XX2-form (xvnegdp XT,XB) 4352 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4353 {XVNEGSP, 0xfc0007fc, 0xf00006e4, 0x1f0000, // VSX Vector Negate Single-Precision XX2-form (xvnegsp XT,XB) 4354 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4355 {XVNMADDADP, 0xfc0007f8, 0xf0000708, 0x0, // VSX Vector Negative Multiply-Add Double-Precision XX3-form (xvnmaddadp XT,XA,XB) 4356 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4357 {XVNMADDASP, 0xfc0007f8, 0xf0000608, 0x0, // VSX Vector Negative Multiply-Add Single-Precision XX3-form (xvnmaddasp XT,XA,XB) 4358 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4359 {XVNMSUBADP, 0xfc0007f8, 0xf0000788, 0x0, // VSX Vector Negative Multiply-Subtract Double-Precision XX3-form (xvnmsubadp XT,XA,XB) 4360 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4361 {XVNMSUBASP, 0xfc0007f8, 0xf0000688, 0x0, // VSX Vector Negative Multiply-Subtract Single-Precision XX3-form (xvnmsubasp XT,XA,XB) 4362 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4363 {XVRDPI, 0xfc0007fc, 0xf0000324, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round to Nearest Away XX2-form (xvrdpi XT,XB) 4364 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4365 {XVRDPIC, 0xfc0007fc, 0xf00003ac, 0x1f0000, // VSX Vector Round to Double-Precision Integer Exact using Current rounding mode XX2-form (xvrdpic XT,XB) 4366 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4367 {XVRDPIM, 0xfc0007fc, 0xf00003e4, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round toward -Infinity XX2-form (xvrdpim XT,XB) 4368 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4369 {XVRDPIP, 0xfc0007fc, 0xf00003a4, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round toward +Infinity XX2-form (xvrdpip XT,XB) 4370 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4371 {XVRDPIZ, 0xfc0007fc, 0xf0000364, 0x1f0000, // VSX Vector Round to Double-Precision Integer using round toward Zero XX2-form (xvrdpiz XT,XB) 4372 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4373 {XVREDP, 0xfc0007fc, 0xf0000368, 0x1f0000, // VSX Vector Reciprocal Estimate Double-Precision XX2-form (xvredp XT,XB) 4374 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4375 {XVRESP, 0xfc0007fc, 0xf0000268, 0x1f0000, // VSX Vector Reciprocal Estimate Single-Precision XX2-form (xvresp XT,XB) 4376 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4377 {XVRSPI, 0xfc0007fc, 0xf0000224, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round to Nearest Away XX2-form (xvrspi XT,XB) 4378 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4379 {XVRSPIC, 0xfc0007fc, 0xf00002ac, 0x1f0000, // VSX Vector Round to Single-Precision Integer Exact using Current rounding mode XX2-form (xvrspic XT,XB) 4380 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4381 {XVRSPIM, 0xfc0007fc, 0xf00002e4, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round toward -Infinity XX2-form (xvrspim XT,XB) 4382 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4383 {XVRSPIP, 0xfc0007fc, 0xf00002a4, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round toward +Infinity XX2-form (xvrspip XT,XB) 4384 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4385 {XVRSPIZ, 0xfc0007fc, 0xf0000264, 0x1f0000, // VSX Vector Round to Single-Precision Integer using round toward Zero XX2-form (xvrspiz XT,XB) 4386 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4387 {XVRSQRTEDP, 0xfc0007fc, 0xf0000328, 0x1f0000, // VSX Vector Reciprocal Square Root Estimate Double-Precision XX2-form (xvrsqrtedp XT,XB) 4388 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4389 {XVRSQRTESP, 0xfc0007fc, 0xf0000228, 0x1f0000, // VSX Vector Reciprocal Square Root Estimate Single-Precision XX2-form (xvrsqrtesp XT,XB) 4390 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4391 {XVSQRTDP, 0xfc0007fc, 0xf000032c, 0x1f0000, // VSX Vector Square Root Double-Precision XX2-form (xvsqrtdp XT,XB) 4392 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4393 {XVSQRTSP, 0xfc0007fc, 0xf000022c, 0x1f0000, // VSX Vector Square Root Single-Precision XX2-form (xvsqrtsp XT,XB) 4394 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20}}, 4395 {XVSUBDP, 0xfc0007f8, 0xf0000340, 0x0, // VSX Vector Subtract Double-Precision XX3-form (xvsubdp XT,XA,XB) 4396 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4397 {XVSUBSP, 0xfc0007f8, 0xf0000240, 0x0, // VSX Vector Subtract Single-Precision XX3-form (xvsubsp XT,XA,XB) 4398 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4399 {XVTDIVDP, 0xfc0007f8, 0xf00003e8, 0x600001, // VSX Vector Test for software Divide Double-Precision XX3-form (xvtdivdp BF,XA,XB) 4400 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4401 {XVTDIVSP, 0xfc0007f8, 0xf00002e8, 0x600001, // VSX Vector Test for software Divide Single-Precision XX3-form (xvtdivsp BF,XA,XB) 4402 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4403 {XVTSQRTDP, 0xfc0007fc, 0xf00003a8, 0x7f0001, // VSX Vector Test for software Square Root Double-Precision XX2-form (xvtsqrtdp BF,XB) 4404 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}}, 4405 {XVTSQRTSP, 0xfc0007fc, 0xf00002a8, 0x7f0001, // VSX Vector Test for software Square Root Single-Precision XX2-form (xvtsqrtsp BF,XB) 4406 [5]*argField{ap_CondRegField_6_8, ap_VecSReg_30_30_16_20}}, 4407 {XXLAND, 0xfc0007f8, 0xf0000410, 0x0, // VSX Logical AND XX3-form (xxland XT,XA,XB) 4408 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4409 {XXLANDC, 0xfc0007f8, 0xf0000450, 0x0, // VSX Logical AND with Complement XX3-form (xxlandc XT,XA,XB) 4410 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4411 {XXLEQV, 0xfc0007f8, 0xf00005d0, 0x0, // VSX Logical Equivalence XX3-form (xxleqv XT,XA,XB) 4412 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4413 {XXLNAND, 0xfc0007f8, 0xf0000590, 0x0, // VSX Logical NAND XX3-form (xxlnand XT,XA,XB) 4414 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4415 {XXLORC, 0xfc0007f8, 0xf0000550, 0x0, // VSX Logical OR with Complement XX3-form (xxlorc XT,XA,XB) 4416 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4417 {XXLNOR, 0xfc0007f8, 0xf0000510, 0x0, // VSX Logical NOR XX3-form (xxlnor XT,XA,XB) 4418 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4419 {XXLOR, 0xfc0007f8, 0xf0000490, 0x0, // VSX Logical OR XX3-form (xxlor XT,XA,XB) 4420 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4421 {XXLXOR, 0xfc0007f8, 0xf00004d0, 0x0, // VSX Logical XOR XX3-form (xxlxor XT,XA,XB) 4422 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4423 {XXMRGHW, 0xfc0007f8, 0xf0000090, 0x0, // VSX Merge High Word XX3-form (xxmrghw XT,XA,XB) 4424 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4425 {XXMRGLW, 0xfc0007f8, 0xf0000190, 0x0, // VSX Merge Low Word XX3-form (xxmrglw XT,XA,XB) 4426 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20}}, 4427 {XXPERMDI, 0xfc0004f8, 0xf0000050, 0x0, // VSX Permute Doubleword Immediate XX3-form (xxpermdi XT,XA,XB,DM) 4428 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}}, 4429 {XXSEL, 0xfc000030, 0xf0000030, 0x0, // VSX Select XX4-form (xxsel XT,XA,XB,XC) 4430 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_VecSReg_28_28_21_25}}, 4431 {XXSLDWI, 0xfc0004f8, 0xf0000010, 0x0, // VSX Shift Left Double by Word Immediate XX3-form (xxsldwi XT,XA,XB,SHW) 4432 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_29_29_11_15, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_22_23}}, 4433 {XXSPLTW, 0xfc0007fc, 0xf0000290, 0x1c0000, // VSX Splat Word XX2-form (xxspltw XT,XB,UIM) 4434 [5]*argField{ap_VecSReg_31_31_6_10, ap_VecSReg_30_30_16_20, ap_ImmUnsigned_14_15}}, 4435 {BRINC, 0xfc0007ff, 0x1000020f, 0x0, // Bit Reversed Increment EVX-form (brinc RT,RA,RB) 4436 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4437 {EVABS, 0xfc0007ff, 0x10000208, 0xf800, // Vector Absolute Value EVX-form (evabs RT,RA) 4438 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4439 {EVADDIW, 0xfc0007ff, 0x10000202, 0x0, // Vector Add Immediate Word EVX-form (evaddiw RT,RB,UI) 4440 [5]*argField{ap_Reg_6_10, ap_Reg_16_20, ap_ImmUnsigned_11_15}}, 4441 {EVADDSMIAAW, 0xfc0007ff, 0x100004c9, 0xf800, // Vector Add Signed, Modulo, Integer to Accumulator Word EVX-form (evaddsmiaaw RT,RA) 4442 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4443 {EVADDSSIAAW, 0xfc0007ff, 0x100004c1, 0xf800, // Vector Add Signed, Saturate, Integer to Accumulator Word EVX-form (evaddssiaaw RT,RA) 4444 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4445 {EVADDUMIAAW, 0xfc0007ff, 0x100004c8, 0xf800, // Vector Add Unsigned, Modulo, Integer to Accumulator Word EVX-form (evaddumiaaw RT,RA) 4446 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4447 {EVADDUSIAAW, 0xfc0007ff, 0x100004c0, 0xf800, // Vector Add Unsigned, Saturate, Integer to Accumulator Word EVX-form (evaddusiaaw RT,RA) 4448 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4449 {EVADDW, 0xfc0007ff, 0x10000200, 0x0, // Vector Add Word EVX-form (evaddw RT,RA,RB) 4450 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4451 {EVAND, 0xfc0007ff, 0x10000211, 0x0, // Vector AND EVX-form (evand RT,RA,RB) 4452 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4453 {EVCMPEQ, 0xfc0007ff, 0x10000234, 0x600000, // Vector Compare Equal EVX-form (evcmpeq BF,RA,RB) 4454 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4455 {EVANDC, 0xfc0007ff, 0x10000212, 0x0, // Vector AND with Complement EVX-form (evandc RT,RA,RB) 4456 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4457 {EVCMPGTS, 0xfc0007ff, 0x10000231, 0x600000, // Vector Compare Greater Than Signed EVX-form (evcmpgts BF,RA,RB) 4458 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4459 {EVCMPGTU, 0xfc0007ff, 0x10000230, 0x600000, // Vector Compare Greater Than Unsigned EVX-form (evcmpgtu BF,RA,RB) 4460 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4461 {EVCMPLTU, 0xfc0007ff, 0x10000232, 0x600000, // Vector Compare Less Than Unsigned EVX-form (evcmpltu BF,RA,RB) 4462 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4463 {EVCMPLTS, 0xfc0007ff, 0x10000233, 0x600000, // Vector Compare Less Than Signed EVX-form (evcmplts BF,RA,RB) 4464 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4465 {EVCNTLSW, 0xfc0007ff, 0x1000020e, 0xf800, // Vector Count Leading Signed Bits Word EVX-form (evcntlsw RT,RA) 4466 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4467 {EVCNTLZW, 0xfc0007ff, 0x1000020d, 0xf800, // Vector Count Leading Zeros Word EVX-form (evcntlzw RT,RA) 4468 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4469 {EVDIVWS, 0xfc0007ff, 0x100004c6, 0x0, // Vector Divide Word Signed EVX-form (evdivws RT,RA,RB) 4470 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4471 {EVDIVWU, 0xfc0007ff, 0x100004c7, 0x0, // Vector Divide Word Unsigned EVX-form (evdivwu RT,RA,RB) 4472 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4473 {EVEQV, 0xfc0007ff, 0x10000219, 0x0, // Vector Equivalent EVX-form (eveqv RT,RA,RB) 4474 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4475 {EVEXTSB, 0xfc0007ff, 0x1000020a, 0xf800, // Vector Extend Sign Byte EVX-form (evextsb RT,RA) 4476 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4477 {EVEXTSH, 0xfc0007ff, 0x1000020b, 0xf800, // Vector Extend Sign Halfword EVX-form (evextsh RT,RA) 4478 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4479 {EVLDD, 0xfc0007ff, 0x10000301, 0x0, // Vector Load Double Word into Double Word EVX-form (evldd RT,D(RA)) 4480 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4481 {EVLDH, 0xfc0007ff, 0x10000305, 0x0, // Vector Load Double into Four Halfwords EVX-form (evldh RT,D(RA)) 4482 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4483 {EVLDDX, 0xfc0007ff, 0x10000300, 0x0, // Vector Load Double Word into Double Word Indexed EVX-form (evlddx RT,RA,RB) 4484 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4485 {EVLDHX, 0xfc0007ff, 0x10000304, 0x0, // Vector Load Double into Four Halfwords Indexed EVX-form (evldhx RT,RA,RB) 4486 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4487 {EVLDW, 0xfc0007ff, 0x10000303, 0x0, // Vector Load Double into Two Words EVX-form (evldw RT,D(RA)) 4488 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4489 {EVLHHESPLAT, 0xfc0007ff, 0x10000309, 0x0, // Vector Load Halfword into Halfwords Even and Splat EVX-form (evlhhesplat RT,D(RA)) 4490 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4491 {EVLDWX, 0xfc0007ff, 0x10000302, 0x0, // Vector Load Double into Two Words Indexed EVX-form (evldwx RT,RA,RB) 4492 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4493 {EVLHHESPLATX, 0xfc0007ff, 0x10000308, 0x0, // Vector Load Halfword into Halfwords Even and Splat Indexed EVX-form (evlhhesplatx RT,RA,RB) 4494 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4495 {EVLHHOSSPLAT, 0xfc0007ff, 0x1000030f, 0x0, // Vector Load Halfword into Halfword Odd Signed and Splat EVX-form (evlhhossplat RT,D(RA)) 4496 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4497 {EVLHHOUSPLAT, 0xfc0007ff, 0x1000030d, 0x0, // Vector Load Halfword into Halfword Odd Unsigned and Splat EVX-form (evlhhousplat RT,D(RA)) 4498 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4499 {EVLHHOSSPLATX, 0xfc0007ff, 0x1000030e, 0x0, // Vector Load Halfword into Halfword Odd Signed and Splat Indexed EVX-form (evlhhossplatx RT,RA,RB) 4500 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4501 {EVLHHOUSPLATX, 0xfc0007ff, 0x1000030c, 0x0, // Vector Load Halfword into Halfword Odd Unsigned and Splat Indexed EVX-form (evlhhousplatx RT,RA,RB) 4502 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4503 {EVLWHE, 0xfc0007ff, 0x10000311, 0x0, // Vector Load Word into Two Halfwords Even EVX-form (evlwhe RT,D(RA)) 4504 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4505 {EVLWHOS, 0xfc0007ff, 0x10000317, 0x0, // Vector Load Word into Two Halfwords Odd Signed (with sign extension) EVX-form (evlwhos RT,D(RA)) 4506 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4507 {EVLWHEX, 0xfc0007ff, 0x10000310, 0x0, // Vector Load Word into Two Halfwords Even Indexed EVX-form (evlwhex RT,RA,RB) 4508 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4509 {EVLWHOSX, 0xfc0007ff, 0x10000316, 0x0, // Vector Load Word into Two Halfwords Odd Signed Indexed (with sign extension) EVX-form (evlwhosx RT,RA,RB) 4510 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4511 {EVLWHOU, 0xfc0007ff, 0x10000315, 0x0, // Vector Load Word into Two Halfwords Odd Unsigned (zero-extended) EVX-form (evlwhou RT,D(RA)) 4512 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4513 {EVLWHSPLAT, 0xfc0007ff, 0x1000031d, 0x0, // Vector Load Word into Two Halfwords and Splat EVX-form (evlwhsplat RT,D(RA)) 4514 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4515 {EVLWHOUX, 0xfc0007ff, 0x10000314, 0x0, // Vector Load Word into Two Halfwords Odd Unsigned Indexed (zero-extended) EVX-form (evlwhoux RT,RA,RB) 4516 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4517 {EVLWHSPLATX, 0xfc0007ff, 0x1000031c, 0x0, // Vector Load Word into Two Halfwords and Splat Indexed EVX-form (evlwhsplatx RT,RA,RB) 4518 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4519 {EVLWWSPLAT, 0xfc0007ff, 0x10000319, 0x0, // Vector Load Word into Word and Splat EVX-form (evlwwsplat RT,D(RA)) 4520 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4521 {EVMERGEHI, 0xfc0007ff, 0x1000022c, 0x0, // Vector Merge High EVX-form (evmergehi RT,RA,RB) 4522 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4523 {EVLWWSPLATX, 0xfc0007ff, 0x10000318, 0x0, // Vector Load Word into Word and Splat Indexed EVX-form (evlwwsplatx RT,RA,RB) 4524 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4525 {EVMERGELO, 0xfc0007ff, 0x1000022d, 0x0, // Vector Merge Low EVX-form (evmergelo RT,RA,RB) 4526 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4527 {EVMERGEHILO, 0xfc0007ff, 0x1000022e, 0x0, // Vector Merge High/Low EVX-form (evmergehilo RT,RA,RB) 4528 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4529 {EVMHEGSMFAA, 0xfc0007ff, 0x1000052b, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate EVX-form (evmhegsmfaa RT,RA,RB) 4530 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4531 {EVMERGELOHI, 0xfc0007ff, 0x1000022f, 0x0, // Vector Merge Low/High EVX-form (evmergelohi RT,RA,RB) 4532 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4533 {EVMHEGSMFAN, 0xfc0007ff, 0x100005ab, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Fractional and Accumulate Negative EVX-form (evmhegsmfan RT,RA,RB) 4534 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4535 {EVMHEGSMIAA, 0xfc0007ff, 0x10000529, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate EVX-form (evmhegsmiaa RT,RA,RB) 4536 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4537 {EVMHEGUMIAA, 0xfc0007ff, 0x10000528, 0x0, // Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate EVX-form (evmhegumiaa RT,RA,RB) 4538 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4539 {EVMHEGSMIAN, 0xfc0007ff, 0x100005a9, 0x0, // Vector Multiply Halfwords, Even, Guarded, Signed, Modulo, Integer and Accumulate Negative EVX-form (evmhegsmian RT,RA,RB) 4540 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4541 {EVMHEGUMIAN, 0xfc0007ff, 0x100005a8, 0x0, // Vector Multiply Halfwords, Even, Guarded, Unsigned, Modulo, Integer and Accumulate Negative EVX-form (evmhegumian RT,RA,RB) 4542 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4543 {EVMHESMF, 0xfc0007ff, 0x1000040b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional EVX-form (evmhesmf RT,RA,RB) 4544 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4545 {EVMHESMFAAW, 0xfc0007ff, 0x1000050b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate into Words EVX-form (evmhesmfaaw RT,RA,RB) 4546 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4547 {EVMHESMFA, 0xfc0007ff, 0x1000042b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional to Accumulator EVX-form (evmhesmfa RT,RA,RB) 4548 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4549 {EVMHESMFANW, 0xfc0007ff, 0x1000058b, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Fractional and Accumulate Negative into Words EVX-form (evmhesmfanw RT,RA,RB) 4550 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4551 {EVMHESMI, 0xfc0007ff, 0x10000409, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer EVX-form (evmhesmi RT,RA,RB) 4552 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4553 {EVMHESMIAAW, 0xfc0007ff, 0x10000509, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate into Words EVX-form (evmhesmiaaw RT,RA,RB) 4554 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4555 {EVMHESMIA, 0xfc0007ff, 0x10000429, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer to Accumulator EVX-form (evmhesmia RT,RA,RB) 4556 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4557 {EVMHESMIANW, 0xfc0007ff, 0x10000589, 0x0, // Vector Multiply Halfwords, Even, Signed, Modulo, Integer and Accumulate Negative into Words EVX-form (evmhesmianw RT,RA,RB) 4558 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4559 {EVMHESSF, 0xfc0007ff, 0x10000403, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional EVX-form (evmhessf RT,RA,RB) 4560 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4561 {EVMHESSFA, 0xfc0007ff, 0x10000423, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional to Accumulator EVX-form (evmhessfa RT,RA,RB) 4562 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4563 {EVMHESSFAAW, 0xfc0007ff, 0x10000503, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate into Words EVX-form (evmhessfaaw RT,RA,RB) 4564 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4565 {EVMHESSFANW, 0xfc0007ff, 0x10000583, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Fractional and Accumulate Negative into Words EVX-form (evmhessfanw RT,RA,RB) 4566 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4567 {EVMHESSIAAW, 0xfc0007ff, 0x10000501, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate into Words EVX-form (evmhessiaaw RT,RA,RB) 4568 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4569 {EVMHESSIANW, 0xfc0007ff, 0x10000581, 0x0, // Vector Multiply Halfwords, Even, Signed, Saturate, Integer and Accumulate Negative into Words EVX-form (evmhessianw RT,RA,RB) 4570 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4571 {EVMHEUMI, 0xfc0007ff, 0x10000408, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer EVX-form (evmheumi RT,RA,RB) 4572 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4573 {EVMHEUMIAAW, 0xfc0007ff, 0x10000508, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate into Words EVX-form (evmheumiaaw RT,RA,RB) 4574 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4575 {EVMHEUMIA, 0xfc0007ff, 0x10000428, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer to Accumulator EVX-form (evmheumia RT,RA,RB) 4576 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4577 {EVMHEUMIANW, 0xfc0007ff, 0x10000588, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Modulo, Integer and Accumulate Negative into Words EVX-form (evmheumianw RT,RA,RB) 4578 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4579 {EVMHEUSIAAW, 0xfc0007ff, 0x10000500, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate into Words EVX-form (evmheusiaaw RT,RA,RB) 4580 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4581 {EVMHEUSIANW, 0xfc0007ff, 0x10000580, 0x0, // Vector Multiply Halfwords, Even, Unsigned, Saturate, Integer and Accumulate Negative into Words EVX-form (evmheusianw RT,RA,RB) 4582 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4583 {EVMHOGSMFAA, 0xfc0007ff, 0x1000052f, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate EVX-form (evmhogsmfaa RT,RA,RB) 4584 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4585 {EVMHOGSMIAA, 0xfc0007ff, 0x1000052d, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate EVX-form (evmhogsmiaa RT,RA,RB) 4586 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4587 {EVMHOGSMFAN, 0xfc0007ff, 0x100005af, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Fractional and Accumulate Negative EVX-form (evmhogsmfan RT,RA,RB) 4588 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4589 {EVMHOGSMIAN, 0xfc0007ff, 0x100005ad, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Signed, Modulo, Integer and Accumulate Negative EVX-form (evmhogsmian RT,RA,RB) 4590 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4591 {EVMHOGUMIAA, 0xfc0007ff, 0x1000052c, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate EVX-form (evmhogumiaa RT,RA,RB) 4592 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4593 {EVMHOSMF, 0xfc0007ff, 0x1000040f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional EVX-form (evmhosmf RT,RA,RB) 4594 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4595 {EVMHOGUMIAN, 0xfc0007ff, 0x100005ac, 0x0, // Vector Multiply Halfwords, Odd, Guarded, Unsigned, Modulo, Integer and Accumulate Negative EVX-form (evmhogumian RT,RA,RB) 4596 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4597 {EVMHOSMFA, 0xfc0007ff, 0x1000042f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional to Accumulator EVX-form (evmhosmfa RT,RA,RB) 4598 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4599 {EVMHOSMFAAW, 0xfc0007ff, 0x1000050f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate into Words EVX-form (evmhosmfaaw RT,RA,RB) 4600 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4601 {EVMHOSMI, 0xfc0007ff, 0x1000040d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer EVX-form (evmhosmi RT,RA,RB) 4602 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4603 {EVMHOSMFANW, 0xfc0007ff, 0x1000058f, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Fractional and Accumulate Negative into Words EVX-form (evmhosmfanw RT,RA,RB) 4604 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4605 {EVMHOSMIA, 0xfc0007ff, 0x1000042d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer to Accumulator EVX-form (evmhosmia RT,RA,RB) 4606 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4607 {EVMHOSMIAAW, 0xfc0007ff, 0x1000050d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate into Words EVX-form (evmhosmiaaw RT,RA,RB) 4608 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4609 {EVMHOSMIANW, 0xfc0007ff, 0x1000058d, 0x0, // Vector Multiply Halfwords, Odd, Signed, Modulo, Integer and Accumulate Negative into Words EVX-form (evmhosmianw RT,RA,RB) 4610 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4611 {EVMHOSSF, 0xfc0007ff, 0x10000407, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional EVX-form (evmhossf RT,RA,RB) 4612 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4613 {EVMHOSSFA, 0xfc0007ff, 0x10000427, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional to Accumulator EVX-form (evmhossfa RT,RA,RB) 4614 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4615 {EVMHOSSFAAW, 0xfc0007ff, 0x10000507, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate into Words EVX-form (evmhossfaaw RT,RA,RB) 4616 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4617 {EVMHOSSFANW, 0xfc0007ff, 0x10000587, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Fractional and Accumulate Negative into Words EVX-form (evmhossfanw RT,RA,RB) 4618 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4619 {EVMHOSSIAAW, 0xfc0007ff, 0x10000505, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate into Words EVX-form (evmhossiaaw RT,RA,RB) 4620 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4621 {EVMHOUMI, 0xfc0007ff, 0x1000040c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer EVX-form (evmhoumi RT,RA,RB) 4622 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4623 {EVMHOSSIANW, 0xfc0007ff, 0x10000585, 0x0, // Vector Multiply Halfwords, Odd, Signed, Saturate, Integer and Accumulate Negative into Words EVX-form (evmhossianw RT,RA,RB) 4624 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4625 {EVMHOUMIA, 0xfc0007ff, 0x1000042c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer to Accumulator EVX-form (evmhoumia RT,RA,RB) 4626 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4627 {EVMHOUMIAAW, 0xfc0007ff, 0x1000050c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate into Words EVX-form (evmhoumiaaw RT,RA,RB) 4628 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4629 {EVMHOUSIAAW, 0xfc0007ff, 0x10000504, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate into Words EVX-form (evmhousiaaw RT,RA,RB) 4630 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4631 {EVMHOUMIANW, 0xfc0007ff, 0x1000058c, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Modulo, Integer and Accumulate Negative into Words EVX-form (evmhoumianw RT,RA,RB) 4632 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4633 {EVMHOUSIANW, 0xfc0007ff, 0x10000584, 0x0, // Vector Multiply Halfwords, Odd, Unsigned, Saturate, Integer and Accumulate Negative into Words EVX-form (evmhousianw RT,RA,RB) 4634 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4635 {EVMRA, 0xfc0007ff, 0x100004c4, 0xf800, // Initialize Accumulator EVX-form (evmra RT,RA) 4636 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4637 {EVMWHSMF, 0xfc0007ff, 0x1000044f, 0x0, // Vector Multiply Word High Signed, Modulo, Fractional EVX-form (evmwhsmf RT,RA,RB) 4638 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4639 {EVMWHSMI, 0xfc0007ff, 0x1000044d, 0x0, // Vector Multiply Word High Signed, Modulo, Integer EVX-form (evmwhsmi RT,RA,RB) 4640 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4641 {EVMWHSMFA, 0xfc0007ff, 0x1000046f, 0x0, // Vector Multiply Word High Signed, Modulo, Fractional to Accumulator EVX-form (evmwhsmfa RT,RA,RB) 4642 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4643 {EVMWHSMIA, 0xfc0007ff, 0x1000046d, 0x0, // Vector Multiply Word High Signed, Modulo, Integer to Accumulator EVX-form (evmwhsmia RT,RA,RB) 4644 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4645 {EVMWHSSF, 0xfc0007ff, 0x10000447, 0x0, // Vector Multiply Word High Signed, Saturate, Fractional EVX-form (evmwhssf RT,RA,RB) 4646 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4647 {EVMWHUMI, 0xfc0007ff, 0x1000044c, 0x0, // Vector Multiply Word High Unsigned, Modulo, Integer EVX-form (evmwhumi RT,RA,RB) 4648 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4649 {EVMWHSSFA, 0xfc0007ff, 0x10000467, 0x0, // Vector Multiply Word High Signed, Saturate, Fractional to Accumulator EVX-form (evmwhssfa RT,RA,RB) 4650 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4651 {EVMWHUMIA, 0xfc0007ff, 0x1000046c, 0x0, // Vector Multiply Word High Unsigned, Modulo, Integer to Accumulator EVX-form (evmwhumia RT,RA,RB) 4652 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4653 {EVMWLSMIAAW, 0xfc0007ff, 0x10000549, 0x0, // Vector Multiply Word Low Signed, Modulo, Integer and Accumulate into Words EVX-form (evmwlsmiaaw RT,RA,RB) 4654 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4655 {EVMWLSSIAAW, 0xfc0007ff, 0x10000541, 0x0, // Vector Multiply Word Low Signed, Saturate, Integer and Accumulate into Words EVX-form (evmwlssiaaw RT,RA,RB) 4656 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4657 {EVMWLSMIANW, 0xfc0007ff, 0x100005c9, 0x0, // Vector Multiply Word Low Signed, Modulo, Integer and Accumulate Negative in Words EVX-form (evmwlsmianw RT,RA,RB) 4658 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4659 {EVMWLSSIANW, 0xfc0007ff, 0x100005c1, 0x0, // Vector Multiply Word Low Signed, Saturate, Integer and Accumulate Negative in Words EVX-form (evmwlssianw RT,RA,RB) 4660 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4661 {EVMWLUMI, 0xfc0007ff, 0x10000448, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer EVX-form (evmwlumi RT,RA,RB) 4662 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4663 {EVMWLUMIAAW, 0xfc0007ff, 0x10000548, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate into Words EVX-form (evmwlumiaaw RT,RA,RB) 4664 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4665 {EVMWLUMIA, 0xfc0007ff, 0x10000468, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer to Accumulator EVX-form (evmwlumia RT,RA,RB) 4666 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4667 {EVMWLUMIANW, 0xfc0007ff, 0x100005c8, 0x0, // Vector Multiply Word Low Unsigned, Modulo, Integer and Accumulate Negative in Words EVX-form (evmwlumianw RT,RA,RB) 4668 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4669 {EVMWLUSIAAW, 0xfc0007ff, 0x10000540, 0x0, // Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate into Words EVX-form (evmwlusiaaw RT,RA,RB) 4670 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4671 {EVMWSMF, 0xfc0007ff, 0x1000045b, 0x0, // Vector Multiply Word Signed, Modulo, Fractional EVX-form (evmwsmf RT,RA,RB) 4672 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4673 {EVMWLUSIANW, 0xfc0007ff, 0x100005c0, 0x0, // Vector Multiply Word Low Unsigned, Saturate, Integer and Accumulate Negative in Words EVX-form (evmwlusianw RT,RA,RB) 4674 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4675 {EVMWSMFA, 0xfc0007ff, 0x1000047b, 0x0, // Vector Multiply Word Signed, Modulo, Fractional to Accumulator EVX-form (evmwsmfa RT,RA,RB) 4676 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4677 {EVMWSMFAA, 0xfc0007ff, 0x1000055b, 0x0, // Vector Multiply Word Signed, Modulo, Fractional and Accumulate EVX-form (evmwsmfaa RT,RA,RB) 4678 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4679 {EVMWSMI, 0xfc0007ff, 0x10000459, 0x0, // Vector Multiply Word Signed, Modulo, Integer EVX-form (evmwsmi RT,RA,RB) 4680 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4681 {EVMWSMIAA, 0xfc0007ff, 0x10000559, 0x0, // Vector Multiply Word Signed, Modulo, Integer and Accumulate EVX-form (evmwsmiaa RT,RA,RB) 4682 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4683 {EVMWSMFAN, 0xfc0007ff, 0x100005db, 0x0, // Vector Multiply Word Signed, Modulo, Fractional and Accumulate Negative EVX-form (evmwsmfan RT,RA,RB) 4684 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4685 {EVMWSMIA, 0xfc0007ff, 0x10000479, 0x0, // Vector Multiply Word Signed, Modulo, Integer to Accumulator EVX-form (evmwsmia RT,RA,RB) 4686 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4687 {EVMWSMIAN, 0xfc0007ff, 0x100005d9, 0x0, // Vector Multiply Word Signed, Modulo, Integer and Accumulate Negative EVX-form (evmwsmian RT,RA,RB) 4688 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4689 {EVMWSSF, 0xfc0007ff, 0x10000453, 0x0, // Vector Multiply Word Signed, Saturate, Fractional EVX-form (evmwssf RT,RA,RB) 4690 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4691 {EVMWSSFA, 0xfc0007ff, 0x10000473, 0x0, // Vector Multiply Word Signed, Saturate, Fractional to Accumulator EVX-form (evmwssfa RT,RA,RB) 4692 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4693 {EVMWSSFAA, 0xfc0007ff, 0x10000553, 0x0, // Vector Multiply Word Signed, Saturate, Fractional and Accumulate EVX-form (evmwssfaa RT,RA,RB) 4694 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4695 {EVMWUMI, 0xfc0007ff, 0x10000458, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer EVX-form (evmwumi RT,RA,RB) 4696 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4697 {EVMWSSFAN, 0xfc0007ff, 0x100005d3, 0x0, // Vector Multiply Word Signed, Saturate, Fractional and Accumulate Negative EVX-form (evmwssfan RT,RA,RB) 4698 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4699 {EVMWUMIA, 0xfc0007ff, 0x10000478, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer to Accumulator EVX-form (evmwumia RT,RA,RB) 4700 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4701 {EVMWUMIAA, 0xfc0007ff, 0x10000558, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer and Accumulate EVX-form (evmwumiaa RT,RA,RB) 4702 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4703 {EVNAND, 0xfc0007ff, 0x1000021e, 0x0, // Vector NAND EVX-form (evnand RT,RA,RB) 4704 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4705 {EVMWUMIAN, 0xfc0007ff, 0x100005d8, 0x0, // Vector Multiply Word Unsigned, Modulo, Integer and Accumulate Negative EVX-form (evmwumian RT,RA,RB) 4706 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4707 {EVNEG, 0xfc0007ff, 0x10000209, 0xf800, // Vector Negate EVX-form (evneg RT,RA) 4708 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4709 {EVNOR, 0xfc0007ff, 0x10000218, 0x0, // Vector NOR EVX-form (evnor RT,RA,RB) 4710 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4711 {EVORC, 0xfc0007ff, 0x1000021b, 0x0, // Vector OR with Complement EVX-form (evorc RT,RA,RB) 4712 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4713 {EVOR, 0xfc0007ff, 0x10000217, 0x0, // Vector OR EVX-form (evor RT,RA,RB) 4714 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4715 {EVRLW, 0xfc0007ff, 0x10000228, 0x0, // Vector Rotate Left Word EVX-form (evrlw RT,RA,RB) 4716 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4717 {EVRLWI, 0xfc0007ff, 0x1000022a, 0x0, // Vector Rotate Left Word Immediate EVX-form (evrlwi RT,RA,UI) 4718 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, 4719 {EVSEL, 0xfc0007f8, 0x10000278, 0x0, // Vector Select EVS-form (evsel RT,RA,RB,BFA) 4720 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_CondRegField_29_31}}, 4721 {EVRNDW, 0xfc0007ff, 0x1000020c, 0xf800, // Vector Round Word EVX-form (evrndw RT,RA) 4722 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4723 {EVSLW, 0xfc0007ff, 0x10000224, 0x0, // Vector Shift Left Word EVX-form (evslw RT,RA,RB) 4724 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4725 {EVSPLATFI, 0xfc0007ff, 0x1000022b, 0xf800, // Vector Splat Fractional Immediate EVX-form (evsplatfi RT,SI) 4726 [5]*argField{ap_Reg_6_10, ap_ImmSigned_11_15}}, 4727 {EVSRWIS, 0xfc0007ff, 0x10000223, 0x0, // Vector Shift Right Word Immediate Signed EVX-form (evsrwis RT,RA,UI) 4728 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, 4729 {EVSLWI, 0xfc0007ff, 0x10000226, 0x0, // Vector Shift Left Word Immediate EVX-form (evslwi RT,RA,UI) 4730 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, 4731 {EVSPLATI, 0xfc0007ff, 0x10000229, 0xf800, // Vector Splat Immediate EVX-form (evsplati RT,SI) 4732 [5]*argField{ap_Reg_6_10, ap_ImmSigned_11_15}}, 4733 {EVSRWIU, 0xfc0007ff, 0x10000222, 0x0, // Vector Shift Right Word Immediate Unsigned EVX-form (evsrwiu RT,RA,UI) 4734 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_ImmUnsigned_16_20}}, 4735 {EVSRWS, 0xfc0007ff, 0x10000221, 0x0, // Vector Shift Right Word Signed EVX-form (evsrws RT,RA,RB) 4736 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4737 {EVSTDD, 0xfc0007ff, 0x10000321, 0x0, // Vector Store Double of Double EVX-form (evstdd RS,D(RA)) 4738 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4739 {EVSRWU, 0xfc0007ff, 0x10000220, 0x0, // Vector Shift Right Word Unsigned EVX-form (evsrwu RT,RA,RB) 4740 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4741 {EVSTDDX, 0xfc0007ff, 0x10000320, 0x0, // Vector Store Double of Double Indexed EVX-form (evstddx RS,RA,RB) 4742 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4743 {EVSTDH, 0xfc0007ff, 0x10000325, 0x0, // Vector Store Double of Four Halfwords EVX-form (evstdh RS,D(RA)) 4744 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4745 {EVSTDW, 0xfc0007ff, 0x10000323, 0x0, // Vector Store Double of Two Words EVX-form (evstdw RS,D(RA)) 4746 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4747 {EVSTDHX, 0xfc0007ff, 0x10000324, 0x0, // Vector Store Double of Four Halfwords Indexed EVX-form (evstdhx RS,RA,RB) 4748 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4749 {EVSTDWX, 0xfc0007ff, 0x10000322, 0x0, // Vector Store Double of Two Words Indexed EVX-form (evstdwx RS,RA,RB) 4750 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4751 {EVSTWHE, 0xfc0007ff, 0x10000331, 0x0, // Vector Store Word of Two Halfwords from Even EVX-form (evstwhe RS,D(RA)) 4752 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4753 {EVSTWHO, 0xfc0007ff, 0x10000335, 0x0, // Vector Store Word of Two Halfwords from Odd EVX-form (evstwho RS,D(RA)) 4754 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4755 {EVSTWWE, 0xfc0007ff, 0x10000339, 0x0, // Vector Store Word of Word from Even EVX-form (evstwwe RS,D(RA)) 4756 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4757 {EVSTWHEX, 0xfc0007ff, 0x10000330, 0x0, // Vector Store Word of Two Halfwords from Even Indexed EVX-form (evstwhex RS,RA,RB) 4758 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4759 {EVSTWHOX, 0xfc0007ff, 0x10000334, 0x0, // Vector Store Word of Two Halfwords from Odd Indexed EVX-form (evstwhox RS,RA,RB) 4760 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4761 {EVSTWWEX, 0xfc0007ff, 0x10000338, 0x0, // Vector Store Word of Word from Even Indexed EVX-form (evstwwex RS,RA,RB) 4762 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4763 {EVSTWWO, 0xfc0007ff, 0x1000033d, 0x0, // Vector Store Word of Word from Odd EVX-form (evstwwo RS,D(RA)) 4764 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_16_20, ap_Reg_11_15}}, 4765 {EVSUBFSMIAAW, 0xfc0007ff, 0x100004cb, 0xf800, // Vector Subtract Signed, Modulo, Integer to Accumulator Word EVX-form (evsubfsmiaaw RT,RA) 4766 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4767 {EVSTWWOX, 0xfc0007ff, 0x1000033c, 0x0, // Vector Store Word of Word from Odd Indexed EVX-form (evstwwox RS,RA,RB) 4768 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4769 {EVSUBFSSIAAW, 0xfc0007ff, 0x100004c3, 0xf800, // Vector Subtract Signed, Saturate, Integer to Accumulator Word EVX-form (evsubfssiaaw RT,RA) 4770 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4771 {EVSUBFUMIAAW, 0xfc0007ff, 0x100004ca, 0xf800, // Vector Subtract Unsigned, Modulo, Integer to Accumulator Word EVX-form (evsubfumiaaw RT,RA) 4772 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4773 {EVSUBFUSIAAW, 0xfc0007ff, 0x100004c2, 0xf800, // Vector Subtract Unsigned, Saturate, Integer to Accumulator Word EVX-form (evsubfusiaaw RT,RA) 4774 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4775 {EVSUBFW, 0xfc0007ff, 0x10000204, 0x0, // Vector Subtract from Word EVX-form (evsubfw RT,RA,RB) 4776 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4777 {EVSUBIFW, 0xfc0007ff, 0x10000206, 0x0, // Vector Subtract Immediate from Word EVX-form (evsubifw RT,UI,RB) 4778 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_11_15, ap_Reg_16_20}}, 4779 {EVXOR, 0xfc0007ff, 0x10000216, 0x0, // Vector XOR EVX-form (evxor RT,RA,RB) 4780 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4781 {EVFSABS, 0xfc0007ff, 0x10000284, 0xf800, // Vector Floating-Point Single-Precision Absolute Value EVX-form (evfsabs RT,RA) 4782 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4783 {EVFSNABS, 0xfc0007ff, 0x10000285, 0xf800, // Vector Floating-Point Single-Precision Negative Absolute Value EVX-form (evfsnabs RT,RA) 4784 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4785 {EVFSNEG, 0xfc0007ff, 0x10000286, 0xf800, // Vector Floating-Point Single-Precision Negate EVX-form (evfsneg RT,RA) 4786 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4787 {EVFSADD, 0xfc0007ff, 0x10000280, 0x0, // Vector Floating-Point Single-Precision Add EVX-form (evfsadd RT,RA,RB) 4788 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4789 {EVFSMUL, 0xfc0007ff, 0x10000288, 0x0, // Vector Floating-Point Single-Precision Multiply EVX-form (evfsmul RT,RA,RB) 4790 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4791 {EVFSSUB, 0xfc0007ff, 0x10000281, 0x0, // Vector Floating-Point Single-Precision Subtract EVX-form (evfssub RT,RA,RB) 4792 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4793 {EVFSDIV, 0xfc0007ff, 0x10000289, 0x0, // Vector Floating-Point Single-Precision Divide EVX-form (evfsdiv RT,RA,RB) 4794 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4795 {EVFSCMPGT, 0xfc0007ff, 0x1000028c, 0x600000, // Vector Floating-Point Single-Precision Compare Greater Than EVX-form (evfscmpgt BF,RA,RB) 4796 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4797 {EVFSCMPLT, 0xfc0007ff, 0x1000028d, 0x600000, // Vector Floating-Point Single-Precision Compare Less Than EVX-form (evfscmplt BF,RA,RB) 4798 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4799 {EVFSCMPEQ, 0xfc0007ff, 0x1000028e, 0x600000, // Vector Floating-Point Single-Precision Compare Equal EVX-form (evfscmpeq BF,RA,RB) 4800 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4801 {EVFSTSTGT, 0xfc0007ff, 0x1000029c, 0x600000, // Vector Floating-Point Single-Precision Test Greater Than EVX-form (evfststgt BF,RA,RB) 4802 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4803 {EVFSTSTLT, 0xfc0007ff, 0x1000029d, 0x600000, // Vector Floating-Point Single-Precision Test Less Than EVX-form (evfststlt BF,RA,RB) 4804 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4805 {EVFSTSTEQ, 0xfc0007ff, 0x1000029e, 0x600000, // Vector Floating-Point Single-Precision Test Equal EVX-form (evfststeq BF,RA,RB) 4806 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4807 {EVFSCFSI, 0xfc0007ff, 0x10000291, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Signed Integer EVX-form (evfscfsi RT,RB) 4808 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4809 {EVFSCFSF, 0xfc0007ff, 0x10000293, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Signed Fraction EVX-form (evfscfsf RT,RB) 4810 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4811 {EVFSCFUI, 0xfc0007ff, 0x10000290, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Unsigned Integer EVX-form (evfscfui RT,RB) 4812 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4813 {EVFSCFUF, 0xfc0007ff, 0x10000292, 0x1f0000, // Vector Convert Floating-Point Single-Precision from Unsigned Fraction EVX-form (evfscfuf RT,RB) 4814 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4815 {EVFSCTSI, 0xfc0007ff, 0x10000295, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Signed Integer EVX-form (evfsctsi RT,RB) 4816 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4817 {EVFSCTUI, 0xfc0007ff, 0x10000294, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Unsigned Integer EVX-form (evfsctui RT,RB) 4818 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4819 {EVFSCTSIZ, 0xfc0007ff, 0x1000029a, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Signed Integer with Round toward Zero EVX-form (evfsctsiz RT,RB) 4820 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4821 {EVFSCTUIZ, 0xfc0007ff, 0x10000298, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Unsigned Integer with Round toward Zero EVX-form (evfsctuiz RT,RB) 4822 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4823 {EVFSCTSF, 0xfc0007ff, 0x10000297, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Signed Fraction EVX-form (evfsctsf RT,RB) 4824 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4825 {EVFSCTUF, 0xfc0007ff, 0x10000296, 0x1f0000, // Vector Convert Floating-Point Single-Precision to Unsigned Fraction EVX-form (evfsctuf RT,RB) 4826 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4827 {EFSABS, 0xfc0007ff, 0x100002c4, 0xf800, // Floating-Point Single-Precision Absolute Value EVX-form (efsabs RT,RA) 4828 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4829 {EFSNEG, 0xfc0007ff, 0x100002c6, 0xf800, // Floating-Point Single-Precision Negate EVX-form (efsneg RT,RA) 4830 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4831 {EFSNABS, 0xfc0007ff, 0x100002c5, 0xf800, // Floating-Point Single-Precision Negative Absolute Value EVX-form (efsnabs RT,RA) 4832 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4833 {EFSADD, 0xfc0007ff, 0x100002c0, 0x0, // Floating-Point Single-Precision Add EVX-form (efsadd RT,RA,RB) 4834 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4835 {EFSMUL, 0xfc0007ff, 0x100002c8, 0x0, // Floating-Point Single-Precision Multiply EVX-form (efsmul RT,RA,RB) 4836 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4837 {EFSSUB, 0xfc0007ff, 0x100002c1, 0x0, // Floating-Point Single-Precision Subtract EVX-form (efssub RT,RA,RB) 4838 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4839 {EFSDIV, 0xfc0007ff, 0x100002c9, 0x0, // Floating-Point Single-Precision Divide EVX-form (efsdiv RT,RA,RB) 4840 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4841 {EFSCMPGT, 0xfc0007ff, 0x100002cc, 0x600000, // Floating-Point Single-Precision Compare Greater Than EVX-form (efscmpgt BF,RA,RB) 4842 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4843 {EFSCMPLT, 0xfc0007ff, 0x100002cd, 0x600000, // Floating-Point Single-Precision Compare Less Than EVX-form (efscmplt BF,RA,RB) 4844 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4845 {EFSCMPEQ, 0xfc0007ff, 0x100002ce, 0x600000, // Floating-Point Single-Precision Compare Equal EVX-form (efscmpeq BF,RA,RB) 4846 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4847 {EFSTSTGT, 0xfc0007ff, 0x100002dc, 0x600000, // Floating-Point Single-Precision Test Greater Than EVX-form (efststgt BF,RA,RB) 4848 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4849 {EFSTSTLT, 0xfc0007ff, 0x100002dd, 0x600000, // Floating-Point Single-Precision Test Less Than EVX-form (efststlt BF,RA,RB) 4850 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4851 {EFSTSTEQ, 0xfc0007ff, 0x100002de, 0x600000, // Floating-Point Single-Precision Test Equal EVX-form (efststeq BF,RA,RB) 4852 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4853 {EFSCFSI, 0xfc0007ff, 0x100002d1, 0x1f0000, // Convert Floating-Point Single-Precision from Signed Integer EVX-form (efscfsi RT,RB) 4854 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4855 {EFSCFSF, 0xfc0007ff, 0x100002d3, 0x1f0000, // Convert Floating-Point Single-Precision from Signed Fraction EVX-form (efscfsf RT,RB) 4856 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4857 {EFSCTSI, 0xfc0007ff, 0x100002d5, 0x1f0000, // Convert Floating-Point Single-Precision to Signed Integer EVX-form (efsctsi RT,RB) 4858 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4859 {EFSCFUI, 0xfc0007ff, 0x100002d0, 0x1f0000, // Convert Floating-Point Single-Precision from Unsigned Integer EVX-form (efscfui RT,RB) 4860 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4861 {EFSCFUF, 0xfc0007ff, 0x100002d2, 0x1f0000, // Convert Floating-Point Single-Precision from Unsigned Fraction EVX-form (efscfuf RT,RB) 4862 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4863 {EFSCTUI, 0xfc0007ff, 0x100002d4, 0x1f0000, // Convert Floating-Point Single-Precision to Unsigned Integer EVX-form (efsctui RT,RB) 4864 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4865 {EFSCTSIZ, 0xfc0007ff, 0x100002da, 0x1f0000, // Convert Floating-Point Single-Precision to Signed Integer with Round toward Zero EVX-form (efsctsiz RT,RB) 4866 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4867 {EFSCTSF, 0xfc0007ff, 0x100002d7, 0x1f0000, // Convert Floating-Point Single-Precision to Signed Fraction EVX-form (efsctsf RT,RB) 4868 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4869 {EFSCTUIZ, 0xfc0007ff, 0x100002d8, 0x1f0000, // Convert Floating-Point Single-Precision to Unsigned Integer with Round toward Zero EVX-form (efsctuiz RT,RB) 4870 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4871 {EFSCTUF, 0xfc0007ff, 0x100002d6, 0x1f0000, // Convert Floating-Point Single-Precision to Unsigned Fraction EVX-form (efsctuf RT,RB) 4872 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4873 {EFDABS, 0xfc0007ff, 0x100002e4, 0xf800, // Floating-Point Double-Precision Absolute Value EVX-form (efdabs RT,RA) 4874 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4875 {EFDNEG, 0xfc0007ff, 0x100002e6, 0xf800, // Floating-Point Double-Precision Negate EVX-form (efdneg RT,RA) 4876 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4877 {EFDNABS, 0xfc0007ff, 0x100002e5, 0xf800, // Floating-Point Double-Precision Negative Absolute Value EVX-form (efdnabs RT,RA) 4878 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 4879 {EFDADD, 0xfc0007ff, 0x100002e0, 0x0, // Floating-Point Double-Precision Add EVX-form (efdadd RT,RA,RB) 4880 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4881 {EFDMUL, 0xfc0007ff, 0x100002e8, 0x0, // Floating-Point Double-Precision Multiply EVX-form (efdmul RT,RA,RB) 4882 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4883 {EFDSUB, 0xfc0007ff, 0x100002e1, 0x0, // Floating-Point Double-Precision Subtract EVX-form (efdsub RT,RA,RB) 4884 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4885 {EFDDIV, 0xfc0007ff, 0x100002e9, 0x0, // Floating-Point Double-Precision Divide EVX-form (efddiv RT,RA,RB) 4886 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4887 {EFDCMPGT, 0xfc0007ff, 0x100002ec, 0x600000, // Floating-Point Double-Precision Compare Greater Than EVX-form (efdcmpgt BF,RA,RB) 4888 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4889 {EFDCMPEQ, 0xfc0007ff, 0x100002ee, 0x600000, // Floating-Point Double-Precision Compare Equal EVX-form (efdcmpeq BF,RA,RB) 4890 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4891 {EFDCMPLT, 0xfc0007ff, 0x100002ed, 0x600000, // Floating-Point Double-Precision Compare Less Than EVX-form (efdcmplt BF,RA,RB) 4892 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4893 {EFDTSTGT, 0xfc0007ff, 0x100002fc, 0x600000, // Floating-Point Double-Precision Test Greater Than EVX-form (efdtstgt BF,RA,RB) 4894 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4895 {EFDTSTLT, 0xfc0007ff, 0x100002fd, 0x600000, // Floating-Point Double-Precision Test Less Than EVX-form (efdtstlt BF,RA,RB) 4896 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4897 {EFDCFSI, 0xfc0007ff, 0x100002f1, 0x1f0000, // Convert Floating-Point Double-Precision from Signed Integer EVX-form (efdcfsi RT,RB) 4898 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4899 {EFDTSTEQ, 0xfc0007ff, 0x100002fe, 0x600000, // Floating-Point Double-Precision Test Equal EVX-form (efdtsteq BF,RA,RB) 4900 [5]*argField{ap_CondRegField_6_8, ap_Reg_11_15, ap_Reg_16_20}}, 4901 {EFDCFUI, 0xfc0007ff, 0x100002f0, 0x1f0000, // Convert Floating-Point Double-Precision from Unsigned Integer EVX-form (efdcfui RT,RB) 4902 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4903 {EFDCFSID, 0xfc0007ff, 0x100002e3, 0x1f0000, // Convert Floating-Point Double-Precision from Signed Integer Doubleword EVX-form (efdcfsid RT,RB) 4904 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4905 {EFDCFSF, 0xfc0007ff, 0x100002f3, 0x1f0000, // Convert Floating-Point Double-Precision from Signed Fraction EVX-form (efdcfsf RT,RB) 4906 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4907 {EFDCFUF, 0xfc0007ff, 0x100002f2, 0x1f0000, // Convert Floating-Point Double-Precision from Unsigned Fraction EVX-form (efdcfuf RT,RB) 4908 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4909 {EFDCFUID, 0xfc0007ff, 0x100002e2, 0x1f0000, // Convert Floating-Point Double-Precision from Unsigned Integer Doubleword EVX-form (efdcfuid RT,RB) 4910 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4911 {EFDCTSI, 0xfc0007ff, 0x100002f5, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Integer EVX-form (efdctsi RT,RB) 4912 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4913 {EFDCTUI, 0xfc0007ff, 0x100002f4, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Integer EVX-form (efdctui RT,RB) 4914 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4915 {EFDCTSIDZ, 0xfc0007ff, 0x100002eb, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Integer Doubleword with Round toward Zero EVX-form (efdctsidz RT,RB) 4916 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4917 {EFDCTUIDZ, 0xfc0007ff, 0x100002ea, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Integer Doubleword with Round toward Zero EVX-form (efdctuidz RT,RB) 4918 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4919 {EFDCTSIZ, 0xfc0007ff, 0x100002fa, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Integer with Round toward Zero EVX-form (efdctsiz RT,RB) 4920 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4921 {EFDCTSF, 0xfc0007ff, 0x100002f7, 0x1f0000, // Convert Floating-Point Double-Precision to Signed Fraction EVX-form (efdctsf RT,RB) 4922 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4923 {EFDCTUF, 0xfc0007ff, 0x100002f6, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Fraction EVX-form (efdctuf RT,RB) 4924 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4925 {EFDCTUIZ, 0xfc0007ff, 0x100002f8, 0x1f0000, // Convert Floating-Point Double-Precision to Unsigned Integer with Round toward Zero EVX-form (efdctuiz RT,RB) 4926 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4927 {EFDCFS, 0xfc0007ff, 0x100002ef, 0x1f0000, // Floating-Point Double-Precision Convert from Single-Precision EVX-form (efdcfs RT,RB) 4928 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4929 {EFSCFD, 0xfc0007ff, 0x100002cf, 0x1f0000, // Floating-Point Single-Precision Convert from Double-Precision EVX-form (efscfd RT,RB) 4930 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 4931 {DLMZB, 0xfc0007ff, 0x7c00009c, 0x0, // Determine Leftmost Zero Byte X-form (dlmzb RA,RS,RB) 4932 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 4933 {DLMZB_, 0xfc0007ff, 0x7c00009d, 0x0, // Determine Leftmost Zero Byte X-form (dlmzb. RA,RS,RB) 4934 [5]*argField{ap_Reg_11_15, ap_Reg_6_10, ap_Reg_16_20}}, 4935 {MACCHW, 0xfc0007ff, 0x10000158, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchw RT,RA,RB) 4936 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4937 {MACCHW_, 0xfc0007ff, 0x10000159, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchw. RT,RA,RB) 4938 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4939 {MACCHWO, 0xfc0007ff, 0x10000558, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchwo RT,RA,RB) 4940 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4941 {MACCHWO_, 0xfc0007ff, 0x10000559, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (macchwo. RT,RA,RB) 4942 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4943 {MACCHWS, 0xfc0007ff, 0x100001d8, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchws RT,RA,RB) 4944 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4945 {MACCHWS_, 0xfc0007ff, 0x100001d9, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchws. RT,RA,RB) 4946 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4947 {MACCHWSO, 0xfc0007ff, 0x100005d8, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchwso RT,RA,RB) 4948 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4949 {MACCHWSO_, 0xfc0007ff, 0x100005d9, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (macchwso. RT,RA,RB) 4950 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4951 {MACCHWU, 0xfc0007ff, 0x10000118, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwu RT,RA,RB) 4952 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4953 {MACCHWU_, 0xfc0007ff, 0x10000119, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwu. RT,RA,RB) 4954 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4955 {MACCHWUO, 0xfc0007ff, 0x10000518, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwuo RT,RA,RB) 4956 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4957 {MACCHWUO_, 0xfc0007ff, 0x10000519, 0x0, // Multiply Accumulate Cross Halfword to Word Modulo Unsigned XO-form (macchwuo. RT,RA,RB) 4958 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4959 {MACCHWSU, 0xfc0007ff, 0x10000198, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsu RT,RA,RB) 4960 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4961 {MACCHWSU_, 0xfc0007ff, 0x10000199, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsu. RT,RA,RB) 4962 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4963 {MACCHWSUO, 0xfc0007ff, 0x10000598, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsuo RT,RA,RB) 4964 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4965 {MACCHWSUO_, 0xfc0007ff, 0x10000599, 0x0, // Multiply Accumulate Cross Halfword to Word Saturate Unsigned XO-form (macchwsuo. RT,RA,RB) 4966 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4967 {MACHHW, 0xfc0007ff, 0x10000058, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhw RT,RA,RB) 4968 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4969 {MACHHW_, 0xfc0007ff, 0x10000059, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhw. RT,RA,RB) 4970 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4971 {MACHHWO, 0xfc0007ff, 0x10000458, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhwo RT,RA,RB) 4972 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4973 {MACHHWO_, 0xfc0007ff, 0x10000459, 0x0, // Multiply Accumulate High Halfword to Word Modulo Signed XO-form (machhwo. RT,RA,RB) 4974 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4975 {MACHHWS, 0xfc0007ff, 0x100000d8, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhws RT,RA,RB) 4976 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4977 {MACHHWS_, 0xfc0007ff, 0x100000d9, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhws. RT,RA,RB) 4978 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4979 {MACHHWSO, 0xfc0007ff, 0x100004d8, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhwso RT,RA,RB) 4980 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4981 {MACHHWSO_, 0xfc0007ff, 0x100004d9, 0x0, // Multiply Accumulate High Halfword to Word Saturate Signed XO-form (machhwso. RT,RA,RB) 4982 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4983 {MACHHWU, 0xfc0007ff, 0x10000018, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwu RT,RA,RB) 4984 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4985 {MACHHWU_, 0xfc0007ff, 0x10000019, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwu. RT,RA,RB) 4986 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4987 {MACHHWUO, 0xfc0007ff, 0x10000418, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwuo RT,RA,RB) 4988 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4989 {MACHHWUO_, 0xfc0007ff, 0x10000419, 0x0, // Multiply Accumulate High Halfword to Word Modulo Unsigned XO-form (machhwuo. RT,RA,RB) 4990 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4991 {MACHHWSU, 0xfc0007ff, 0x10000098, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsu RT,RA,RB) 4992 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4993 {MACHHWSU_, 0xfc0007ff, 0x10000099, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsu. RT,RA,RB) 4994 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4995 {MACHHWSUO, 0xfc0007ff, 0x10000498, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsuo RT,RA,RB) 4996 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4997 {MACHHWSUO_, 0xfc0007ff, 0x10000499, 0x0, // Multiply Accumulate High Halfword to Word Saturate Unsigned XO-form (machhwsuo. RT,RA,RB) 4998 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 4999 {MACLHW, 0xfc0007ff, 0x10000358, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhw RT,RA,RB) 5000 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5001 {MACLHW_, 0xfc0007ff, 0x10000359, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhw. RT,RA,RB) 5002 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5003 {MACLHWO, 0xfc0007ff, 0x10000758, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhwo RT,RA,RB) 5004 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5005 {MACLHWO_, 0xfc0007ff, 0x10000759, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (maclhwo. RT,RA,RB) 5006 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5007 {MACLHWS, 0xfc0007ff, 0x100003d8, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhws RT,RA,RB) 5008 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5009 {MACLHWS_, 0xfc0007ff, 0x100003d9, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhws. RT,RA,RB) 5010 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5011 {MACLHWSO, 0xfc0007ff, 0x100007d8, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhwso RT,RA,RB) 5012 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5013 {MACLHWSO_, 0xfc0007ff, 0x100007d9, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (maclhwso. RT,RA,RB) 5014 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5015 {MACLHWU, 0xfc0007ff, 0x10000318, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwu RT,RA,RB) 5016 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5017 {MACLHWU_, 0xfc0007ff, 0x10000319, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwu. RT,RA,RB) 5018 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5019 {MACLHWUO, 0xfc0007ff, 0x10000718, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwuo RT,RA,RB) 5020 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5021 {MACLHWUO_, 0xfc0007ff, 0x10000719, 0x0, // Multiply Accumulate Low Halfword to Word Modulo Unsigned XO-form (maclhwuo. RT,RA,RB) 5022 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5023 {MULCHW, 0xfc0007ff, 0x10000150, 0x0, // Multiply Cross Halfword to Word Signed X-form (mulchw RT,RA,RB) 5024 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5025 {MULCHW_, 0xfc0007ff, 0x10000151, 0x0, // Multiply Cross Halfword to Word Signed X-form (mulchw. RT,RA,RB) 5026 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5027 {MACLHWSU, 0xfc0007ff, 0x10000398, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsu RT,RA,RB) 5028 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5029 {MACLHWSU_, 0xfc0007ff, 0x10000399, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsu. RT,RA,RB) 5030 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5031 {MACLHWSUO, 0xfc0007ff, 0x10000798, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsuo RT,RA,RB) 5032 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5033 {MACLHWSUO_, 0xfc0007ff, 0x10000799, 0x0, // Multiply Accumulate Low Halfword to Word Saturate Unsigned XO-form (maclhwsuo. RT,RA,RB) 5034 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5035 {MULCHWU, 0xfc0007ff, 0x10000110, 0x0, // Multiply Cross Halfword to Word Unsigned X-form (mulchwu RT,RA,RB) 5036 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5037 {MULCHWU_, 0xfc0007ff, 0x10000111, 0x0, // Multiply Cross Halfword to Word Unsigned X-form (mulchwu. RT,RA,RB) 5038 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5039 {MULHHW, 0xfc0007ff, 0x10000050, 0x0, // Multiply High Halfword to Word Signed X-form (mulhhw RT,RA,RB) 5040 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5041 {MULHHW_, 0xfc0007ff, 0x10000051, 0x0, // Multiply High Halfword to Word Signed X-form (mulhhw. RT,RA,RB) 5042 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5043 {MULLHW, 0xfc0007ff, 0x10000350, 0x0, // Multiply Low Halfword to Word Signed X-form (mullhw RT,RA,RB) 5044 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5045 {MULLHW_, 0xfc0007ff, 0x10000351, 0x0, // Multiply Low Halfword to Word Signed X-form (mullhw. RT,RA,RB) 5046 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5047 {MULHHWU, 0xfc0007ff, 0x10000010, 0x0, // Multiply High Halfword to Word Unsigned X-form (mulhhwu RT,RA,RB) 5048 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5049 {MULHHWU_, 0xfc0007ff, 0x10000011, 0x0, // Multiply High Halfword to Word Unsigned X-form (mulhhwu. RT,RA,RB) 5050 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5051 {MULLHWU, 0xfc0007ff, 0x10000310, 0x0, // Multiply Low Halfword to Word Unsigned X-form (mullhwu RT,RA,RB) 5052 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5053 {MULLHWU_, 0xfc0007ff, 0x10000311, 0x0, // Multiply Low Halfword to Word Unsigned X-form (mullhwu. RT,RA,RB) 5054 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5055 {NMACCHW, 0xfc0007ff, 0x1000015c, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchw RT,RA,RB) 5056 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5057 {NMACCHW_, 0xfc0007ff, 0x1000015d, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchw. RT,RA,RB) 5058 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5059 {NMACCHWO, 0xfc0007ff, 0x1000055c, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchwo RT,RA,RB) 5060 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5061 {NMACCHWO_, 0xfc0007ff, 0x1000055d, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Modulo Signed XO-form (nmacchwo. RT,RA,RB) 5062 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5063 {NMACCHWS, 0xfc0007ff, 0x100001dc, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchws RT,RA,RB) 5064 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5065 {NMACCHWS_, 0xfc0007ff, 0x100001dd, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchws. RT,RA,RB) 5066 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5067 {NMACCHWSO, 0xfc0007ff, 0x100005dc, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchwso RT,RA,RB) 5068 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5069 {NMACCHWSO_, 0xfc0007ff, 0x100005dd, 0x0, // Negative Multiply Accumulate Cross Halfword to Word Saturate Signed XO-form (nmacchwso. RT,RA,RB) 5070 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5071 {NMACHHW, 0xfc0007ff, 0x1000005c, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhw RT,RA,RB) 5072 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5073 {NMACHHW_, 0xfc0007ff, 0x1000005d, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhw. RT,RA,RB) 5074 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5075 {NMACHHWO, 0xfc0007ff, 0x1000045c, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhwo RT,RA,RB) 5076 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5077 {NMACHHWO_, 0xfc0007ff, 0x1000045d, 0x0, // Negative Multiply Accumulate High Halfword to Word Modulo Signed XO-form (nmachhwo. RT,RA,RB) 5078 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5079 {NMACHHWS, 0xfc0007ff, 0x100000dc, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhws RT,RA,RB) 5080 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5081 {NMACHHWS_, 0xfc0007ff, 0x100000dd, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhws. RT,RA,RB) 5082 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5083 {NMACHHWSO, 0xfc0007ff, 0x100004dc, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhwso RT,RA,RB) 5084 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5085 {NMACHHWSO_, 0xfc0007ff, 0x100004dd, 0x0, // Negative Multiply Accumulate High Halfword to Word Saturate Signed XO-form (nmachhwso. RT,RA,RB) 5086 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5087 {NMACLHW, 0xfc0007ff, 0x1000035c, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhw RT,RA,RB) 5088 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5089 {NMACLHW_, 0xfc0007ff, 0x1000035d, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhw. RT,RA,RB) 5090 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5091 {NMACLHWO, 0xfc0007ff, 0x1000075c, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhwo RT,RA,RB) 5092 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5093 {NMACLHWO_, 0xfc0007ff, 0x1000075d, 0x0, // Negative Multiply Accumulate Low Halfword to Word Modulo Signed XO-form (nmaclhwo. RT,RA,RB) 5094 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5095 {NMACLHWS, 0xfc0007ff, 0x100003dc, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhws RT,RA,RB) 5096 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5097 {NMACLHWS_, 0xfc0007ff, 0x100003dd, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhws. RT,RA,RB) 5098 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5099 {NMACLHWSO, 0xfc0007ff, 0x100007dc, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhwso RT,RA,RB) 5100 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5101 {NMACLHWSO_, 0xfc0007ff, 0x100007dd, 0x0, // Negative Multiply Accumulate Low Halfword to Word Saturate Signed XO-form (nmaclhwso. RT,RA,RB) 5102 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5103 {ICBI, 0xfc0007fe, 0x7c0007ac, 0x3e00001, // Instruction Cache Block Invalidate X-form (icbi RA,RB) 5104 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5105 {ICBT, 0xfc0007fe, 0x7c00002c, 0x2000001, // Instruction Cache Block Touch X-form (icbt CT, RA, RB) 5106 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, 5107 {DCBA, 0xfc0007fe, 0x7c0005ec, 0x3e00001, // Data Cache Block Allocate X-form (dcba RA,RB) 5108 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5109 {DCBT, 0xfc0007fe, 0x7c00022c, 0x1, // Data Cache Block Touch X-form (dcbt RA,RB,TH) 5110 [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}}, 5111 {DCBT, 0xfc0007fe, 0x7c00022c, 0x1, // Data Cache Block Touch X-form (dcbt TH,RA,RB) 5112 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5113 {DCBTST, 0xfc0007fe, 0x7c0001ec, 0x1, // Data Cache Block Touch for Store X-form (dcbtst RA,RB,TH) 5114 [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_6_10}}, 5115 {DCBTST, 0xfc0007fe, 0x7c0001ec, 0x1, // Data Cache Block Touch for Store X-form (dcbtst TH,RA,RB) 5116 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5117 {DCBZ, 0xfc0007fe, 0x7c0007ec, 0x3e00001, // Data Cache Block set to Zero X-form (dcbz RA,RB) 5118 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5119 {DCBST, 0xfc0007fe, 0x7c00006c, 0x3e00001, // Data Cache Block Store X-form (dcbst RA,RB) 5120 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5121 {DCBF, 0xfc0007fe, 0x7c0000ac, 0x3800001, // Data Cache Block Flush X-form (dcbf RA,RB,L) 5122 [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_9_10}}, 5123 {ISYNC, 0xfc0007fe, 0x4c00012c, 0x3fff801, // Instruction Synchronize XL-form (isync) 5124 [5]*argField{}}, 5125 {LBARX, 0xfc0007ff, 0x7c000068, 0x0, // Load Byte And Reserve Indexed X-form [Category: Phased-In] (lbarx RT,RA,RB) 5126 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5127 {LBARX, 0xfc0007fe, 0x7c000068, 0x0, // Load Byte And Reserve Indexed X-form [Category: Phased-In] (lbarx RT,RA,RB,EH) 5128 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, 5129 {LHARX, 0xfc0007ff, 0x7c0000e8, 0x0, // Load Halfword And Reserve Indexed X-form [Category: Phased-In] (lharx RT,RA,RB) 5130 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5131 {LHARX, 0xfc0007fe, 0x7c0000e8, 0x0, // Load Halfword And Reserve Indexed X-form [Category: Phased-In] (lharx RT,RA,RB,EH) 5132 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, 5133 {LWARX, 0xfc0007ff, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB) 5134 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5135 {LWARX, 0xfc0007ff, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB) 5136 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5137 {LWARX, 0xfc0007fe, 0x7c000028, 0x0, // Load Word And Reserve Indexed X-form (lwarx RT,RA,RB,EH) 5138 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, 5139 {STBCX_, 0xfc0007ff, 0x7c00056d, 0x0, // Store Byte Conditional Indexed X-form [Category: Phased-In] (stbcx. RS,RA,RB) 5140 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5141 {STHCX_, 0xfc0007ff, 0x7c0005ad, 0x0, // Store Halfword Conditional Indexed X-form [Category: Phased-In] (sthcx. RS,RA,RB) 5142 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5143 {STWCX_, 0xfc0007ff, 0x7c00012d, 0x0, // Store Word Conditional Indexed X-form (stwcx. RS,RA,RB) 5144 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5145 {LDARX, 0xfc0007ff, 0x7c0000a8, 0x0, // Load Doubleword And Reserve Indexed X-form (ldarx RT,RA,RB) 5146 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5147 {LDARX, 0xfc0007fe, 0x7c0000a8, 0x0, // Load Doubleword And Reserve Indexed X-form (ldarx RT,RA,RB,EH) 5148 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, 5149 {STDCX_, 0xfc0007ff, 0x7c0001ad, 0x0, // Store Doubleword Conditional Indexed X-form (stdcx. RS,RA,RB) 5150 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5151 {LQARX, 0xfc0007ff, 0x7c000228, 0x0, // Load Quadword And Reserve Indexed X-form (lqarx RTp,RA,RB) 5152 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5153 {LQARX, 0xfc0007fe, 0x7c000228, 0x0, // Load Quadword And Reserve Indexed X-form (lqarx RTp,RA,RB,EH) 5154 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_31_31}}, 5155 {STQCX_, 0xfc0007ff, 0x7c00016d, 0x0, // Store Quadword Conditional Indexed X-form (stqcx. RSp,RA,RB) 5156 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5157 {SYNC, 0xfc0007fe, 0x7c0004ac, 0x390f801, // Synchronize X-form (sync L, E) 5158 [5]*argField{ap_ImmUnsigned_9_10, ap_ImmUnsigned_12_15}}, 5159 {EIEIO, 0xfc0007fe, 0x7c0006ac, 0x3fff801, // Enforce In-order Execution of I/O X-form (eieio) 5160 [5]*argField{}}, 5161 {MBAR, 0xfc0007fe, 0x7c0006ac, 0x1ff801, // Memory Barrier X-form (mbar MO) 5162 [5]*argField{ap_ImmUnsigned_6_10}}, 5163 {WAIT, 0xfc0007fe, 0x7c00007c, 0x39ff801, // Wait X-form (wait WC) 5164 [5]*argField{ap_ImmUnsigned_9_10}}, 5165 {TBEGIN_, 0xfc0007ff, 0x7c00051d, 0x1dff800, // Transaction Begin X-form (tbegin. R) 5166 [5]*argField{ap_ImmUnsigned_10_10}}, 5167 {TEND_, 0xfc0007ff, 0x7c00055d, 0x1fff800, // Transaction End X-form (tend. A) 5168 [5]*argField{ap_ImmUnsigned_6_6}}, 5169 {TABORT_, 0xfc0007ff, 0x7c00071d, 0x3e0f800, // Transaction Abort X-form (tabort. RA) 5170 [5]*argField{ap_Reg_11_15}}, 5171 {TABORTWC_, 0xfc0007ff, 0x7c00061d, 0x0, // Transaction Abort Word Conditional X-form (tabortwc. TO,RA,RB) 5172 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5173 {TABORTWCI_, 0xfc0007ff, 0x7c00069d, 0x0, // Transaction Abort Word Conditional Immediate X-form (tabortwci. TO,RA,SI) 5174 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_20}}, 5175 {TABORTDC_, 0xfc0007ff, 0x7c00065d, 0x0, // Transaction Abort Doubleword Conditional X-form (tabortdc. TO,RA,RB) 5176 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5177 {TABORTDCI_, 0xfc0007ff, 0x7c0006dd, 0x0, // Transaction Abort Doubleword Conditional Immediate X-form (tabortdci. TO,RA, SI) 5178 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_ImmSigned_16_20}}, 5179 {TSR_, 0xfc0007ff, 0x7c0005dd, 0x3dff800, // Transaction Suspend or Resume X-form (tsr. L) 5180 [5]*argField{ap_ImmUnsigned_10_10}}, 5181 {TCHECK, 0xfc0007fe, 0x7c00059c, 0x7ff801, // Transaction Check X-form (tcheck BF) 5182 [5]*argField{ap_CondRegField_6_8}}, 5183 {MFTB, 0xfc0007fe, 0x7c0002e6, 0x1, // Move From Time Base XFX-form (mftb RT,TBR) 5184 [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, 5185 {RFEBB, 0xfc0007fe, 0x4c000124, 0x3fff001, // Return from Event-Based Branch XL-form (rfebb S) 5186 [5]*argField{ap_ImmUnsigned_20_20}}, 5187 {LBDX, 0xfc0007fe, 0x7c000406, 0x1, // Load Byte with Decoration Indexed X-form (lbdx RT,RA,RB) 5188 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5189 {LHDX, 0xfc0007fe, 0x7c000446, 0x1, // Load Halfword with Decoration Indexed X-form (lhdx RT,RA,RB) 5190 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5191 {LWDX, 0xfc0007fe, 0x7c000486, 0x1, // Load Word with Decoration Indexed X-form (lwdx RT,RA,RB) 5192 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5193 {LDDX, 0xfc0007fe, 0x7c0004c6, 0x1, // Load Doubleword with Decoration Indexed X-form (lddx RT,RA,RB) 5194 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5195 {LFDDX, 0xfc0007fe, 0x7c000646, 0x1, // Load Floating Doubleword with Decoration Indexed X-form (lfddx FRT,RA,RB) 5196 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5197 {STBDX, 0xfc0007fe, 0x7c000506, 0x1, // Store Byte with Decoration Indexed X-form (stbdx RS,RA,RB) 5198 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5199 {STHDX, 0xfc0007fe, 0x7c000546, 0x1, // Store Halfword with Decoration Indexed X-form (sthdx RS,RA,RB) 5200 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5201 {STWDX, 0xfc0007fe, 0x7c000586, 0x1, // Store Word with Decoration Indexed X-form (stwdx RS,RA,RB) 5202 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5203 {STDDX, 0xfc0007fe, 0x7c0005c6, 0x1, // Store Doubleword with Decoration Indexed X-form (stddx RS,RA,RB) 5204 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5205 {STFDDX, 0xfc0007fe, 0x7c000746, 0x1, // Store Floating Doubleword with Decoration Indexed X-form (stfddx FRS,RA,RB) 5206 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5207 {DSN, 0xfc0007fe, 0x7c0003c6, 0x3e00001, // Decorated Storage Notify X-form (dsn RA,RB) 5208 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5209 {ECIWX, 0xfc0007fe, 0x7c00026c, 0x1, // External Control In Word Indexed X-form (eciwx RT,RA,RB) 5210 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5211 {ECOWX, 0xfc0007fe, 0x7c00036c, 0x1, // External Control Out Word Indexed X-form (ecowx RS,RA,RB) 5212 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5213 {SC, 0xfc000002, 0x44000002, 0x3fff01d, // System Call SC-form (sc LEV) 5214 [5]*argField{ap_ImmUnsigned_20_26}}, 5215 {RFID, 0xfc0007fe, 0x4c000024, 0x3fff801, // Return From Interrupt Doubleword XL-form (rfid) 5216 [5]*argField{}}, 5217 {HRFID, 0xfc0007fe, 0x4c000224, 0x3fff801, // Hypervisor Return From Interrupt Doubleword XL-form (hrfid) 5218 [5]*argField{}}, 5219 {DOZE, 0xfc0007fe, 0x4c000324, 0x3fff801, // Doze XL-form (doze) 5220 [5]*argField{}}, 5221 {NAP, 0xfc0007fe, 0x4c000364, 0x3fff801, // Nap XL-form (nap) 5222 [5]*argField{}}, 5223 {SLEEP, 0xfc0007fe, 0x4c0003a4, 0x3fff801, // Sleep XL-form (sleep) 5224 [5]*argField{}}, 5225 {RVWINKLE, 0xfc0007fe, 0x4c0003e4, 0x3fff801, // Rip Van Winkle XL-form (rvwinkle) 5226 [5]*argField{}}, 5227 {LBZCIX, 0xfc0007fe, 0x7c0006aa, 0x1, // Load Byte and Zero Caching Inhibited Indexed X-form (lbzcix RT,RA,RB) 5228 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5229 {LWZCIX, 0xfc0007fe, 0x7c00062a, 0x1, // Load Word and Zero Caching Inhibited Indexed X-form (lwzcix RT,RA,RB) 5230 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5231 {LHZCIX, 0xfc0007fe, 0x7c00066a, 0x1, // Load Halfword and Zero Caching Inhibited Indexed X-form (lhzcix RT,RA,RB) 5232 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5233 {LDCIX, 0xfc0007fe, 0x7c0006ea, 0x1, // Load Doubleword Caching Inhibited Indexed X-form (ldcix RT,RA,RB) 5234 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5235 {STBCIX, 0xfc0007fe, 0x7c0007aa, 0x1, // Store Byte Caching Inhibited Indexed X-form (stbcix RS,RA,RB) 5236 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5237 {STWCIX, 0xfc0007fe, 0x7c00072a, 0x1, // Store Word Caching Inhibited Indexed X-form (stwcix RS,RA,RB) 5238 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5239 {STHCIX, 0xfc0007fe, 0x7c00076a, 0x1, // Store Halfword Caching Inhibited Indexed X-form (sthcix RS,RA,RB) 5240 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5241 {STDCIX, 0xfc0007fe, 0x7c0007ea, 0x1, // Store Doubleword Caching Inhibited Indexed X-form (stdcix RS,RA,RB) 5242 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5243 {TRECLAIM_, 0xfc0007ff, 0x7c00075d, 0x3e0f800, // Transaction Reclaim X-form (treclaim. RA) 5244 [5]*argField{ap_Reg_11_15}}, 5245 {TRECHKPT_, 0xfc0007ff, 0x7c0007dd, 0x3fff800, // Transaction Recheckpoint X-form (trechkpt.) 5246 [5]*argField{}}, 5247 {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS) 5248 [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, 5249 {MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR) 5250 [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, 5251 {MTMSR, 0xfc0007fe, 0x7c000124, 0x1ef801, // Move To Machine State Register X-form (mtmsr RS,L) 5252 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}}, 5253 {MTMSRD, 0xfc0007fe, 0x7c000164, 0x1ef801, // Move To Machine State Register Doubleword X-form (mtmsrd RS,L) 5254 [5]*argField{ap_Reg_6_10, ap_ImmUnsigned_15_15}}, 5255 {MFMSR, 0xfc0007fe, 0x7c0000a6, 0x1ff801, // Move From Machine State Register X-form (mfmsr RT) 5256 [5]*argField{ap_Reg_6_10}}, 5257 {SLBIE, 0xfc0007fe, 0x7c000364, 0x3ff0001, // SLB Invalidate Entry X-form (slbie RB) 5258 [5]*argField{ap_Reg_16_20}}, 5259 {SLBIA, 0xfc0007fe, 0x7c0003e4, 0x31ff801, // SLB Invalidate All X-form (slbia IH) 5260 [5]*argField{ap_ImmUnsigned_8_10}}, 5261 {SLBMTE, 0xfc0007fe, 0x7c000324, 0x1f0001, // SLB Move To Entry X-form (slbmte RS,RB) 5262 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 5263 {SLBMFEV, 0xfc0007fe, 0x7c0006a6, 0x1f0001, // SLB Move From Entry VSID X-form (slbmfev RT,RB) 5264 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 5265 {SLBMFEE, 0xfc0007fe, 0x7c000726, 0x1f0001, // SLB Move From Entry ESID X-form (slbmfee RT,RB) 5266 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 5267 {SLBFEE_, 0xfc0007ff, 0x7c0007a7, 0x1f0000, // SLB Find Entry ESID X-form (slbfee. RT,RB) 5268 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 5269 {MTSR, 0xfc0007fe, 0x7c0001a4, 0x10f801, // Move To Segment Register X-form (mtsr SR,RS) 5270 [5]*argField{ap_SpReg_12_15, ap_Reg_6_10}}, 5271 {MTSRIN, 0xfc0007fe, 0x7c0001e4, 0x1f0001, // Move To Segment Register Indirect X-form (mtsrin RS,RB) 5272 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 5273 {MFSR, 0xfc0007fe, 0x7c0004a6, 0x10f801, // Move From Segment Register X-form (mfsr RT,SR) 5274 [5]*argField{ap_Reg_6_10, ap_SpReg_12_15}}, 5275 {MFSRIN, 0xfc0007fe, 0x7c000526, 0x1f0001, // Move From Segment Register Indirect X-form (mfsrin RT,RB) 5276 [5]*argField{ap_Reg_6_10, ap_Reg_16_20}}, 5277 {TLBIE, 0xfc0007fe, 0x7c000264, 0x1f0001, // TLB Invalidate Entry X-form (tlbie RB,RS) 5278 [5]*argField{ap_Reg_16_20, ap_Reg_6_10}}, 5279 {TLBIEL, 0xfc0007fe, 0x7c000224, 0x3ff0001, // TLB Invalidate Entry Local X-form (tlbiel RB) 5280 [5]*argField{ap_Reg_16_20}}, 5281 {TLBIA, 0xfc0007fe, 0x7c0002e4, 0x3fff801, // TLB Invalidate All X-form (tlbia) 5282 [5]*argField{}}, 5283 {TLBSYNC, 0xfc0007fe, 0x7c00046c, 0x3fff801, // TLB Synchronize X-form (tlbsync) 5284 [5]*argField{}}, 5285 {MSGSND, 0xfc0007fe, 0x7c00019c, 0x3ff0001, // Message Send X-form (msgsnd RB) 5286 [5]*argField{ap_Reg_16_20}}, 5287 {MSGCLR, 0xfc0007fe, 0x7c0001dc, 0x3ff0001, // Message Clear X-form (msgclr RB) 5288 [5]*argField{ap_Reg_16_20}}, 5289 {MSGSNDP, 0xfc0007fe, 0x7c00011c, 0x3ff0001, // Message Send Privileged X-form (msgsndp RB) 5290 [5]*argField{ap_Reg_16_20}}, 5291 {MSGCLRP, 0xfc0007fe, 0x7c00015c, 0x3ff0001, // Message Clear Privileged X-form (msgclrp RB) 5292 [5]*argField{ap_Reg_16_20}}, 5293 {MTTMR, 0xfc0007fe, 0x7c0003dc, 0x1, // Move To Thread Management Register XFX-form (mttmr TMR,RS) 5294 [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, 5295 {SC, 0xfc000002, 0x44000002, 0x3fffffd, // System Call SC-form (sc) 5296 [5]*argField{}}, 5297 {RFI, 0xfc0007fe, 0x4c000064, 0x3fff801, // Return From Interrupt XL-form (rfi) 5298 [5]*argField{}}, 5299 {RFCI, 0xfc0007fe, 0x4c000066, 0x3fff801, // Return From Critical Interrupt XL-form (rfci) 5300 [5]*argField{}}, 5301 {RFDI, 0xfc0007fe, 0x4c00004e, 0x3fff801, // Return From Debug Interrupt X-form (rfdi) 5302 [5]*argField{}}, 5303 {RFMCI, 0xfc0007fe, 0x4c00004c, 0x3fff801, // Return From Machine Check Interrupt XL-form (rfmci) 5304 [5]*argField{}}, 5305 {RFGI, 0xfc0007fe, 0x4c0000cc, 0x3fff801, // Return From Guest Interrupt XL-form (rfgi) 5306 [5]*argField{}}, 5307 {EHPRIV, 0xfc0007fe, 0x7c00021c, 0x1, // Embedded Hypervisor Privilege XL-form (ehpriv OC) 5308 [5]*argField{ap_ImmUnsigned_6_20}}, 5309 {MTSPR, 0xfc0007fe, 0x7c0003a6, 0x1, // Move To Special Purpose Register XFX-form (mtspr SPR,RS) 5310 [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, 5311 {MFSPR, 0xfc0007fe, 0x7c0002a6, 0x1, // Move From Special Purpose Register XFX-form (mfspr RT,SPR) 5312 [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, 5313 {MTDCR, 0xfc0007fe, 0x7c000386, 0x1, // Move To Device Control Register XFX-form (mtdcr DCRN,RS) 5314 [5]*argField{ap_SpReg_16_20_11_15, ap_Reg_6_10}}, 5315 {MTDCRX, 0xfc0007fe, 0x7c000306, 0xf801, // Move To Device Control Register Indexed X-form (mtdcrx RA,RS) 5316 [5]*argField{ap_Reg_11_15, ap_Reg_6_10}}, 5317 {MFDCR, 0xfc0007fe, 0x7c000286, 0x1, // Move From Device Control Register XFX-form (mfdcr RT,DCRN) 5318 [5]*argField{ap_Reg_6_10, ap_SpReg_16_20_11_15}}, 5319 {MFDCRX, 0xfc0007fe, 0x7c000206, 0xf801, // Move From Device Control Register Indexed X-form (mfdcrx RT,RA) 5320 [5]*argField{ap_Reg_6_10, ap_Reg_11_15}}, 5321 {MTMSR, 0xfc0007fe, 0x7c000124, 0x1ff801, // Move To Machine State Register X-form (mtmsr RS) 5322 [5]*argField{ap_Reg_6_10}}, 5323 {MFMSR, 0xfc0007fe, 0x7c0000a6, 0x1ff801, // Move From Machine State Register X-form (mfmsr RT) 5324 [5]*argField{ap_Reg_6_10}}, 5325 {WRTEE, 0xfc0007fe, 0x7c000106, 0x1ff801, // Write MSR External Enable X-form (wrtee RS) 5326 [5]*argField{ap_Reg_6_10}}, 5327 {WRTEEI, 0xfc0007fe, 0x7c000146, 0x3ff7801, // Write MSR External Enable Immediate X-form (wrteei E) 5328 [5]*argField{ap_ImmUnsigned_16_16}}, 5329 {LBEPX, 0xfc0007fe, 0x7c0000be, 0x1, // Load Byte by External Process ID Indexed X-form (lbepx RT,RA,RB) 5330 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5331 {LHEPX, 0xfc0007fe, 0x7c00023e, 0x1, // Load Halfword by External Process ID Indexed X-form (lhepx RT,RA,RB) 5332 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5333 {LWEPX, 0xfc0007fe, 0x7c00003e, 0x1, // Load Word by External Process ID Indexed X-form (lwepx RT,RA,RB) 5334 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5335 {LDEPX, 0xfc0007fe, 0x7c00003a, 0x1, // Load Doubleword by External Process ID Indexed X-form (ldepx RT,RA,RB) 5336 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5337 {STBEPX, 0xfc0007fe, 0x7c0001be, 0x1, // Store Byte by External Process ID Indexed X-form (stbepx RS,RA,RB) 5338 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5339 {STHEPX, 0xfc0007fe, 0x7c00033e, 0x1, // Store Halfword by External Process ID Indexed X-form (sthepx RS,RA,RB) 5340 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5341 {STWEPX, 0xfc0007fe, 0x7c00013e, 0x1, // Store Word by External Process ID Indexed X-form (stwepx RS,RA,RB) 5342 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5343 {STDEPX, 0xfc0007fe, 0x7c00013a, 0x1, // Store Doubleword by External Process ID Indexed X-form (stdepx RS,RA,RB) 5344 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5345 {DCBSTEP, 0xfc0007fe, 0x7c00007e, 0x3e00001, // Data Cache Block Store by External PID X-form (dcbstep RA,RB) 5346 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5347 {DCBTEP, 0xfc0007fe, 0x7c00027e, 0x1, // Data Cache Block Touch by External PID X-form (dcbtep TH,RA,RB) 5348 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5349 {DCBFEP, 0xfc0007fe, 0x7c0000fe, 0x3800001, // Data Cache Block Flush by External PID X-form (dcbfep RA,RB,L) 5350 [5]*argField{ap_Reg_11_15, ap_Reg_16_20, ap_ImmUnsigned_9_10}}, 5351 {DCBTSTEP, 0xfc0007fe, 0x7c0001fe, 0x1, // Data Cache Block Touch for Store by External PID X-form (dcbtstep TH,RA,RB) 5352 [5]*argField{ap_ImmUnsigned_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5353 {ICBIEP, 0xfc0007fe, 0x7c0007be, 0x3e00001, // Instruction Cache Block Invalidate by External PID X-form (icbiep RA,RB) 5354 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5355 {DCBZEP, 0xfc0007fe, 0x7c0007fe, 0x3e00001, // Data Cache Block set to Zero by External PID X-form (dcbzep RA,RB) 5356 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5357 {LFDEPX, 0xfc0007fe, 0x7c0004be, 0x1, // Load Floating-Point Double by External Process ID Indexed X-form (lfdepx FRT,RA,RB) 5358 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5359 {STFDEPX, 0xfc0007fe, 0x7c0005be, 0x1, // Store Floating-Point Double by External Process ID Indexed X-form (stfdepx FRS,RA,RB) 5360 [5]*argField{ap_FPReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5361 {EVLDDEPX, 0xfc0007fe, 0x7c00063e, 0x1, // Vector Load Doubleword into Doubleword by External Process ID Indexed EVX-form (evlddepx RT,RA,RB) 5362 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5363 {EVSTDDEPX, 0xfc0007fe, 0x7c00073e, 0x1, // Vector Store Doubleword into Doubleword by External Process ID Indexed EVX-form (evstddepx RT,RA,RB) 5364 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5365 {LVEPX, 0xfc0007fe, 0x7c00024e, 0x1, // Load Vector by External Process ID Indexed X-form (lvepx VRT,RA,RB) 5366 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5367 {LVEPXL, 0xfc0007fe, 0x7c00020e, 0x1, // Load Vector by External Process ID Indexed LRU X-form (lvepxl VRT,RA,RB) 5368 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5369 {STVEPX, 0xfc0007fe, 0x7c00064e, 0x1, // Store Vector by External Process ID Indexed X-form (stvepx VRS,RA,RB) 5370 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5371 {STVEPXL, 0xfc0007fe, 0x7c00060e, 0x1, // Store Vector by External Process ID Indexed LRU X-form (stvepxl VRS,RA,RB) 5372 [5]*argField{ap_VecReg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5373 {DCBI, 0xfc0007fe, 0x7c0003ac, 0x3e00001, // Data Cache Block Invalidate X-form (dcbi RA,RB) 5374 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5375 {DCBLQ_, 0xfc0007ff, 0x7c00034d, 0x2000000, // Data Cache Block Lock Query X-form (dcblq. CT,RA,RB) 5376 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, 5377 {ICBLQ_, 0xfc0007ff, 0x7c00018d, 0x2000000, // Instruction Cache Block Lock Query X-form (icblq. CT,RA,RB) 5378 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, 5379 {DCBTLS, 0xfc0007fe, 0x7c00014c, 0x2000001, // Data Cache Block Touch and Lock Set X-form (dcbtls CT,RA,RB) 5380 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, 5381 {DCBTSTLS, 0xfc0007fe, 0x7c00010c, 0x2000001, // Data Cache Block Touch for Store and Lock Set X-form (dcbtstls CT,RA,RB) 5382 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, 5383 {ICBTLS, 0xfc0007fe, 0x7c0003cc, 0x2000001, // Instruction Cache Block Touch and Lock Set X-form (icbtls CT,RA,RB) 5384 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, 5385 {ICBLC, 0xfc0007fe, 0x7c0001cc, 0x2000001, // Instruction Cache Block Lock Clear X-form (icblc CT,RA,RB) 5386 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, 5387 {DCBLC, 0xfc0007fe, 0x7c00030c, 0x2000001, // Data Cache Block Lock Clear X-form (dcblc CT,RA,RB) 5388 [5]*argField{ap_ImmUnsigned_7_10, ap_Reg_11_15, ap_Reg_16_20}}, 5389 {TLBIVAX, 0xfc0007fe, 0x7c000624, 0x3e00001, // TLB Invalidate Virtual Address Indexed X-form (tlbivax RA,RB) 5390 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5391 {TLBILX, 0xfc0007fe, 0x7c000024, 0x3800001, // TLB Invalidate Local Indexed X-form (tlbilx RA,RB]) 5392 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5393 {TLBSX, 0xfc0007fe, 0x7c000724, 0x3e00001, // TLB Search Indexed X-form (tlbsx RA,RB) 5394 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5395 {TLBSRX_, 0xfc0007ff, 0x7c0006a5, 0x3e00000, // TLB Search and Reserve Indexed X-form (tlbsrx. RA,RB) 5396 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5397 {TLBRE, 0xfc0007fe, 0x7c000764, 0x3fff801, // TLB Read Entry X-form (tlbre) 5398 [5]*argField{}}, 5399 {TLBSYNC, 0xfc0007fe, 0x7c00046c, 0x3fff801, // TLB Synchronize X-form (tlbsync) 5400 [5]*argField{}}, 5401 {TLBWE, 0xfc0007fe, 0x7c0007a4, 0x3fff801, // TLB Write Entry X-form (tlbwe) 5402 [5]*argField{}}, 5403 {DNH, 0xfc0007fe, 0x4c00018c, 0x1, // Debugger Notify Halt XFX-form (dnh DUI,DUIS) 5404 [5]*argField{ap_ImmUnsigned_6_10, ap_ImmUnsigned_11_20}}, 5405 {MSGSND, 0xfc0007fe, 0x7c00019c, 0x3ff0001, // Message Send X-form (msgsnd RB) 5406 [5]*argField{ap_Reg_16_20}}, 5407 {MSGCLR, 0xfc0007fe, 0x7c0001dc, 0x3ff0001, // Message Clear X-form (msgclr RB) 5408 [5]*argField{ap_Reg_16_20}}, 5409 {DCI, 0xfc0007fe, 0x7c00038c, 0x21ff801, // Data Cache Invalidate X-form (dci CT) 5410 [5]*argField{ap_ImmUnsigned_7_10}}, 5411 {ICI, 0xfc0007fe, 0x7c00078c, 0x21ff801, // Instruction Cache Invalidate X-form (ici CT) 5412 [5]*argField{ap_ImmUnsigned_7_10}}, 5413 {DCREAD, 0xfc0007fe, 0x7c0003cc, 0x1, // Data Cache Read X-form (dcread RT,RA,RB) 5414 [5]*argField{ap_Reg_6_10, ap_Reg_11_15, ap_Reg_16_20}}, 5415 {ICREAD, 0xfc0007fe, 0x7c0007cc, 0x3e00001, // Instruction Cache Read X-form (icread RA,RB) 5416 [5]*argField{ap_Reg_11_15, ap_Reg_16_20}}, 5417 {MFPMR, 0xfc0007fe, 0x7c00029c, 0x1, // Move From Performance Monitor Register XFX-form (mfpmr RT,PMRN) 5418 [5]*argField{ap_Reg_6_10, ap_SpReg_11_20}}, 5419 {MTPMR, 0xfc0007fe, 0x7c00039c, 0x1, // Move To Performance Monitor Register XFX-form (mtpmr PMRN,RS) 5420 [5]*argField{ap_SpReg_11_20, ap_Reg_6_10}}, 5421} 5422