1 /* vax780_defs.h: VAX 780 model-specific definitions file 2 3 Copyright (c) 2004-2011, Robert M Supnik 4 5 Permission is hereby granted, free of charge, to any person obtaining a 6 copy of this software and associated documentation files (the "Software"), 7 to deal in the Software without restriction, including without limitation 8 the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 and/or sell copies of the Software, and to permit persons to whom the 10 Software is furnished to do so, subject to the following conditions: 11 12 The above copyright notice and this permission notice shall be included in 13 all copies or substantial portions of the Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 22 Except as contained in this notice, the name of Robert M Supnik shall not be 23 used in advertising or otherwise to promote the sale, use or other dealings 24 in this Software without prior written authorization from Robert M Supnik. 25 26 05-Nov-11 RMS Added VEC_QMODE definition 27 19-Nov-08 RMS Moved I/O support routines to I/O library 28 29-Apr-07 RMS Modified model-specific reserved operand check macros 29 to reflect 780 microcode patches (found by Naoki Hamada) 30 29-Oct-06 RMS Added clock coscheduler function 31 17-May-06 RMS Added CR11/CD11 support (from John Dundas) 32 10-May-06 RMS Added model-specific reserved operand check macros 33 34 This file covers the VAX 11/780, the first VAX. 35 36 System memory map 37 38 0000 0000 - 1FFF FFFF main memory 39 40 2000 0000 - 2001 FFFF nexus register space 41 2002 0000 - 200F FFFF reserved 42 2010 0000 - 2013 FFFF Unibus address space, Unibus 0 43 2014 0000 - 2017 FFFF Unibus address space, Unibus 1 44 2018 0000 - 201B FFFF Unibus address space, Unibus 2 45 201C 0000 - 201F FFFF Unibus address space, Unibus 3 46 2020 0000 - 3FFF FFFF reserved 47 */ 48 49 #ifndef FULL_VAX 50 #define FULL_VAX 1 51 #endif 52 53 #ifndef _VAX_780_DEFS_H_ 54 #define _VAX_780_DEFS_H_ 1 55 56 /* Microcode constructs */ 57 58 #define VAX780_SID (1 << 24) /* system ID */ 59 #define VAX780_ECO (7 << 19) /* ucode revision */ 60 #define VAX780_PLANT (0 << 12) /* plant (Salem NH) */ 61 #define VAX780_SN (1234) 62 #define CON_HLTPIN 0x0200 /* external CPU halt */ 63 #define CON_HLTINS 0x0600 /* HALT instruction */ 64 #define MCHK_RD_F 0x00 /* read fault */ 65 #define MCHK_RD_A 0xF4 /* read abort */ 66 #define MCHK_IBUF 0x0D /* read istream */ 67 #define VER_FPLA 0x0C /* FPLA version */ 68 #define VER_WCSP (VER_FPLA) /* WCS primary version */ 69 #define VER_WCSS 0x12 /* WCS secondary version */ 70 #define VER_PCS ((VER_WCSS >> 4) & 0x3) /* PCS version */ 71 72 /* Interrupts */ 73 74 #define IPL_HMAX 0x17 /* highest hwre level */ 75 #define IPL_HMIN 0x14 /* lowest hwre level */ 76 #define IPL_HLVL (IPL_HMAX - IPL_HMIN + 1) /* # hardware levels */ 77 #define IPL_SMAX 0xF /* highest swre level */ 78 79 /* Nexus constants */ 80 81 #define NEXUS_NUM 16 /* number of nexus */ 82 #define MCTL_NUM 2 /* number of mem ctrl */ 83 #define MBA_NUM 2 /* number of MBA's */ 84 #define TR_MCTL0 1 /* nexus assignments */ 85 #define TR_MCTL1 2 86 #define TR_UBA 3 87 #define TR_MBA0 8 88 #define TR_MBA1 9 89 #define NEXUS_HLVL (IPL_HMAX - IPL_HMIN + 1) 90 #define SCB_NEXUS 0x100 /* nexus intr base */ 91 #define SBI_FAULTS 0xFC000000 /* SBI fault flags */ 92 93 /* Internal I/O interrupts - relative except for clock and console */ 94 95 #define IPL_CLKINT 0x18 /* clock IPL */ 96 #define IPL_TTINT 0x14 /* console IPL */ 97 98 #define IPL_MCTL0 (0x15 - IPL_HMIN) 99 #define IPL_MCTL1 (0x15 - IPL_HMIN) 100 #define IPL_UBA (0x15 - IPL_HMIN) 101 #define IPL_MBA0 (0x15 - IPL_HMIN) 102 #define IPL_MBA1 (0x15 - IPL_HMIN) 103 104 /* Nexus interrupt macros */ 105 106 #define SET_NEXUS_INT(dv) nexus_req[IPL_##dv] |= (1 << TR_##dv) 107 #define CLR_NEXUS_INT(dv) nexus_req[IPL_##dv] &= ~(1 << TR_##dv) 108 109 /* Machine specific IPRs */ 110 111 #define MT_ACCS 40 /* FPA control */ 112 #define MT_ACCR 41 /* FPA maint */ 113 #define MT_WCSA 44 /* WCS address */ 114 #define MT_WCSD 45 /* WCS data */ 115 #define MT_SBIFS 48 /* SBI fault status */ 116 #define MT_SBIS 49 /* SBI silo */ 117 #define MT_SBISC 50 /* SBI silo comparator */ 118 #define MT_SBIMT 51 /* SBI maint */ 119 #define MT_SBIER 52 /* SBI error */ 120 #define MT_SBITA 53 /* SBI timeout addr */ 121 #define MT_SBIQC 54 /* SBI timeout clear */ 122 #define MT_MBRK 60 /* microbreak */ 123 124 /* Machine specific reserved operand tests */ 125 126 /* 780 microcode patch 37 - only test LR<23:0> for appropriate length */ 127 128 #define ML_LR_TEST(r) if (((uint32)((r) & 0xFFFFFF)) > 0x200000) RSVD_OPND_FAULT 129 130 /* 780 microcode patch 38 - only test PxBR<31>=1, PxBR<30> = 0, and xBR<1:0> = 0 */ 131 132 #define ML_PXBR_TEST(r) if (((((uint32)(r)) & 0x80000000) == 0) || \ 133 ((((uint32)(r)) & 0x40000003) != 0)) RSVD_OPND_FAULT 134 #define ML_SBR_TEST(r) if ((((uint32)(r)) & 0xC0000003) != 0) RSVD_OPND_FAULT 135 136 /* 780 microcode patch 78 - only test xCBB<1:0> = 0 */ 137 138 #define ML_PA_TEST(r) if ((((uint32)(r)) & 0x00000003) != 0) RSVD_OPND_FAULT 139 140 #define LP_AST_TEST(r) if ((r) > AST_MAX) RSVD_OPND_FAULT 141 #define LP_MBZ84_TEST(r) if ((((uint32)(r)) & 0xF8C00000) != 0) RSVD_OPND_FAULT 142 #define LP_MBZ92_TEST(r) if ((((uint32)(r)) & 0x7FC00000) != 0) RSVD_OPND_FAULT 143 144 /* Memory */ 145 146 #define MAXMEMWIDTH 23 /* max mem, MS780C */ 147 #define MAXMEMSIZE (1 << MAXMEMWIDTH) 148 #define MAXMEMWIDTH_X 27 /* max mem, MS780E */ 149 #define MAXMEMSIZE_X (1 << MAXMEMWIDTH_X) 150 #define INITMEMSIZE (1 << MAXMEMWIDTH) /* initial memory size */ 151 #define MEMSIZE (cpu_unit.capac) 152 #define ADDR_IS_MEM(x) (((uint32) (x)) < MEMSIZE) 153 154 /* Unibus I/O registers */ 155 156 #define UBADDRWIDTH 18 /* Unibus addr width */ 157 #define UBADDRSIZE (1u << UBADDRWIDTH) /* Unibus addr length */ 158 #define UBADDRMASK (UBADDRSIZE - 1) /* Unibus addr mask */ 159 #define IOPAGEAWIDTH 13 /* IO addr width */ 160 #define IOPAGESIZE (1u << IOPAGEAWIDTH) /* IO page length */ 161 #define IOPAGEMASK (IOPAGESIZE - 1) /* IO addr mask */ 162 #define UBADDRBASE 0x20100000 /* Unibus addr base */ 163 #define IOPAGEBASE 0x2013E000 /* IO page base */ 164 #define ADDR_IS_IO(x) ((((uint32) (x)) >= UBADDRBASE) && \ 165 (((uint32) (x)) < (UBADDRBASE + UBADDRSIZE))) 166 #define ADDR_IS_IOP(x) (((uint32) (x)) >= IOPAGEBASE) 167 168 /* Nexus register space */ 169 170 #define REGAWIDTH 17 /* REG addr width */ 171 #define REG_V_NEXUS 13 /* nexus number */ 172 #define REG_M_NEXUS 0xF 173 #define REG_V_OFS 2 /* register number */ 174 #define REG_M_OFS 0x7FF 175 #define REGSIZE (1u << REGAWIDTH) /* REG length */ 176 #define REGBASE 0x20000000 /* REG addr base */ 177 #define ADDR_IS_REG(x) ((((uint32) (x)) >= REGBASE) && \ 178 (((uint32) (x)) < (REGBASE + REGSIZE))) 179 #define NEXUS_GETNEX(x) (((x) >> REG_V_NEXUS) & REG_M_NEXUS) 180 #define NEXUS_GETOFS(x) (((x) >> REG_V_OFS) & REG_M_OFS) 181 182 /* ROM address space in memory controllers */ 183 184 #define ROMAWIDTH 12 /* ROM addr width */ 185 #define ROMSIZE (1u << ROMAWIDTH) /* ROM size */ 186 #define ROM0BASE (REGBASE + (TR_MCTL0 << REG_V_NEXUS) + 0x1000) 187 #define ROM1BASE (REGBASE + (TR_MCTL1 << REG_V_NEXUS) + 0x1000) 188 #define ADDR_IS_ROM0(x) ((((uint32) (x)) >= ROM0BASE) && \ 189 (((uint32) (x)) < (ROM0BASE + ROMSIZE))) 190 #define ADDR_IS_ROM1(x) ((((uint32) (x)) >= ROM1BASE) && \ 191 (((uint32) (x)) < (ROM1BASE + ROMSIZE))) 192 #define ADDR_IS_ROM(x) (ADDR_IS_ROM0 (x) || ADDR_IS_ROM1 (x)) 193 194 /* Other address spaces */ 195 196 #define ADDR_IS_CDG(x) (0) 197 #define ADDR_IS_NVR(x) (0) 198 199 /* Unibus I/O modes */ 200 201 #define READ 0 /* PDP-11 compatibility */ 202 #define WRITE (L_WORD) 203 #define WRITEB (L_BYTE) 204 205 /* Common CSI flags */ 206 207 #define CSR_V_GO 0 /* go */ 208 #define CSR_V_IE 6 /* interrupt enable */ 209 #define CSR_V_DONE 7 /* done */ 210 #define CSR_V_BUSY 11 /* busy */ 211 #define CSR_V_ERR 15 /* error */ 212 #define CSR_GO (1u << CSR_V_GO) 213 #define CSR_IE (1u << CSR_V_IE) 214 #define CSR_DONE (1u << CSR_V_DONE) 215 #define CSR_BUSY (1u << CSR_V_BUSY) 216 #define CSR_ERR (1u << CSR_V_ERR) 217 218 /* Timers */ 219 220 #define TMR_CLK 0 /* 100Hz clock */ 221 222 /* I/O system definitions */ 223 224 #define DZ_MUXES 4 /* max # of DZV muxes */ 225 #define DZ_LINES 8 /* lines per DZV mux */ 226 #define VH_MUXES 4 /* max # of DHQ muxes */ 227 #define DLX_LINES 16 /* max # of KL11/DL11's */ 228 #define DCX_LINES 16 /* max # of DC11's */ 229 #define MT_MAXFR (1 << 16) /* magtape max rec */ 230 231 #define DEV_V_UBUS (DEV_V_UF + 0) /* Unibus */ 232 #define DEV_V_MBUS (DEV_V_UF + 1) /* Massbus */ 233 #define DEV_V_NEXUS (DEV_V_UF + 2) /* Nexus */ 234 #define DEV_V_FLTA (DEV_V_UF + 3) /* flt addr */ 235 #define DEV_V_FFUF (DEV_V_UF + 4) /* first free flag */ 236 #define DEV_UBUS (1u << DEV_V_UBUS) 237 #define DEV_MBUS (1u << DEV_V_MBUS) 238 #define DEV_NEXUS (1u << DEV_V_NEXUS) 239 #define DEV_FLTA (1u << DEV_V_FLTA) 240 #define DEV_QBUS (0) 241 #define DEV_Q18 (0) 242 243 #define UNIBUS TRUE /* Unibus only */ 244 245 #define DEV_RDX 16 /* default device radix */ 246 247 /* Device information block 248 249 For Massbus devices, 250 ba = Massbus number 251 lnt = Massbus ctrl type 252 ack[0] = abort routine 253 254 For Nexus devices, 255 ba = Nexus number 256 lnt = number of consecutive nexi */ 257 258 #define VEC_DEVMAX 4 /* max device vec */ 259 260 typedef struct { 261 uint32 ba; /* base addr */ 262 uint32 lnt; /* length */ 263 t_stat (*rd)(int32 *dat, int32 ad, int32 md); 264 t_stat (*wr)(int32 dat, int32 ad, int32 md); 265 int32 vnum; /* vectors: number */ 266 int32 vloc; /* locator */ 267 int32 vec; /* value */ 268 int32 (*ack[VEC_DEVMAX])(void); /* ack routine */ 269 } DIB; 270 271 /* Unibus I/O page layout - XUB,RQB,RQC,RQD float based on number of DZ's 272 Massbus devices (RP, TU) do not appear in the Unibus IO page */ 273 274 #define IOBA_DZ (IOPAGEBASE + 000100) /* DZ11 */ 275 #define IOLN_DZ 010 276 #define IOBA_XUB (IOPAGEBASE + 000330 + (020 * (DZ_MUXES / 2))) 277 #define IOLN_XUB 010 278 #define IOBA_RQB (IOPAGEBASE + 000334 + (020 * (DZ_MUXES / 2))) 279 #define IOLN_RQB 004 280 #define IOBA_RQC (IOPAGEBASE + IOBA_RQB + IOLN_RQB) 281 #define IOLN_RQC 004 282 #define IOBA_RQD (IOPAGEBASE + IOBA_RQC + IOLN_RQC) 283 #define IOLN_RQD 004 284 #define IOBA_RQ (IOPAGEBASE + 012150) /* UDA50 */ 285 #define IOLN_RQ 004 286 #define IOBA_TS (IOPAGEBASE + 012520) /* TS11 */ 287 #define IOLN_TS 004 288 #define IOBA_RL (IOPAGEBASE + 014400) /* RL11 */ 289 #define IOLN_RL 012 290 #define IOBA_XQ (IOPAGEBASE + 014440) /* DEQNA/DELQA */ 291 #define IOLN_XQ 020 292 #define IOBA_XQB (IOPAGEBASE + 014460) /* 2nd DEQNA/DELQA */ 293 #define IOLN_XQB 020 294 #define IOBA_TQ (IOPAGEBASE + 014500) /* TMSCP */ 295 #define IOLN_TQ 004 296 #define IOBA_XU (IOPAGEBASE + 014510) /* DEUNA/DELUA */ 297 #define IOLN_XU 010 298 #define IOBA_CR (IOPAGEBASE + 017160) /* CD/CR/CM */ 299 #define IOLN_CR 010 300 #define IOBA_RX (IOPAGEBASE + 017170) /* RX11 */ 301 #define IOLN_RX 004 302 #define IOBA_RY (IOPAGEBASE + 017170) /* RXV21 */ 303 #define IOLN_RY 004 304 #define IOBA_QDSS (IOPAGEBASE + 017400) /* QDSS */ 305 #define IOLN_QDSS 002 306 #define IOBA_HK (IOPAGEBASE + 017440) /* RK611 */ 307 #define IOLN_HK 040 308 #define IOBA_LPT (IOPAGEBASE + 017514) /* LP11 */ 309 #define IOLN_LPT 004 310 #define IOBA_PTR (IOPAGEBASE + 017550) /* PC11 reader */ 311 #define IOLN_PTR 004 312 #define IOBA_PTP (IOPAGEBASE + 017554) /* PC11 punch */ 313 #define IOLN_PTP 004 314 315 /* Interrupt assignments; within each level, priority is right to left */ 316 317 #define INT_V_DZRX 0 /* BR5 */ 318 #define INT_V_DZTX 1 319 #define INT_V_HK 2 320 #define INT_V_RL 3 321 #define INT_V_RQ 4 322 #define INT_V_TQ 5 323 #define INT_V_TS 6 324 #define INT_V_RY 7 325 #define INT_V_XU 8 326 327 #define INT_V_LPT 0 /* BR4 */ 328 #define INT_V_PTR 1 329 #define INT_V_PTP 2 330 #define INT_V_CR 3 331 332 #define INT_DZRX (1u << INT_V_DZRX) 333 #define INT_DZTX (1u << INT_V_DZTX) 334 #define INT_HK (1u << INT_V_HK) 335 #define INT_RL (1u << INT_V_RL) 336 #define INT_RQ (1u << INT_V_RQ) 337 #define INT_TQ (1u << INT_V_TQ) 338 #define INT_TS (1u << INT_V_TS) 339 #define INT_RY (1u << INT_V_RY) 340 #define INT_XU (1u << INT_V_XU) 341 #define INT_LPT (1u << INT_V_LPT) 342 #define INT_PTR (1u << INT_V_PTR) 343 #define INT_PTP (1u << INT_V_PTP) 344 #define INT_CR (1u << INT_V_CR) 345 346 #define IPL_DZRX (0x15 - IPL_HMIN) 347 #define IPL_DZTX (0x15 - IPL_HMIN) 348 #define IPL_HK (0x15 - IPL_HMIN) 349 #define IPL_RL (0x15 - IPL_HMIN) 350 #define IPL_RQ (0x15 - IPL_HMIN) 351 #define IPL_TQ (0x15 - IPL_HMIN) 352 #define IPL_TS (0x15 - IPL_HMIN) 353 #define IPL_RY (0x15 - IPL_HMIN) 354 #define IPL_XU (0x15 - IPL_HMIN) 355 #define IPL_LPT (0x14 - IPL_HMIN) 356 #define IPL_PTR (0x14 - IPL_HMIN) 357 #define IPL_PTP (0x14 - IPL_HMIN) 358 #define IPL_CR (0x14 - IPL_HMIN) 359 360 /* Device vectors */ 361 362 #define VEC_QBUS 0 363 #define VEC_Q 0000 364 #define VEC_PTR 0070 365 #define VEC_PTP 0074 366 #define VEC_XQ 0120 367 #define VEC_XU 0120 368 #define VEC_RQ 0154 369 #define VEC_RL 0160 370 #define VEC_LPT 0200 371 #define VEC_HK 0210 372 #define VEC_TS 0224 373 #define VEC_CR 0230 374 #define VEC_TQ 0260 375 #define VEC_RX 0264 376 #define VEC_RY 0264 377 #define VEC_DZRX 0300 378 #define VEC_DZTX 0304 379 380 /* Interrupt macros */ 381 382 #define IVCL(dv) ((IPL_##dv * 32) + INT_V_##dv) 383 #define NVCL(dv) ((IPL_##dv * 32) + TR_##dv) 384 #define IREQ(dv) int_req[IPL_##dv] 385 #define SET_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] | (INT_##dv) 386 #define CLR_INT(dv) int_req[IPL_##dv] = int_req[IPL_##dv] & ~(INT_##dv) 387 #define IORETURN(f,v) ((f)? (v): SCPE_OK) /* cond error return */ 388 389 /* Logging */ 390 391 #define LOG_CPU_I 0x1 /* intexc */ 392 #define LOG_CPU_R 0x2 /* REI */ 393 #define LOG_CPU_P 0x4 /* context */ 394 395 /* Massbus definitions */ 396 397 #define MBA_RP (TR_MBA0 - TR_MBA0) /* MBA for RP */ 398 #define MBA_TU (TR_MBA1 - TR_MBA0) /* MBA for TU */ 399 #define MBA_RMASK 0x1F /* max 32 reg */ 400 #define MBE_NXD 1 /* nx drive */ 401 #define MBE_NXR 2 /* nx reg */ 402 #define MBE_GOE 3 /* err on GO */ 403 404 /* Boot definitions */ 405 406 #define BOOT_MB 0 /* device codes */ 407 #define BOOT_HK 1 /* for VMB */ 408 #define BOOT_RL 2 409 #define BOOT_UDA 17 410 #define BOOT_TK 18 411 412 /* Function prototypes for virtual memory interface */ 413 414 int32 Read (uint32 va, int32 lnt, int32 acc); 415 void Write (uint32 va, int32 val, int32 lnt, int32 acc); 416 417 /* Function prototypes for physical memory interface (inlined) */ 418 419 SIM_INLINE int32 ReadB (uint32 pa); 420 SIM_INLINE int32 ReadW (uint32 pa); 421 SIM_INLINE int32 ReadL (uint32 pa); 422 SIM_INLINE int32 ReadLP (uint32 pa); 423 SIM_INLINE void WriteB (uint32 pa, int32 val); 424 SIM_INLINE void WriteW (uint32 pa, int32 val); 425 SIM_INLINE void WriteL (uint32 pa, int32 val); 426 void WriteLP (uint32 pa, int32 val); 427 428 /* Function prototypes for I/O */ 429 430 int32 Map_ReadB (uint32 ba, int32 bc, uint8 *buf); 431 int32 Map_ReadW (uint32 ba, int32 bc, uint16 *buf); 432 int32 Map_WriteB (uint32 ba, int32 bc, uint8 *buf); 433 int32 Map_WriteW (uint32 ba, int32 bc, uint16 *buf); 434 435 int32 mba_rdbufW (uint32 mbus, int32 bc, uint16 *buf); 436 int32 mba_wrbufW (uint32 mbus, int32 bc, uint16 *buf); 437 int32 mba_chbufW (uint32 mbus, int32 bc, uint16 *buf); 438 int32 mba_get_bc (uint32 mbus); 439 void mba_upd_ata (uint32 mbus, uint32 val); 440 void mba_set_exc (uint32 mbus); 441 void mba_set_don (uint32 mbus); 442 void mba_set_enbdis (uint32 mbus, t_bool dis); 443 t_stat mba_show_num (FILE *st, UNIT *uptr, int32 val, void *desc); 444 445 t_stat show_nexus (FILE *st, UNIT *uptr, int32 val, void *desc); 446 447 void sbi_set_errcnf (void); 448 int32 clk_cosched (int32 wait); 449 450 #include "pdp11_io_lib.h" 451 452 #endif 453