1 /** 2 * Freeverb3 definition 3 * 4 * Copyright (C) 2006-2018 Teru Kamogashira 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. 19 */ 20 21 #ifndef _FV3_DEFS_H 22 #define _FV3_DEFS_H 23 24 #include <cmath> 25 26 #include "fv3_config.h" 27 28 #ifndef isfinite 29 #define isfinite(v) std::isfinite(v) 30 #endif 31 #ifndef isnormal 32 #define isnormal(v) std::isnormal(v) 33 #endif 34 #ifndef fpclassify 35 #define fpclassify(v) std::fpclassify(v) 36 #endif 37 #define STRINGIZEx(x) #x 38 #define STRINGIZE(x) STRINGIZEx(x) 39 40 #ifdef DISABLE_UNDENORMAL 41 #define UNDENORMAL(v) 42 #else 43 #define UNDENORMAL(v) if(fpclassify(v) != FP_NORMAL&&fpclassify(v) != FP_ZERO){v=0;} 44 #endif 45 46 #ifndef LIMIT_PLUSMINUS_ONE 47 #define LIMIT_PLUSMINUS_ONE(v) if(v < -1.){ v = -1.; } if(v > 1.){ v = 1.; } 48 #endif 49 50 #ifndef M_PI 51 #define M_PI 3.1415926535897932384626433832795028841971693993751 52 #endif 53 #ifndef M_LN2 54 #define M_LN2 0.69314718055994530941723212145817656807550013436 55 #endif 56 #ifndef LN_2_2 57 #define LN_2_2 0.34657359027997265470861606072908828403775006718 58 #endif 59 60 #define FV3_X86SIMD_NULL 0x00000000 61 #define FV3_X86SIMD_CPUID_FPU 0x00000001 // edx/eax=1 62 #define FV3_X86SIMD_CPUID_MMX 0x00800000 // edx/eax=1 63 #define FV3_X86SIMD_CPUID_SSE 0x02000000 // edx/eax=1 64 #define FV3_X86SIMD_CPUID_SSE2 0x04000000 // edx/eax=1 65 #define FV3_X86SIMD_CPUID_SSE3 0x00000001 // ecx/eax=1 66 #define FV3_X86SIMD_CPUID_SSE4_1 0x00080000 // ecx/eax=1 67 #define FV3_X86SIMD_CPUID_SSE4_2 0x00100000 // ecx/eax=1 68 #define FV3_X86SIMD_CPUID_XSAVE 0x04000000 // ecx/eax=1 69 #define FV3_X86SIMD_CPUID_OSXSAVE 0x08000000 // ecx/eax=1 70 #define FV3_X86SIMD_CPUID_AVX 0x10000000 // ecx/eax=1 71 #define FV3_X86SIMD_CPUID_FMA3 0x00001000 // ecx/eax=1 72 73 #define FV3_X86SIMD_CPUID_3DNOW 0x80000000 // edx/eax=0x80000001 74 #define FV3_X86SIMD_CPUID_3DNOWEXT 0x40000000 // edx/eax=0x80000001 75 #define FV3_X86SIMD_CPUID_3DNOW_PREF 0x00000100 // ecx/eax=0x80000001 76 #define FV3_X86SIMD_CPUID_XOP 0x00000800 // ecx/eax=0x80000001 77 #define FV3_X86SIMD_CPUID_FMA4 0x00010000 // ecx/eax=0x80000001 78 79 // SIMD code select, size div (X:depreciated F:float D:double L:long double) 80 #define FV3_X86SIMD_FLAG_NULL 0x00000000 81 #define FV3_X86SIMD_FLAG_FPU 0x00000001 // - FDL 82 #define FV3_X86SIMD_FLAG_SSE_V1 0x00000002 // 4 F To use SSE version 1 code, use with FV3_X86SIMD_FLAG_SSE (see sample) 83 #define FV3_X86SIMD_FLAG_SSE 0x00000004 // 4 F 84 #define FV3_X86SIMD_FLAG_SSE2 0x00000008 // /2 D 85 #define FV3_X86SIMD_FLAG_SSE3 0x00000010 // 4 F 86 #define FV3_X86SIMD_FLAG_SSE4_1 0x00000020 // /2 D 87 #define FV3_X86SIMD_FLAG_AVX 0x00000040 // 16/8 FD 88 #define FV3_X86SIMD_FLAG_FMA3 0x00000080 // 16/8 FD Not AVX2 89 #define FV3_X86SIMD_FLAG_3DNOWP 0x00000100 // 2 XF AMD 3DNow! with prefetch, depreciated: Bulldozer/Bobcat~ no-support 90 #define FV3_X86SIMD_FLAG_FMA4 0x00000200 // 16/8 XFD AMD, depreciated: Ryzen~ no-support 91 92 #define FV3_X86SIMD_MXCSR_FZ 0x00008000 // Flush To Zero 93 #define FV3_X86SIMD_MXCSR_DAZ 0x00000040 // Denormals Are Zero 94 #define FV3_X86SIMD_MXCSR_EMASK_ALL 0x00001F80 // All Exceptions Masks 95 96 // for maximum support 97 // AVX FMA3 FMA4 98 #define FV3_PTR_ALIGN_BYTE 32 99 // SSE SSE2 SSE3 SSE4 100 // #define FV3_PTR_ALIGN_BYTE 16 101 // FPU 102 // #define FV3_PTR_ALIGN_BYTE 8 103 104 #define FV3_IR_DEFAULT (0U) 105 #define FV3_IR_MUTE_DRY (1U << 1) 106 #define FV3_IR_MUTE_WET (1U << 2) 107 #define FV3_IR_SKIP_FILTER (1U << 3) 108 #define FV3_IR_MONO2STEREO (1U << 4) 109 #define FV3_IR_SKIP_INIT (1U << 5) 110 #define FV3_IR_SWAP_LR (1U << 6) 111 112 /* SIMD size */ 113 #define FV3_IR_Min_FragmentSize 16 114 #define FV3_IR2_DFragmentSize 16384 115 #define FV3_IR3_DFragmentSize 1024 116 #define FV3_IR3_DefaultFactor 16 117 118 #define FV3_3BS_IR2_DFragmentSize 1024 119 #define FV3_3BS_IR3_DFragmentSize 256 120 #define FV3_3BS_IR3_DefaultFactor 4 121 122 #define FV3_LFO_RCOUNT 10000 123 124 #define FV3_EARLYREF_PRESET_DEFAULT 0 125 #define FV3_EARLYREF_PRESET_0 0 126 #define FV3_EARLYREF_PRESET_1 1 127 #define FV3_EARLYREF_PRESET_2 2 128 129 #define FV3_EARLYREF_PRESET_11 11 130 #define FV3_EARLYREF_PRESET_12 12 131 #define FV3_EARLYREF_PRESET_13 13 132 #define FV3_EARLYREF_PRESET_14 14 133 #define FV3_EARLYREF_PRESET_15 15 134 #define FV3_EARLYREF_PRESET_16 16 135 #define FV3_EARLYREF_PRESET_17 17 136 #define FV3_EARLYREF_PRESET_18 18 137 #define FV3_EARLYREF_PRESET_19 19 138 #define FV3_EARLYREF_PRESET_20 20 139 #define FV3_EARLYREF_PRESET_21 21 140 #define FV3_EARLYREF_PRESET_22 22 141 142 #define FV3_REVBASE_DEFAULT_FS 48000 143 #define FV3_REVTYPE_SELF 0 144 #define FV3_REVTYPE_PROG 30 145 #define FV3_REVTYPE_PROG2 31 146 #define FV3_REVTYPE_ZREV 40 147 #define FV3_REVTYPE_ZREV2 41 148 149 #define FV3_NOISEGEN_PINK_FRACTAL_1_DEFAULT_HURST_CONST 0.5 150 #define FV3_NOISEGEN_PINK_FRACTAL_1_DEFAULT_BUFSIZE 15 151 #define FV3_NOISEGEN_GAUSSIAN_WHITE_3_DEFAULT_PRECISION 32 152 153 #define FV3_MLS_INT_BIT 32 154 #define FV3_MLS_MAX_BITS 168 155 #define FV3_MLS_MAX_TAPS 6 156 #define FV3_MLS_MAX_COUNTBIT 60 157 158 #define FV3_SWP_DEFAULT 0 159 #define FV3_SWP_EXP 0 160 #define FV3_SWP_LIN 1 161 162 #ifdef __cplusplus 163 extern "C" { 164 #endif 165 enum 166 { 167 FV3_W_BLACKMAN = 1, 168 FV3_W_HANNING = 2, 169 FV3_W_HAMMING = 3, 170 FV3_W_KAISER = 4, 171 FV3_W_COSRO = 5, 172 FV3_W_SQUARE = 6, 173 }; 174 175 enum 176 { 177 FV3_3BSPLIT_IR_IR2 = 0, 178 FV3_3BSPLIT_IR_IR3 = 1, 179 }; 180 181 enum 182 { 183 FV3_SRC_SINC_BEST_QUALITY = 0, 184 FV3_SRC_SINC_MEDIUM_QUALITY = 1, 185 FV3_SRC_SINC_FASTEST = 2, 186 FV3_SRC_ZERO_ORDER_HOLD = 3, 187 FV3_SRC_LINEAR = 4, 188 FV3_SRC_SINC_SLOW_BEST_QUALITY = 10, 189 FV3_SRC_SINC_SLOW_MEDIUM_QUALITY = 11, 190 FV3_SRC_LPF_IIR_1 = 100, 191 FV3_SRC_LPF_IIR_2 = 101, 192 }; 193 #ifdef __cplusplus 194 } 195 #endif 196 #endif 197