1 /* $FreeBSD: src/sys/dev/iir/iir_pci.c,v 1.22 2010/01/08 20:40:28 trasz Exp $ */
2 /* $Id: iir_pci.c 1.2 2003/08/26 12:29:55 achim Exp $ */
3 /*-
4 * Copyright (c) 2000-03 ICP vortex GmbH
5 * Copyright (c) 2002-03 Intel Corporation
6 * Copyright (c) 2003 Adaptec Inc.
7 * All Rights Reserved
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions, and the following disclaimer,
14 * without modification, immediately at the beginning of the file.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
25 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 */
33
34 /*
35 * iir_pci.c: PCI Bus Attachment for Intel Integrated RAID Controller driver
36 *
37 * Written by: Achim Leubner <achim_leubner@adaptec.com>
38 * Fixes/Additions: Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com>
39 *
40 * TODO:
41 */
42
43 /* #include "opt_iir.h" */
44
45 #include <sys/param.h>
46 #include <sys/systm.h>
47 #include <sys/endian.h>
48 #include <sys/kernel.h>
49 #include <sys/module.h>
50 #include <sys/bus.h>
51 #include <sys/rman.h>
52
53 #include "pcidevs.h"
54 #include <bus/pci/pcireg.h>
55 #include <bus/pci/pcivar.h>
56
57 #include <bus/cam/scsi/scsi_all.h>
58
59 #include "iir.h"
60
61 /* Mapping registers for various areas */
62 #define PCI_DPMEM PCIR_BAR(0)
63
64 /* Product numbers for Fibre-Channel are greater than or equal to 0x200 */
65 #define GDT_PCI_PRODUCT_FC 0x200
66
67 /* PCI SRAM structure */
68 #define GDT_MAGIC 0x00 /* u_int32_t, controller ID from BIOS */
69 #define GDT_NEED_DEINIT 0x04 /* u_int16_t, switch between BIOS/driver */
70 #define GDT_SWITCH_SUPPORT 0x06 /* u_int8_t, see GDT_NEED_DEINIT */
71 #define GDT_OS_USED 0x10 /* u_int8_t [16], OS code per service */
72 #define GDT_FW_MAGIC 0x3c /* u_int8_t, controller ID from firmware */
73 #define GDT_SRAM_SZ 0x40
74
75 /* DPRAM PCI controllers */
76 #define GDT_DPR_IF 0x00 /* interface area */
77 #define GDT_6SR (0xff0 - GDT_SRAM_SZ)
78 #define GDT_SEMA1 0xff1 /* volatile u_int8_t, command semaphore */
79 #define GDT_IRQEN 0xff5 /* u_int8_t, board interrupts enable */
80 #define GDT_EVENT 0xff8 /* u_int8_t, release event */
81 #define GDT_IRQDEL 0xffc /* u_int8_t, acknowledge board interrupt */
82 #define GDT_DPRAM_SZ 0x1000
83
84 /* PLX register structure (new PCI controllers) */
85 #define GDT_CFG_REG 0x00 /* u_int8_t, DPRAM cfg. (2: < 1MB, 0: any) */
86 #define GDT_SEMA0_REG 0x40 /* volatile u_int8_t, command semaphore */
87 #define GDT_SEMA1_REG 0x41 /* volatile u_int8_t, status semaphore */
88 #define GDT_PLX_STATUS 0x44 /* volatile u_int16_t, command status */
89 #define GDT_PLX_SERVICE 0x46 /* u_int16_t, service */
90 #define GDT_PLX_INFO 0x48 /* u_int32_t [2], additional info */
91 #define GDT_LDOOR_REG 0x60 /* u_int8_t, PCI to local doorbell */
92 #define GDT_EDOOR_REG 0x64 /* volatile u_int8_t, local to PCI doorbell */
93 #define GDT_CONTROL0 0x68 /* u_int8_t, control0 register (unused) */
94 #define GDT_CONTROL1 0x69 /* u_int8_t, board interrupts enable */
95 #define GDT_PLX_SZ 0x80
96
97 /* DPRAM new PCI controllers */
98 #define GDT_IC 0x00 /* interface */
99 #define GDT_PCINEW_6SR (0x4000 - GDT_SRAM_SZ)
100 /* SRAM structure */
101 #define GDT_PCINEW_SZ 0x4000
102
103 /* i960 register structure (PCI MPR controllers) */
104 #define GDT_MPR_SEMA0 0x10 /* volatile u_int8_t, command semaphore */
105 #define GDT_MPR_SEMA1 0x12 /* volatile u_int8_t, status semaphore */
106 #define GDT_MPR_STATUS 0x14 /* volatile u_int16_t, command status */
107 #define GDT_MPR_SERVICE 0x16 /* u_int16_t, service */
108 #define GDT_MPR_INFO 0x18 /* u_int32_t [2], additional info */
109 #define GDT_MPR_LDOOR 0x20 /* u_int8_t, PCI to local doorbell */
110 #define GDT_MPR_EDOOR 0x2c /* volatile u_int8_t, locl to PCI doorbell */
111 #define GDT_EDOOR_EN 0x34 /* u_int8_t, board interrupts enable */
112 #define GDT_SEVERITY 0xefc /* u_int8_t, event severity */
113 #define GDT_EVT_BUF 0xf00 /* u_int8_t [256], event buffer */
114 #define GDT_I960_SZ 0x1000
115
116 /* DPRAM PCI MPR controllers */
117 #define GDT_I960R 0x00 /* 4KB i960 registers */
118 #define GDT_MPR_IC GDT_I960_SZ
119 /* i960 register area */
120 #define GDT_MPR_6SR (GDT_I960_SZ + 0x3000 - GDT_SRAM_SZ)
121 /* DPRAM struct. */
122 #define GDT_MPR_SZ (0x3000 - GDT_SRAM_SZ)
123
124 static int iir_pci_probe(device_t dev);
125 static int iir_pci_attach(device_t dev);
126
127 void gdt_pci_enable_intr(struct gdt_softc *);
128
129 void gdt_mpr_copy_cmd(struct gdt_softc *, struct gdt_ccb *);
130 u_int8_t gdt_mpr_get_status(struct gdt_softc *);
131 void gdt_mpr_intr(struct gdt_softc *, struct gdt_intr_ctx *);
132 void gdt_mpr_release_event(struct gdt_softc *);
133 void gdt_mpr_set_sema0(struct gdt_softc *);
134 int gdt_mpr_test_busy(struct gdt_softc *);
135
136 static device_method_t iir_pci_methods[] = {
137 /* Device interface */
138 DEVMETHOD(device_probe, iir_pci_probe),
139 DEVMETHOD(device_attach, iir_pci_attach),
140 DEVMETHOD_END
141 };
142
143
144 static driver_t iir_pci_driver =
145 {
146 "iir",
147 iir_pci_methods,
148 sizeof(struct gdt_softc)
149 };
150
151 static devclass_t iir_devclass;
152
153 DRIVER_MODULE(iir, pci, iir_pci_driver, iir_devclass, NULL, NULL);
154 MODULE_DEPEND(iir, pci, 1, 1, 1);
155 MODULE_DEPEND(iir, cam, 1, 1, 1);
156
157 static int
iir_pci_probe(device_t dev)158 iir_pci_probe(device_t dev)
159 {
160 if (pci_get_vendor(dev) == PCI_VENDOR_INTEL &&
161 pci_get_device(dev) == INTEL_DEVICE_ID_IIR) {
162 device_set_desc(dev, "Intel Integrated RAID Controller");
163 return (BUS_PROBE_DEFAULT);
164 }
165 if (pci_get_vendor(dev) == GDT_VENDOR_ID &&
166 ((pci_get_device(dev) >= GDT_DEVICE_ID_MIN &&
167 pci_get_device(dev) <= GDT_DEVICE_ID_MAX) ||
168 pci_get_device(dev) == GDT_DEVICE_ID_NEWRX)) {
169 device_set_desc(dev, "ICP Disk Array Controller");
170 return (BUS_PROBE_DEFAULT);
171 }
172 return (ENXIO);
173 }
174
175
176 static int
iir_pci_attach(device_t dev)177 iir_pci_attach(device_t dev)
178 {
179 struct gdt_softc *gdt;
180 struct resource *io = NULL, *irq = NULL;
181 int retries, rid, error = 0;
182 void *ih;
183 u_int8_t protocol;
184
185 /* map DPMEM */
186 rid = PCI_DPMEM;
187 io = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
188 if (io == NULL) {
189 device_printf(dev, "can't allocate register resources\n");
190 error = ENOMEM;
191 goto err;
192 }
193
194 /* get IRQ */
195 rid = 0;
196 irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
197 RF_ACTIVE | RF_SHAREABLE);
198 if (irq == NULL) {
199 device_printf(dev, "can't find IRQ value\n");
200 error = ENOMEM;
201 goto err;
202 }
203
204 gdt = device_get_softc(dev);
205 gdt->sc_init_level = 0;
206 gdt->sc_dpmemt = rman_get_bustag(io);
207 gdt->sc_dpmemh = rman_get_bushandle(io);
208 gdt->sc_dpmembase = rman_get_start(io);
209 gdt->sc_hanum = device_get_unit(dev);
210 gdt->sc_bus = pci_get_bus(dev);
211 gdt->sc_slot = pci_get_slot(dev);
212 gdt->sc_vendor = pci_get_vendor(dev);
213 gdt->sc_device = pci_get_device(dev);
214 gdt->sc_subdevice = pci_get_subdevice(dev);
215 gdt->sc_class = GDT_MPR;
216 /* no FC ctr.
217 if (gdt->sc_device >= GDT_PCI_PRODUCT_FC)
218 gdt->sc_class |= GDT_FC;
219 */
220
221 /* initialize RP controller */
222 /* check and reset interface area */
223 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC,
224 htole32(GDT_MPR_MAGIC));
225 if (bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC) !=
226 htole32(GDT_MPR_MAGIC)) {
227 kprintf("cannot access DPMEM at 0x%jx (shadowed?)\n",
228 (uintmax_t)gdt->sc_dpmembase);
229 error = ENXIO;
230 goto err;
231 }
232 bus_space_set_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_I960_SZ, htole32(0),
233 GDT_MPR_SZ >> 2);
234
235 /* Disable everything */
236 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN,
237 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
238 GDT_EDOOR_EN) | 4);
239 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
240 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
241 0);
242 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_CMD_INDEX,
243 0);
244
245 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO,
246 htole32(gdt->sc_dpmembase));
247 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
248 0xff);
249 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
250
251 DELAY(20);
252 retries = GDT_RETRIES;
253 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
254 GDT_MPR_IC + GDT_S_STATUS) != 0xff) {
255 if (--retries == 0) {
256 kprintf("DEINIT failed\n");
257 error = ENXIO;
258 goto err;
259 }
260 DELAY(1);
261 }
262
263 protocol = (uint8_t)le32toh(bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
264 GDT_MPR_IC + GDT_S_INFO));
265 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
266 0);
267 if (protocol != GDT_PROTOCOL_VERSION) {
268 kprintf("unsupported protocol %d\n", protocol);
269 error = ENXIO;
270 goto err;
271 }
272
273 /* special commnd to controller BIOS */
274 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_INFO,
275 htole32(0));
276 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
277 GDT_MPR_IC + GDT_S_INFO + sizeof (u_int32_t), htole32(0));
278 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
279 GDT_MPR_IC + GDT_S_INFO + 2 * sizeof (u_int32_t),
280 htole32(1));
281 bus_space_write_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
282 GDT_MPR_IC + GDT_S_INFO + 3 * sizeof (u_int32_t),
283 htole32(0));
284 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_CMD_INDX,
285 0xfe);
286 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
287
288 DELAY(20);
289 retries = GDT_RETRIES;
290 while (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
291 GDT_MPR_IC + GDT_S_STATUS) != 0xfe) {
292 if (--retries == 0) {
293 kprintf("initialization error\n");
294 error = ENXIO;
295 goto err;
296 }
297 DELAY(1);
298 }
299
300 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_IC + GDT_S_STATUS,
301 0);
302
303 gdt->sc_ic_all_size = GDT_MPR_SZ;
304
305 gdt->sc_copy_cmd = gdt_mpr_copy_cmd;
306 gdt->sc_get_status = gdt_mpr_get_status;
307 gdt->sc_intr = gdt_mpr_intr;
308 gdt->sc_release_event = gdt_mpr_release_event;
309 gdt->sc_set_sema0 = gdt_mpr_set_sema0;
310 gdt->sc_test_busy = gdt_mpr_test_busy;
311
312 /* Allocate a dmatag representing the capabilities of this attachment */
313 /* XXX Should be a child of the PCI bus dma tag */
314 if (bus_dma_tag_create(/*parent*/NULL, /*alignemnt*/1, /*boundary*/0,
315 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
316 /*highaddr*/BUS_SPACE_MAXADDR,
317 /*maxsize*/BUS_SPACE_MAXSIZE_32BIT,
318 /*nsegments*/GDT_MAXSG,
319 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
320 /*flags*/0, &gdt->sc_parent_dmat) != 0) {
321 error = ENXIO;
322 goto err;
323 }
324 gdt->sc_init_level++;
325
326 if (iir_init(gdt) != 0) {
327 iir_free(gdt);
328 error = ENXIO;
329 goto err;
330 }
331
332 /* Register with the XPT */
333 iir_attach(gdt);
334
335 /* associate interrupt handler */
336 error = bus_setup_intr(dev, irq, 0, iir_intr, gdt, &ih, NULL);
337 if (error) {
338 device_printf(dev, "Unable to register interrupt handler\n");
339 error = ENXIO;
340 goto err;
341 }
342
343 gdt_pci_enable_intr(gdt);
344 return (0);
345
346 err:
347 if (irq)
348 bus_release_resource( dev, SYS_RES_IRQ, 0, irq );
349 /*
350 if (io)
351 bus_release_resource( dev, SYS_RES_MEMORY, rid, io );
352 */
353 return (error);
354 }
355
356
357 /* Enable interrupts */
358 void
gdt_pci_enable_intr(struct gdt_softc * gdt)359 gdt_pci_enable_intr(struct gdt_softc *gdt)
360 {
361 GDT_DPRINTF(GDT_D_INTR, ("gdt_pci_enable_intr(%p) ", gdt));
362
363 switch(GDT_CLASS(gdt)) {
364 case GDT_MPR:
365 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
366 GDT_MPR_EDOOR, 0xff);
367 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_EDOOR_EN,
368 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
369 GDT_EDOOR_EN) & ~4);
370 break;
371 }
372 }
373
374
375 /*
376 * MPR PCI controller-specific functions
377 */
378
379 void
gdt_mpr_copy_cmd(struct gdt_softc * gdt,struct gdt_ccb * gccb)380 gdt_mpr_copy_cmd(struct gdt_softc *gdt, struct gdt_ccb *gccb)
381 {
382 u_int16_t cp_count = roundup(gccb->gc_cmd_len, sizeof (u_int32_t));
383 u_int16_t dp_offset = gdt->sc_cmd_off;
384 u_int16_t cmd_no = gdt->sc_cmd_cnt++;
385
386 GDT_DPRINTF(GDT_D_CMD, ("gdt_mpr_copy_cmd(%p) ", gdt));
387
388 gdt->sc_cmd_off += cp_count;
389
390 bus_space_write_region_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
391 GDT_MPR_IC + GDT_DPR_CMD + dp_offset,
392 (u_int32_t *)gccb->gc_cmd, cp_count >> 2);
393 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh,
394 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_OFFSET,
395 htole16(GDT_DPMEM_COMMAND_OFFSET + dp_offset));
396 bus_space_write_2(gdt->sc_dpmemt, gdt->sc_dpmemh,
397 GDT_MPR_IC + GDT_COMM_QUEUE + cmd_no * GDT_COMM_Q_SZ + GDT_SERV_ID,
398 htole16(gccb->gc_service));
399 }
400
401 u_int8_t
gdt_mpr_get_status(struct gdt_softc * gdt)402 gdt_mpr_get_status(struct gdt_softc *gdt)
403 {
404 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_get_status(%p) ", gdt));
405
406 return bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR);
407 }
408
409 void
gdt_mpr_intr(struct gdt_softc * gdt,struct gdt_intr_ctx * ctx)410 gdt_mpr_intr(struct gdt_softc *gdt, struct gdt_intr_ctx *ctx)
411 {
412 int i;
413
414 GDT_DPRINTF(GDT_D_INTR, ("gdt_mpr_intr(%p) ", gdt));
415
416 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_EDOOR, 0xff);
417
418 if (ctx->istatus & 0x80) { /* error flag */
419 ctx->istatus &= ~0x80;
420 ctx->cmd_status = bus_space_read_2(gdt->sc_dpmemt,
421 gdt->sc_dpmemh, GDT_MPR_STATUS);
422 } else /* no error */
423 ctx->cmd_status = GDT_S_OK;
424
425 ctx->info =
426 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_INFO);
427 ctx->service =
428 bus_space_read_2(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SERVICE);
429 ctx->info2 =
430 bus_space_read_4(gdt->sc_dpmemt, gdt->sc_dpmemh,
431 GDT_MPR_INFO + sizeof (u_int32_t));
432
433 /* event string */
434 if (ctx->istatus == GDT_ASYNCINDEX) {
435 if (ctx->service != GDT_SCREENSERVICE &&
436 (gdt->sc_fw_vers & 0xff) >= 0x1a) {
437 gdt->sc_dvr.severity =
438 bus_space_read_1(gdt->sc_dpmemt,gdt->sc_dpmemh, GDT_SEVERITY);
439 for (i = 0; i < 256; ++i) {
440 gdt->sc_dvr.event_string[i] =
441 bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
442 GDT_EVT_BUF + i);
443 if (gdt->sc_dvr.event_string[i] == 0)
444 break;
445 }
446 }
447 }
448 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA1, 0);
449 }
450
451 void
gdt_mpr_release_event(struct gdt_softc * gdt)452 gdt_mpr_release_event(struct gdt_softc *gdt)
453 {
454 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_release_event(%p) ", gdt));
455
456 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_LDOOR, 1);
457 }
458
459 void
gdt_mpr_set_sema0(struct gdt_softc * gdt)460 gdt_mpr_set_sema0(struct gdt_softc *gdt)
461 {
462 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_set_sema0(%p) ", gdt));
463
464 bus_space_write_1(gdt->sc_dpmemt, gdt->sc_dpmemh, GDT_MPR_SEMA0, 1);
465 }
466
467 int
gdt_mpr_test_busy(struct gdt_softc * gdt)468 gdt_mpr_test_busy(struct gdt_softc *gdt)
469 {
470 GDT_DPRINTF(GDT_D_MISC, ("gdt_mpr_test_busy(%p) ", gdt));
471
472 return (bus_space_read_1(gdt->sc_dpmemt, gdt->sc_dpmemh,
473 GDT_MPR_SEMA0) & 1);
474 }
475