1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_GT_REGS__ 7 #define __INTEL_GT_REGS__ 8 9 #include "i915_reg_defs.h" 10 11 #define VLV_GUNIT_BASE 0x180000 12 13 /* 14 * The perf control registers are technically multicast registers, but the 15 * driver never needs to read/write them directly; we only use them to build 16 * lists of registers (where they're mixed in with other non-MCR registers) 17 * and then operate on the offset directly. For now we'll just define them 18 * as non-multicast so we can place them on the same list, but we may want 19 * to try to come up with a better way to handle heterogeneous lists of 20 * registers in the future. 21 */ 22 #define PERF_REG(offset) _MMIO(offset) 23 24 /* MTL workpoint reg to get core C state and actual freq of 3D, SAMedia */ 25 #define MTL_MIRROR_TARGET_WP1 _MMIO(0xc60) 26 #define MTL_CAGF_MASK REG_GENMASK(8, 0) 27 #define MTL_CC0 0x0 28 #define MTL_CC6 0x3 29 #define MTL_CC_MASK REG_GENMASK(12, 9) 30 31 /* RPM unit config (Gen8+) */ 32 #define RPM_CONFIG0 _MMIO(0xd00) 33 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 34 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) 35 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 0 36 #define GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 1 37 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT 3 38 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK (0x7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT) 39 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ 0 40 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ 1 41 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ 2 42 #define GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ 3 43 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT 1 44 #define GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK (0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT) 45 46 #define RPM_CONFIG1 _MMIO(0xd04) 47 #define GEN10_GT_NOA_ENABLE (1 << 9) 48 49 /* RCP unit config (Gen8+) */ 50 #define RCP_CONFIG _MMIO(0xd08) 51 52 #define RC6_LOCATION _MMIO(0xd40) 53 #define RC6_CTX_IN_DRAM (1 << 0) 54 #define RC6_CTX_BASE _MMIO(0xd48) 55 #define RC6_CTX_BASE_MASK 0xFFFFFFF0 56 57 #define FORCEWAKE_ACK_MEDIA_VDBOX_GEN11(n) _MMIO(0xd50 + (n) * 4) 58 #define FORCEWAKE_ACK_MEDIA_VEBOX_GEN11(n) _MMIO(0xd70 + (n) * 4) 59 #define FORCEWAKE_ACK_RENDER_GEN9 _MMIO(0xd84) 60 #define FORCEWAKE_ACK_MEDIA_GEN9 _MMIO(0xd88) 61 62 #define FORCEWAKE_ACK_GSC _MMIO(0xdf8) 63 #define FORCEWAKE_ACK_GT_MTL _MMIO(0xdfc) 64 65 #define GMD_ID_GRAPHICS _MMIO(0xd8c) 66 #define GMD_ID_MEDIA _MMIO(MTL_MEDIA_GSI_BASE + 0xd8c) 67 68 #define MCFG_MCR_SELECTOR _MMIO(0xfd0) 69 #define MTL_STEER_SEMAPHORE _MMIO(0xfd0) 70 #define MTL_MCR_SELECTOR _MMIO(0xfd4) 71 #define SF_MCR_SELECTOR _MMIO(0xfd8) 72 #define GEN8_MCR_SELECTOR _MMIO(0xfdc) 73 #define GAM_MCR_SELECTOR _MMIO(0xfe0) 74 #define GEN8_MCR_SLICE(slice) (((slice) & 3) << 26) 75 #define GEN8_MCR_SLICE_MASK GEN8_MCR_SLICE(3) 76 #define GEN8_MCR_SUBSLICE(subslice) (((subslice) & 3) << 24) 77 #define GEN8_MCR_SUBSLICE_MASK GEN8_MCR_SUBSLICE(3) 78 #define GEN11_MCR_MULTICAST REG_BIT(31) 79 #define GEN11_MCR_SLICE(slice) (((slice) & 0xf) << 27) 80 #define GEN11_MCR_SLICE_MASK GEN11_MCR_SLICE(0xf) 81 #define GEN11_MCR_SUBSLICE(subslice) (((subslice) & 0x7) << 24) 82 #define GEN11_MCR_SUBSLICE_MASK GEN11_MCR_SUBSLICE(0x7) 83 #define MTL_MCR_GROUPID REG_GENMASK(11, 8) 84 #define MTL_MCR_INSTANCEID REG_GENMASK(3, 0) 85 86 #define IPEIR_I965 _MMIO(0x2064) 87 #define IPEHR_I965 _MMIO(0x2068) 88 89 /* 90 * On GEN4, only the render ring INSTDONE exists and has a different 91 * layout than the GEN7+ version. 92 * The GEN2 counterpart of this register is GEN2_INSTDONE. 93 */ 94 #define INSTPS _MMIO(0x2070) /* 965+ only */ 95 #define GEN4_INSTDONE1 _MMIO(0x207c) /* 965+ only, aka INSTDONE_2 on SNB */ 96 #define ACTHD_I965 _MMIO(0x2074) 97 #define HWS_PGA _MMIO(0x2080) 98 #define HWS_ADDRESS_MASK 0xfffff000 99 #define HWS_START_ADDRESS_SHIFT 4 100 101 #define _3D_CHICKEN _MMIO(0x2084) 102 #define _3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB (1 << 10) 103 104 #define PWRCTXA _MMIO(0x2088) /* 965GM+ only */ 105 #define PWRCTX_EN (1 << 0) 106 107 #define FF_SLICE_CHICKEN _MMIO(0x2088) 108 #define FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX (1 << 1) 109 110 /* GM45+ chicken bits -- debug workaround bits that may be required 111 * for various sorts of correct behavior. The top 16 bits of each are 112 * the enables for writing to the corresponding low bit. 113 */ 114 #define _3D_CHICKEN2 _MMIO(0x208c) 115 /* Disables pipelining of read flushes past the SF-WIZ interface. 116 * Required on all Ironlake steppings according to the B-Spec, but the 117 * particular danger of not doing so is not specified. 118 */ 119 #define _3D_CHICKEN2_WM_READ_PIPELINED (1 << 14) 120 121 #define _3D_CHICKEN3 _MMIO(0x2090) 122 #define _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX (1 << 12) 123 #define _3D_CHICKEN_SF_DISABLE_OBJEND_CULL (1 << 10) 124 #define _3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE (1 << 5) 125 #define _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL (1 << 5) 126 #define _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(x) ((x) << 1) /* gen8+ */ 127 #define _3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH (1 << 1) /* gen6 */ 128 129 #define GEN2_INSTDONE _MMIO(0x2090) 130 #define NOPID _MMIO(0x2094) 131 #define HWSTAM _MMIO(0x2098) 132 133 #define WAIT_FOR_RC6_EXIT _MMIO(0x20cc) 134 /* HSW only */ 135 #define HSW_SELECTIVE_READ_ADDRESSING_SHIFT 2 136 #define HSW_SELECTIVE_READ_ADDRESSING_MASK (0x3 << HSW_SLECTIVE_READ_ADDRESSING_SHIFT) 137 #define HSW_SELECTIVE_WRITE_ADDRESS_SHIFT 4 138 #define HSW_SELECTIVE_WRITE_ADDRESS_MASK (0x7 << HSW_SELECTIVE_WRITE_ADDRESS_SHIFT) 139 /* HSW+ */ 140 #define HSW_WAIT_FOR_RC6_EXIT_ENABLE (1 << 0) 141 #define HSW_RCS_CONTEXT_ENABLE (1 << 7) 142 #define HSW_RCS_INHIBIT (1 << 8) 143 /* Gen8 */ 144 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 145 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) 146 #define GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT 4 147 #define GEN8_SELECTIVE_WRITE_ADDRESS_MASK (0x3 << GEN8_SELECTIVE_WRITE_ADDRESS_SHIFT) 148 #define GEN8_SELECTIVE_WRITE_ADDRESSING_ENABLE (1 << 6) 149 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT 9 150 #define GEN8_SELECTIVE_READ_SUBSLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SUBSLICE_SELECT_SHIFT) 151 #define GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT 11 152 #define GEN8_SELECTIVE_READ_SLICE_SELECT_MASK (0x3 << GEN8_SELECTIVE_READ_SLICE_SELECT_SHIFT) 153 #define GEN8_SELECTIVE_READ_ADDRESSING_ENABLE (1 << 13) 154 155 #define GEN6_GT_MODE _MMIO(0x20d0) 156 #define GEN6_WIZ_HASHING(hi, lo) (((hi) << 9) | ((lo) << 7)) 157 #define GEN6_WIZ_HASHING_8x8 GEN6_WIZ_HASHING(0, 0) 158 #define GEN6_WIZ_HASHING_8x4 GEN6_WIZ_HASHING(0, 1) 159 #define GEN6_WIZ_HASHING_16x4 GEN6_WIZ_HASHING(1, 0) 160 #define GEN6_WIZ_HASHING_MASK GEN6_WIZ_HASHING(1, 1) 161 #define GEN6_TD_FOUR_ROW_DISPATCH_DISABLE (1 << 5) 162 163 /* chicken reg for WaConextSwitchWithConcurrentTLBInvalidate */ 164 #define GEN9_CSFE_CHICKEN1_RCS _MMIO(0x20d4) 165 #define GEN9_PREEMPT_GPGPU_SYNC_SWITCH_DISABLE (1 << 2) 166 #define GEN11_ENABLE_32_PLANE_MODE (1 << 7) 167 168 #define GEN7_FF_SLICE_CS_CHICKEN1 _MMIO(0x20e0) 169 #define GEN9_FFSC_PERCTX_PREEMPT_CTRL (1 << 14) 170 171 #define FF_SLICE_CS_CHICKEN2 _MMIO(0x20e4) 172 #define GEN9_TSG_BARRIER_ACK_DISABLE (1 << 8) 173 #define GEN9_POOLED_EU_LOAD_BALANCING_FIX_DISABLE (1 << 10) 174 #define GEN12_PERF_FIX_BALANCING_CFE_DISABLE REG_BIT(15) 175 176 #define GEN9_CS_DEBUG_MODE1 _MMIO(0x20ec) 177 #define FF_DOP_CLOCK_GATE_DISABLE REG_BIT(1) 178 #define GEN12_CS_DEBUG_MODE1_CCCSUNIT_BE_COMMON _MMIO(0x20ec) 179 #define GEN12_REPLAY_MODE_GRANULARITY REG_BIT(0) 180 181 /* WaClearTdlStateAckDirtyBits */ 182 #define GEN8_STATE_ACK _MMIO(0x20f0) 183 #define GEN9_STATE_ACK_SLICE1 _MMIO(0x20f8) 184 #define GEN9_STATE_ACK_SLICE2 _MMIO(0x2100) 185 #define GEN9_STATE_ACK_TDL0 (1 << 12) 186 #define GEN9_STATE_ACK_TDL1 (1 << 13) 187 #define GEN9_STATE_ACK_TDL2 (1 << 14) 188 #define GEN9_STATE_ACK_TDL3 (1 << 15) 189 #define GEN9_SUBSLICE_TDL_ACK_BITS \ 190 (GEN9_STATE_ACK_TDL3 | GEN9_STATE_ACK_TDL2 | \ 191 GEN9_STATE_ACK_TDL1 | GEN9_STATE_ACK_TDL0) 192 193 #define CACHE_MODE_0 _MMIO(0x2120) /* 915+ only */ 194 #define CM0_PIPELINED_RENDER_FLUSH_DISABLE (1 << 8) 195 #define CM0_IZ_OPT_DISABLE (1 << 6) 196 #define CM0_ZR_OPT_DISABLE (1 << 5) 197 #define CM0_STC_EVICT_DISABLE_LRA_SNB (1 << 5) 198 #define CM0_DEPTH_EVICT_DISABLE (1 << 4) 199 #define CM0_COLOR_EVICT_DISABLE (1 << 3) 200 #define CM0_DEPTH_WRITE_DISABLE (1 << 1) 201 #define CM0_RC_OP_FLUSH_DISABLE (1 << 0) 202 203 #define GFX_FLSH_CNTL _MMIO(0x2170) /* 915+ only */ 204 205 /* 206 * Logical Context regs 207 */ 208 /* 209 * Notes on SNB/IVB/VLV context size: 210 * - Power context is saved elsewhere (LLC or stolen) 211 * - Ring/execlist context is saved on SNB, not on IVB 212 * - Extended context size already includes render context size 213 * - We always need to follow the extended context size. 214 * SNB BSpec has comments indicating that we should use the 215 * render context size instead if execlists are disabled, but 216 * based on empirical testing that's just nonsense. 217 * - Pipelined/VF state is saved on SNB/IVB respectively 218 * - GT1 size just indicates how much of render context 219 * doesn't need saving on GT1 220 */ 221 #define CXT_SIZE _MMIO(0x21a0) 222 #define GEN6_CXT_POWER_SIZE(cxt_reg) (((cxt_reg) >> 24) & 0x3f) 223 #define GEN6_CXT_RING_SIZE(cxt_reg) (((cxt_reg) >> 18) & 0x3f) 224 #define GEN6_CXT_RENDER_SIZE(cxt_reg) (((cxt_reg) >> 12) & 0x3f) 225 #define GEN6_CXT_EXTENDED_SIZE(cxt_reg) (((cxt_reg) >> 6) & 0x3f) 226 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) (((cxt_reg) >> 0) & 0x3f) 227 #define GEN6_CXT_TOTAL_SIZE(cxt_reg) (GEN6_CXT_RING_SIZE(cxt_reg) + \ 228 GEN6_CXT_EXTENDED_SIZE(cxt_reg) + \ 229 GEN6_CXT_PIPELINE_SIZE(cxt_reg)) 230 #define GEN7_CXT_SIZE _MMIO(0x21a8) 231 #define GEN7_CXT_POWER_SIZE(ctx_reg) (((ctx_reg) >> 25) & 0x7f) 232 #define GEN7_CXT_RING_SIZE(ctx_reg) (((ctx_reg) >> 22) & 0x7) 233 #define GEN7_CXT_RENDER_SIZE(ctx_reg) (((ctx_reg) >> 16) & 0x3f) 234 #define GEN7_CXT_EXTENDED_SIZE(ctx_reg) (((ctx_reg) >> 9) & 0x7f) 235 #define GEN7_CXT_GT1_SIZE(ctx_reg) (((ctx_reg) >> 6) & 0x7) 236 #define GEN7_CXT_VFSTATE_SIZE(ctx_reg) (((ctx_reg) >> 0) & 0x3f) 237 #define GEN7_CXT_TOTAL_SIZE(ctx_reg) (GEN7_CXT_EXTENDED_SIZE(ctx_reg) + \ 238 GEN7_CXT_VFSTATE_SIZE(ctx_reg)) 239 240 #define HSW_MI_PREDICATE_RESULT_2 _MMIO(0x2214) 241 242 #define GEN9_CTX_PREEMPT_REG _MMIO(0x2248) 243 #define GEN12_DISABLE_POSH_BUSY_FF_DOP_CG REG_BIT(11) 244 245 #define GPGPU_THREADS_DISPATCHED _MMIO(0x2290) 246 #define GPGPU_THREADS_DISPATCHED_UDW _MMIO(0x2290 + 4) 247 248 #define GEN9_RCS_FE_FSM2 _MMIO(0x22a4) 249 #define GEN6_RCS_PWR_FSM _MMIO(0x22ac) 250 251 #define HS_INVOCATION_COUNT _MMIO(0x2300) 252 #define HS_INVOCATION_COUNT_UDW _MMIO(0x2300 + 4) 253 #define DS_INVOCATION_COUNT _MMIO(0x2308) 254 #define DS_INVOCATION_COUNT_UDW _MMIO(0x2308 + 4) 255 #define IA_VERTICES_COUNT _MMIO(0x2310) 256 #define IA_VERTICES_COUNT_UDW _MMIO(0x2310 + 4) 257 #define IA_PRIMITIVES_COUNT _MMIO(0x2318) 258 #define IA_PRIMITIVES_COUNT_UDW _MMIO(0x2318 + 4) 259 #define VS_INVOCATION_COUNT _MMIO(0x2320) 260 #define VS_INVOCATION_COUNT_UDW _MMIO(0x2320 + 4) 261 #define GS_INVOCATION_COUNT _MMIO(0x2328) 262 #define GS_INVOCATION_COUNT_UDW _MMIO(0x2328 + 4) 263 #define GS_PRIMITIVES_COUNT _MMIO(0x2330) 264 #define GS_PRIMITIVES_COUNT_UDW _MMIO(0x2330 + 4) 265 #define CL_INVOCATION_COUNT _MMIO(0x2338) 266 #define CL_INVOCATION_COUNT_UDW _MMIO(0x2338 + 4) 267 #define CL_PRIMITIVES_COUNT _MMIO(0x2340) 268 #define CL_PRIMITIVES_COUNT_UDW _MMIO(0x2340 + 4) 269 #define PS_INVOCATION_COUNT _MMIO(0x2348) 270 #define PS_INVOCATION_COUNT_UDW _MMIO(0x2348 + 4) 271 #define PS_DEPTH_COUNT _MMIO(0x2350) 272 #define PS_DEPTH_COUNT_UDW _MMIO(0x2350 + 4) 273 #define GEN7_3DPRIM_END_OFFSET _MMIO(0x2420) 274 #define GEN7_3DPRIM_START_VERTEX _MMIO(0x2430) 275 #define GEN7_3DPRIM_VERTEX_COUNT _MMIO(0x2434) 276 #define GEN7_3DPRIM_INSTANCE_COUNT _MMIO(0x2438) 277 #define GEN7_3DPRIM_START_INSTANCE _MMIO(0x243c) 278 #define GEN7_3DPRIM_BASE_VERTEX _MMIO(0x2440) 279 #define GEN7_GPGPU_DISPATCHDIMX _MMIO(0x2500) 280 #define GEN7_GPGPU_DISPATCHDIMY _MMIO(0x2504) 281 #define GEN7_GPGPU_DISPATCHDIMZ _MMIO(0x2508) 282 283 #define GFX_MODE _MMIO(0x2520) 284 285 #define GEN8_CS_CHICKEN1 _MMIO(0x2580) 286 #define GEN9_PREEMPT_3D_OBJECT_LEVEL (1 << 0) 287 #define GEN9_PREEMPT_GPGPU_LEVEL(hi, lo) (((hi) << 2) | ((lo) << 1)) 288 #define GEN9_PREEMPT_GPGPU_MID_THREAD_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 0) 289 #define GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(0, 1) 290 #define GEN9_PREEMPT_GPGPU_COMMAND_LEVEL GEN9_PREEMPT_GPGPU_LEVEL(1, 0) 291 #define GEN9_PREEMPT_GPGPU_LEVEL_MASK GEN9_PREEMPT_GPGPU_LEVEL(1, 1) 292 293 #define DRAW_WATERMARK _MMIO(0x26c0) 294 #define VERT_WM_VAL REG_GENMASK(9, 0) 295 296 #define GEN12_GLOBAL_MOCS(i) _MMIO(0x4000 + (i) * 4) /* Global MOCS regs */ 297 298 #define RENDER_HWS_PGA_GEN7 _MMIO(0x4080) 299 300 #define GEN8_GAMW_ECO_DEV_RW_IA _MMIO(0x4080) 301 #define GAMW_ECO_ENABLE_64K_IPS_FIELD 0xF 302 #define GAMW_ECO_DEV_CTX_RELOAD_DISABLE (1 << 7) 303 304 #define GAM_ECOCHK _MMIO(0x4090) 305 #define BDW_DISABLE_HDC_INVALIDATION (1 << 25) 306 #define ECOCHK_SNB_BIT (1 << 10) 307 #define ECOCHK_DIS_TLB (1 << 8) 308 #define HSW_ECOCHK_ARB_PRIO_SOL (1 << 6) 309 #define ECOCHK_PPGTT_CACHE64B (0x3 << 3) 310 #define ECOCHK_PPGTT_CACHE4B (0x0 << 3) 311 #define ECOCHK_PPGTT_GFDT_IVB (0x1 << 4) 312 #define ECOCHK_PPGTT_LLC_IVB (0x1 << 3) 313 #define ECOCHK_PPGTT_UC_HSW (0x1 << 3) 314 #define ECOCHK_PPGTT_WT_HSW (0x2 << 3) 315 #define ECOCHK_PPGTT_WB_HSW (0x3 << 3) 316 317 #define GEN8_RING_FAULT_REG _MMIO(0x4094) 318 #define _RING_FAULT_REG_RCS 0x4094 319 #define _RING_FAULT_REG_VCS 0x4194 320 #define _RING_FAULT_REG_BCS 0x4294 321 #define _RING_FAULT_REG_VECS 0x4394 322 #define RING_FAULT_REG(engine) _MMIO(_PICK((engine)->class, \ 323 _RING_FAULT_REG_RCS, \ 324 _RING_FAULT_REG_VCS, \ 325 _RING_FAULT_REG_VECS, \ 326 _RING_FAULT_REG_BCS)) 327 328 #define ERROR_GEN6 _MMIO(0x40a0) 329 330 #define DONE_REG _MMIO(0x40b0) 331 #define GEN8_PRIVATE_PAT_LO _MMIO(0x40e0) 332 #define GEN8_PRIVATE_PAT_HI _MMIO(0x40e0 + 4) 333 #define GEN10_PAT_INDEX(index) _MMIO(0x40e0 + (index) * 4) 334 #define BSD_HWS_PGA_GEN7 _MMIO(0x4180) 335 336 #define GEN12_CCS_AUX_INV _MMIO(0x4208) 337 #define GEN12_VD0_AUX_INV _MMIO(0x4218) 338 #define GEN12_VE0_AUX_INV _MMIO(0x4238) 339 #define GEN12_BCS0_AUX_INV _MMIO(0x4248) 340 341 #define GEN8_RTCR _MMIO(0x4260) 342 #define GEN8_M1TCR _MMIO(0x4264) 343 #define GEN8_M2TCR _MMIO(0x4268) 344 #define GEN8_BTCR _MMIO(0x426c) 345 #define GEN8_VTCR _MMIO(0x4270) 346 347 #define BLT_HWS_PGA_GEN7 _MMIO(0x4280) 348 349 #define GEN12_VD2_AUX_INV _MMIO(0x4298) 350 #define GEN12_CCS0_AUX_INV _MMIO(0x42c8) 351 #define AUX_INV REG_BIT(0) 352 353 #define VEBOX_HWS_PGA_GEN7 _MMIO(0x4380) 354 355 #define GEN12_AUX_ERR_DBG _MMIO(0x43f4) 356 357 #define GEN7_TLB_RD_ADDR _MMIO(0x4700) 358 359 #define GEN12_PAT_INDEX(index) _MMIO(0x4800 + (index) * 4) 360 #define _PAT_INDEX(index) _PICK_EVEN_2RANGES(index, 8, \ 361 0x4800, 0x4804, \ 362 0x4848, 0x484c) 363 #define XEHP_PAT_INDEX(index) MCR_REG(_PAT_INDEX(index)) 364 #define XELPMP_PAT_INDEX(index) _MMIO(_PAT_INDEX(index)) 365 366 #define XEHP_TILE0_ADDR_RANGE MCR_REG(0x4900) 367 #define XEHP_TILE_LMEM_RANGE_SHIFT 8 368 369 #define XEHP_FLAT_CCS_BASE_ADDR MCR_REG(0x4910) 370 #define XEHP_CCS_BASE_SHIFT 8 371 372 #define GAMTARBMODE _MMIO(0x4a08) 373 #define ARB_MODE_BWGTLB_DISABLE (1 << 9) 374 #define ARB_MODE_SWIZZLE_BDW (1 << 1) 375 376 #define GEN9_GAMT_ECO_REG_RW_IA _MMIO(0x4ab0) 377 #define GAMT_ECO_ENABLE_IN_PLACE_DECOMPRESS (1 << 18) 378 379 #define GAMT_CHKN_BIT_REG _MMIO(0x4ab8) 380 #define GAMT_CHKN_DISABLE_L3_COH_PIPE (1 << 31) 381 #define GAMT_CHKN_DISABLE_DYNAMIC_CREDIT_SHARING (1 << 28) 382 #define GAMT_CHKN_DISABLE_I2M_CYCLE_ON_WR_PORT (1 << 24) 383 384 #define GEN8_FAULT_TLB_DATA0 _MMIO(0x4b10) 385 #define GEN8_FAULT_TLB_DATA1 _MMIO(0x4b14) 386 387 #define GEN11_GACB_PERF_CTRL _MMIO(0x4b80) 388 #define GEN11_HASH_CTRL_MASK (0x3 << 12 | 0xf << 0) 389 #define GEN11_HASH_CTRL_BIT0 (1 << 0) 390 #define GEN11_HASH_CTRL_BIT4 (1 << 12) 391 392 /* gamt regs */ 393 #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4) 394 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for LRA1/2 */ 395 #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for LRA1/2 */ 396 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " " */ 397 #define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " " */ 398 399 #define MMCD_MISC_CTRL _MMIO(0x4ddc) /* skl+ */ 400 #define MMCD_PCLA (1 << 31) 401 #define MMCD_HOTSPOT_EN (1 << 27) 402 403 /* There are the 4 64-bit counter registers, one for each stream output */ 404 #define GEN7_SO_NUM_PRIMS_WRITTEN(n) _MMIO(0x5200 + (n) * 8) 405 #define GEN7_SO_NUM_PRIMS_WRITTEN_UDW(n) _MMIO(0x5200 + (n) * 8 + 4) 406 407 #define GEN7_SO_PRIM_STORAGE_NEEDED(n) _MMIO(0x5240 + (n) * 8) 408 #define GEN7_SO_PRIM_STORAGE_NEEDED_UDW(n) _MMIO(0x5240 + (n) * 8 + 4) 409 410 #define GEN9_WM_CHICKEN3 _MMIO(0x5588) 411 #define GEN9_FACTOR_IN_CLR_VAL_HIZ (1 << 9) 412 413 #define XEHP_CULLBIT1 MCR_REG(0x6100) 414 415 #define CHICKEN_RASTER_1 MCR_REG(0x6204) 416 #define DIS_SF_ROUND_NEAREST_EVEN REG_BIT(8) 417 418 #define CHICKEN_RASTER_2 MCR_REG(0x6208) 419 #define TBIMR_FAST_CLIP REG_BIT(5) 420 421 #define VFLSKPD MCR_REG(0x62a8) 422 #define VF_PREFETCH_TLB_DIS REG_BIT(5) 423 #define DIS_OVER_FETCH_CACHE REG_BIT(1) 424 #define DIS_MULT_MISS_RD_SQUASH REG_BIT(0) 425 426 #define GEN12_FF_MODE2 _MMIO(0x6604) 427 #define XEHP_FF_MODE2 MCR_REG(0x6604) 428 #define FF_MODE2_GS_TIMER_MASK REG_GENMASK(31, 24) 429 #define FF_MODE2_GS_TIMER_224 REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224) 430 #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16) 431 #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4) 432 433 #define XEHPG_INSTDONE_GEOM_SVG MCR_REG(0x666c) 434 435 #define CACHE_MODE_0_GEN7 _MMIO(0x7000) /* IVB+ */ 436 #define RC_OP_FLUSH_ENABLE (1 << 0) 437 #define HIZ_RAW_STALL_OPT_DISABLE (1 << 2) 438 #define CACHE_MODE_1 _MMIO(0x7004) /* IVB+ */ 439 #define MSAA_OPTIMIZATION_REDUC_DISABLE REG_BIT(11) 440 #define PIXEL_SUBSPAN_COLLECT_OPT_DISABLE REG_BIT(6) 441 #define GEN8_4x4_STC_OPTIMIZATION_DISABLE REG_BIT(6) 442 #define GEN9_PARTIAL_RESOLVE_IN_VC_DISABLE REG_BIT(1) 443 444 #define GEN7_GT_MODE _MMIO(0x7008) 445 #define GEN9_IZ_HASHING_MASK(slice) (0x3 << ((slice) * 2)) 446 #define GEN9_IZ_HASHING(slice, val) ((val) << ((slice) * 2)) 447 448 /* GEN7 chicken */ 449 #define GEN7_COMMON_SLICE_CHICKEN1 _MMIO(0x7010) 450 #define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1 << 10) 451 #define GEN9_RHWO_OPTIMIZATION_DISABLE (1 << 14) 452 453 #define COMMON_SLICE_CHICKEN2 _MMIO(0x7014) 454 #define GEN9_PBE_COMPRESSED_HASH_SELECTION (1 << 13) 455 #define GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE (1 << 12) 456 #define GEN8_SBE_DISABLE_REPLAY_BUF_OPTIMIZATION (1 << 8) 457 #define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1 << 0) 458 459 #define HIZ_CHICKEN _MMIO(0x7018) 460 #define CHV_HZ_8X8_MODE_IN_1X REG_BIT(15) 461 #define DG1_HZ_READ_SUPPRESSION_OPTIMIZATION_DISABLE REG_BIT(14) 462 #define HZ_DEPTH_TEST_LE_GE_OPT_DISABLE REG_BIT(13) 463 #define BDW_HIZ_POWER_COMPILER_CLOCK_GATING_DISABLE REG_BIT(3) 464 465 #define XEHP_CULLBIT2 MCR_REG(0x7030) 466 467 #define GEN8_L3CNTLREG _MMIO(0x7034) 468 #define GEN8_ERRDETBCTRL (1 << 9) 469 470 #define XEHP_PSS_MODE2 MCR_REG(0x703c) 471 #define SCOREBOARD_STALL_FLUSH_CONTROL REG_BIT(5) 472 473 #define XEHP_PSS_CHICKEN MCR_REG(0x7044) 474 #define FD_END_COLLECT REG_BIT(5) 475 476 #define GEN7_SC_INSTDONE _MMIO(0x7100) 477 #define GEN12_SC_INSTDONE_EXTRA _MMIO(0x7104) 478 #define GEN12_SC_INSTDONE_EXTRA2 _MMIO(0x7108) 479 480 /* GEN8 chicken */ 481 #define HDC_CHICKEN0 _MMIO(0x7300) 482 #define HDC_FORCE_CSR_NON_COHERENT_OVR_DISABLE (1 << 15) 483 #define HDC_FENCE_DEST_SLM_DISABLE (1 << 14) 484 #define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1 << 11) 485 #define HDC_FORCE_CONTEXT_SAVE_RESTORE_NON_COHERENT (1 << 5) 486 #define HDC_FORCE_NON_COHERENT (1 << 4) 487 #define HDC_BARRIER_PERFORMANCE_DISABLE (1 << 10) 488 489 #define COMMON_SLICE_CHICKEN4 _MMIO(0x7300) 490 #define DISABLE_TDC_LOAD_BALANCING_CALC REG_BIT(6) 491 492 #define GEN8_HDC_CHICKEN1 _MMIO(0x7304) 493 494 #define GEN11_COMMON_SLICE_CHICKEN3 _MMIO(0x7304) 495 #define XEHP_COMMON_SLICE_CHICKEN3 MCR_REG(0x7304) 496 #define DG1_FLOAT_POINT_BLEND_OPT_STRICT_MODE_EN REG_BIT(12) 497 #define XEHP_DUAL_SIMD8_SEQ_MERGE_DISABLE REG_BIT(12) 498 #define GEN11_BLEND_EMB_FIX_DISABLE_IN_RCC REG_BIT(11) 499 #define GEN12_DISABLE_CPS_AWARE_COLOR_PIPE REG_BIT(9) 500 501 #define GEN9_SLICE_COMMON_ECO_CHICKEN1 _MMIO(0x731c) 502 #define XEHP_SLICE_COMMON_ECO_CHICKEN1 MCR_REG(0x731c) 503 #define MSC_MSAA_REODER_BUF_BYPASS_DISABLE REG_BIT(14) 504 #define GEN11_STATE_CACHE_REDIRECT_TO_CS (1 << 11) 505 506 #define GEN9_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + (slice) * 0x4) 507 #define GEN10_SLICE_PGCTL_ACK(slice) _MMIO(0x804c + ((slice) / 3) * 0x34 + \ 508 ((slice) % 3) * 0x4) 509 #define GEN9_PGCTL_SLICE_ACK (1 << 0) 510 #define GEN9_PGCTL_SS_ACK(subslice) (1 << (2 + (subslice) * 2)) 511 #define GEN10_PGCTL_VALID_SS_MASK(slice) ((slice) == 0 ? 0x7F : 0x1F) 512 513 #define GEN9_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + (slice) * 0x8) 514 #define GEN10_SS01_EU_PGCTL_ACK(slice) _MMIO(0x805c + ((slice) / 3) * 0x30 + \ 515 ((slice) % 3) * 0x8) 516 #define GEN9_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + (slice) * 0x8) 517 #define GEN10_SS23_EU_PGCTL_ACK(slice) _MMIO(0x8060 + ((slice) / 3) * 0x30 + \ 518 ((slice) % 3) * 0x8) 519 #define GEN9_PGCTL_SSA_EU08_ACK (1 << 0) 520 #define GEN9_PGCTL_SSA_EU19_ACK (1 << 2) 521 #define GEN9_PGCTL_SSA_EU210_ACK (1 << 4) 522 #define GEN9_PGCTL_SSA_EU311_ACK (1 << 6) 523 #define GEN9_PGCTL_SSB_EU08_ACK (1 << 8) 524 #define GEN9_PGCTL_SSB_EU19_ACK (1 << 10) 525 #define GEN9_PGCTL_SSB_EU210_ACK (1 << 12) 526 #define GEN9_PGCTL_SSB_EU311_ACK (1 << 14) 527 528 #define VF_PREEMPTION _MMIO(0x83a4) 529 #define PREEMPTION_VERTEX_COUNT REG_GENMASK(15, 0) 530 531 #define VFG_PREEMPTION_CHICKEN _MMIO(0x83b4) 532 #define POLYGON_TRIFAN_LINELOOP_DISABLE REG_BIT(4) 533 534 #define GEN8_RC6_CTX_INFO _MMIO(0x8504) 535 536 #define GEN12_SQCNT1 _MMIO(0x8718) 537 #define GEN12_SQCNT1_PMON_ENABLE REG_BIT(30) 538 #define GEN12_SQCNT1_OABPC REG_BIT(29) 539 #define GEN12_STRICT_RAR_ENABLE REG_BIT(23) 540 541 #define XEHP_SQCM MCR_REG(0x8724) 542 #define EN_32B_ACCESS REG_BIT(30) 543 544 #define MTL_GSCPSMI_BASEADDR_LSB _MMIO(0x880c) 545 #define MTL_GSCPSMI_BASEADDR_MSB _MMIO(0x8810) 546 547 #define HSW_IDICR _MMIO(0x9008) 548 #define IDIHASHMSK(x) (((x) & 0x3f) << 16) 549 550 #define GEN6_MBCUNIT_SNPCR _MMIO(0x900c) /* for LLC config */ 551 #define GEN6_MBC_SNPCR_SHIFT 21 552 #define GEN6_MBC_SNPCR_MASK (3 << 21) 553 #define GEN6_MBC_SNPCR_MAX (0 << 21) 554 #define GEN6_MBC_SNPCR_MED (1 << 21) 555 #define GEN6_MBC_SNPCR_LOW (2 << 21) 556 #define GEN6_MBC_SNPCR_MIN (3 << 21) /* only 1/16th of the cache is shared */ 557 558 #define VLV_G3DCTL _MMIO(0x9024) 559 #define VLV_GSCKGCTL _MMIO(0x9028) 560 561 /* WaCatErrorRejectionIssue */ 562 #define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG _MMIO(0x9030) 563 #define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1 << 11) 564 565 #define FBC_LLC_READ_CTRL _MMIO(0x9044) 566 #define FBC_LLC_FULLY_OPEN REG_BIT(30) 567 568 #define GEN6_MBCTL _MMIO(0x907c) 569 #define GEN6_MBCTL_ENABLE_BOOT_FETCH (1 << 4) 570 #define GEN6_MBCTL_CTX_FETCH_NEEDED (1 << 3) 571 #define GEN6_MBCTL_BME_UPDATE_ENABLE (1 << 2) 572 #define GEN6_MBCTL_MAE_UPDATE_ENABLE (1 << 1) 573 #define GEN6_MBCTL_BOOT_FETCH_MECH (1 << 0) 574 575 /* Fuse readout registers for GT */ 576 #define XEHP_FUSE4 _MMIO(0x9114) 577 #define GT_L3_EXC_MASK REG_GENMASK(6, 4) 578 #define GEN10_MIRROR_FUSE3 _MMIO(0x9118) 579 #define GEN10_L3BANK_PAIR_COUNT 4 580 #define GEN10_L3BANK_MASK 0x0F 581 /* on Xe_HP the same fuses indicates mslices instead of L3 banks */ 582 #define GEN12_MAX_MSLICES 4 583 #define GEN12_MEML3_EN_MASK 0x0F 584 585 #define HSW_PAVP_FUSE1 _MMIO(0x911c) 586 #define XEHP_SFC_ENABLE_MASK REG_GENMASK(27, 24) 587 #define HSW_F1_EU_DIS_MASK REG_GENMASK(17, 16) 588 #define HSW_F1_EU_DIS_10EUS 0 589 #define HSW_F1_EU_DIS_8EUS 1 590 #define HSW_F1_EU_DIS_6EUS 2 591 592 #define GEN8_FUSE2 _MMIO(0x9120) 593 #define GEN8_F2_SS_DIS_SHIFT 21 594 #define GEN8_F2_SS_DIS_MASK (0x7 << GEN8_F2_SS_DIS_SHIFT) 595 #define GEN8_F2_S_ENA_SHIFT 25 596 #define GEN8_F2_S_ENA_MASK (0x7 << GEN8_F2_S_ENA_SHIFT) 597 #define GEN9_F2_SS_DIS_SHIFT 20 598 #define GEN9_F2_SS_DIS_MASK (0xf << GEN9_F2_SS_DIS_SHIFT) 599 #define GEN10_F2_S_ENA_SHIFT 22 600 #define GEN10_F2_S_ENA_MASK (0x3f << GEN10_F2_S_ENA_SHIFT) 601 #define GEN10_F2_SS_DIS_SHIFT 18 602 #define GEN10_F2_SS_DIS_MASK (0xf << GEN10_F2_SS_DIS_SHIFT) 603 604 #define GEN8_EU_DISABLE0 _MMIO(0x9134) 605 #define GEN9_EU_DISABLE(slice) _MMIO(0x9134 + (slice) * 0x4) 606 #define GEN11_EU_DISABLE _MMIO(0x9134) 607 #define GEN8_EU_DIS0_S0_MASK 0xffffff 608 #define GEN8_EU_DIS0_S1_SHIFT 24 609 #define GEN8_EU_DIS0_S1_MASK (0xff << GEN8_EU_DIS0_S1_SHIFT) 610 #define GEN11_EU_DIS_MASK 0xFF 611 #define XEHP_EU_ENABLE _MMIO(0x9134) 612 #define XEHP_EU_ENA_MASK 0xFF 613 614 #define GEN8_EU_DISABLE1 _MMIO(0x9138) 615 #define GEN8_EU_DIS1_S1_MASK 0xffff 616 #define GEN8_EU_DIS1_S2_SHIFT 16 617 #define GEN8_EU_DIS1_S2_MASK (0xffff << GEN8_EU_DIS1_S2_SHIFT) 618 619 #define GEN11_GT_SLICE_ENABLE _MMIO(0x9138) 620 #define GEN11_GT_S_ENA_MASK 0xFF 621 622 #define GEN8_EU_DISABLE2 _MMIO(0x913c) 623 #define GEN8_EU_DIS2_S2_MASK 0xff 624 625 #define GEN11_GT_SUBSLICE_DISABLE _MMIO(0x913c) 626 #define GEN12_GT_GEOMETRY_DSS_ENABLE _MMIO(0x913c) 627 628 #define GEN10_EU_DISABLE3 _MMIO(0x9140) 629 #define GEN10_EU_DIS_SS_MASK 0xff 630 #define GEN11_GT_VEBOX_VDBOX_DISABLE _MMIO(0x9140) 631 #define GEN11_GT_VDBOX_DISABLE_MASK 0xff 632 #define GEN11_GT_VEBOX_DISABLE_SHIFT 16 633 #define GEN11_GT_VEBOX_DISABLE_MASK (0x0f << GEN11_GT_VEBOX_DISABLE_SHIFT) 634 635 #define GEN12_GT_COMPUTE_DSS_ENABLE _MMIO(0x9144) 636 #define XEHPC_GT_COMPUTE_DSS_ENABLE_EXT _MMIO(0x9148) 637 638 #define GEN6_UCGCTL1 _MMIO(0x9400) 639 #define GEN6_GAMUNIT_CLOCK_GATE_DISABLE (1 << 22) 640 #define GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE (1 << 16) 641 #define GEN6_BLBUNIT_CLOCK_GATE_DISABLE (1 << 5) 642 #define GEN6_CSUNIT_CLOCK_GATE_DISABLE (1 << 7) 643 644 #define GEN6_UCGCTL2 _MMIO(0x9404) 645 #define GEN6_VFUNIT_CLOCK_GATE_DISABLE (1 << 31) 646 #define GEN7_VDSUNIT_CLOCK_GATE_DISABLE (1 << 30) 647 #define GEN7_TDLUNIT_CLOCK_GATE_DISABLE (1 << 22) 648 #define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13) 649 #define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12) 650 #define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) 651 652 #define GEN6_UCGCTL3 _MMIO(0x9408) 653 #define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20) 654 655 #define GEN7_UCGCTL4 _MMIO(0x940c) 656 #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1 << 25) 657 #define GEN8_EU_GAUNIT_CLOCK_GATE_DISABLE (1 << 14) 658 659 #define GEN6_RCGCTL1 _MMIO(0x9410) 660 #define GEN6_RCGCTL2 _MMIO(0x9414) 661 662 #define GEN6_GDRST _MMIO(0x941c) 663 #define GEN6_GRDOM_FULL (1 << 0) 664 #define GEN6_GRDOM_RENDER (1 << 1) 665 #define GEN6_GRDOM_MEDIA (1 << 2) 666 #define GEN6_GRDOM_BLT (1 << 3) 667 #define GEN6_GRDOM_VECS (1 << 4) 668 #define GEN9_GRDOM_GUC (1 << 5) 669 #define GEN8_GRDOM_MEDIA2 (1 << 7) 670 /* GEN11 changed all bit defs except for FULL & RENDER */ 671 #define GEN11_GRDOM_FULL GEN6_GRDOM_FULL 672 #define GEN11_GRDOM_RENDER GEN6_GRDOM_RENDER 673 #define XEHPC_GRDOM_BLT8 REG_BIT(31) 674 #define XEHPC_GRDOM_BLT7 REG_BIT(30) 675 #define XEHPC_GRDOM_BLT6 REG_BIT(29) 676 #define XEHPC_GRDOM_BLT5 REG_BIT(28) 677 #define XEHPC_GRDOM_BLT4 REG_BIT(27) 678 #define XEHPC_GRDOM_BLT3 REG_BIT(26) 679 #define XEHPC_GRDOM_BLT2 REG_BIT(25) 680 #define XEHPC_GRDOM_BLT1 REG_BIT(24) 681 #define GEN12_GRDOM_GSC REG_BIT(21) 682 #define GEN11_GRDOM_SFC3 REG_BIT(20) 683 #define GEN11_GRDOM_SFC2 REG_BIT(19) 684 #define GEN11_GRDOM_SFC1 REG_BIT(18) 685 #define GEN11_GRDOM_SFC0 REG_BIT(17) 686 #define GEN11_GRDOM_VECS4 REG_BIT(16) 687 #define GEN11_GRDOM_VECS3 REG_BIT(15) 688 #define GEN11_GRDOM_VECS2 REG_BIT(14) 689 #define GEN11_GRDOM_VECS REG_BIT(13) 690 #define GEN11_GRDOM_MEDIA8 REG_BIT(12) 691 #define GEN11_GRDOM_MEDIA7 REG_BIT(11) 692 #define GEN11_GRDOM_MEDIA6 REG_BIT(10) 693 #define GEN11_GRDOM_MEDIA5 REG_BIT(9) 694 #define GEN11_GRDOM_MEDIA4 REG_BIT(8) 695 #define GEN11_GRDOM_MEDIA3 REG_BIT(7) 696 #define GEN11_GRDOM_MEDIA2 REG_BIT(6) 697 #define GEN11_GRDOM_MEDIA REG_BIT(5) 698 #define GEN11_GRDOM_GUC REG_BIT(3) 699 #define GEN11_GRDOM_BLT REG_BIT(2) 700 #define GEN11_VCS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << ((instance) >> 1)) 701 #define GEN11_VECS_SFC_RESET_BIT(instance) (GEN11_GRDOM_SFC0 << (instance)) 702 703 #define GEN6_RSTCTL _MMIO(0x9420) 704 705 #define GEN7_MISCCPCTL _MMIO(0x9424) 706 #define GEN7_DOP_CLOCK_GATE_ENABLE REG_BIT(0) 707 #define GEN12_DOP_CLOCK_GATE_RENDER_ENABLE REG_BIT(1) 708 #define GEN8_DOP_CLOCK_GATE_CFCLK_ENABLE (1 << 2) 709 #define GEN8_DOP_CLOCK_GATE_GUC_ENABLE (1 << 4) 710 #define GEN8_DOP_CLOCK_GATE_MEDIA_ENABLE (1 << 6) 711 712 #define GEN8_UCGCTL6 _MMIO(0x9430) 713 #define GEN8_GAPSUNIT_CLOCK_GATE_DISABLE (1 << 24) 714 #define GEN8_SDEUNIT_CLOCK_GATE_DISABLE (1 << 14) 715 #define GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ (1 << 28) 716 717 #define UNSLCGCTL9430 _MMIO(0x9430) 718 #define MSQDUNIT_CLKGATE_DIS REG_BIT(3) 719 720 #define UNSLICE_UNIT_LEVEL_CLKGATE _MMIO(0x9434) 721 #define VFUNIT_CLKGATE_DIS REG_BIT(20) 722 #define TSGUNIT_CLKGATE_DIS REG_BIT(17) /* XEHPSDV */ 723 #define CG3DDISCFEG_CLKGATE_DIS REG_BIT(17) /* DG2 */ 724 #define GAMEDIA_CLKGATE_DIS REG_BIT(11) 725 #define HSUNIT_CLKGATE_DIS REG_BIT(8) 726 #define VSUNIT_CLKGATE_DIS REG_BIT(3) 727 728 #define UNSLCGCTL9440 _MMIO(0x9440) 729 #define GAMTLBOACS_CLKGATE_DIS REG_BIT(28) 730 #define GAMTLBVDBOX5_CLKGATE_DIS REG_BIT(27) 731 #define GAMTLBVDBOX6_CLKGATE_DIS REG_BIT(26) 732 #define GAMTLBVDBOX3_CLKGATE_DIS REG_BIT(24) 733 #define GAMTLBVDBOX4_CLKGATE_DIS REG_BIT(23) 734 #define GAMTLBVDBOX7_CLKGATE_DIS REG_BIT(22) 735 #define GAMTLBVDBOX2_CLKGATE_DIS REG_BIT(21) 736 #define GAMTLBVDBOX0_CLKGATE_DIS REG_BIT(17) 737 #define GAMTLBKCR_CLKGATE_DIS REG_BIT(16) 738 #define GAMTLBGUC_CLKGATE_DIS REG_BIT(15) 739 #define GAMTLBBLT_CLKGATE_DIS REG_BIT(14) 740 #define GAMTLBVDBOX1_CLKGATE_DIS REG_BIT(6) 741 742 #define UNSLCGCTL9444 _MMIO(0x9444) 743 #define GAMTLBGFXA0_CLKGATE_DIS REG_BIT(30) 744 #define GAMTLBGFXA1_CLKGATE_DIS REG_BIT(29) 745 #define GAMTLBCOMPA0_CLKGATE_DIS REG_BIT(28) 746 #define GAMTLBCOMPA1_CLKGATE_DIS REG_BIT(27) 747 #define GAMTLBCOMPB0_CLKGATE_DIS REG_BIT(26) 748 #define GAMTLBCOMPB1_CLKGATE_DIS REG_BIT(25) 749 #define GAMTLBCOMPC0_CLKGATE_DIS REG_BIT(24) 750 #define GAMTLBCOMPC1_CLKGATE_DIS REG_BIT(23) 751 #define GAMTLBCOMPD0_CLKGATE_DIS REG_BIT(22) 752 #define GAMTLBCOMPD1_CLKGATE_DIS REG_BIT(21) 753 #define GAMTLBMERT_CLKGATE_DIS REG_BIT(20) 754 #define GAMTLBVEBOX3_CLKGATE_DIS REG_BIT(19) 755 #define GAMTLBVEBOX2_CLKGATE_DIS REG_BIT(18) 756 #define GAMTLBVEBOX1_CLKGATE_DIS REG_BIT(17) 757 #define GAMTLBVEBOX0_CLKGATE_DIS REG_BIT(16) 758 #define LTCDD_CLKGATE_DIS REG_BIT(10) 759 760 #define GEN11_SLICE_UNIT_LEVEL_CLKGATE _MMIO(0x94d4) 761 #define XEHP_SLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x94d4) 762 #define SARBUNIT_CLKGATE_DIS (1 << 5) 763 #define RCCUNIT_CLKGATE_DIS (1 << 7) 764 #define MSCUNIT_CLKGATE_DIS (1 << 10) 765 #define NODEDSS_CLKGATE_DIS REG_BIT(12) 766 #define L3_CLKGATE_DIS REG_BIT(16) 767 #define L3_CR2X_CLKGATE_DIS REG_BIT(17) 768 769 #define SCCGCTL94DC MCR_REG(0x94dc) 770 #define CG3DDISURB REG_BIT(14) 771 772 #define UNSLICE_UNIT_LEVEL_CLKGATE2 _MMIO(0x94e4) 773 #define VSUNIT_CLKGATE_DIS_TGL REG_BIT(19) 774 #define PSDUNIT_CLKGATE_DIS REG_BIT(5) 775 776 #define GEN11_SUBSLICE_UNIT_LEVEL_CLKGATE MCR_REG(0x9524) 777 #define DSS_ROUTER_CLKGATE_DIS REG_BIT(28) 778 #define GWUNIT_CLKGATE_DIS REG_BIT(16) 779 780 #define SUBSLICE_UNIT_LEVEL_CLKGATE2 MCR_REG(0x9528) 781 #define CPSSUNIT_CLKGATE_DIS REG_BIT(9) 782 783 #define SSMCGCTL9530 MCR_REG(0x9530) 784 #define RTFUNIT_CLKGATE_DIS REG_BIT(18) 785 786 #define GEN10_DFR_RATIO_EN_AND_CHICKEN MCR_REG(0x9550) 787 #define DFR_DISABLE (1 << 9) 788 789 #define MICRO_BP0_0 _MMIO(0x9800) 790 #define MICRO_BP0_2 _MMIO(0x9804) 791 #define MICRO_BP0_1 _MMIO(0x9808) 792 #define MICRO_BP1_0 _MMIO(0x980c) 793 #define MICRO_BP1_2 _MMIO(0x9810) 794 #define MICRO_BP1_1 _MMIO(0x9814) 795 #define MICRO_BP2_0 _MMIO(0x9818) 796 #define MICRO_BP2_2 _MMIO(0x981c) 797 #define MICRO_BP2_1 _MMIO(0x9820) 798 #define MICRO_BP3_0 _MMIO(0x9824) 799 #define MICRO_BP3_2 _MMIO(0x9828) 800 #define MICRO_BP3_1 _MMIO(0x982c) 801 #define MICRO_BP_TRIGGER _MMIO(0x9830) 802 #define MICRO_BP3_COUNT_STATUS01 _MMIO(0x9834) 803 #define MICRO_BP3_COUNT_STATUS23 _MMIO(0x9838) 804 #define MICRO_BP_FIRED_ARMED _MMIO(0x983c) 805 806 #define GEN6_GFXPAUSE _MMIO(0xa000) 807 #define GEN6_RPNSWREQ _MMIO(0xa008) 808 #define GEN6_TURBO_DISABLE (1 << 31) 809 #define GEN6_FREQUENCY(x) ((x) << 25) 810 #define HSW_FREQUENCY(x) ((x) << 24) 811 #define GEN9_FREQUENCY(x) ((x) << 23) 812 #define GEN6_OFFSET(x) ((x) << 19) 813 #define GEN6_AGGRESSIVE_TURBO (0 << 15) 814 #define GEN9_SW_REQ_UNSLICE_RATIO_SHIFT 23 815 #define GEN9_IGNORE_SLICE_RATIO (0 << 0) 816 #define GEN12_MEDIA_FREQ_RATIO REG_BIT(13) 817 818 #define GEN6_RC_VIDEO_FREQ _MMIO(0xa00c) 819 #define GEN6_RC_CTL_RC6pp_ENABLE (1 << 16) 820 #define GEN6_RC_CTL_RC6p_ENABLE (1 << 17) 821 #define GEN6_RC_CTL_RC6_ENABLE (1 << 18) 822 #define GEN6_RC_CTL_RC1e_ENABLE (1 << 20) 823 #define GEN6_RC_CTL_RC7_ENABLE (1 << 22) 824 #define VLV_RC_CTL_CTX_RST_PARALLEL (1 << 24) 825 #define GEN7_RC_CTL_TO_MODE (1 << 28) 826 #define GEN6_RC_CTL_EI_MODE(x) ((x) << 27) 827 #define GEN6_RC_CTL_HW_ENABLE (1 << 31) 828 #define GEN6_RP_DOWN_TIMEOUT _MMIO(0xa010) 829 #define GEN6_RP_INTERRUPT_LIMITS _MMIO(0xa014) 830 #define GEN6_RPSTAT1 _MMIO(0xa01c) 831 #define GEN6_CAGF_MASK REG_GENMASK(14, 8) 832 #define HSW_CAGF_MASK REG_GENMASK(13, 7) 833 #define GEN9_CAGF_MASK REG_GENMASK(31, 23) 834 #define GEN6_RP_CONTROL _MMIO(0xa024) 835 #define GEN6_RP_MEDIA_TURBO (1 << 11) 836 #define GEN6_RP_MEDIA_MODE_MASK (3 << 9) 837 #define GEN6_RP_MEDIA_HW_TURBO_MODE (3 << 9) 838 #define GEN6_RP_MEDIA_HW_NORMAL_MODE (2 << 9) 839 #define GEN6_RP_MEDIA_HW_MODE (1 << 9) 840 #define GEN6_RP_MEDIA_SW_MODE (0 << 9) 841 #define GEN6_RP_MEDIA_IS_GFX (1 << 8) 842 #define GEN6_RP_ENABLE (1 << 7) 843 #define GEN6_RP_UP_IDLE_MIN (0x1 << 3) 844 #define GEN6_RP_UP_BUSY_AVG (0x2 << 3) 845 #define GEN6_RP_UP_BUSY_CONT (0x4 << 3) 846 #define GEN6_RP_DOWN_IDLE_AVG (0x2 << 0) 847 #define GEN6_RP_DOWN_IDLE_CONT (0x1 << 0) 848 #define GEN6_RPSWCTL_SHIFT 9 849 #define GEN9_RPSWCTL_ENABLE (0x2 << GEN6_RPSWCTL_SHIFT) 850 #define GEN9_RPSWCTL_DISABLE (0x0 << GEN6_RPSWCTL_SHIFT) 851 #define GEN6_RP_UP_THRESHOLD _MMIO(0xa02c) 852 #define GEN6_RP_DOWN_THRESHOLD _MMIO(0xa030) 853 #define GEN6_RP_CUR_UP_EI _MMIO(0xa050) 854 #define GEN6_RP_EI_MASK 0xffffff 855 #define GEN6_CURICONT_MASK GEN6_RP_EI_MASK 856 #define GEN6_RP_CUR_UP _MMIO(0xa054) 857 #define GEN6_CURBSYTAVG_MASK GEN6_RP_EI_MASK 858 #define GEN6_RP_PREV_UP _MMIO(0xa058) 859 #define GEN6_RP_CUR_DOWN_EI _MMIO(0xa05c) 860 #define GEN6_CURIAVG_MASK GEN6_RP_EI_MASK 861 #define GEN6_RP_CUR_DOWN _MMIO(0xa060) 862 #define GEN6_RP_PREV_DOWN _MMIO(0xa064) 863 #define GEN6_RP_UP_EI _MMIO(0xa068) 864 #define GEN6_RP_DOWN_EI _MMIO(0xa06c) 865 #define GEN6_RP_IDLE_HYSTERSIS _MMIO(0xa070) 866 #define GEN6_RPDEUHWTC _MMIO(0xa080) 867 #define GEN6_RPDEUC _MMIO(0xa084) 868 #define GEN6_RPDEUCSW _MMIO(0xa088) 869 #define GEN6_RC_CONTROL _MMIO(0xa090) 870 #define GEN6_RC_STATE _MMIO(0xa094) 871 #define RC_SW_TARGET_STATE_SHIFT 16 872 #define RC_SW_TARGET_STATE_MASK (7 << RC_SW_TARGET_STATE_SHIFT) 873 #define GEN6_RC1_WAKE_RATE_LIMIT _MMIO(0xa098) 874 #define GEN6_RC6_WAKE_RATE_LIMIT _MMIO(0xa09c) 875 #define GEN6_RC6pp_WAKE_RATE_LIMIT _MMIO(0xa0a0) 876 #define GEN10_MEDIA_WAKE_RATE_LIMIT _MMIO(0xa0a0) 877 #define GEN6_RC_EVALUATION_INTERVAL _MMIO(0xa0a8) 878 #define GEN6_RC_IDLE_HYSTERSIS _MMIO(0xa0ac) 879 #define GEN6_RC_SLEEP _MMIO(0xa0b0) 880 #define GEN6_RCUBMABDTMR _MMIO(0xa0b0) 881 #define GEN6_RC1e_THRESHOLD _MMIO(0xa0b4) 882 #define GEN6_RC6_THRESHOLD _MMIO(0xa0b8) 883 #define GEN6_RC6p_THRESHOLD _MMIO(0xa0bc) 884 #define VLV_RCEDATA _MMIO(0xa0bc) 885 #define GEN6_RC6pp_THRESHOLD _MMIO(0xa0c0) 886 #define GEN9_MEDIA_PG_IDLE_HYSTERESIS _MMIO(0xa0c4) 887 #define GEN9_RENDER_PG_IDLE_HYSTERESIS _MMIO(0xa0c8) 888 889 #define GEN6_PMINTRMSK _MMIO(0xa168) 890 #define GEN8_PMINTR_DISABLE_REDIRECT_TO_GUC (1 << 31) 891 #define ARAT_EXPIRED_INTRMSK (1 << 9) 892 893 #define GEN8_MISC_CTRL0 _MMIO(0xa180) 894 895 #define ECOBUS _MMIO(0xa180) 896 #define FORCEWAKE_MT_ENABLE (1 << 5) 897 898 #define FORCEWAKE_MT _MMIO(0xa188) /* multi-threaded */ 899 #define FORCEWAKE_GT_GEN9 _MMIO(0xa188) 900 #define FORCEWAKE _MMIO(0xa18c) 901 902 #define VLV_SPAREG2H _MMIO(0xa194) 903 904 #define GEN9_PG_ENABLE _MMIO(0xa210) 905 #define GEN9_RENDER_PG_ENABLE REG_BIT(0) 906 #define GEN9_MEDIA_PG_ENABLE REG_BIT(1) 907 #define GEN11_MEDIA_SAMPLER_PG_ENABLE REG_BIT(2) 908 #define VDN_HCP_POWERGATE_ENABLE(n) REG_BIT(3 + 2 * (n)) 909 #define VDN_MFX_POWERGATE_ENABLE(n) REG_BIT(4 + 2 * (n)) 910 911 #define GEN8_PUSHBUS_CONTROL _MMIO(0xa248) 912 #define GEN8_PUSHBUS_ENABLE _MMIO(0xa250) 913 #define GEN8_PUSHBUS_SHIFT _MMIO(0xa25c) 914 915 /* GPM unit config (Gen9+) */ 916 #define CTC_MODE _MMIO(0xa26c) 917 #define CTC_SOURCE_PARAMETER_MASK 1 918 #define CTC_SOURCE_CRYSTAL_CLOCK 0 919 #define CTC_SOURCE_DIVIDE_LOGIC 1 920 #define CTC_SHIFT_PARAMETER_SHIFT 1 921 #define CTC_SHIFT_PARAMETER_MASK (0x3 << CTC_SHIFT_PARAMETER_SHIFT) 922 923 /* GPM MSG_IDLE */ 924 #define MSG_IDLE_CS _MMIO(0x8000) 925 #define MSG_IDLE_VCS0 _MMIO(0x8004) 926 #define MSG_IDLE_VCS1 _MMIO(0x8008) 927 #define MSG_IDLE_BCS _MMIO(0x800C) 928 #define MSG_IDLE_VECS0 _MMIO(0x8010) 929 #define MSG_IDLE_VCS2 _MMIO(0x80C0) 930 #define MSG_IDLE_VCS3 _MMIO(0x80C4) 931 #define MSG_IDLE_VCS4 _MMIO(0x80C8) 932 #define MSG_IDLE_VCS5 _MMIO(0x80CC) 933 #define MSG_IDLE_VCS6 _MMIO(0x80D0) 934 #define MSG_IDLE_VCS7 _MMIO(0x80D4) 935 #define MSG_IDLE_VECS1 _MMIO(0x80D8) 936 #define MSG_IDLE_VECS2 _MMIO(0x80DC) 937 #define MSG_IDLE_VECS3 _MMIO(0x80E0) 938 #define MSG_IDLE_FW_MASK REG_GENMASK(13, 9) 939 #define MSG_IDLE_FW_SHIFT 9 940 941 #define RC_PSMI_CTRL_GSCCS _MMIO(0x11a050) 942 #define IDLE_MSG_DISABLE REG_BIT(0) 943 #define PWRCTX_MAXCNT_GSCCS _MMIO(0x11a054) 944 945 #define FORCEWAKE_MEDIA_GEN9 _MMIO(0xa270) 946 #define FORCEWAKE_RENDER_GEN9 _MMIO(0xa278) 947 948 #define VLV_PWRDWNUPCTL _MMIO(0xa294) 949 950 #define GEN9_PWRGT_DOMAIN_STATUS _MMIO(0xa2a0) 951 #define GEN9_PWRGT_MEDIA_STATUS_MASK (1 << 0) 952 #define GEN9_PWRGT_RENDER_STATUS_MASK (1 << 1) 953 954 #define MISC_STATUS0 _MMIO(0xa500) 955 #define MISC_STATUS1 _MMIO(0xa504) 956 957 #define FORCEWAKE_MEDIA_VDBOX_GEN11(n) _MMIO(0xa540 + (n) * 4) 958 #define FORCEWAKE_MEDIA_VEBOX_GEN11(n) _MMIO(0xa560 + (n) * 4) 959 960 #define FORCEWAKE_REQ_GSC _MMIO(0xa618) 961 962 #define CHV_POWER_SS0_SIG1 _MMIO(0xa720) 963 #define CHV_POWER_SS0_SIG2 _MMIO(0xa724) 964 #define CHV_POWER_SS1_SIG1 _MMIO(0xa728) 965 #define CHV_SS_PG_ENABLE (1 << 1) 966 #define CHV_EU08_PG_ENABLE (1 << 9) 967 #define CHV_EU19_PG_ENABLE (1 << 17) 968 #define CHV_EU210_PG_ENABLE (1 << 25) 969 #define CHV_POWER_SS1_SIG2 _MMIO(0xa72c) 970 #define CHV_EU311_PG_ENABLE (1 << 1) 971 972 #define GEN7_SARCHKMD _MMIO(0xb000) 973 #define GEN7_DISABLE_DEMAND_PREFETCH (1 << 31) 974 #define GEN7_DISABLE_SAMPLER_PREFETCH (1 << 30) 975 976 #define GEN8_GARBCNTL _MMIO(0xb004) 977 #define GEN11_ARBITRATION_PRIO_ORDER_MASK REG_GENMASK(27, 22) 978 #define GEN12_BUS_HASH_CTL_BIT_EXC REG_BIT(7) 979 #define GEN9_GAPS_TSV_CREDIT_DISABLE REG_BIT(7) 980 #define GEN11_HASH_CTRL_EXCL_MASK REG_GENMASK(6, 0) 981 #define GEN11_HASH_CTRL_EXCL_BIT0 REG_FIELD_PREP(GEN11_HASH_CTRL_EXCL_MASK, 0x1) 982 983 #define GEN9_SCRATCH_LNCF1 _MMIO(0xb008) 984 #define GEN9_LNCF_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(0) 985 986 #define GEN7_L3SQCREG1 _MMIO(0xb010) 987 #define VLV_B0_WA_L3SQCREG1_VALUE 0x00D30000 988 989 #define GEN7_L3CNTLREG1 _MMIO(0xb01c) 990 #define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C47FF8C 991 #define GEN7_L3AGDIS (1 << 19) 992 993 #define XEHPC_LNCFMISCCFGREG0 MCR_REG(0xb01c) 994 #define XEHPC_HOSTCACHEEN REG_BIT(1) 995 #define XEHPC_OVRLSCCC REG_BIT(0) 996 997 #define GEN7_L3CNTLREG2 _MMIO(0xb020) 998 999 /* MOCS (Memory Object Control State) registers */ 1000 #define GEN9_LNCFCMOCS(i) _MMIO(0xb020 + (i) * 4) /* L3 Cache Control */ 1001 #define XEHP_LNCFCMOCS(i) MCR_REG(0xb020 + (i) * 4) 1002 #define LNCFCMOCS_REG_COUNT 32 1003 1004 #define GEN7_L3CNTLREG3 _MMIO(0xb024) 1005 1006 #define GEN7_L3_CHICKEN_MODE_REGISTER _MMIO(0xb030) 1007 #define GEN7_WA_L3_CHICKEN_MODE 0x20000000 1008 1009 #define GEN7_L3SQCREG4 _MMIO(0xb034) 1010 #define L3SQ_URB_READ_CAM_MATCH_DISABLE (1 << 27) 1011 1012 #define HSW_SCRATCH1 _MMIO(0xb038) 1013 #define HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE (1 << 27) 1014 1015 #define GEN7_L3LOG(slice, i) _MMIO(0xb070 + (slice) * 0x200 + (i) * 4) 1016 #define GEN7_L3LOG_SIZE 0x80 1017 1018 #define XEHP_L3NODEARBCFG MCR_REG(0xb0b4) 1019 #define XEHP_LNESPARE REG_BIT(19) 1020 1021 #define GEN8_L3SQCREG1 MCR_REG(0xb100) 1022 /* 1023 * Note that on CHV the following has an off-by-one error wrt. to BSpec. 1024 * Using the formula in BSpec leads to a hang, while the formula here works 1025 * fine and matches the formulas for all other platforms. A BSpec change 1026 * request has been filed to clarify this. 1027 */ 1028 #define L3_GENERAL_PRIO_CREDITS(x) (((x) >> 1) << 19) 1029 #define L3_HIGH_PRIO_CREDITS(x) (((x) >> 1) << 14) 1030 #define L3_PRIO_CREDITS_MASK ((0x1f << 19) | (0x1f << 14)) 1031 1032 #define GEN8_L3SQCREG4 MCR_REG(0xb118) 1033 #define GEN11_LQSC_CLEAN_EVICT_DISABLE (1 << 6) 1034 #define GEN8_LQSC_RO_PERF_DIS (1 << 27) 1035 #define GEN8_LQSC_FLUSH_COHERENT_LINES (1 << 21) 1036 #define GEN8_LQSQ_NONIA_COHERENT_ATOMICS_ENABLE REG_BIT(22) 1037 1038 #define GEN9_SCRATCH1 MCR_REG(0xb11c) 1039 #define EVICTION_PERF_FIX_ENABLE REG_BIT(8) 1040 1041 #define BDW_SCRATCH1 MCR_REG(0xb11c) 1042 #define GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE (1 << 2) 1043 1044 #define GEN11_SCRATCH2 MCR_REG(0xb140) 1045 #define GEN11_COHERENT_PARTIAL_WRITE_MERGE_ENABLE (1 << 19) 1046 1047 #define XEHP_L3SQCREG5 MCR_REG(0xb158) 1048 #define L3_PWM_TIMER_INIT_VAL_MASK REG_GENMASK(9, 0) 1049 1050 #define MLTICTXCTL MCR_REG(0xb170) 1051 #define TDONRENDER REG_BIT(2) 1052 1053 #define XEHP_L3SCQREG7 MCR_REG(0xb188) 1054 #define BLEND_FILL_CACHING_OPT_DIS REG_BIT(3) 1055 1056 #define XEHPC_L3SCRUB MCR_REG(0xb18c) 1057 #define SCRUB_CL_DWNGRADE_SHARED REG_BIT(12) 1058 #define SCRUB_RATE_PER_BANK_MASK REG_GENMASK(2, 0) 1059 #define SCRUB_RATE_4B_PER_CLK REG_FIELD_PREP(SCRUB_RATE_PER_BANK_MASK, 0x6) 1060 1061 #define L3SQCREG1_CCS0 MCR_REG(0xb200) 1062 #define FLUSHALLNONCOH REG_BIT(5) 1063 1064 #define GEN11_GLBLINVL _MMIO(0xb404) 1065 #define GEN11_BANK_HASH_ADDR_EXCL_MASK (0x7f << 5) 1066 #define GEN11_BANK_HASH_ADDR_EXCL_BIT0 (1 << 5) 1067 1068 #define GEN11_LSN_UNSLCVC _MMIO(0xb43c) 1069 #define GEN11_LSN_UNSLCVC_GAFS_HALF_CL2_MAXALLOC (1 << 9) 1070 #define GEN11_LSN_UNSLCVC_GAFS_HALF_SF_MAXALLOC (1 << 7) 1071 1072 #define GUCPMTIMESTAMP _MMIO(0xc3e8) 1073 1074 #define __GEN9_RCS0_MOCS0 0xc800 1075 #define GEN9_GFX_MOCS(i) _MMIO(__GEN9_RCS0_MOCS0 + (i) * 4) 1076 #define __GEN9_VCS0_MOCS0 0xc900 1077 #define GEN9_MFX0_MOCS(i) _MMIO(__GEN9_VCS0_MOCS0 + (i) * 4) 1078 #define __GEN9_VCS1_MOCS0 0xca00 1079 #define GEN9_MFX1_MOCS(i) _MMIO(__GEN9_VCS1_MOCS0 + (i) * 4) 1080 #define __GEN9_VECS0_MOCS0 0xcb00 1081 #define GEN9_VEBOX_MOCS(i) _MMIO(__GEN9_VECS0_MOCS0 + (i) * 4) 1082 #define __GEN9_BCS0_MOCS0 0xcc00 1083 #define GEN9_BLT_MOCS(i) _MMIO(__GEN9_BCS0_MOCS0 + (i) * 4) 1084 1085 #define GEN12_FAULT_TLB_DATA0 _MMIO(0xceb8) 1086 #define XEHP_FAULT_TLB_DATA0 MCR_REG(0xceb8) 1087 #define GEN12_FAULT_TLB_DATA1 _MMIO(0xcebc) 1088 #define XEHP_FAULT_TLB_DATA1 MCR_REG(0xcebc) 1089 #define FAULT_VA_HIGH_BITS (0xf << 0) 1090 #define FAULT_GTT_SEL (1 << 4) 1091 1092 #define GEN12_RING_FAULT_REG _MMIO(0xcec4) 1093 #define XEHP_RING_FAULT_REG MCR_REG(0xcec4) 1094 #define GEN8_RING_FAULT_ENGINE_ID(x) (((x) >> 12) & 0x7) 1095 #define RING_FAULT_GTTSEL_MASK (1 << 11) 1096 #define RING_FAULT_SRCID(x) (((x) >> 3) & 0xff) 1097 #define RING_FAULT_FAULT_TYPE(x) (((x) >> 1) & 0x3) 1098 #define RING_FAULT_VALID (1 << 0) 1099 1100 #define GEN12_GFX_TLB_INV_CR _MMIO(0xced8) 1101 #define XEHP_GFX_TLB_INV_CR MCR_REG(0xced8) 1102 #define GEN12_VD_TLB_INV_CR _MMIO(0xcedc) 1103 #define XEHP_VD_TLB_INV_CR MCR_REG(0xcedc) 1104 #define GEN12_VE_TLB_INV_CR _MMIO(0xcee0) 1105 #define XEHP_VE_TLB_INV_CR MCR_REG(0xcee0) 1106 #define GEN12_BLT_TLB_INV_CR _MMIO(0xcee4) 1107 #define XEHP_BLT_TLB_INV_CR MCR_REG(0xcee4) 1108 #define GEN12_COMPCTX_TLB_INV_CR _MMIO(0xcf04) 1109 #define XEHP_COMPCTX_TLB_INV_CR MCR_REG(0xcf04) 1110 #define XELPMP_GSC_TLB_INV_CR _MMIO(0xcf04) /* media GT only */ 1111 1112 #define XEHP_MERT_MOD_CTRL MCR_REG(0xcf28) 1113 #define RENDER_MOD_CTRL MCR_REG(0xcf2c) 1114 #define COMP_MOD_CTRL MCR_REG(0xcf30) 1115 #define XELPMP_GSC_MOD_CTRL _MMIO(0xcf30) /* media GT only */ 1116 #define XEHP_VDBX_MOD_CTRL MCR_REG(0xcf34) 1117 #define XELPMP_VDBX_MOD_CTRL _MMIO(0xcf34) 1118 #define XEHP_VEBX_MOD_CTRL MCR_REG(0xcf38) 1119 #define XELPMP_VEBX_MOD_CTRL _MMIO(0xcf38) 1120 #define FORCE_MISS_FTLB REG_BIT(3) 1121 1122 #define XEHP_GAMSTLB_CTRL MCR_REG(0xcf4c) 1123 #define CONTROL_BLOCK_CLKGATE_DIS REG_BIT(12) 1124 #define EGRESS_BLOCK_CLKGATE_DIS REG_BIT(11) 1125 #define TAG_BLOCK_CLKGATE_DIS REG_BIT(7) 1126 1127 #define XEHP_GAMCNTRL_CTRL MCR_REG(0xcf54) 1128 #define INVALIDATION_BROADCAST_MODE_DIS REG_BIT(12) 1129 #define GLOBAL_INVALIDATION_MODE REG_BIT(2) 1130 1131 #define GEN12_GAM_DONE _MMIO(0xcf68) 1132 1133 #define GEN7_HALF_SLICE_CHICKEN1 _MMIO(0xe100) /* IVB GT1 + VLV */ 1134 #define GEN8_HALF_SLICE_CHICKEN1 MCR_REG(0xe100) 1135 #define GEN7_MAX_PS_THREAD_DEP (8 << 12) 1136 #define GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE (1 << 10) 1137 #define GEN7_SBE_SS_CACHE_DISPATCH_PORT_SHARING_DISABLE (1 << 4) 1138 #define GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE (1 << 3) 1139 1140 #define GEN7_SAMPLER_INSTDONE _MMIO(0xe160) 1141 #define GEN8_SAMPLER_INSTDONE MCR_REG(0xe160) 1142 #define GEN7_ROW_INSTDONE _MMIO(0xe164) 1143 #define GEN8_ROW_INSTDONE MCR_REG(0xe164) 1144 1145 #define HALF_SLICE_CHICKEN2 MCR_REG(0xe180) 1146 #define GEN8_ST_PO_DISABLE (1 << 13) 1147 1148 #define HSW_HALF_SLICE_CHICKEN3 _MMIO(0xe184) 1149 #define GEN8_HALF_SLICE_CHICKEN3 MCR_REG(0xe184) 1150 #define HSW_SAMPLE_C_PERFORMANCE (1 << 9) 1151 #define GEN8_CENTROID_PIXEL_OPT_DIS (1 << 8) 1152 #define GEN9_DISABLE_OCL_OOB_SUPPRESS_LOGIC (1 << 5) 1153 #define GEN8_SAMPLER_POWER_BYPASS_DIS (1 << 1) 1154 1155 #define GEN9_HALF_SLICE_CHICKEN5 MCR_REG(0xe188) 1156 #define GEN9_DG_MIRROR_FIX_ENABLE (1 << 5) 1157 #define GEN9_CCS_TLB_PREFETCH_ENABLE (1 << 3) 1158 1159 #define GEN10_SAMPLER_MODE MCR_REG(0xe18c) 1160 #define ENABLE_SMALLPL REG_BIT(15) 1161 #define SC_DISABLE_POWER_OPTIMIZATION_EBB REG_BIT(9) 1162 #define GEN11_SAMPLER_ENABLE_HEADLESS_MSG REG_BIT(5) 1163 #define MTL_DISABLE_SAMPLER_SC_OOO REG_BIT(3) 1164 #define GEN11_INDIRECT_STATE_BASE_ADDR_OVERRIDE REG_BIT(0) 1165 1166 #define GEN9_HALF_SLICE_CHICKEN7 MCR_REG(0xe194) 1167 #define DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA REG_BIT(15) 1168 #define GEN9_SAMPLER_HASH_COMPRESSED_READ_ADDR REG_BIT(8) 1169 #define GEN9_ENABLE_YV12_BUGFIX REG_BIT(4) 1170 #define GEN9_ENABLE_GPGPU_PREEMPTION REG_BIT(2) 1171 1172 #define GEN10_CACHE_MODE_SS MCR_REG(0xe420) 1173 #define ENABLE_EU_COUNT_FOR_TDL_FLUSH REG_BIT(10) 1174 #define DISABLE_ECC REG_BIT(5) 1175 #define FLOAT_BLEND_OPTIMIZATION_ENABLE REG_BIT(4) 1176 /* 1177 * We have both ENABLE and DISABLE defines below using the same bit because the 1178 * meaning depends on the target platform. There are no platform prefix for them 1179 * because different steppings of DG2 pick one or the other semantics. 1180 */ 1181 #define ENABLE_PREFETCH_INTO_IC REG_BIT(3) 1182 #define DISABLE_PREFETCH_INTO_IC REG_BIT(3) 1183 1184 #define EU_PERF_CNTL0 PERF_REG(0xe458) 1185 #define EU_PERF_CNTL4 PERF_REG(0xe45c) 1186 1187 #define GEN9_ROW_CHICKEN4 MCR_REG(0xe48c) 1188 #define GEN12_DISABLE_GRF_CLEAR REG_BIT(13) 1189 #define XEHP_DIS_BBL_SYSPIPE REG_BIT(11) 1190 #define GEN12_DISABLE_TDL_PUSH REG_BIT(9) 1191 #define GEN11_DIS_PICK_2ND_EU REG_BIT(7) 1192 #define GEN12_DISABLE_HDR_PAST_PAYLOAD_HOLD_FIX REG_BIT(4) 1193 #define THREAD_EX_ARB_MODE REG_GENMASK(3, 2) 1194 #define THREAD_EX_ARB_MODE_RR_AFTER_DEP REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2) 1195 1196 #define HSW_ROW_CHICKEN3 _MMIO(0xe49c) 1197 #define GEN9_ROW_CHICKEN3 MCR_REG(0xe49c) 1198 #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6) 1199 #define MTL_DISABLE_FIX_FOR_EOT_FLUSH REG_BIT(9) 1200 1201 #define GEN8_ROW_CHICKEN MCR_REG(0xe4f0) 1202 #define FLOW_CONTROL_ENABLE REG_BIT(15) 1203 #define UGM_BACKUP_MODE REG_BIT(13) 1204 #define MDQ_ARBITRATION_MODE REG_BIT(12) 1205 #define SYSTOLIC_DOP_CLOCK_GATING_DIS REG_BIT(10) 1206 #define PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE REG_BIT(8) 1207 #define STALL_DOP_GATING_DISABLE REG_BIT(5) 1208 #define THROTTLE_12_5 REG_GENMASK(4, 2) 1209 #define DISABLE_EARLY_EOT REG_BIT(1) 1210 1211 #define GEN7_ROW_CHICKEN2 _MMIO(0xe4f4) 1212 1213 #define GEN8_ROW_CHICKEN2 MCR_REG(0xe4f4) 1214 #define GEN12_DISABLE_READ_SUPPRESSION REG_BIT(15) 1215 #define GEN12_DISABLE_EARLY_READ REG_BIT(14) 1216 #define GEN12_ENABLE_LARGE_GRF_MODE REG_BIT(12) 1217 #define GEN12_PUSH_CONST_DEREF_HOLD_DIS REG_BIT(8) 1218 #define XELPG_DISABLE_TDL_SVHS_GATING REG_BIT(1) 1219 #define GEN12_DISABLE_DOP_GATING REG_BIT(0) 1220 1221 #define RT_CTRL MCR_REG(0xe530) 1222 #define DIS_NULL_QUERY REG_BIT(10) 1223 #define STACKID_CTRL REG_GENMASK(6, 5) 1224 #define STACKID_CTRL_512 REG_FIELD_PREP(STACKID_CTRL, 0x2) 1225 1226 #define EU_PERF_CNTL1 PERF_REG(0xe558) 1227 #define EU_PERF_CNTL5 PERF_REG(0xe55c) 1228 1229 #define XEHP_HDC_CHICKEN0 MCR_REG(0xe5f0) 1230 #define LSC_L1_FLUSH_CTL_3D_DATAPORT_FLUSH_EVENTS_MASK REG_GENMASK(13, 11) 1231 #define DIS_ATOMIC_CHAINING_TYPED_WRITES REG_BIT(3) 1232 1233 #define ICL_HDC_MODE MCR_REG(0xe5f4) 1234 1235 #define EU_PERF_CNTL2 PERF_REG(0xe658) 1236 #define EU_PERF_CNTL6 PERF_REG(0xe65c) 1237 #define EU_PERF_CNTL3 PERF_REG(0xe758) 1238 1239 #define LSC_CHICKEN_BIT_0 MCR_REG(0xe7c8) 1240 #define DISABLE_D8_D16_COASLESCE REG_BIT(30) 1241 #define FORCE_1_SUB_MESSAGE_PER_FRAGMENT REG_BIT(15) 1242 #define LSC_CHICKEN_BIT_0_UDW MCR_REG(0xe7c8 + 4) 1243 #define DIS_CHAIN_2XSIMD8 REG_BIT(55 - 32) 1244 #define FORCE_SLM_FENCE_SCOPE_TO_TILE REG_BIT(42 - 32) 1245 #define FORCE_UGM_FENCE_SCOPE_TO_TILE REG_BIT(41 - 32) 1246 #define MAXREQS_PER_BANK REG_GENMASK(39 - 32, 37 - 32) 1247 #define DISABLE_128B_EVICTION_COMMAND_UDW REG_BIT(36 - 32) 1248 1249 #define SARB_CHICKEN1 MCR_REG(0xe90c) 1250 #define COMP_CKN_IN REG_GENMASK(30, 29) 1251 1252 #define GEN7_ROW_CHICKEN2_GT2 _MMIO(0xf4f4) 1253 #define DOP_CLOCK_GATING_DISABLE (1 << 0) 1254 #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8) 1255 #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1) 1256 1257 #define __GEN11_VCS2_MOCS0 0x10000 1258 #define GEN11_MFX2_MOCS(i) _MMIO(__GEN11_VCS2_MOCS0 + (i) * 4) 1259 1260 #define CRSTANDVID _MMIO(0x11100) 1261 #define PXVFREQ(fstart) _MMIO(0x11110 + (fstart) * 4) /* P[0-15]VIDFREQ (0x1114c) (Ironlake) */ 1262 #define PXVFREQ_PX_MASK 0x7f000000 1263 #define PXVFREQ_PX_SHIFT 24 1264 #define VIDFREQ_BASE _MMIO(0x11110) 1265 #define VIDFREQ1 _MMIO(0x11110) /* VIDFREQ1-4 (0x1111c) (Cantiga) */ 1266 #define VIDFREQ2 _MMIO(0x11114) 1267 #define VIDFREQ3 _MMIO(0x11118) 1268 #define VIDFREQ4 _MMIO(0x1111c) 1269 #define VIDFREQ_P0_MASK 0x1f000000 1270 #define VIDFREQ_P0_SHIFT 24 1271 #define VIDFREQ_P0_CSCLK_MASK 0x00f00000 1272 #define VIDFREQ_P0_CSCLK_SHIFT 20 1273 #define VIDFREQ_P0_CRCLK_MASK 0x000f0000 1274 #define VIDFREQ_P0_CRCLK_SHIFT 16 1275 #define VIDFREQ_P1_MASK 0x00001f00 1276 #define VIDFREQ_P1_SHIFT 8 1277 #define VIDFREQ_P1_CSCLK_MASK 0x000000f0 1278 #define VIDFREQ_P1_CSCLK_SHIFT 4 1279 #define VIDFREQ_P1_CRCLK_MASK 0x0000000f 1280 #define INTTOEXT_BASE _MMIO(0x11120) /* INTTOEXT1-8 (0x1113c) */ 1281 #define INTTOEXT_MAP3_SHIFT 24 1282 #define INTTOEXT_MAP3_MASK (0x1f << INTTOEXT_MAP3_SHIFT) 1283 #define INTTOEXT_MAP2_SHIFT 16 1284 #define INTTOEXT_MAP2_MASK (0x1f << INTTOEXT_MAP2_SHIFT) 1285 #define INTTOEXT_MAP1_SHIFT 8 1286 #define INTTOEXT_MAP1_MASK (0x1f << INTTOEXT_MAP1_SHIFT) 1287 #define INTTOEXT_MAP0_SHIFT 0 1288 #define INTTOEXT_MAP0_MASK (0x1f << INTTOEXT_MAP0_SHIFT) 1289 #define MEMSWCTL _MMIO(0x11170) /* Ironlake only */ 1290 #define MEMCTL_CMD_MASK 0xe000 1291 #define MEMCTL_CMD_SHIFT 13 1292 #define MEMCTL_CMD_RCLK_OFF 0 1293 #define MEMCTL_CMD_RCLK_ON 1 1294 #define MEMCTL_CMD_CHFREQ 2 1295 #define MEMCTL_CMD_CHVID 3 1296 #define MEMCTL_CMD_VMMOFF 4 1297 #define MEMCTL_CMD_VMMON 5 1298 #define MEMCTL_CMD_STS (1 << 12) /* write 1 triggers command, clears 1299 when command complete */ 1300 #define MEMCTL_FREQ_MASK 0x0f00 /* jitter, from 0-15 */ 1301 #define MEMCTL_FREQ_SHIFT 8 1302 #define MEMCTL_SFCAVM (1 << 7) 1303 #define MEMCTL_TGT_VID_MASK 0x007f 1304 #define MEMIHYST _MMIO(0x1117c) 1305 #define MEMINTREN _MMIO(0x11180) /* 16 bits */ 1306 #define MEMINT_RSEXIT_EN (1 << 8) 1307 #define MEMINT_CX_SUPR_EN (1 << 7) 1308 #define MEMINT_CONT_BUSY_EN (1 << 6) 1309 #define MEMINT_AVG_BUSY_EN (1 << 5) 1310 #define MEMINT_EVAL_CHG_EN (1 << 4) 1311 #define MEMINT_MON_IDLE_EN (1 << 3) 1312 #define MEMINT_UP_EVAL_EN (1 << 2) 1313 #define MEMINT_DOWN_EVAL_EN (1 << 1) 1314 #define MEMINT_SW_CMD_EN (1 << 0) 1315 #define MEMINTRSTR _MMIO(0x11182) /* 16 bits */ 1316 #define MEM_RSEXIT_MASK 0xc000 1317 #define MEM_RSEXIT_SHIFT 14 1318 #define MEM_CONT_BUSY_MASK 0x3000 1319 #define MEM_CONT_BUSY_SHIFT 12 1320 #define MEM_AVG_BUSY_MASK 0x0c00 1321 #define MEM_AVG_BUSY_SHIFT 10 1322 #define MEM_EVAL_CHG_MASK 0x0300 1323 #define MEM_EVAL_BUSY_SHIFT 8 1324 #define MEM_MON_IDLE_MASK 0x00c0 1325 #define MEM_MON_IDLE_SHIFT 6 1326 #define MEM_UP_EVAL_MASK 0x0030 1327 #define MEM_UP_EVAL_SHIFT 4 1328 #define MEM_DOWN_EVAL_MASK 0x000c 1329 #define MEM_DOWN_EVAL_SHIFT 2 1330 #define MEM_SW_CMD_MASK 0x0003 1331 #define MEM_INT_STEER_GFX 0 1332 #define MEM_INT_STEER_CMR 1 1333 #define MEM_INT_STEER_SMI 2 1334 #define MEM_INT_STEER_SCI 3 1335 #define MEMINTRSTS _MMIO(0x11184) 1336 #define MEMINT_RSEXIT (1 << 7) 1337 #define MEMINT_CONT_BUSY (1 << 6) 1338 #define MEMINT_AVG_BUSY (1 << 5) 1339 #define MEMINT_EVAL_CHG (1 << 4) 1340 #define MEMINT_MON_IDLE (1 << 3) 1341 #define MEMINT_UP_EVAL (1 << 2) 1342 #define MEMINT_DOWN_EVAL (1 << 1) 1343 #define MEMINT_SW_CMD (1 << 0) 1344 #define MEMMODECTL _MMIO(0x11190) 1345 #define MEMMODE_BOOST_EN (1 << 31) 1346 #define MEMMODE_BOOST_FREQ_MASK 0x0f000000 /* jitter for boost, 0-15 */ 1347 #define MEMMODE_BOOST_FREQ_SHIFT 24 1348 #define MEMMODE_IDLE_MODE_MASK 0x00030000 1349 #define MEMMODE_IDLE_MODE_SHIFT 16 1350 #define MEMMODE_IDLE_MODE_EVAL 0 1351 #define MEMMODE_IDLE_MODE_CONT 1 1352 #define MEMMODE_HWIDLE_EN (1 << 15) 1353 #define MEMMODE_SWMODE_EN (1 << 14) 1354 #define MEMMODE_RCLK_GATE (1 << 13) 1355 #define MEMMODE_HW_UPDATE (1 << 12) 1356 #define MEMMODE_FSTART_MASK 0x00000f00 /* starting jitter, 0-15 */ 1357 #define MEMMODE_FSTART_SHIFT 8 1358 #define MEMMODE_FMAX_MASK 0x000000f0 /* max jitter, 0-15 */ 1359 #define MEMMODE_FMAX_SHIFT 4 1360 #define MEMMODE_FMIN_MASK 0x0000000f /* min jitter, 0-15 */ 1361 #define RCBMAXAVG _MMIO(0x1119c) 1362 #define MEMSWCTL2 _MMIO(0x1119e) /* Cantiga only */ 1363 #define SWMEMCMD_RENDER_OFF (0 << 13) 1364 #define SWMEMCMD_RENDER_ON (1 << 13) 1365 #define SWMEMCMD_SWFREQ (2 << 13) 1366 #define SWMEMCMD_TARVID (3 << 13) 1367 #define SWMEMCMD_VRM_OFF (4 << 13) 1368 #define SWMEMCMD_VRM_ON (5 << 13) 1369 #define CMDSTS (1 << 12) 1370 #define SFCAVM (1 << 11) 1371 #define SWFREQ_MASK 0x0380 /* P0-7 */ 1372 #define SWFREQ_SHIFT 7 1373 #define TARVID_MASK 0x001f 1374 #define MEMSTAT_CTG _MMIO(0x111a0) 1375 #define RCBMINAVG _MMIO(0x111a0) 1376 #define RCUPEI _MMIO(0x111b0) 1377 #define RCDNEI _MMIO(0x111b4) 1378 #define RSTDBYCTL _MMIO(0x111b8) 1379 #define RS1EN (1 << 31) 1380 #define RS2EN (1 << 30) 1381 #define RS3EN (1 << 29) 1382 #define D3RS3EN (1 << 28) /* Display D3 imlies RS3 */ 1383 #define SWPROMORSX (1 << 27) /* RSx promotion timers ignored */ 1384 #define RCWAKERW (1 << 26) /* Resetwarn from PCH causes wakeup */ 1385 #define DPRSLPVREN (1 << 25) /* Fast voltage ramp enable */ 1386 #define GFXTGHYST (1 << 24) /* Hysteresis to allow trunk gating */ 1387 #define RCX_SW_EXIT (1 << 23) /* Leave RSx and prevent re-entry */ 1388 #define RSX_STATUS_MASK (7 << 20) 1389 #define RSX_STATUS_ON (0 << 20) 1390 #define RSX_STATUS_RC1 (1 << 20) 1391 #define RSX_STATUS_RC1E (2 << 20) 1392 #define RSX_STATUS_RS1 (3 << 20) 1393 #define RSX_STATUS_RS2 (4 << 20) /* aka rc6 */ 1394 #define RSX_STATUS_RSVD (5 << 20) /* deep rc6 unsupported on ilk */ 1395 #define RSX_STATUS_RS3 (6 << 20) /* rs3 unsupported on ilk */ 1396 #define RSX_STATUS_RSVD2 (7 << 20) 1397 #define UWRCRSXE (1 << 19) /* wake counter limit prevents rsx */ 1398 #define RSCRP (1 << 18) /* rs requests control on rs1/2 reqs */ 1399 #define JRSC (1 << 17) /* rsx coupled to cpu c-state */ 1400 #define RS2INC0 (1 << 16) /* allow rs2 in cpu c0 */ 1401 #define RS1CONTSAV_MASK (3 << 14) 1402 #define RS1CONTSAV_NO_RS1 (0 << 14) /* rs1 doesn't save/restore context */ 1403 #define RS1CONTSAV_RSVD (1 << 14) 1404 #define RS1CONTSAV_SAVE_RS1 (2 << 14) /* rs1 saves context */ 1405 #define RS1CONTSAV_FULL_RS1 (3 << 14) /* rs1 saves and restores context */ 1406 #define NORMSLEXLAT_MASK (3 << 12) 1407 #define SLOW_RS123 (0 << 12) 1408 #define SLOW_RS23 (1 << 12) 1409 #define SLOW_RS3 (2 << 12) 1410 #define NORMAL_RS123 (3 << 12) 1411 #define RCMODE_TIMEOUT (1 << 11) /* 0 is eval interval method */ 1412 #define IMPROMOEN (1 << 10) /* promo is immediate or delayed until next idle interval (only for timeout method above) */ 1413 #define RCENTSYNC (1 << 9) /* rs coupled to cpu c-state (3/6/7) */ 1414 #define STATELOCK (1 << 7) /* locked to rs_cstate if 0 */ 1415 #define RS_CSTATE_MASK (3 << 4) 1416 #define RS_CSTATE_C367_RS1 (0 << 4) 1417 #define RS_CSTATE_C36_RS1_C7_RS2 (1 << 4) 1418 #define RS_CSTATE_RSVD (2 << 4) 1419 #define RS_CSTATE_C367_RS2 (3 << 4) 1420 #define REDSAVES (1 << 3) /* no context save if was idle during rs0 */ 1421 #define REDRESTORES (1 << 2) /* no restore if was idle during rs0 */ 1422 #define VIDCTL _MMIO(0x111c0) 1423 #define VIDSTS _MMIO(0x111c8) 1424 #define VIDSTART _MMIO(0x111cc) /* 8 bits */ 1425 #define MEMSTAT_ILK _MMIO(0x111f8) 1426 #define MEMSTAT_VID_MASK 0x7f00 1427 #define MEMSTAT_VID_SHIFT 8 1428 #define MEMSTAT_PSTATE_MASK REG_GENMASK(7, 3) 1429 #define MEMSTAT_MON_ACTV (1 << 2) 1430 #define MEMSTAT_SRC_CTL_MASK 0x0003 1431 #define MEMSTAT_SRC_CTL_CORE 0 1432 #define MEMSTAT_SRC_CTL_TRB 1 1433 #define MEMSTAT_SRC_CTL_THM 2 1434 #define MEMSTAT_SRC_CTL_STDBY 3 1435 #define PMMISC _MMIO(0x11214) 1436 #define MCPPCE_EN (1 << 0) /* enable PM_MSG from PCH->MPC */ 1437 #define SDEW _MMIO(0x1124c) 1438 #define CSIEW0 _MMIO(0x11250) 1439 #define CSIEW1 _MMIO(0x11254) 1440 #define CSIEW2 _MMIO(0x11258) 1441 #define PEW(i) _MMIO(0x1125c + (i) * 4) /* 5 registers */ 1442 #define DEW(i) _MMIO(0x11270 + (i) * 4) /* 3 registers */ 1443 #define MCHAFE _MMIO(0x112c0) 1444 #define CSIEC _MMIO(0x112e0) 1445 #define DMIEC _MMIO(0x112e4) 1446 #define DDREC _MMIO(0x112e8) 1447 #define PEG0EC _MMIO(0x112ec) 1448 #define PEG1EC _MMIO(0x112f0) 1449 #define GFXEC _MMIO(0x112f4) 1450 #define INTTOEXT_BASE_ILK _MMIO(0x11300) 1451 #define RPPREVBSYTUPAVG _MMIO(0x113b8) 1452 #define RCPREVBSYTUPAVG _MMIO(0x113b8) 1453 #define RCPREVBSYTDNAVG _MMIO(0x113bc) 1454 #define RPPREVBSYTDNAVG _MMIO(0x113bc) 1455 #define ECR _MMIO(0x11600) 1456 #define ECR_GPFE (1 << 31) 1457 #define ECR_IMONE (1 << 30) 1458 #define ECR_CAP_MASK 0x0000001f /* Event range, 0-31 */ 1459 #define OGW0 _MMIO(0x11608) 1460 #define OGW1 _MMIO(0x1160c) 1461 #define EG0 _MMIO(0x11610) 1462 #define EG1 _MMIO(0x11614) 1463 #define EG2 _MMIO(0x11618) 1464 #define EG3 _MMIO(0x1161c) 1465 #define EG4 _MMIO(0x11620) 1466 #define EG5 _MMIO(0x11624) 1467 #define EG6 _MMIO(0x11628) 1468 #define EG7 _MMIO(0x1162c) 1469 #define PXW(i) _MMIO(0x11664 + (i) * 4) /* 4 registers */ 1470 #define PXWL(i) _MMIO(0x11680 + (i) * 8) /* 8 registers */ 1471 #define LCFUSE02 _MMIO(0x116c0) 1472 #define LCFUSE_HIV_MASK 0x000000ff 1473 1474 #define GAC_ECO_BITS _MMIO(0x14090) 1475 #define ECOBITS_SNB_BIT (1 << 13) 1476 #define ECOBITS_PPGTT_CACHE64B (3 << 8) 1477 #define ECOBITS_PPGTT_CACHE4B (0 << 8) 1478 1479 #define GEN12_RCU_MODE _MMIO(0x14800) 1480 #define XEHP_RCU_MODE_FIXED_SLICE_CCS_MODE REG_BIT(1) 1481 #define GEN12_RCU_MODE_CCS_ENABLE REG_BIT(0) 1482 1483 #define XEHP_CCS_MODE _MMIO(0x14804) 1484 #define XEHP_CCS_MODE_CSLICE_MASK REG_GENMASK(2, 0) /* CCS0-3 + rsvd */ 1485 #define XEHP_CCS_MODE_CSLICE_WIDTH ilog2(XEHP_CCS_MODE_CSLICE_MASK + 1) 1486 #define XEHP_CCS_MODE_CSLICE(cslice, ccs) (ccs << (cslice * XEHP_CCS_MODE_CSLICE_WIDTH)) 1487 1488 #define CHV_FUSE_GT _MMIO(VLV_GUNIT_BASE + 0x2168) 1489 #define CHV_FGT_DISABLE_SS0 (1 << 10) 1490 #define CHV_FGT_DISABLE_SS1 (1 << 11) 1491 #define CHV_FGT_EU_DIS_SS0_R0_SHIFT 16 1492 #define CHV_FGT_EU_DIS_SS0_R0_MASK (0xf << CHV_FGT_EU_DIS_SS0_R0_SHIFT) 1493 #define CHV_FGT_EU_DIS_SS0_R1_SHIFT 20 1494 #define CHV_FGT_EU_DIS_SS0_R1_MASK (0xf << CHV_FGT_EU_DIS_SS0_R1_SHIFT) 1495 #define CHV_FGT_EU_DIS_SS1_R0_SHIFT 24 1496 #define CHV_FGT_EU_DIS_SS1_R0_MASK (0xf << CHV_FGT_EU_DIS_SS1_R0_SHIFT) 1497 #define CHV_FGT_EU_DIS_SS1_R1_SHIFT 28 1498 #define CHV_FGT_EU_DIS_SS1_R1_MASK (0xf << CHV_FGT_EU_DIS_SS1_R1_SHIFT) 1499 1500 #define BCS_SWCTRL _MMIO(0x22200) 1501 #define BCS_SRC_Y REG_BIT(0) 1502 #define BCS_DST_Y REG_BIT(1) 1503 1504 #define GAB_CTL _MMIO(0x24000) 1505 #define GAB_CTL_CONT_AFTER_PAGEFAULT (1 << 8) 1506 1507 #define GEN6_PMISR _MMIO(0x44020) 1508 #define GEN6_PMIMR _MMIO(0x44024) /* rps_lock */ 1509 #define GEN6_PMIIR _MMIO(0x44028) 1510 #define GEN6_PMIER _MMIO(0x4402c) 1511 #define GEN6_PM_MBOX_EVENT (1 << 25) 1512 #define GEN6_PM_THERMAL_EVENT (1 << 24) 1513 /* 1514 * For Gen11 these are in the upper word of the GPM_WGBOXPERF 1515 * registers. Shifting is handled on accessing the imr and ier. 1516 */ 1517 #define GEN6_PM_RP_DOWN_TIMEOUT (1 << 6) 1518 #define GEN6_PM_RP_UP_THRESHOLD (1 << 5) 1519 #define GEN6_PM_RP_DOWN_THRESHOLD (1 << 4) 1520 #define GEN6_PM_RP_UP_EI_EXPIRED (1 << 2) 1521 #define GEN6_PM_RP_DOWN_EI_EXPIRED (1 << 1) 1522 #define GEN6_PM_RPS_EVENTS (GEN6_PM_RP_UP_EI_EXPIRED | \ 1523 GEN6_PM_RP_UP_THRESHOLD | \ 1524 GEN6_PM_RP_DOWN_EI_EXPIRED | \ 1525 GEN6_PM_RP_DOWN_THRESHOLD | \ 1526 GEN6_PM_RP_DOWN_TIMEOUT) 1527 1528 #define GEN7_GT_SCRATCH(i) _MMIO(0x4f100 + (i) * 4) 1529 #define GEN7_GT_SCRATCH_REG_NUM 8 1530 1531 #define GFX_FLSH_CNTL_GEN6 _MMIO(0x101008) 1532 #define GFX_FLSH_CNTL_EN (1 << 0) 1533 1534 #define GTFIFODBG _MMIO(0x120000) 1535 #define GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV (0x1f << 20) 1536 #define GT_FIFO_FREE_ENTRIES_CHV (0x7f << 13) 1537 #define GT_FIFO_SBDROPERR (1 << 6) 1538 #define GT_FIFO_BLOBDROPERR (1 << 5) 1539 #define GT_FIFO_SB_READ_ABORTERR (1 << 4) 1540 #define GT_FIFO_DROPERR (1 << 3) 1541 #define GT_FIFO_OVFERR (1 << 2) 1542 #define GT_FIFO_IAWRERR (1 << 1) 1543 #define GT_FIFO_IARDERR (1 << 0) 1544 1545 #define GTFIFOCTL _MMIO(0x120008) 1546 #define GT_FIFO_FREE_ENTRIES_MASK 0x7f 1547 #define GT_FIFO_NUM_RESERVED_ENTRIES 20 1548 #define GT_FIFO_CTL_BLOCK_ALL_POLICY_STALL (1 << 12) 1549 #define GT_FIFO_CTL_RC6_POLICY_STALL (1 << 11) 1550 1551 #define FORCEWAKE_MT_ACK _MMIO(0x130040) 1552 #define FORCEWAKE_ACK_HSW _MMIO(0x130044) 1553 #define FORCEWAKE_ACK_GT_GEN9 _MMIO(0x130044) 1554 #define FORCEWAKE_KERNEL BIT(0) 1555 #define FORCEWAKE_USER BIT(1) 1556 #define FORCEWAKE_KERNEL_FALLBACK BIT(15) 1557 #define FORCEWAKE_ACK _MMIO(0x130090) 1558 #define VLV_GTLC_WAKE_CTRL _MMIO(0x130090) 1559 #define VLV_GTLC_RENDER_CTX_EXISTS (1 << 25) 1560 #define VLV_GTLC_MEDIA_CTX_EXISTS (1 << 24) 1561 #define VLV_GTLC_ALLOWWAKEREQ (1 << 0) 1562 #define VLV_GTLC_PW_STATUS _MMIO(0x130094) 1563 #define VLV_GTLC_ALLOWWAKEACK (1 << 0) 1564 #define VLV_GTLC_ALLOWWAKEERR (1 << 1) 1565 #define VLV_GTLC_PW_MEDIA_STATUS_MASK (1 << 5) 1566 #define VLV_GTLC_PW_RENDER_STATUS_MASK (1 << 7) 1567 #define VLV_GTLC_SURVIVABILITY_REG _MMIO(0x130098) 1568 #define VLV_GFX_CLK_STATUS_BIT (1 << 3) 1569 #define VLV_GFX_CLK_FORCE_ON_BIT (1 << 2) 1570 #define FORCEWAKE_VLV _MMIO(0x1300b0) 1571 #define FORCEWAKE_ACK_VLV _MMIO(0x1300b4) 1572 #define FORCEWAKE_MEDIA_VLV _MMIO(0x1300b8) 1573 #define FORCEWAKE_ACK_MEDIA_VLV _MMIO(0x1300bc) 1574 1575 #define MTL_MEDIA_MC6 _MMIO(0x138048) 1576 1577 #define MTL_GT_ACTIVITY_FACTOR _MMIO(0x138010) 1578 #define MTL_GT_L3_EXC_MASK REG_GENMASK(5, 3) 1579 1580 #define GEN6_GT_THREAD_STATUS_REG _MMIO(0x13805c) 1581 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 1582 1583 #define GEN6_GT_CORE_STATUS _MMIO(0x138060) 1584 #define GEN6_CORE_CPD_STATE_MASK (7 << 4) 1585 #define GEN6_RCn_MASK 7 1586 #define GEN6_RC0 0 1587 #define GEN6_RC3 2 1588 #define GEN6_RC6 3 1589 #define GEN6_RC7 4 1590 1591 #define GEN8_GT_SLICE_INFO _MMIO(0x138064) 1592 #define GEN8_LSLICESTAT_MASK 0x7 1593 1594 #define GEN6_GT_GFX_RC6_LOCKED _MMIO(0x138104) 1595 #define VLV_COUNTER_CONTROL _MMIO(0x138104) 1596 #define VLV_COUNT_RANGE_HIGH (1 << 15) 1597 #define VLV_MEDIA_RC0_COUNT_EN (1 << 5) 1598 #define VLV_RENDER_RC0_COUNT_EN (1 << 4) 1599 #define VLV_MEDIA_RC6_COUNT_EN (1 << 1) 1600 #define VLV_RENDER_RC6_COUNT_EN (1 << 0) 1601 #define GEN6_GT_GFX_RC6 _MMIO(0x138108) 1602 #define VLV_GT_MEDIA_RC6 _MMIO(0x13810c) 1603 1604 #define GEN6_GT_GFX_RC6p _MMIO(0x13810c) 1605 #define GEN6_GT_GFX_RC6pp _MMIO(0x138110) 1606 #define VLV_RENDER_C0_COUNT _MMIO(0x138118) 1607 #define VLV_MEDIA_C0_COUNT _MMIO(0x13811c) 1608 1609 #define GEN12_RPSTAT1 _MMIO(0x1381b4) 1610 #define GEN12_VOLTAGE_MASK REG_GENMASK(10, 0) 1611 #define GEN12_CAGF_MASK REG_GENMASK(19, 11) 1612 1613 #define GEN11_GT_INTR_DW(x) _MMIO(0x190018 + ((x) * 4)) 1614 #define GEN11_CSME (31) 1615 #define GEN12_HECI_2 (30) 1616 #define GEN11_GUNIT (28) 1617 #define GEN11_GUC (25) 1618 #define MTL_MGUC (24) 1619 #define GEN11_WDPERF (20) 1620 #define GEN11_KCR (19) 1621 #define GEN11_GTPM (16) 1622 #define GEN11_BCS (15) 1623 #define XEHPC_BCS1 (14) 1624 #define XEHPC_BCS2 (13) 1625 #define XEHPC_BCS3 (12) 1626 #define XEHPC_BCS4 (11) 1627 #define XEHPC_BCS5 (10) 1628 #define XEHPC_BCS6 (9) 1629 #define XEHPC_BCS7 (8) 1630 #define XEHPC_BCS8 (23) 1631 #define GEN12_CCS3 (7) 1632 #define GEN12_CCS2 (6) 1633 #define GEN12_CCS1 (5) 1634 #define GEN12_CCS0 (4) 1635 #define GEN11_RCS0 (0) 1636 #define GEN11_VECS(x) (31 - (x)) 1637 #define GEN11_VCS(x) (x) 1638 1639 #define GEN11_RENDER_COPY_INTR_ENABLE _MMIO(0x190030) 1640 #define GEN11_VCS_VECS_INTR_ENABLE _MMIO(0x190034) 1641 #define GEN11_GUC_SG_INTR_ENABLE _MMIO(0x190038) 1642 #define ENGINE1_MASK REG_GENMASK(31, 16) 1643 #define ENGINE0_MASK REG_GENMASK(15, 0) 1644 #define GEN11_GPM_WGBOXPERF_INTR_ENABLE _MMIO(0x19003c) 1645 #define GEN11_CRYPTO_RSVD_INTR_ENABLE _MMIO(0x190040) 1646 #define GEN11_GUNIT_CSME_INTR_ENABLE _MMIO(0x190044) 1647 #define GEN12_CCS_RSVD_INTR_ENABLE _MMIO(0x190048) 1648 1649 #define GEN11_INTR_IDENTITY_REG(x) _MMIO(0x190060 + ((x) * 4)) 1650 #define GEN11_INTR_DATA_VALID (1 << 31) 1651 #define GEN11_INTR_ENGINE_CLASS(x) (((x) & GENMASK(18, 16)) >> 16) 1652 #define GEN11_INTR_ENGINE_INSTANCE(x) (((x) & GENMASK(25, 20)) >> 20) 1653 #define GEN11_INTR_ENGINE_INTR(x) ((x) & 0xffff) 1654 /* irq instances for OTHER_CLASS */ 1655 #define OTHER_GUC_INSTANCE 0 1656 #define OTHER_GTPM_INSTANCE 1 1657 #define OTHER_GSC_HECI_2_INSTANCE 3 1658 #define OTHER_KCR_INSTANCE 4 1659 #define OTHER_GSC_INSTANCE 6 1660 #define OTHER_MEDIA_GUC_INSTANCE 16 1661 #define OTHER_MEDIA_GTPM_INSTANCE 17 1662 1663 #define GEN11_IIR_REG_SELECTOR(x) _MMIO(0x190070 + ((x) * 4)) 1664 1665 #define GEN11_RCS0_RSVD_INTR_MASK _MMIO(0x190090) 1666 #define GEN11_BCS_RSVD_INTR_MASK _MMIO(0x1900a0) 1667 #define GEN11_VCS0_VCS1_INTR_MASK _MMIO(0x1900a8) 1668 #define GEN11_VCS2_VCS3_INTR_MASK _MMIO(0x1900ac) 1669 #define GEN12_VCS4_VCS5_INTR_MASK _MMIO(0x1900b0) 1670 #define GEN12_VCS6_VCS7_INTR_MASK _MMIO(0x1900b4) 1671 #define GEN11_VECS0_VECS1_INTR_MASK _MMIO(0x1900d0) 1672 #define GEN12_VECS2_VECS3_INTR_MASK _MMIO(0x1900d4) 1673 #define GEN12_HECI2_RSVD_INTR_MASK _MMIO(0x1900e4) 1674 #define GEN11_GUC_SG_INTR_MASK _MMIO(0x1900e8) 1675 #define MTL_GUC_MGUC_INTR_MASK _MMIO(0x1900e8) /* MTL+ */ 1676 #define GEN11_GPM_WGBOXPERF_INTR_MASK _MMIO(0x1900ec) 1677 #define GEN11_CRYPTO_RSVD_INTR_MASK _MMIO(0x1900f0) 1678 #define GEN11_GUNIT_CSME_INTR_MASK _MMIO(0x1900f4) 1679 #define GEN12_CCS0_CCS1_INTR_MASK _MMIO(0x190100) 1680 #define GEN12_CCS2_CCS3_INTR_MASK _MMIO(0x190104) 1681 #define XEHPC_BCS1_BCS2_INTR_MASK _MMIO(0x190110) 1682 #define XEHPC_BCS3_BCS4_INTR_MASK _MMIO(0x190114) 1683 #define XEHPC_BCS5_BCS6_INTR_MASK _MMIO(0x190118) 1684 #define XEHPC_BCS7_BCS8_INTR_MASK _MMIO(0x19011c) 1685 1686 #define GEN12_SFC_DONE(n) _MMIO(0x1cc000 + (n) * 0x1000) 1687 1688 #define GT0_PACKAGE_ENERGY_STATUS _MMIO(0x250004) 1689 #define GT0_PACKAGE_RAPL_LIMIT _MMIO(0x250008) 1690 #define GT0_PACKAGE_POWER_SKU_UNIT _MMIO(0x250068) 1691 #define GT0_PLATFORM_ENERGY_STATUS _MMIO(0x25006c) 1692 1693 /* 1694 * Standalone Media's non-engine GT registers are located at their regular GT 1695 * offsets plus 0x380000. This extra offset is stored inside the intel_uncore 1696 * structure so that the existing code can be used for both GTs without 1697 * modification. 1698 */ 1699 #define MTL_MEDIA_GSI_BASE 0x380000 1700 1701 #endif /* __INTEL_GT_REGS__ */ 1702