1 /*
2  * Copyright � 2014 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the
6  * "Software"), to deal in the Software without restriction, including
7  * without limitation the rights to use, copy, modify, merge, publish,
8  * distribute, sub license, and/or sell copies of the Software, and to
9  * permit persons to whom the Software is furnished to do so, subject to
10  * the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the
13  * next paragraph) shall be included in all copies or substantial portions
14  * of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
17  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
18  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
19  * IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
20  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
21  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
22  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors:
25  *     Wei Lin<wei.w.lin@intel.com>
26  *     Yuting Yang<yuting.yang@intel.com>
27  */
28 
29 #ifndef __HW_INTERFACE_G75_H__
30 #define __HW_INTERFACE_G75_H__
31 
32 #include "os_interface.h"
33 #include "hw_interface.h"
34 
35 #define GENHW_REG_L3_CACHE_SQCREG1_G75		0xB010
36 #define GENHW_REG_L3_CACHE_CNTLREG2_G75		0xB020
37 #define GENHW_REG_L3_CACHE_CNTLREG3_G75		0xB024
38 
39 #define GENHW_REG_L3_CACHE_L3LRA1_G75		0x4040
40 
41 #define GENHW_REG_INSTPM			0x20c0
42 #define GENHW_REG_INSTPM_GLOBAL_DEBUG		(1 << 4)
43 #define GENHW_REG_INSTPM_PREDICATE_DISABLE	(3 << 13)
44 
45 #define GENHW_REG_TD_CTL			0xe400
46 #define GENHW_REG_TD_CTL_S0_SS0			GENHW_REG_TD_CTL
47 #define GENHW_REG_TD_CTL_S0_SS1			0xe500
48 #define GENHW_REG_TD_CTL_S1_SS0			0xe600
49 #define GENHW_REG_TD_CTL_S1_SS1			0xe700
50 #define GENHW_REG_TD_CTL_FORCE_BKPT_ENABLE	(1 << 4)
51 #define GENHW_REG_TD_CTL_FORCE_EXCEPTION_ENABLE	(1 << 7)
52 
53 #define GENHW_REG_MBCTL				0x907c
54 #define GENHW_REG_MBCHT_RDRETSEL_OFFSET		17
55 
56 extern CONST GENHW_PIPECONTROL_PARAM g_PipeControlParam_g75;
57 extern CONST GENHW_SSH_SETTINGS g_SSH_Settings_g75;
58 extern CONST GENHW_STORE_DATA_IMM_PARAM g_StoreDataImmParam_g75;
59 extern CONST GENHW_INDIRECT_PATCH_PARAM g_IndirectPatchParam_g75;
60 
61 VOID IntelGen_HwSetupMediaObjectHeader_g75(PMEDIA_OBJECT_KA2_CMD pMediaCmd,
62 					   INT iMediaID, INT iSize);
63 
64 INT IntelGen_HwGetMediaObjectSize_g75(PGENHW_HW_INTERFACE pHwInterface,
65 				      BOOL bNLAS);
66 
67 GENOS_STATUS IntelGen_HwSendCurbeLoad_g75(PGENHW_HW_INTERFACE pHwInterface,
68 					  PGENOS_COMMAND_BUFFER pCmdBuffer);
69 
70 GENOS_STATUS IntelGen_HwSendIDLoad_g75(PGENHW_HW_INTERFACE pHwInterface,
71 				       PGENOS_COMMAND_BUFFER pCmdBuffer);
72 
73 VOID IntelGen_HwAddMediaObjectCmdBb_g75(PGENHW_HW_INTERFACE pHwInterface,
74 					PGENHW_BATCH_BUFFER pBatchBuffer,
75 					PGENHW_HW_MEDIAOBJECT_PARAM pParam);
76 
77 VOID IntelGen_HwAddPipeControlCmdBb_g75(PGENHW_HW_INTERFACE pHwInterface,
78 					PGENHW_BATCH_BUFFER pBatchBuffer,
79 					PGENHW_PIPECONTROL_PARAM pParam);
80 
81 VOID IntelGen_HwSkipPipeControlCmdBb_g75(PGENHW_HW_INTERFACE pHwInterface,
82 					 PGENHW_BATCH_BUFFER pBatchBuffer,
83 					 PGENHW_PIPECONTROL_PARAM pParam);
84 
85 VOID IntelGen_HwConvertToNanoSeconds_g75(PGENHW_HW_INTERFACE pHwInterface,
86 					 UINT64 iTicks, PUINT64 piNs);
87 
88 BOOL IntelGen_HwIsCSCCoeffPatchMode_g75(PGENHW_HW_INTERFACE pHwInterface);
89 
90 GENOS_STATUS IntelGen_HwSendPipelineSelectCmd_g75(PGENHW_HW_INTERFACE
91 						  pHwInterface,
92 						  PGENOS_COMMAND_BUFFER
93 						  pCmdBuffer,
94 						  DWORD dwGfxPipelineSelect);
95 
96 DWORD IntelGen_GetScratchSpaceSize_g8(PGENHW_HW_INTERFACE pHwInterface,
97 				      DWORD iPerThreadScratchSpaceSize);
98 BOOL IntelGen_HwGetMediaWalkerStatus_g75(PGENHW_HW_INTERFACE pHwInterface);
99 
100 BOOL IntelGen_HwGetVDIWalkerStatus_g75(PGENHW_HW_INTERFACE pHwInterface,
101 				       PGENHW_SURFACE pSurface,
102 				       BOOL bDn, BOOL bDiVariance);
103 
104 GENOS_STATUS IntelGen_HwSubmitBuffer_g75(PGENHW_HW_INTERFACE pHwInterface,
105 					 PGENHW_BATCH_BUFFER pBatchBuffer,
106 					 BOOL bNullRendering,
107 					 PGENHW_WALKER_PARAMS pWalkerParams,
108 					 PGENHW_GPGPU_WALKER_PARAMS
109 					 pGpGpuWalkerParams);
110 
111 GENOS_STATUS IntelGen_HwSendMediaStateFlush_g75(PGENHW_HW_INTERFACE
112 						pHwInterface,
113 						PGENOS_COMMAND_BUFFER
114 						pCmdBuffer);
115 
116 VOID IntelGen_HwAddGpuStatusWriteTagCmdBb_g75(PGENHW_HW_INTERFACE pHwInterface,
117 					      PGENHW_BATCH_BUFFER pBatchBuffer);
118 
119 GENOS_STATUS IntelGen_HwSendMISetPredicateCmd_g75(PGENHW_HW_INTERFACE
120 						  pHwInterface,
121 						  PGENOS_COMMAND_BUFFER
122 						  pCmdBuffer,
123 						  DWORD PredicateEnable);
124 
125 GENHW_MEDIA_WALKER_MODE IntelGen_HwSelectWalkerStateMode_g75(PGENHW_HW_INTERFACE
126 							     pHwInterface);
127 
128 GENOS_STATUS IntelGen_HwSendWalkerState_g75(PGENHW_HW_INTERFACE pHwInterface,
129 					    PGENOS_COMMAND_BUFFER pCmdBuffer,
130 					    PGENHW_WALKER_PARAMS pWalkerParams);
131 
132 BOOL IntelGen_HwIs2PlaneNV12Needed_g75(PGENHW_HW_INTERFACE pHwInterface,
133 				       PGENHW_SURFACE pSurface);
134 
135 DWORD IntelGen_GetScratchSpaceSize_g75(PGENHW_HW_INTERFACE pHwInterface,
136 				       DWORD iPerThreadScratchSpaceSize);
137 
138 UINT IntelGen_HwGetMediaWalkerBlockSize_g75(PGENHW_HW_INTERFACE pHwInterface);
139 
140 #endif
141