xref: /openbsd/sys/dev/pci/drm/amd/amdgpu/psp_gfx_if.h (revision f005ef32)
1 /*
2  * Copyright 2017 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef _PSP_TEE_GFX_IF_H_
25 #define _PSP_TEE_GFX_IF_H_
26 
27 #define PSP_GFX_CMD_BUF_VERSION     0x00000001
28 
29 #define GFX_CMD_STATUS_MASK         0x0000FFFF
30 #define GFX_CMD_ID_MASK             0x000F0000
31 #define GFX_CMD_RESERVED_MASK       0x7FF00000
32 #define GFX_CMD_RESPONSE_MASK       0x80000000
33 
34 /* USBC PD FW version retrieval command */
35 #define C2PMSG_CMD_GFX_USB_PD_FW_VER 0x2000000
36 
37 /* TEE Gfx Command IDs for the register interface.
38 *  Command ID must be between 0x00010000 and 0x000F0000.
39 */
40 enum psp_gfx_crtl_cmd_id
41 {
42     GFX_CTRL_CMD_ID_INIT_RBI_RING   = 0x00010000,   /* initialize RBI ring */
43     GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000,   /* initialize GPCOM ring */
44     GFX_CTRL_CMD_ID_DESTROY_RINGS   = 0x00030000,   /* destroy rings */
45     GFX_CTRL_CMD_ID_CAN_INIT_RINGS  = 0x00040000,   /* is it allowed to initialized the rings */
46     GFX_CTRL_CMD_ID_ENABLE_INT      = 0x00050000,   /* enable PSP-to-Gfx interrupt */
47     GFX_CTRL_CMD_ID_DISABLE_INT     = 0x00060000,   /* disable PSP-to-Gfx interrupt */
48     GFX_CTRL_CMD_ID_MODE1_RST       = 0x00070000,   /* trigger the Mode 1 reset */
49     GFX_CTRL_CMD_ID_GBR_IH_SET      = 0x00080000,   /* set Gbr IH_RB_CNTL registers */
50     GFX_CTRL_CMD_ID_CONSUME_CMD     = 0x00090000,   /* send interrupt to psp for updating write pointer of vf */
51     GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */
52 
53     GFX_CTRL_CMD_ID_MAX             = 0x000F0000,   /* max command ID */
54 };
55 
56 
57 /*-----------------------------------------------------------------------------
58     NOTE:   All physical addresses used in this interface are actually
59             GPU Virtual Addresses.
60 */
61 
62 
63 /* Control registers of the TEE Gfx interface. These are located in
64 *  SRBM-to-PSP mailbox registers (total 8 registers).
65 */
66 struct psp_gfx_ctrl
67 {
68     volatile uint32_t   cmd_resp;         /* +0   Command/Response register for Gfx commands */
69     volatile uint32_t   rbi_wptr;         /* +4   Write pointer (index) of RBI ring */
70     volatile uint32_t   rbi_rptr;         /* +8   Read pointer (index) of RBI ring */
71     volatile uint32_t   gpcom_wptr;       /* +12  Write pointer (index) of GPCOM ring */
72     volatile uint32_t   gpcom_rptr;       /* +16  Read pointer (index) of GPCOM ring */
73     volatile uint32_t   ring_addr_lo;     /* +20  bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/
74     volatile uint32_t   ring_addr_hi;     /* +24  bits [63:32] of GPU Virtual of ring buffer (VMID=0) */
75     volatile uint32_t   ring_buf_size;    /* +28  Ring buffer size (in bytes) */
76 
77 };
78 
79 
80 /* Response flag is set in the command when command is completed by PSP.
81 *  Used in the GFX_CTRL.CmdResp.
82 *  When PSP GFX I/F is initialized, the flag is set.
83 */
84 #define GFX_FLAG_RESPONSE               0x80000000
85 
86 /* TEE Gfx Command IDs for the ring buffer interface. */
87 enum psp_gfx_cmd_id
88 {
89     GFX_CMD_ID_LOAD_TA            = 0x00000001,   /* load TA */
90     GFX_CMD_ID_UNLOAD_TA          = 0x00000002,   /* unload TA */
91     GFX_CMD_ID_INVOKE_CMD         = 0x00000003,   /* send command to TA */
92     GFX_CMD_ID_LOAD_ASD           = 0x00000004,   /* load ASD Driver */
93     GFX_CMD_ID_SETUP_TMR          = 0x00000005,   /* setup TMR region */
94     GFX_CMD_ID_LOAD_IP_FW         = 0x00000006,   /* load HW IP FW */
95     GFX_CMD_ID_DESTROY_TMR        = 0x00000007,   /* destroy TMR region */
96     GFX_CMD_ID_SAVE_RESTORE       = 0x00000008,   /* save/restore HW IP FW */
97     GFX_CMD_ID_SETUP_VMR          = 0x00000009,   /* setup VMR region */
98     GFX_CMD_ID_DESTROY_VMR        = 0x0000000A,   /* destroy VMR region */
99     GFX_CMD_ID_PROG_REG           = 0x0000000B,   /* program regs */
100     GFX_CMD_ID_GET_FW_ATTESTATION = 0x0000000F,   /* Query GPUVA of the Fw Attestation DB */
101     /* IDs upto 0x1F are reserved for older programs (Raven, Vega 10/12/20) */
102     GFX_CMD_ID_LOAD_TOC           = 0x00000020,   /* Load TOC and obtain TMR size */
103     GFX_CMD_ID_AUTOLOAD_RLC       = 0x00000021,   /* Indicates all graphics fw loaded, start RLC autoload */
104     GFX_CMD_ID_BOOT_CFG           = 0x00000022,   /* Boot Config */
105     GFX_CMD_ID_SRIOV_SPATIAL_PART = 0x00000027,   /* Configure spatial partitioning mode */
106 };
107 
108 /* PSP boot config sub-commands */
109 enum psp_gfx_boot_config_cmd
110 {
111     BOOTCFG_CMD_SET         = 1, /* Set boot configuration settings */
112     BOOTCFG_CMD_GET         = 2, /* Get boot configuration settings */
113     BOOTCFG_CMD_INVALIDATE  = 3  /* Reset current boot configuration settings to VBIOS defaults */
114 };
115 
116 /* PSP boot config bitmask values */
117 enum psp_gfx_boot_config
118 {
119     BOOT_CONFIG_GECC = 0x1,
120 };
121 
122 /* Command to load Trusted Application binary into PSP OS. */
123 struct psp_gfx_cmd_load_ta
124 {
125     uint32_t        app_phy_addr_lo;        /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */
126     uint32_t        app_phy_addr_hi;        /* bits [63:32] of the GPU Virtual address of the TA binary */
127     uint32_t        app_len;                /* length of the TA binary in bytes */
128     uint32_t        cmd_buf_phy_addr_lo;    /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */
129     uint32_t        cmd_buf_phy_addr_hi;    /* bits [63:32] of the GPU Virtual address of CMD buffer */
130     uint32_t        cmd_buf_len;            /* length of the CMD buffer in bytes; must be multiple of 4 KB */
131 
132     /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided
133     *       for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead
134     *       of using global persistent buffer.
135     */
136 };
137 
138 
139 /* Command to Unload Trusted Application binary from PSP OS. */
140 struct psp_gfx_cmd_unload_ta
141 {
142     uint32_t        session_id;          /* Session ID of the loaded TA to be unloaded */
143 
144 };
145 
146 
147 /* Shared buffers for InvokeCommand.
148 */
149 struct psp_gfx_buf_desc
150 {
151     uint32_t        buf_phy_addr_lo;       /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */
152     uint32_t        buf_phy_addr_hi;       /* bits [63:32] of GPU Virtual address of the buffer */
153     uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */
154 
155 };
156 
157 /* Max number of descriptors for one shared buffer (in how many different
158 *  physical locations one shared buffer can be stored). If buffer is too much
159 *  fragmented, error will be returned.
160 */
161 #define GFX_BUF_MAX_DESC        64
162 
163 struct psp_gfx_buf_list
164 {
165     uint32_t                num_desc;                    /* number of buffer descriptors in the list */
166     uint32_t                total_size;                  /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */
167     struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC];  /* list of buffer descriptors */
168 
169     /* total 776 bytes */
170 };
171 
172 /* Command to execute InvokeCommand entry point of the TA. */
173 struct psp_gfx_cmd_invoke_cmd
174 {
175     uint32_t                session_id;           /* Session ID of the TA to be executed */
176     uint32_t                ta_cmd_id;            /* Command ID to be sent to TA */
177     struct psp_gfx_buf_list buf;                  /* one indirect buffer (scatter/gather list) */
178 
179 };
180 
181 
182 /* Command to setup TMR region. */
183 struct psp_gfx_cmd_setup_tmr
184 {
185     uint32_t        buf_phy_addr_lo;       /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */
186     uint32_t        buf_phy_addr_hi;       /* bits [63:32] of GPU Virtual address of TMR buffer */
187     uint32_t        buf_size;              /* buffer size in bytes (must be multiple of 4 KB) */
188     union {
189 	struct {
190 		uint32_t	sriov_enabled:1; /* whether the device runs under SR-IOV*/
191 		uint32_t	virt_phy_addr:1; /* driver passes both virtual and physical address to PSP*/
192 		uint32_t	reserved:30;
193 	} bitfield;
194 	uint32_t        tmr_flags;
195     };
196     uint32_t        system_phy_addr_lo;        /* bits [31:0] of system physical address of TMR buffer (must be 4 KB aligned) */
197     uint32_t        system_phy_addr_hi;        /* bits [63:32] of system physical address of TMR buffer */
198 
199 };
200 
201 /* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */
202 enum psp_gfx_fw_type {
203 	GFX_FW_TYPE_NONE        = 0,    /* */
204 	GFX_FW_TYPE_CP_ME       = 1,    /* CP-ME                    VG + RV */
205 	GFX_FW_TYPE_CP_PFP      = 2,    /* CP-PFP                   VG + RV */
206 	GFX_FW_TYPE_CP_CE       = 3,    /* CP-CE                    VG + RV */
207 	GFX_FW_TYPE_CP_MEC      = 4,    /* CP-MEC FW                VG + RV */
208 	GFX_FW_TYPE_CP_MEC_ME1  = 5,    /* CP-MEC Jump Table 1      VG + RV */
209 	GFX_FW_TYPE_CP_MEC_ME2  = 6,    /* CP-MEC Jump Table 2      VG      */
210 	GFX_FW_TYPE_RLC_V       = 7,    /* RLC-V                    VG      */
211 	GFX_FW_TYPE_RLC_G       = 8,    /* RLC-G                    VG + RV */
212 	GFX_FW_TYPE_SDMA0       = 9,    /* SDMA0                    VG + RV */
213 	GFX_FW_TYPE_SDMA1       = 10,   /* SDMA1                    VG      */
214 	GFX_FW_TYPE_DMCU_ERAM   = 11,   /* DMCU-ERAM                VG + RV */
215 	GFX_FW_TYPE_DMCU_ISR    = 12,   /* DMCU-ISR                 VG + RV */
216 	GFX_FW_TYPE_VCN         = 13,   /* VCN                           RV */
217 	GFX_FW_TYPE_UVD         = 14,   /* UVD                      VG      */
218 	GFX_FW_TYPE_VCE         = 15,   /* VCE                      VG      */
219 	GFX_FW_TYPE_ISP         = 16,   /* ISP                           RV */
220 	GFX_FW_TYPE_ACP         = 17,   /* ACP                           RV */
221 	GFX_FW_TYPE_SMU         = 18,   /* SMU                      VG      */
222 	GFX_FW_TYPE_MMSCH       = 19,   /* MMSCH                    VG      */
223 	GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM        = 20,   /* RLC GPM                  VG + RV */
224 	GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM        = 21,   /* RLC SRM                  VG + RV */
225 	GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL       = 22,   /* RLC CNTL                 VG + RV */
226 	GFX_FW_TYPE_UVD1        = 23,   /* UVD1                     VG-20   */
227 	GFX_FW_TYPE_TOC         = 24,   /* TOC                      NV-10   */
228 	GFX_FW_TYPE_RLC_P                           = 25,   /* RLC P                    NV      */
229 	GFX_FW_TYPE_RLC_IRAM                        = 26,   /* RLC_IRAM                 NV      */
230 	GFX_FW_TYPE_GLOBAL_TAP_DELAYS               = 27,   /* GLOBAL TAP DELAYS        NV      */
231 	GFX_FW_TYPE_SE0_TAP_DELAYS                  = 28,   /* SE0 TAP DELAYS           NV      */
232 	GFX_FW_TYPE_SE1_TAP_DELAYS                  = 29,   /* SE1 TAP DELAYS           NV      */
233 	GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS      = 30,   /* GLOBAL SE0/1 SKEW DELAYS NV      */
234 	GFX_FW_TYPE_SDMA0_JT                        = 31,   /* SDMA0 JT                 NV      */
235 	GFX_FW_TYPE_SDMA1_JT                        = 32,   /* SDNA1 JT                 NV      */
236 	GFX_FW_TYPE_CP_MES                          = 33,   /* CP MES                   NV      */
237 	GFX_FW_TYPE_MES_STACK                       = 34,   /* MES STACK                NV      */
238 	GFX_FW_TYPE_RLC_SRM_DRAM_SR                 = 35,   /* RLC SRM DRAM             NV      */
239 	GFX_FW_TYPE_RLCG_SCRATCH_SR                 = 36,   /* RLCG SCRATCH             NV      */
240 	GFX_FW_TYPE_RLCP_SCRATCH_SR                 = 37,   /* RLCP SCRATCH             NV      */
241 	GFX_FW_TYPE_RLCV_SCRATCH_SR                 = 38,   /* RLCV SCRATCH             NV      */
242 	GFX_FW_TYPE_RLX6_DRAM_SR                    = 39,   /* RLX6 DRAM                NV      */
243 	GFX_FW_TYPE_SDMA0_PG_CONTEXT                = 40,   /* SDMA0 PG CONTEXT         NV      */
244 	GFX_FW_TYPE_SDMA1_PG_CONTEXT                = 41,   /* SDMA1 PG CONTEXT         NV      */
245 	GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM           = 42,   /* GLOBAL MUX SEL RAM       NV      */
246 	GFX_FW_TYPE_SE0_MUX_SELECT_RAM              = 43,   /* SE0 MUX SEL RAM          NV      */
247 	GFX_FW_TYPE_SE1_MUX_SELECT_RAM              = 44,   /* SE1 MUX SEL RAM          NV      */
248 	GFX_FW_TYPE_ACCUM_CTRL_RAM                  = 45,   /* ACCUM CTRL RAM           NV      */
249 	GFX_FW_TYPE_RLCP_CAM                        = 46,   /* RLCP CAM                 NV      */
250 	GFX_FW_TYPE_RLC_SPP_CAM_EXT                 = 47,   /* RLC SPP CAM EXT          NV      */
251 	GFX_FW_TYPE_RLC_DRAM_BOOT                   = 48,   /* RLC DRAM BOOT            NV      */
252 	GFX_FW_TYPE_VCN0_RAM                        = 49,   /* VCN_RAM                  NV + RN */
253 	GFX_FW_TYPE_VCN1_RAM                        = 50,   /* VCN_RAM                  NV + RN */
254 	GFX_FW_TYPE_DMUB                            = 51,   /* DMUB                          RN */
255 	GFX_FW_TYPE_SDMA2                           = 52,   /* SDMA2                    MI      */
256 	GFX_FW_TYPE_SDMA3                           = 53,   /* SDMA3                    MI      */
257 	GFX_FW_TYPE_SDMA4                           = 54,   /* SDMA4                    MI      */
258 	GFX_FW_TYPE_SDMA5                           = 55,   /* SDMA5                    MI      */
259 	GFX_FW_TYPE_SDMA6                           = 56,   /* SDMA6                    MI      */
260 	GFX_FW_TYPE_SDMA7                           = 57,   /* SDMA7                    MI      */
261 	GFX_FW_TYPE_VCN1                            = 58,   /* VCN1                     MI      */
262 	GFX_FW_TYPE_CAP                             = 62,   /* CAP_FW                           */
263 	GFX_FW_TYPE_SE2_TAP_DELAYS                  = 65,   /* SE2 TAP DELAYS           NV      */
264 	GFX_FW_TYPE_SE3_TAP_DELAYS                  = 66,   /* SE3 TAP DELAYS           NV      */
265 	GFX_FW_TYPE_REG_LIST                        = 67,   /* REG_LIST                 MI      */
266 	GFX_FW_TYPE_IMU_I                           = 68,   /* IMU Instruction FW       SOC21   */
267 	GFX_FW_TYPE_IMU_D                           = 69,   /* IMU Data FW              SOC21   */
268 	GFX_FW_TYPE_LSDMA                           = 70,   /* LSDMA FW                 SOC21   */
269 	GFX_FW_TYPE_SDMA_UCODE_TH0                  = 71,   /* SDMA Thread 0/CTX        SOC21   */
270 	GFX_FW_TYPE_SDMA_UCODE_TH1                  = 72,   /* SDMA Thread 1/CTL        SOC21   */
271 	GFX_FW_TYPE_PPTABLE                         = 73,   /* PPTABLE                  SOC21   */
272 	GFX_FW_TYPE_DISCRETE_USB4                   = 74,   /* dUSB4 FW                 SOC21   */
273 	GFX_FW_TYPE_TA                              = 75,   /* SRIOV TA FW UUID         SOC21   */
274 	GFX_FW_TYPE_RS64_MES                        = 76,   /* RS64 MES ucode           SOC21   */
275 	GFX_FW_TYPE_RS64_MES_STACK                  = 77,   /* RS64 MES stack ucode     SOC21   */
276 	GFX_FW_TYPE_RS64_KIQ                        = 78,   /* RS64 KIQ ucode           SOC21   */
277 	GFX_FW_TYPE_RS64_KIQ_STACK                  = 79,   /* RS64 KIQ Heap stack      SOC21   */
278 	GFX_FW_TYPE_ISP_DATA                        = 80,   /* ISP DATA                 SOC21   */
279 	GFX_FW_TYPE_CP_MES_KIQ                      = 81,   /* MES KIQ ucode            SOC21   */
280 	GFX_FW_TYPE_MES_KIQ_STACK                   = 82,   /* MES KIQ stack            SOC21   */
281 	GFX_FW_TYPE_UMSCH_DATA                      = 83,   /* User Mode Scheduler Data SOC21   */
282 	GFX_FW_TYPE_UMSCH_UCODE                     = 84,   /* User Mode Scheduler Ucode SOC21  */
283 	GFX_FW_TYPE_UMSCH_CMD_BUFFER                = 85,   /* User Mode Scheduler Command Buffer SOC21 */
284 	GFX_FW_TYPE_USB_DP_COMBO_PHY                = 86,   /* USB-Display port Combo   SOC21   */
285 	GFX_FW_TYPE_RS64_PFP                        = 87,   /* RS64 PFP                 SOC21   */
286 	GFX_FW_TYPE_RS64_ME                         = 88,   /* RS64 ME                  SOC21   */
287 	GFX_FW_TYPE_RS64_MEC                        = 89,   /* RS64 MEC                 SOC21   */
288 	GFX_FW_TYPE_RS64_PFP_P0_STACK               = 90,   /* RS64 PFP stack P0        SOC21   */
289 	GFX_FW_TYPE_RS64_PFP_P1_STACK               = 91,   /* RS64 PFP stack P1        SOC21   */
290 	GFX_FW_TYPE_RS64_ME_P0_STACK                = 92,   /* RS64 ME stack P0         SOC21   */
291 	GFX_FW_TYPE_RS64_ME_P1_STACK                = 93,   /* RS64 ME stack P1         SOC21   */
292 	GFX_FW_TYPE_RS64_MEC_P0_STACK               = 94,   /* RS64 MEC stack P0        SOC21   */
293 	GFX_FW_TYPE_RS64_MEC_P1_STACK               = 95,   /* RS64 MEC stack P1        SOC21   */
294 	GFX_FW_TYPE_RS64_MEC_P2_STACK               = 96,   /* RS64 MEC stack P2        SOC21   */
295 	GFX_FW_TYPE_RS64_MEC_P3_STACK               = 97,   /* RS64 MEC stack P3        SOC21   */
296 	GFX_FW_TYPE_MAX
297 };
298 
299 /* Command to load HW IP FW. */
300 struct psp_gfx_cmd_load_ip_fw
301 {
302     uint32_t                fw_phy_addr_lo;    /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
303     uint32_t                fw_phy_addr_hi;    /* bits [63:32] of GPU Virtual address of FW location */
304     uint32_t                fw_size;           /* FW buffer size in bytes */
305     enum psp_gfx_fw_type    fw_type;           /* FW type */
306 
307 };
308 
309 /* Command to save/restore HW IP FW. */
310 struct psp_gfx_cmd_save_restore_ip_fw
311 {
312     uint32_t                save_fw;              /* if set, command is used for saving fw otherwise for resetoring*/
313     uint32_t                save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */
314     uint32_t                save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */
315     uint32_t                buf_size;             /* Size of the save/restore buffer in bytes */
316     enum psp_gfx_fw_type    fw_type;              /* FW type */
317 };
318 
319 /* Command to setup register program */
320 struct psp_gfx_cmd_reg_prog {
321 	uint32_t	reg_value;
322 	uint32_t	reg_id;
323 };
324 
325 /* Command to load TOC */
326 struct psp_gfx_cmd_load_toc
327 {
328     uint32_t        toc_phy_addr_lo;        /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
329     uint32_t        toc_phy_addr_hi;        /* bits [63:32] of GPU Virtual address of FW location */
330     uint32_t        toc_size;               /* FW buffer size in bytes */
331 };
332 
333 /* Dynamic boot configuration */
334 struct psp_gfx_cmd_boot_cfg
335 {
336     uint32_t                        timestamp;            /* calendar time as number of seconds */
337     enum psp_gfx_boot_config_cmd    sub_cmd;              /* sub-command indicating how to process command data */
338     uint32_t                        boot_config;          /* dynamic boot configuration bitmask */
339     uint32_t                        boot_config_valid;    /* dynamic boot configuration valid bits bitmask */
340 };
341 
342 struct psp_gfx_cmd_sriov_spatial_part {
343 	uint32_t mode;
344 	uint32_t override_ips;
345 	uint32_t override_xcds_avail;
346 	uint32_t override_this_aid;
347 };
348 
349 /* All GFX ring buffer commands. */
350 union psp_gfx_commands
351 {
352     struct psp_gfx_cmd_load_ta          cmd_load_ta;
353     struct psp_gfx_cmd_unload_ta        cmd_unload_ta;
354     struct psp_gfx_cmd_invoke_cmd       cmd_invoke_cmd;
355     struct psp_gfx_cmd_setup_tmr        cmd_setup_tmr;
356     struct psp_gfx_cmd_load_ip_fw       cmd_load_ip_fw;
357     struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw;
358     struct psp_gfx_cmd_reg_prog       cmd_setup_reg_prog;
359     struct psp_gfx_cmd_setup_tmr        cmd_setup_vmr;
360     struct psp_gfx_cmd_load_toc         cmd_load_toc;
361     struct psp_gfx_cmd_boot_cfg         boot_cfg;
362     struct psp_gfx_cmd_sriov_spatial_part cmd_spatial_part;
363 };
364 
365 struct psp_gfx_uresp_reserved
366 {
367     uint32_t reserved[8];
368 };
369 
370 /* Command-specific response for Fw Attestation Db */
371 struct psp_gfx_uresp_fwar_db_info
372 {
373     uint32_t fwar_db_addr_lo;
374     uint32_t fwar_db_addr_hi;
375 };
376 
377 /* Command-specific response for boot config. */
378 struct psp_gfx_uresp_bootcfg {
379 	uint32_t boot_cfg;	/* boot config data */
380 };
381 
382 /* Union of command-specific responses for GPCOM ring. */
383 union psp_gfx_uresp {
384 	struct psp_gfx_uresp_reserved		reserved;
385 	struct psp_gfx_uresp_bootcfg		boot_cfg;
386 	struct psp_gfx_uresp_fwar_db_info	fwar_db_info;
387 };
388 
389 /* Structure of GFX Response buffer.
390 * For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI
391 * it is separate buffer.
392 */
393 struct psp_gfx_resp
394 {
395     uint32_t	status;		/* +0  status of command execution */
396     uint32_t	session_id;	/* +4  session ID in response to LoadTa command */
397     uint32_t	fw_addr_lo;	/* +8  bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */
398     uint32_t	fw_addr_hi;	/* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */
399     uint32_t	tmr_size;	/* +16 size of the TMR to be reserved including MM fw and Gfx fw in response to cmd_load_toc command */
400 
401     uint32_t	reserved[11];
402 
403     union psp_gfx_uresp uresp;      /* +64 response union containing command-specific responses */
404 
405     /* total 96 bytes */
406 };
407 
408 /* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi
409 *  and psp_gfx_rb_frame.cmd_buf_addr_lo.
410 */
411 struct psp_gfx_cmd_resp
412 {
413     uint32_t        buf_size;           /* +0  total size of the buffer in bytes */
414     uint32_t        buf_version;        /* +4  version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */
415     uint32_t        cmd_id;             /* +8  command ID */
416 
417     /* These fields are used for RBI only. They are all 0 in GPCOM commands
418     */
419     uint32_t        resp_buf_addr_lo;   /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */
420     uint32_t        resp_buf_addr_hi;   /* +16 bits [63:32] of GPU Virtual address of response buffer */
421     uint32_t        resp_offset;        /* +20 offset within response buffer */
422     uint32_t        resp_buf_size;      /* +24 total size of the response buffer in bytes */
423 
424     union psp_gfx_commands  cmd;        /* +28 command specific structures */
425 
426     uint8_t         reserved_1[864 - sizeof(union psp_gfx_commands) - 28];
427 
428     /* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response
429     *        is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo.
430     */
431     struct psp_gfx_resp     resp;       /* +864 response */
432 
433     uint8_t         reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];
434 
435     /* total size 1024 bytes */
436 };
437 
438 
439 #define FRAME_TYPE_DESTROY          1   /* frame sent by KMD driver when UMD Scheduler context is destroyed*/
440 
441 /* Structure of the Ring Buffer Frame */
442 struct psp_gfx_rb_frame
443 {
444     uint32_t    cmd_buf_addr_lo;    /* +0  bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */
445     uint32_t    cmd_buf_addr_hi;    /* +4  bits [63:32] of GPU Virtual address of command buffer */
446     uint32_t    cmd_buf_size;       /* +8  command buffer size in bytes */
447     uint32_t    fence_addr_lo;      /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */
448     uint32_t    fence_addr_hi;      /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */
449     uint32_t    fence_value;        /* +20 Fence value */
450     uint32_t    sid_lo;             /* +24 bits [31:0] of SID value (used only for RBI frames) */
451     uint32_t    sid_hi;             /* +28 bits [63:32] of SID value (used only for RBI frames) */
452     uint8_t     vmid;               /* +32 VMID value used for mapping of all addresses for this frame */
453     uint8_t     frame_type;         /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */
454     uint8_t     reserved1[2];       /* +34 reserved, must be 0 */
455     uint32_t    reserved2[7];       /* +36 reserved, must be 0 */
456                 /* total 64 bytes */
457 };
458 
459 #define PSP_ERR_UNKNOWN_COMMAND 0x00000100
460 
461 enum tee_error_code {
462     TEE_SUCCESS                         = 0x00000000,
463     TEE_ERROR_NOT_SUPPORTED             = 0xFFFF000A,
464 };
465 
466 #endif /* _PSP_TEE_GFX_IF_H_ */
467