1 //===-- TargetParser - Parser for target features ---------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a target parser to recognise hardware features such as 10 // FPU/CPU/ARCH names as well as specific support such as HDIV, etc. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef LLVM_SUPPORT_TARGETPARSER_H 15 #define LLVM_SUPPORT_TARGETPARSER_H 16 17 // FIXME: vector is used because that's what clang uses for subtarget feature 18 // lists, but SmallVector would probably be better 19 #include "llvm/ADT/Triple.h" 20 #include "llvm/Support/ARMTargetParser.h" 21 #include "llvm/Support/AArch64TargetParser.h" 22 #include <vector> 23 24 namespace llvm { 25 class StringRef; 26 27 // Target specific information in their own namespaces. 28 // (ARM/AArch64/X86 are declared in ARM/AArch64/X86TargetParser.h) 29 // These should be generated from TableGen because the information is already 30 // there, and there is where new information about targets will be added. 31 // FIXME: To TableGen this we need to make some table generated files available 32 // even if the back-end is not compiled with LLVM, plus we need to create a new 33 // back-end to TableGen to create these clean tables. 34 namespace AMDGPU { 35 36 /// GPU kinds supported by the AMDGPU target. 37 enum GPUKind : uint32_t { 38 // Not specified processor. 39 GK_NONE = 0, 40 41 // R600-based processors. 42 GK_R600 = 1, 43 GK_R630 = 2, 44 GK_RS880 = 3, 45 GK_RV670 = 4, 46 GK_RV710 = 5, 47 GK_RV730 = 6, 48 GK_RV770 = 7, 49 GK_CEDAR = 8, 50 GK_CYPRESS = 9, 51 GK_JUNIPER = 10, 52 GK_REDWOOD = 11, 53 GK_SUMO = 12, 54 GK_BARTS = 13, 55 GK_CAICOS = 14, 56 GK_CAYMAN = 15, 57 GK_TURKS = 16, 58 59 GK_R600_FIRST = GK_R600, 60 GK_R600_LAST = GK_TURKS, 61 62 // AMDGCN-based processors. 63 GK_GFX600 = 32, 64 GK_GFX601 = 33, 65 GK_GFX602 = 34, 66 67 GK_GFX700 = 40, 68 GK_GFX701 = 41, 69 GK_GFX702 = 42, 70 GK_GFX703 = 43, 71 GK_GFX704 = 44, 72 GK_GFX705 = 45, 73 74 GK_GFX801 = 50, 75 GK_GFX802 = 51, 76 GK_GFX803 = 52, 77 GK_GFX805 = 53, 78 GK_GFX810 = 54, 79 80 GK_GFX900 = 60, 81 GK_GFX902 = 61, 82 GK_GFX904 = 62, 83 GK_GFX906 = 63, 84 GK_GFX908 = 64, 85 GK_GFX909 = 65, 86 GK_GFX90A = 66, 87 GK_GFX90C = 67, 88 89 GK_GFX1010 = 71, 90 GK_GFX1011 = 72, 91 GK_GFX1012 = 73, 92 GK_GFX1030 = 75, 93 GK_GFX1031 = 76, 94 GK_GFX1032 = 77, 95 GK_GFX1033 = 78, 96 GK_GFX1034 = 79, 97 98 GK_AMDGCN_FIRST = GK_GFX600, 99 GK_AMDGCN_LAST = GK_GFX1034, 100 }; 101 102 /// Instruction set architecture version. 103 struct IsaVersion { 104 unsigned Major; 105 unsigned Minor; 106 unsigned Stepping; 107 }; 108 109 // This isn't comprehensive for now, just things that are needed from the 110 // frontend driver. 111 enum ArchFeatureKind : uint32_t { 112 FEATURE_NONE = 0, 113 114 // These features only exist for r600, and are implied true for amdgcn. 115 FEATURE_FMA = 1 << 1, 116 FEATURE_LDEXP = 1 << 2, 117 FEATURE_FP64 = 1 << 3, 118 119 // Common features. 120 FEATURE_FAST_FMA_F32 = 1 << 4, 121 FEATURE_FAST_DENORMAL_F32 = 1 << 5, 122 123 // Wavefront 32 is available. 124 FEATURE_WAVE32 = 1 << 6, 125 126 // Xnack is available. 127 FEATURE_XNACK = 1 << 7, 128 129 // Sram-ecc is available. 130 FEATURE_SRAMECC = 1 << 8, 131 }; 132 133 StringRef getArchNameAMDGCN(GPUKind AK); 134 StringRef getArchNameR600(GPUKind AK); 135 StringRef getCanonicalArchName(const Triple &T, StringRef Arch); 136 GPUKind parseArchAMDGCN(StringRef CPU); 137 GPUKind parseArchR600(StringRef CPU); 138 unsigned getArchAttrAMDGCN(GPUKind AK); 139 unsigned getArchAttrR600(GPUKind AK); 140 141 void fillValidArchListAMDGCN(SmallVectorImpl<StringRef> &Values); 142 void fillValidArchListR600(SmallVectorImpl<StringRef> &Values); 143 144 IsaVersion getIsaVersion(StringRef GPU); 145 146 } // namespace AMDGPU 147 148 namespace RISCV { 149 150 enum CPUKind : unsigned { 151 #define PROC(ENUM, NAME, FEATURES, DEFAULT_MARCH) CK_##ENUM, 152 #include "RISCVTargetParser.def" 153 }; 154 155 enum FeatureKind : unsigned { 156 FK_INVALID = 0, 157 FK_NONE = 1, 158 FK_STDEXTM = 1 << 2, 159 FK_STDEXTA = 1 << 3, 160 FK_STDEXTF = 1 << 4, 161 FK_STDEXTD = 1 << 5, 162 FK_STDEXTC = 1 << 6, 163 FK_64BIT = 1 << 7, 164 }; 165 166 bool checkCPUKind(CPUKind Kind, bool IsRV64); 167 bool checkTuneCPUKind(CPUKind Kind, bool IsRV64); 168 CPUKind parseCPUKind(StringRef CPU); 169 CPUKind parseTuneCPUKind(StringRef CPU, bool IsRV64); 170 StringRef getMArchFromMcpu(StringRef CPU); 171 void fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64); 172 void fillValidTuneCPUArchList(SmallVectorImpl<StringRef> &Values, bool IsRV64); 173 bool getCPUFeaturesExceptStdExt(CPUKind Kind, std::vector<StringRef> &Features); 174 StringRef resolveTuneCPUAlias(StringRef TuneCPU, bool IsRV64); 175 176 } // namespace RISCV 177 178 } // namespace llvm 179 180 #endif 181