1 /* $OpenBSD: dwqereg.h,v 1.10 2024/06/05 10:19:55 stsp Exp $ */ 2 /* 3 * Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org> 4 * Copyright (c) 2017, 2022 Patrick Wildt <patrick@blueri.se> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #define GMAC_MAC_CONF 0x0000 20 #define GMAC_MAC_CONF_IPC (1 << 27) 21 #define GMAC_MAC_CONF_CST (1 << 21) 22 #define GMAC_MAC_CONF_ACS (1 << 20) 23 #define GMAC_MAC_CONF_BE (1 << 18) 24 #define GMAC_MAC_CONF_JD (1 << 17) 25 #define GMAC_MAC_CONF_JE (1 << 16) 26 #define GMAC_MAC_CONF_PS (1 << 15) 27 #define GMAC_MAC_CONF_FES (1 << 14) 28 #define GMAC_MAC_CONF_DM (1 << 13) 29 #define GMAC_MAC_CONF_DCRS (1 << 9) 30 #define GMAC_MAC_CONF_TE (1 << 1) 31 #define GMAC_MAC_CONF_RE (1 << 0) 32 #define GMAC_MAC_PACKET_FILTER 0x0008 33 #define GMAC_MAC_PACKET_FILTER_HPF (1 << 10) 34 #define GMAC_MAC_PACKET_FILTER_PCF_MASK (3 << 6) 35 #define GMAC_MAC_PACKET_FILTER_PCF_ALL (2 << 6) 36 #define GMAC_MAC_PACKET_FILTER_DBF (1 << 5) 37 #define GMAC_MAC_PACKET_FILTER_PM (1 << 4) 38 #define GMAC_MAC_PACKET_FILTER_HMC (1 << 2) 39 #define GMAC_MAC_PACKET_FILTER_HUC (1 << 1) 40 #define GMAC_MAC_PACKET_FILTER_PR (1 << 0) 41 #define GMAC_MAC_HASH_TAB_REG0 0x0010 42 #define GMAC_MAC_HASH_TAB_REG1 0x0014 43 #define GMAC_INT_MASK 0x003c 44 #define GMAC_INT_MASK_LPIIM (1 << 10) 45 #define GMAC_INT_MASK_PIM (1 << 3) 46 #define GMAC_INT_MASK_RIM (1 << 0) 47 #define GMAC_VLAN_TAG_CTRL 0x0050 48 #define GMAC_VLAN_TAG_CTRL_EVLRXS (1 << 24) 49 #define GMAC_VLAN_TAG_CTRL_STRIP_ALWAYS ((1 << 21) | (1 << 22)) 50 #define GMAC_VLAN_TAG_DATA 0x0054 51 #define GMAC_VLAN_TAG_INCL 0x0060 52 #define GMAC_VLAN_TAG_INCL_VLTI (1 << 20) 53 #define GMAC_VLAN_TAG_INCL_CSVL (1 << 19) 54 #define GMAC_VLAN_TAG_INCL_DELETE 0x10000 55 #define GMAC_VLAN_TAG_INCL_INSERT 0x20000 56 #define GMAC_VLAN_TAG_INCL_REPLACE 0x30000 57 #define GMAC_VLAN_TAG_INCL_VLT 0x0ffff 58 #define GMAC_VLAN_TAG_INCL_RDWR (1U << 30) 59 #define GMAC_VLAN_TAG_INCL_BUSY (1U << 31) 60 #define GMAC_QX_TX_FLOW_CTRL(x) (0x0070 + (x) * 4) 61 #define GMAC_QX_TX_FLOW_CTRL_PT_SHIFT 16 62 #define GMAC_QX_TX_FLOW_CTRL_TFE (1 << 0) 63 #define GMAC_RX_FLOW_CTRL 0x0090 64 #define GMAC_RX_FLOW_CTRL_RFE (1 << 0) 65 #define GMAC_RXQ_CTRL0 0x00a0 66 #define GMAC_RXQ_CTRL0_QUEUE_CLR(x) (0x3 << ((x) * 2) 67 #define GMAC_RXQ_CTRL0_AVB_QUEUE_EN(x) (1 << ((x) * 2)) 68 #define GMAC_RXQ_CTRL0_DCB_QUEUE_EN(x) (2 << ((x) * 2)) 69 #define GMAC_RXQ_CTRL1 0x00a4 70 #define GMAC_RXQ_CTRL2 0x00a8 71 #define GMAC_RXQ_CTRL3 0x00ac 72 #define GMAC_INT_STATUS 0x00b0 73 #define GMAC_INT_EN 0x00b4 74 #define GMAC_MAC_1US_TIC_CTR 0x00dc 75 #define GMAC_VERSION 0x0110 76 #define GMAC_VERSION_SNPS_MASK 0xff 77 #define GMAC_MAC_HW_FEATURE(x) (0x011c + (x) * 0x4) 78 #define GMAC_MAC_HW_FEATURE0_TXCOESEL (1 << 14) 79 #define GMAC_MAC_HW_FEATURE0_RXCOESEL (1 << 16) 80 #define GMAC_MAC_HW_FEATURE0_SAVLANINS (1 << 27) 81 #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(x) (((x) >> 6) & 0x1f) 82 #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(x) (((x) >> 0) & 0x1f) 83 #define GMAC_MAC_MDIO_ADDR 0x0200 84 #define GMAC_MAC_MDIO_ADDR_PA_SHIFT 21 85 #define GMAC_MAC_MDIO_ADDR_RDA_SHIFT 16 86 #define GMAC_MAC_MDIO_ADDR_CR_SHIFT 8 87 #define GMAC_MAC_MDIO_ADDR_CR_60_100 0 88 #define GMAC_MAC_MDIO_ADDR_CR_100_150 1 89 #define GMAC_MAC_MDIO_ADDR_CR_20_35 2 90 #define GMAC_MAC_MDIO_ADDR_CR_35_60 3 91 #define GMAC_MAC_MDIO_ADDR_CR_150_250 4 92 #define GMAC_MAC_MDIO_ADDR_CR_250_300 5 93 #define GMAC_MAC_MDIO_ADDR_CR_300_500 6 94 #define GMAC_MAC_MDIO_ADDR_CR_500_800 7 95 #define GMAC_MAC_MDIO_ADDR_SKAP (1 << 4) 96 #define GMAC_MAC_MDIO_ADDR_GOC_READ (3 << 2) 97 #define GMAC_MAC_MDIO_ADDR_GOC_WRITE (1 << 2) 98 #define GMAC_MAC_MDIO_ADDR_C45E (1 << 1) 99 #define GMAC_MAC_MDIO_ADDR_GB (1 << 0) 100 #define GMAC_MAC_MDIO_DATA 0x0204 101 #define GMAC_MAC_ADDR0_HI 0x0300 102 #define GMAC_MAC_ADDR0_LO 0x0304 103 #define GMAC_MMC_RX_INT_MASK 0x070c 104 #define GMAC_MMC_TX_INT_MASK 0x0710 105 106 #define GMAC_MTL_OPERATION_MODE 0x0c00 107 #define GMAC_MTL_FRPE (1 << 15) 108 #define GMAC_MTL_OPERATION_SCHALG_MASK (0x3 << 5) 109 #define GMAC_MTL_OPERATION_SCHALG_WRR (0x0 << 5) 110 #define GMAC_MTL_OPERATION_SCHALG_WFQ (0x1 << 5) 111 #define GMAC_MTL_OPERATION_SCHALG_DWRR (0x2 << 5) 112 #define GMAC_MTL_OPERATION_SCHALG_SP (0x3 << 5) 113 #define GMAC_MTL_OPERATION_RAA_MASK (0x1 << 2) 114 #define GMAC_MTL_OPERATION_RAA_SP (0x0 << 2) 115 #define GMAC_MTL_OPERATION_RAA_WSP (0x1 << 2) 116 117 #define GMAC_MTL_CHAN_BASE_ADDR(x) (0x0d00 + (x) * 0x40) 118 #define GMAC_MTL_CHAN_TX_OP_MODE(x) (GMAC_MTL_CHAN_BASE_ADDR(x) + 0x0) 119 #define GMAC_MTL_CHAN_TX_OP_MODE_TQS_MASK (0x1ffU << 16) 120 #define GMAC_MTL_CHAN_TX_OP_MODE_TQS_SHIFT 16 121 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_MASK (0x7 << 4) 122 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_SHIFT 4 123 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_32 0 124 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_64 (1 << 4) 125 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_96 (2 << 4) 126 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_128 (3 << 4) 127 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_192 (4 << 4) 128 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_256 (5 << 4) 129 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_384 (6 << 4) 130 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_512 (7 << 4) 131 #define GMAC_MTL_CHAN_TX_OP_MODE_TXQEN_MASK (0x3 << 2) 132 #define GMAC_MTL_CHAN_TX_OP_MODE_TXQEN_AV (1 << 2) 133 #define GMAC_MTL_CHAN_TX_OP_MODE_TXQEN (2 << 2) 134 #define GMAC_MTL_CHAN_TX_OP_MODE_TSF (1 << 1) 135 #define GMAC_MTL_CHAN_TX_OP_MODE_FTQ (1 << 0) 136 #define GMAC_MTL_CHAN_TX_DEBUG(x) (GMAC_MTL_CHAN_BASE_ADDR(x) + 0x8) 137 #define GMAC_MTL_CHAN_INT_CTRL(x) (GMAC_MTL_CHAN_BASE_ADDR(x) + 0x2c) 138 #define GMAC_MTL_CHAN_RX_OP_MODE(x) (GMAC_MTL_CHAN_BASE_ADDR(x) + 0x30) 139 #define GMAC_MTL_CHAN_RX_OP_MODE_RQS_MASK (0x3ffU << 20) 140 #define GMAC_MTL_CHAN_RX_OP_MODE_RQS_SHIFT 20 141 #define GMAC_MTL_CHAN_RX_OP_MODE_RFD_MASK (0x3fU << 14) 142 #define GMAC_MTL_CHAN_RX_OP_MODE_RFD_SHIFT 14 143 #define GMAC_MTL_CHAN_RX_OP_MODE_RFA_MASK (0x3fU << 8) 144 #define GMAC_MTL_CHAN_RX_OP_MODE_RFA_SHIFT 8 145 #define GMAC_MTL_CHAN_RX_OP_MODE_EHFC (1 << 7) 146 #define GMAC_MTL_CHAN_RX_OP_MODE_RSF (1 << 5) 147 #define GMAC_MTL_CHAN_RX_OP_MODE_RTC_MASK (0x3 << 3) 148 #define GMAC_MTL_CHAN_RX_OP_MODE_RTC_SHIFT 3 149 #define GMAC_MTL_CHAN_RX_OP_MODE_RTC_32 (1 << 3) 150 #define GMAC_MTL_CHAN_RX_OP_MODE_RTC_64 (0 << 3) 151 #define GMAC_MTL_CHAN_RX_OP_MODE_RTC_96 (2 << 3) 152 #define GMAC_MTL_CHAN_RX_OP_MODE_RTC_128 (3 << 3) 153 #define GMAC_MTL_CHAN_RX_DEBUG(x) (GMAC_MTL_CHAN_BASE_ADDR(x) + 0x38) 154 155 #define GMAC_BUS_MODE 0x1000 156 #define GMAC_BUS_MODE_DCHE (1 << 19) 157 #define GMAC_BUS_MODE_SWR (1 << 0) 158 #define GMAC_SYS_BUS_MODE 0x1004 159 #define GMAC_SYS_BUS_MODE_EN_LPI (1U << 31) 160 #define GMAC_SYS_BUS_MODE_LPI_XIT_FRM (1 << 30) 161 #define GMAC_SYS_BUS_MODE_WR_OSR_LMT_MASK (0xf << 24) 162 #define GMAC_SYS_BUS_MODE_WR_OSR_LMT_SHIFT 24 163 #define GMAC_SYS_BUS_MODE_RD_OSR_LMT_MASK (0xf << 16) 164 #define GMAC_SYS_BUS_MODE_RD_OSR_LMT_SHIFT 16 165 #define GMAC_SYS_BUS_MODE_MB (1 << 14) 166 #define GMAC_SYS_BUS_MODE_AAL (1 << 12) 167 #define GMAC_SYS_BUS_MODE_EAME (1 << 11) 168 #define GMAC_SYS_BUS_MODE_BLEN_256 (1 << 7) 169 #define GMAC_SYS_BUS_MODE_BLEN_128 (1 << 6) 170 #define GMAC_SYS_BUS_MODE_BLEN_64 (1 << 5) 171 #define GMAC_SYS_BUS_MODE_BLEN_32 (1 << 4) 172 #define GMAC_SYS_BUS_MODE_BLEN_16 (1 << 3) 173 #define GMAC_SYS_BUS_MODE_BLEN_8 (1 << 2) 174 #define GMAC_SYS_BUS_MODE_BLEN_4 (1 << 1) 175 #define GMAC_SYS_BUS_MODE_FB (1 << 0) 176 177 #define GMAC_CHAN_BASE_ADDR(x) (0x1100 + (x) * 0x80) 178 #define GMAC_CHAN_CONTROL(x) (GMAC_CHAN_BASE_ADDR(x) + 0x0) 179 #define GMAC_CHAN_CONTROL_8XPBL (1 << 16) 180 #define GMAC_CHAN_TX_CONTROL(x) (GMAC_CHAN_BASE_ADDR(x) + 0x4) 181 #define GMAC_CHAN_TX_CONTROL_PBL_MASK (0x3f << 16) 182 #define GMAC_CHAN_TX_CONTROL_PBL_SHIFT 16 183 #define GMAC_CHAN_TX_CONTROL_OSP (1 << 4) 184 #define GMAC_CHAN_TX_CONTROL_ST (1 << 0) 185 #define GMAC_CHAN_RX_CONTROL(x) (GMAC_CHAN_BASE_ADDR(x) + 0x8) 186 #define GMAC_CHAN_RX_CONTROL_RPBL_MASK (0x3f << 16) 187 #define GMAC_CHAN_RX_CONTROL_RPBL_SHIFT 16 188 #define GMAC_CHAN_RX_CONTROL_SR (1 << 0) 189 #define GMAC_CHAN_TX_BASE_ADDR_HI(x) (GMAC_CHAN_BASE_ADDR(x) + 0x10) 190 #define GMAC_CHAN_TX_BASE_ADDR(x) (GMAC_CHAN_BASE_ADDR(x) + 0x14) 191 #define GMAC_CHAN_RX_BASE_ADDR_HI(x) (GMAC_CHAN_BASE_ADDR(x) + 0x18) 192 #define GMAC_CHAN_RX_BASE_ADDR(x) (GMAC_CHAN_BASE_ADDR(x) + 0x1c) 193 #define GMAC_CHAN_TX_END_ADDR(x) (GMAC_CHAN_BASE_ADDR(x) + 0x20) 194 #define GMAC_CHAN_RX_END_ADDR(x) (GMAC_CHAN_BASE_ADDR(x) + 0x28) 195 #define GMAC_CHAN_TX_RING_LEN(x) (GMAC_CHAN_BASE_ADDR(x) + 0x2c) 196 #define GMAC_CHAN_RX_RING_LEN(x) (GMAC_CHAN_BASE_ADDR(x) + 0x30) 197 #define GMAC_CHAN_INTR_ENA(x) (GMAC_CHAN_BASE_ADDR(x) + 0x34) 198 #define GMAC_CHAN_INTR_ENA_NIE (1 << 15) 199 #define GMAC_CHAN_INTR_ENA_AIE (1 << 14) 200 #define GMAC_CHAN_INTR_ENA_CDE (1 << 13) 201 #define GMAC_CHAN_INTR_ENA_FBE (1 << 12) 202 #define GMAC_CHAN_INTR_ENA_ERE (1 << 11) 203 #define GMAC_CHAN_INTR_ENA_ETE (1 << 10) 204 #define GMAC_CHAN_INTR_ENA_RWE (1 << 9) 205 #define GMAC_CHAN_INTR_ENA_RSE (1 << 8) 206 #define GMAC_CHAN_INTR_ENA_RBUE (1 << 7) 207 #define GMAC_CHAN_INTR_ENA_RIE (1 << 6) 208 #define GMAC_CHAN_INTR_ENA_TBUE (1 << 2) 209 #define GMAC_CHAN_INTR_ENA_TSE (1 << 1) 210 #define GMAC_CHAN_INTR_ENA_TIE (1 << 0) 211 #define GMAC_CHAN_RX_WATCHDOG(x) (GMAC_CHAN_CONTROL(x) + 0x38) 212 #define GMAC_CHAN_SLOT_CTRL_STATUS(x) (GMAC_CHAN_CONTROL(x) + 0x3c) 213 #define GMAC_CHAN_CUR_TX_DESC(x) (GMAC_CHAN_CONTROL(x) + 0x44) 214 #define GMAC_CHAN_CUR_RX_DESC(x) (GMAC_CHAN_CONTROL(x) + 0x4c) 215 #define GMAC_CHAN_CUR_TX_BUF_ADDR(x) (GMAC_CHAN_CONTROL(x) + 0x54) 216 #define GMAC_CHAN_CUR_RX_BUF_ADDR(x) (GMAC_CHAN_CONTROL(x) + 0x5c) 217 #define GMAC_CHAN_STATUS(x) (GMAC_CHAN_CONTROL(x) + 0x60) 218 #define GMAC_CHAN_STATUS_REB_MASK 0x7 219 #define GMAC_CHAN_STATUS_REB_SHIFT 19 220 #define GMAC_CHAN_STATUS_TEB_MASK 0x7 221 #define GMAC_CHAN_STATUS_TEB_SHIFT 16 222 #define GMAC_CHAN_STATUS_NIS (1 << 15) 223 #define GMAC_CHAN_STATUS_AIS (1 << 14) 224 #define GMAC_CHAN_STATUS_CDE (1 << 13) 225 #define GMAC_CHAN_STATUS_FBE (1 << 12) 226 #define GMAC_CHAN_STATUS_ERI (1 << 11) 227 #define GMAC_CHAN_STATUS_ETI (1 << 10) 228 #define GMAC_CHAN_STATUS_RWT (1 << 9) 229 #define GMAC_CHAN_STATUS_RPS (1 << 8) 230 #define GMAC_CHAN_STATUS_RBU (1 << 7) 231 #define GMAC_CHAN_STATUS_RI (1 << 6) 232 #define GMAC_CHAN_STATUS_TBU (1 << 2) 233 #define GMAC_CHAN_STATUS_TPS (1 << 1) 234 #define GMAC_CHAN_STATUS_TI (1 << 0) 235 236 /* 237 * DWQE descriptors. 238 */ 239 240 struct dwqe_desc { 241 uint32_t sd_tdes0; 242 uint32_t sd_tdes1; 243 uint32_t sd_tdes2; 244 uint32_t sd_tdes3; 245 }; 246 247 /* Tx context descriptor bits (host to device); precedes regular descriptor */ 248 #define TDES3_CTXT (1 << 30) 249 #define TDES3_VLAN_TAG_VALID (1 << 16) 250 #define TDES3_VLAN_TAG 0xffff 251 /* Bit 31 is the OWN bit, as in regular Tx descriptor. */ 252 253 /* Tx bits (read format; host to device) */ 254 #define TDES2_HDR_LEN 0x000003ff /* if TSO is enabled */ 255 #define TDES2_BUF1_LEN 0x00003fff /* if TSO is disabled */ 256 #define TDES2_VLAN_TIR 0x0000c000 257 #define TDES2_NO_VLAN_TAGGING (0x0 << 14) 258 #define TDES2_VLAN_TAG_STRIP (0x1 << 14) 259 #define TDES2_VLAN_TAG_INSERT (0x2 << 14) 260 #define TDES2_VLAN_TAG_REPLACE (0x3 << 14) 261 #define TDES2_BUF2_LEN 0x3fff0000 262 #define TDES2_TX_TIMESTAMP_EN (1 << 30) /* if TSO is disabled */ 263 #define TDES2_TSO_EXTMEM_DIS (1 << 30) /* if TSO is enabled */ 264 #define TDES2_IC (1U << 31) 265 #define TDES3_TCP_PAYLOAD_LEN 0x0003ffff /* if TSO is enabled */ 266 #define TDES3_FRAME_LEN 0x00007fff /* if TSO is disabled */ 267 #define TDES3_CIC 0x00030000 /* if TSO is disabled */ 268 #define TDES3_CSUM_DISABLE (0x0 << 16) 269 #define TDES3_CSUM_IPHDR (0x1 << 16) 270 #define TDES3_CSUM_IPHDR_PAYLOAD (0x2 << 16) 271 #define TDES3_CSUM_IPHDR_PAYLOAD_PSEUDOHDR (0x3 << 16) 272 #define TDES3_TSO_EN (1 << 18) 273 #define TDES3_CPC ((1 << 26) | (1 << 27)) /* if TSO is disabled */ 274 #define TDES3_CPC_CRC_AND_PAD (0x0 << 26) 275 #define TDES3_CPC_CRC_NO_PAD (0x1 << 26) 276 #define TDES3_CPC_DISABLE (0x2 << 26) 277 #define TDES3_CPC_CRC_REPLACE (0x3 << 26) 278 #define TDES3_LS (1 << 28) 279 #define TDES3_FS (1 << 29) 280 #define TDES3_OWN (1U << 31) 281 282 /* Tx bits (writeback format; device to host) */ 283 #define TDES3_ES (1 << 15) 284 #define TDES3_DE (1 << 23) 285 /* Bit 28 is the LS bit, as in "read" format. */ 286 /* Bit 29 is the FS bit, as in "read" format. */ 287 /* Bit 31 is the OWN bit, as in "read" format. */ 288 289 /* Rx bits (read format; host to device) */ 290 #define RDES3_BUF1V (1 << 24) 291 #define RDES3_BUF2V (1 << 25) 292 #define RDES3_IC (1 << 30) 293 #define RDES3_OWN (1U << 31) 294 295 /* Rx bits (writeback format; device to host) */ 296 #define RDES0_IVT 0xffff0000 297 #define RDES0_OVT 0x0000ffff 298 #define RDES1_IP_PAYLOAD_TYPE 0x7 299 #define RDES1_IP_PAYLOAD_UNKNOWN 0x0 300 #define RDES1_IP_PAYLOAD_UDP 0x1 301 #define RDES1_IP_PAYLOAD_TCP 0x2 302 #define RDES1_IP_PAYLOAD_ICMP 0x3 303 #define RDES1_IP_HDR_ERROR (1 << 3) 304 #define RDES1_IPV4_HDR (1 << 4) 305 #define RDES1_IPV6_HDR (1 << 5) 306 #define RDES1_IP_CSUM_BYPASS (1 << 6) 307 #define RDES1_IP_PAYLOAD_ERROR (1 << 7) 308 #define RDES3_LENGTH (0x7fff << 0) 309 #define RDES3_ES (1 << 15) 310 #define RDES3_LENTYPE 0x70000 311 #define RDES3_LENTYPE_LENGTH (0x0 << 16) 312 #define RDES3_LENTYPE_TYPE (0x1 << 16) 313 /* 0x2 is reserved */ 314 #define RDES3_LENTYPE_ARP (0x3 << 16) 315 #define RDES3_LENTYPE_VLAN (0x4 << 16) 316 #define RDES3_LENTYPE_2VLAN (0x5 << 16) 317 #define RDES3_LENTYPE_MACCTL (0x6 << 16) 318 #define RDES3_LENTYPE_OAM (0x7 << 16) 319 #define RDES3_DE (1 << 19) 320 #define RDES3_RE (1 << 20) 321 #define RDES3_OE (1 << 21) 322 #define RDES3_RWT (1 << 22) 323 #define RDES3_GP (1 << 23) 324 #define RDES3_CE (1 << 24) 325 #define RDES3_RDES0_VALID (1 << 25) 326 #define RDES3_RDES1_VALID (1 << 26) 327 #define RDES3_RDES2_VALID (1 << 27) 328 #define RDES3_LD (1 << 28) 329 #define RDES3_FD (1 << 29) 330 #define RDES3_CTXT (1 << 30) 331 /* Bit 31 is the OWN bit, as in "read" format. */ 332