1 /* $OpenBSD: dwqereg.h,v 1.9 2024/05/06 09:54:38 stsp Exp $ */ 2 /* 3 * Copyright (c) 2008, 2019 Mark Kettenis <kettenis@openbsd.org> 4 * Copyright (c) 2017, 2022 Patrick Wildt <patrick@blueri.se> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #define GMAC_MAC_CONF 0x0000 20 #define GMAC_MAC_CONF_IPC (1 << 27) 21 #define GMAC_MAC_CONF_CST (1 << 21) 22 #define GMAC_MAC_CONF_ACS (1 << 20) 23 #define GMAC_MAC_CONF_BE (1 << 18) 24 #define GMAC_MAC_CONF_JD (1 << 17) 25 #define GMAC_MAC_CONF_JE (1 << 16) 26 #define GMAC_MAC_CONF_PS (1 << 15) 27 #define GMAC_MAC_CONF_FES (1 << 14) 28 #define GMAC_MAC_CONF_DM (1 << 13) 29 #define GMAC_MAC_CONF_DCRS (1 << 9) 30 #define GMAC_MAC_CONF_TE (1 << 1) 31 #define GMAC_MAC_CONF_RE (1 << 0) 32 #define GMAC_MAC_PACKET_FILTER 0x0008 33 #define GMAC_MAC_PACKET_FILTER_HPF (1 << 10) 34 #define GMAC_MAC_PACKET_FILTER_PCF_MASK (3 << 6) 35 #define GMAC_MAC_PACKET_FILTER_PCF_ALL (2 << 6) 36 #define GMAC_MAC_PACKET_FILTER_DBF (1 << 5) 37 #define GMAC_MAC_PACKET_FILTER_PM (1 << 4) 38 #define GMAC_MAC_PACKET_FILTER_HMC (1 << 2) 39 #define GMAC_MAC_PACKET_FILTER_HUC (1 << 1) 40 #define GMAC_MAC_PACKET_FILTER_PR (1 << 0) 41 #define GMAC_MAC_HASH_TAB_REG0 0x0010 42 #define GMAC_MAC_HASH_TAB_REG1 0x0014 43 #define GMAC_INT_MASK 0x003c 44 #define GMAC_INT_MASK_LPIIM (1 << 10) 45 #define GMAC_INT_MASK_PIM (1 << 3) 46 #define GMAC_INT_MASK_RIM (1 << 0) 47 #define GMAC_QX_TX_FLOW_CTRL(x) (0x0070 + (x) * 4) 48 #define GMAC_QX_TX_FLOW_CTRL_PT_SHIFT 16 49 #define GMAC_QX_TX_FLOW_CTRL_TFE (1 << 0) 50 #define GMAC_RX_FLOW_CTRL 0x0090 51 #define GMAC_RX_FLOW_CTRL_RFE (1 << 0) 52 #define GMAC_RXQ_CTRL0 0x00a0 53 #define GMAC_RXQ_CTRL0_QUEUE_CLR(x) (0x3 << ((x) * 2) 54 #define GMAC_RXQ_CTRL0_AVB_QUEUE_EN(x) (1 << ((x) * 2)) 55 #define GMAC_RXQ_CTRL0_DCB_QUEUE_EN(x) (2 << ((x) * 2)) 56 #define GMAC_RXQ_CTRL1 0x00a4 57 #define GMAC_RXQ_CTRL2 0x00a8 58 #define GMAC_RXQ_CTRL3 0x00ac 59 #define GMAC_INT_STATUS 0x00b0 60 #define GMAC_INT_EN 0x00b4 61 #define GMAC_MAC_1US_TIC_CTR 0x00dc 62 #define GMAC_VERSION 0x0110 63 #define GMAC_VERSION_SNPS_MASK 0xff 64 #define GMAC_MAC_HW_FEATURE(x) (0x011c + (x) * 0x4) 65 #define GMAC_MAC_HW_FEATURE0_TXCOESEL (1 << 14) 66 #define GMAC_MAC_HW_FEATURE0_RXCOESEL (1 << 16) 67 #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE(x) (((x) >> 6) & 0x1f) 68 #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE(x) (((x) >> 0) & 0x1f) 69 #define GMAC_MAC_MDIO_ADDR 0x0200 70 #define GMAC_MAC_MDIO_ADDR_PA_SHIFT 21 71 #define GMAC_MAC_MDIO_ADDR_RDA_SHIFT 16 72 #define GMAC_MAC_MDIO_ADDR_CR_SHIFT 8 73 #define GMAC_MAC_MDIO_ADDR_CR_60_100 0 74 #define GMAC_MAC_MDIO_ADDR_CR_100_150 1 75 #define GMAC_MAC_MDIO_ADDR_CR_20_35 2 76 #define GMAC_MAC_MDIO_ADDR_CR_35_60 3 77 #define GMAC_MAC_MDIO_ADDR_CR_150_250 4 78 #define GMAC_MAC_MDIO_ADDR_CR_250_300 5 79 #define GMAC_MAC_MDIO_ADDR_CR_300_500 6 80 #define GMAC_MAC_MDIO_ADDR_CR_500_800 7 81 #define GMAC_MAC_MDIO_ADDR_SKAP (1 << 4) 82 #define GMAC_MAC_MDIO_ADDR_GOC_READ (3 << 2) 83 #define GMAC_MAC_MDIO_ADDR_GOC_WRITE (1 << 2) 84 #define GMAC_MAC_MDIO_ADDR_C45E (1 << 1) 85 #define GMAC_MAC_MDIO_ADDR_GB (1 << 0) 86 #define GMAC_MAC_MDIO_DATA 0x0204 87 #define GMAC_MAC_ADDR0_HI 0x0300 88 #define GMAC_MAC_ADDR0_LO 0x0304 89 #define GMAC_MMC_RX_INT_MASK 0x070c 90 #define GMAC_MMC_TX_INT_MASK 0x0710 91 92 #define GMAC_MTL_OPERATION_MODE 0x0c00 93 #define GMAC_MTL_FRPE (1 << 15) 94 #define GMAC_MTL_OPERATION_SCHALG_MASK (0x3 << 5) 95 #define GMAC_MTL_OPERATION_SCHALG_WRR (0x0 << 5) 96 #define GMAC_MTL_OPERATION_SCHALG_WFQ (0x1 << 5) 97 #define GMAC_MTL_OPERATION_SCHALG_DWRR (0x2 << 5) 98 #define GMAC_MTL_OPERATION_SCHALG_SP (0x3 << 5) 99 #define GMAC_MTL_OPERATION_RAA_MASK (0x1 << 2) 100 #define GMAC_MTL_OPERATION_RAA_SP (0x0 << 2) 101 #define GMAC_MTL_OPERATION_RAA_WSP (0x1 << 2) 102 103 #define GMAC_MTL_CHAN_BASE_ADDR(x) (0x0d00 + (x) * 0x40) 104 #define GMAC_MTL_CHAN_TX_OP_MODE(x) (GMAC_MTL_CHAN_BASE_ADDR(x) + 0x0) 105 #define GMAC_MTL_CHAN_TX_OP_MODE_TQS_MASK (0x1ffU << 16) 106 #define GMAC_MTL_CHAN_TX_OP_MODE_TQS_SHIFT 16 107 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_MASK (0x7 << 4) 108 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_SHIFT 4 109 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_32 0 110 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_64 (1 << 4) 111 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_96 (2 << 4) 112 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_128 (3 << 4) 113 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_192 (4 << 4) 114 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_256 (5 << 4) 115 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_384 (6 << 4) 116 #define GMAC_MTL_CHAN_TX_OP_MODE_TTC_512 (7 << 4) 117 #define GMAC_MTL_CHAN_TX_OP_MODE_TXQEN_MASK (0x3 << 2) 118 #define GMAC_MTL_CHAN_TX_OP_MODE_TXQEN_AV (1 << 2) 119 #define GMAC_MTL_CHAN_TX_OP_MODE_TXQEN (2 << 2) 120 #define GMAC_MTL_CHAN_TX_OP_MODE_TSF (1 << 1) 121 #define GMAC_MTL_CHAN_TX_OP_MODE_FTQ (1 << 0) 122 #define GMAC_MTL_CHAN_TX_DEBUG(x) (GMAC_MTL_CHAN_BASE_ADDR(x) + 0x8) 123 #define GMAC_MTL_CHAN_INT_CTRL(x) (GMAC_MTL_CHAN_BASE_ADDR(x) + 0x2c) 124 #define GMAC_MTL_CHAN_RX_OP_MODE(x) (GMAC_MTL_CHAN_BASE_ADDR(x) + 0x30) 125 #define GMAC_MTL_CHAN_RX_OP_MODE_RQS_MASK (0x3ffU << 20) 126 #define GMAC_MTL_CHAN_RX_OP_MODE_RQS_SHIFT 20 127 #define GMAC_MTL_CHAN_RX_OP_MODE_RFD_MASK (0x3fU << 14) 128 #define GMAC_MTL_CHAN_RX_OP_MODE_RFD_SHIFT 14 129 #define GMAC_MTL_CHAN_RX_OP_MODE_RFA_MASK (0x3fU << 8) 130 #define GMAC_MTL_CHAN_RX_OP_MODE_RFA_SHIFT 8 131 #define GMAC_MTL_CHAN_RX_OP_MODE_EHFC (1 << 7) 132 #define GMAC_MTL_CHAN_RX_OP_MODE_RSF (1 << 5) 133 #define GMAC_MTL_CHAN_RX_OP_MODE_RTC_MASK (0x3 << 3) 134 #define GMAC_MTL_CHAN_RX_OP_MODE_RTC_SHIFT 3 135 #define GMAC_MTL_CHAN_RX_OP_MODE_RTC_32 (1 << 3) 136 #define GMAC_MTL_CHAN_RX_OP_MODE_RTC_64 (0 << 3) 137 #define GMAC_MTL_CHAN_RX_OP_MODE_RTC_96 (2 << 3) 138 #define GMAC_MTL_CHAN_RX_OP_MODE_RTC_128 (3 << 3) 139 #define GMAC_MTL_CHAN_RX_DEBUG(x) (GMAC_MTL_CHAN_BASE_ADDR(x) + 0x38) 140 141 #define GMAC_BUS_MODE 0x1000 142 #define GMAC_BUS_MODE_DCHE (1 << 19) 143 #define GMAC_BUS_MODE_SWR (1 << 0) 144 #define GMAC_SYS_BUS_MODE 0x1004 145 #define GMAC_SYS_BUS_MODE_EN_LPI (1U << 31) 146 #define GMAC_SYS_BUS_MODE_LPI_XIT_FRM (1 << 30) 147 #define GMAC_SYS_BUS_MODE_WR_OSR_LMT_MASK (0xf << 24) 148 #define GMAC_SYS_BUS_MODE_WR_OSR_LMT_SHIFT 24 149 #define GMAC_SYS_BUS_MODE_RD_OSR_LMT_MASK (0xf << 16) 150 #define GMAC_SYS_BUS_MODE_RD_OSR_LMT_SHIFT 16 151 #define GMAC_SYS_BUS_MODE_MB (1 << 14) 152 #define GMAC_SYS_BUS_MODE_AAL (1 << 12) 153 #define GMAC_SYS_BUS_MODE_EAME (1 << 11) 154 #define GMAC_SYS_BUS_MODE_BLEN_256 (1 << 7) 155 #define GMAC_SYS_BUS_MODE_BLEN_128 (1 << 6) 156 #define GMAC_SYS_BUS_MODE_BLEN_64 (1 << 5) 157 #define GMAC_SYS_BUS_MODE_BLEN_32 (1 << 4) 158 #define GMAC_SYS_BUS_MODE_BLEN_16 (1 << 3) 159 #define GMAC_SYS_BUS_MODE_BLEN_8 (1 << 2) 160 #define GMAC_SYS_BUS_MODE_BLEN_4 (1 << 1) 161 #define GMAC_SYS_BUS_MODE_FB (1 << 0) 162 163 #define GMAC_CHAN_BASE_ADDR(x) (0x1100 + (x) * 0x80) 164 #define GMAC_CHAN_CONTROL(x) (GMAC_CHAN_BASE_ADDR(x) + 0x0) 165 #define GMAC_CHAN_CONTROL_8XPBL (1 << 16) 166 #define GMAC_CHAN_TX_CONTROL(x) (GMAC_CHAN_BASE_ADDR(x) + 0x4) 167 #define GMAC_CHAN_TX_CONTROL_PBL_MASK (0x3f << 16) 168 #define GMAC_CHAN_TX_CONTROL_PBL_SHIFT 16 169 #define GMAC_CHAN_TX_CONTROL_OSP (1 << 4) 170 #define GMAC_CHAN_TX_CONTROL_ST (1 << 0) 171 #define GMAC_CHAN_RX_CONTROL(x) (GMAC_CHAN_BASE_ADDR(x) + 0x8) 172 #define GMAC_CHAN_RX_CONTROL_RPBL_MASK (0x3f << 16) 173 #define GMAC_CHAN_RX_CONTROL_RPBL_SHIFT 16 174 #define GMAC_CHAN_RX_CONTROL_SR (1 << 0) 175 #define GMAC_CHAN_TX_BASE_ADDR_HI(x) (GMAC_CHAN_BASE_ADDR(x) + 0x10) 176 #define GMAC_CHAN_TX_BASE_ADDR(x) (GMAC_CHAN_BASE_ADDR(x) + 0x14) 177 #define GMAC_CHAN_RX_BASE_ADDR_HI(x) (GMAC_CHAN_BASE_ADDR(x) + 0x18) 178 #define GMAC_CHAN_RX_BASE_ADDR(x) (GMAC_CHAN_BASE_ADDR(x) + 0x1c) 179 #define GMAC_CHAN_TX_END_ADDR(x) (GMAC_CHAN_BASE_ADDR(x) + 0x20) 180 #define GMAC_CHAN_RX_END_ADDR(x) (GMAC_CHAN_BASE_ADDR(x) + 0x28) 181 #define GMAC_CHAN_TX_RING_LEN(x) (GMAC_CHAN_BASE_ADDR(x) + 0x2c) 182 #define GMAC_CHAN_RX_RING_LEN(x) (GMAC_CHAN_BASE_ADDR(x) + 0x30) 183 #define GMAC_CHAN_INTR_ENA(x) (GMAC_CHAN_BASE_ADDR(x) + 0x34) 184 #define GMAC_CHAN_INTR_ENA_NIE (1 << 15) 185 #define GMAC_CHAN_INTR_ENA_AIE (1 << 14) 186 #define GMAC_CHAN_INTR_ENA_CDE (1 << 13) 187 #define GMAC_CHAN_INTR_ENA_FBE (1 << 12) 188 #define GMAC_CHAN_INTR_ENA_ERE (1 << 11) 189 #define GMAC_CHAN_INTR_ENA_ETE (1 << 10) 190 #define GMAC_CHAN_INTR_ENA_RWE (1 << 9) 191 #define GMAC_CHAN_INTR_ENA_RSE (1 << 8) 192 #define GMAC_CHAN_INTR_ENA_RBUE (1 << 7) 193 #define GMAC_CHAN_INTR_ENA_RIE (1 << 6) 194 #define GMAC_CHAN_INTR_ENA_TBUE (1 << 2) 195 #define GMAC_CHAN_INTR_ENA_TSE (1 << 1) 196 #define GMAC_CHAN_INTR_ENA_TIE (1 << 0) 197 #define GMAC_CHAN_RX_WATCHDOG(x) (GMAC_CHAN_CONTROL(x) + 0x38) 198 #define GMAC_CHAN_SLOT_CTRL_STATUS(x) (GMAC_CHAN_CONTROL(x) + 0x3c) 199 #define GMAC_CHAN_CUR_TX_DESC(x) (GMAC_CHAN_CONTROL(x) + 0x44) 200 #define GMAC_CHAN_CUR_RX_DESC(x) (GMAC_CHAN_CONTROL(x) + 0x4c) 201 #define GMAC_CHAN_CUR_TX_BUF_ADDR(x) (GMAC_CHAN_CONTROL(x) + 0x54) 202 #define GMAC_CHAN_CUR_RX_BUF_ADDR(x) (GMAC_CHAN_CONTROL(x) + 0x5c) 203 #define GMAC_CHAN_STATUS(x) (GMAC_CHAN_CONTROL(x) + 0x60) 204 #define GMAC_CHAN_STATUS_REB_MASK 0x7 205 #define GMAC_CHAN_STATUS_REB_SHIFT 19 206 #define GMAC_CHAN_STATUS_TEB_MASK 0x7 207 #define GMAC_CHAN_STATUS_TEB_SHIFT 16 208 #define GMAC_CHAN_STATUS_NIS (1 << 15) 209 #define GMAC_CHAN_STATUS_AIS (1 << 14) 210 #define GMAC_CHAN_STATUS_CDE (1 << 13) 211 #define GMAC_CHAN_STATUS_FBE (1 << 12) 212 #define GMAC_CHAN_STATUS_ERI (1 << 11) 213 #define GMAC_CHAN_STATUS_ETI (1 << 10) 214 #define GMAC_CHAN_STATUS_RWT (1 << 9) 215 #define GMAC_CHAN_STATUS_RPS (1 << 8) 216 #define GMAC_CHAN_STATUS_RBU (1 << 7) 217 #define GMAC_CHAN_STATUS_RI (1 << 6) 218 #define GMAC_CHAN_STATUS_TBU (1 << 2) 219 #define GMAC_CHAN_STATUS_TPS (1 << 1) 220 #define GMAC_CHAN_STATUS_TI (1 << 0) 221 222 /* 223 * DWQE descriptors. 224 */ 225 226 struct dwqe_desc { 227 uint32_t sd_tdes0; 228 uint32_t sd_tdes1; 229 uint32_t sd_tdes2; 230 uint32_t sd_tdes3; 231 }; 232 233 /* Tx bits (read format; host to device) */ 234 #define TDES2_HDR_LEN 0x000003ff /* if TSO is enabled */ 235 #define TDES2_BUF1_LEN 0x00003fff /* if TSO is disabled */ 236 #define TDES2_VLAN_TIR 0x0000c000 237 #define TDES2_NO_VLAN_TAGGING (0x0 << 14) 238 #define TDES2_VLAN_TAG_STRIP (0x1 << 14) 239 #define TDES2_VLAN_TAG_INSERT (0x2 << 14) 240 #define TDES2_VLAN_TAG_REPLACE (0x3 << 14) 241 #define TDES2_BUF2_LEN 0x3fff0000 242 #define TDES2_TX_TIMESTAMP_EN (1 << 30) /* if TSO is disabled */ 243 #define TDES2_TSO_EXTMEM_DIS (1 << 30) /* if TSO is enabled */ 244 #define TDES2_IC (1U << 31) 245 #define TDES3_TCP_PAYLOAD_LEN 0x0003ffff /* if TSO is enabled */ 246 #define TDES3_FRAME_LEN 0x00007fff /* if TSO is disabled */ 247 #define TDES3_CIC 0x00030000 /* if TSO is disabled */ 248 #define TDES3_CSUM_DISABLE (0x0 << 16) 249 #define TDES3_CSUM_IPHDR (0x1 << 16) 250 #define TDES3_CSUM_IPHDR_PAYLOAD (0x2 << 16) 251 #define TDES3_CSUM_IPHDR_PAYLOAD_PSEUDOHDR (0x3 << 16) 252 #define TDES3_TSO_EN (1 << 18) 253 #define TDES3_LS (1 << 28) 254 #define TDES3_FS (1 << 29) 255 #define TDES3_OWN (1U << 31) 256 257 /* Tx bits (writeback format; device to host) */ 258 #define TDES3_ES (1 << 15) 259 #define TDES3_DE (1 << 23) 260 /* Bit 28 is the LS bit, as in "read" format. */ 261 /* Bit 29 is the FS bit, as in "read" format. */ 262 /* Bit 31 is the OWN bit, as in "read" format. */ 263 264 /* Rx bits (read format; host to device) */ 265 #define RDES3_BUF1V (1 << 24) 266 #define RDES3_BUF2V (1 << 25) 267 #define RDES3_IC (1 << 30) 268 #define RDES3_OWN (1U << 31) 269 270 /* Rx bits (writeback format; device to host) */ 271 #define RDES1_IP_PAYLOAD_TYPE 0x7 272 #define RDES1_IP_PAYLOAD_UNKNOWN 0x0 273 #define RDES1_IP_PAYLOAD_UDP 0x1 274 #define RDES1_IP_PAYLOAD_TCP 0x2 275 #define RDES1_IP_PAYLOAD_ICMP 0x3 276 #define RDES1_IP_HDR_ERROR (1 << 3) 277 #define RDES1_IPV4_HDR (1 << 4) 278 #define RDES1_IPV6_HDR (1 << 5) 279 #define RDES1_IP_CSUM_BYPASS (1 << 6) 280 #define RDES1_IP_PAYLOAD_ERROR (1 << 7) 281 #define RDES3_LENGTH (0x7fff << 0) 282 #define RDES3_ES (1 << 15) 283 #define RDES3_LENTYPE 0x70000 284 #define RDES3_LENTYPE_LENGTH (0x0 << 16) 285 #define RDES3_LENTYPE_TYPE (0x1 << 16) 286 /* 0x2 is reserved */ 287 #define RDES3_LENTYPE_ARP (0x3 << 16) 288 #define RDES3_LENTYPE_VLAN (0x4 << 16) 289 #define RDES3_LENTYPE_2VLAN (0x5 << 16) 290 #define RDES3_LENTYPE_MACCTL (0x6 << 16) 291 #define RDES3_LENTYPE_OAM (0x7 << 16) 292 #define RDES3_DE (1 << 19) 293 #define RDES3_RE (1 << 20) 294 #define RDES3_OE (1 << 21) 295 #define RDES3_RWT (1 << 22) 296 #define RDES3_GP (1 << 23) 297 #define RDES3_CE (1 << 24) 298 #define RDES3_RDES0_VALID (1 << 25) 299 #define RDES3_RDES1_VALID (1 << 26) 300 #define RDES3_RDES2_VALID (1 << 27) 301 #define RDES3_LD (1 << 28) 302 #define RDES3_FD (1 << 29) 303 #define RDES3_CTXT (1 << 30) 304 /* Bit 31 is the OWN bit, as in "read" format. */ 305