1 /* 2 * THIS FILE IS AUTOMATICALLY GENERATED 3 * DONT EDIT THIS FILE 4 */ 5 6 /* $OpenBSD: cn30xxgmxreg.h,v 1.10 2022/12/28 01:39:21 yasuoka Exp $ */ 7 8 /* 9 * Copyright (c) 2007 Internet Initiative Japan, Inc. 10 * All rights reserved. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS OR CONTRIBUTORS BE LIABLE 25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 */ 33 34 /* 35 * Cavium Networks OCTEON CN30XX Hardware Reference Manual 36 * CN30XX-HM-1.0 37 * 13.8 GMX Registers 38 */ 39 40 #ifndef _CN30XXGMXREG_H_ 41 #define _CN30XXGMXREG_H_ 42 43 #define GMX0_RX0_INT_REG 0x000 44 #define GMX0_RX0_INT_EN 0x008 45 #define GMX0_PRT0_CFG 0x010 46 #define GMX0_RX0_FRM_CTL 0x018 47 #define GMX0_RX0_FRM_CHK 0x020 48 #define GMX0_RX0_FRM_MIN 0x028 49 #define GMX0_RX0_FRM_MAX 0x030 50 #define GMX0_RX0_JABBER 0x038 51 #define GMX0_RX0_DECISION 0x040 52 #define GMX0_RX0_UDD_SKP 0x048 53 #define GMX0_RX0_STATS_CTL 0x050 54 #define GMX0_RX0_IFG 0x058 55 #define GMX0_RX0_RX_INBND 0x060 56 #define GMX0_RX0_STATS_PKTS 0x080 57 #define GMX0_RX0_STATS_OCTS 0x088 58 #define GMX0_RX0_STATS_PKTS_CTL 0x090 59 #define GMX0_RX0_STATS_OCTS_CTL 0x098 60 #define GMX0_RX0_STATS_PKTS_DMAC 0x0a0 61 #define GMX0_RX0_STATS_OCTS_DMAC 0x0a8 62 #define GMX0_RX0_STATS_PKTS_DRP 0x0b0 63 #define GMX0_RX0_STATS_OCTS_DRP 0x0b8 64 #define GMX0_RX0_STATS_PKTS_BAD 0x0c0 65 #define GMX0_RX0_ADR_CTL 0x100 66 #define GMX0_RX0_ADR_CAM_EN 0x108 67 #define GMX0_RX0_ADR_CAM(i) (0x180 + (i) * 8) 68 #define GMX0_TX0_CLK 0x208 69 #define GMX0_TX0_THRESH 0x210 70 #define GMX0_TX0_APPEND 0x218 71 #define GMX0_TX0_SLOT 0x220 72 #define GMX0_TX0_BURST 0x228 73 #define GMX0_SMAC0 0x230 74 #define GMX0_TX0_PAUSE_PKT_TIME 0x238 75 #define GMX0_TX0_MIN_PKT 0x240 76 #define GMX0_TX0_PAUSE_PKT_INTERVAL 0x248 77 #define GMX0_TX0_SOFT_PAUSE 0x250 78 #define GMX0_TX0_PAUSE_TOGO 0x258 79 #define GMX0_TX0_PAUSE_ZERO 0x260 80 #define GMX0_TX0_STATS_CTL 0x268 81 #define GMX0_TX0_CTL 0x270 82 #define GMX0_TX0_STAT0 0x280 83 #define GMX0_TX0_STAT1 0x288 84 #define GMX0_TX0_STAT2 0x290 85 #define GMX0_TX0_STAT3 0x298 86 #define GMX0_TX0_STAT4 0x2a0 87 #define GMX0_TX0_STAT5 0x2a8 88 #define GMX0_TX0_STAT6 0x2b0 89 #define GMX0_TX0_STAT7 0x2b8 90 #define GMX0_TX0_STAT8 0x2c0 91 #define GMX0_TX0_STAT9 0x2c8 92 #define GMX0_BIST0 0x400 93 #define GMX0_RX_PRTS 0x410 94 #define GMX0_RX_BP_DROP0 0x420 95 #define GMX0_RX_BP_DROP1 0x428 96 #define GMX0_RX_BP_DROP2 0x430 97 #define GMX0_RX_BP_ON0 0x440 98 #define GMX0_RX_BP_ON1 0x448 99 #define GMX0_RX_BP_ON2 0x450 100 #define GMX0_RX_BP_OFF0 0x460 101 #define GMX0_RX_BP_OFF1 0x468 102 #define GMX0_RX_BP_OFF2 0x470 103 #define GMX0_TX_PRTS 0x480 104 #define GMX0_TX_IFG 0x488 105 #define GMX0_TX_JAM 0x490 106 #define GMX0_TX_COL_ATTEMPT 0x498 107 #define GMX0_TX_PAUSE_PKT_DMAC 0x4a0 108 #define GMX0_TX_PAUSE_PKT_TYPE 0x4a8 109 #define GMX0_TX_OVR_BP 0x4c8 110 #define GMX0_TX_BP 0x4d0 111 #define GMX0_TX_CORRUPT 0x4d8 112 #define GMX0_RX_PRT_INFO 0x4e8 113 #define GMX0_TX_LFSR 0x4f8 114 #define GMX0_TX_INT_REG 0x500 115 #define GMX0_TX_INT_EN 0x508 116 #define GMX0_NXA_ADR 0x510 117 #define GMX0_BAD_REG 0x518 118 #define GMX0_STAT_BP 0x520 119 #define GMX0_TX_CLK_MSK0 0x780 120 #define GMX0_TX_CLK_MSK1 0x788 121 #define GMX0_RX_TX_STATUS 0x7e8 122 #define GMX0_INF_MODE 0x7f8 123 124 /* -------------------------------------------------------------------------- */ 125 126 /* GMX Interrupt Registers */ 127 128 #define RXN_INT_REG_XXX_63_19 0xfffffffffff80000ULL 129 #define RXN_INT_REG_PHY_DUPX 0x0000000000040000ULL 130 #define RXN_INT_REG_PHY_SPD 0x0000000000020000ULL 131 #define RXN_INT_REG_PHY_LINK 0x0000000000010000ULL 132 #define RXN_INT_REG_IFGERR 0x0000000000008000ULL 133 #define RXN_INT_REG_COLDET 0x0000000000004000ULL 134 #define RXN_INT_REG_FALERR 0x0000000000002000ULL 135 #define RXN_INT_REG_RSVERR 0x0000000000001000ULL 136 #define RXN_INT_REG_PCTERR 0x0000000000000800ULL 137 #define RXN_INT_REG_OVRERR 0x0000000000000400ULL 138 #define RXN_INT_REG_NIBERR 0x0000000000000200ULL 139 #define RXN_INT_REG_SKPERR 0x0000000000000100ULL 140 #define RXN_INT_REG_RCVERR 0x0000000000000080ULL 141 #define RXN_INT_REG_LENERR 0x0000000000000040ULL 142 #define RXN_INT_REG_ALNERR 0x0000000000000020ULL 143 #define RXN_INT_REG_FCSERR 0x0000000000000010ULL 144 #define RXN_INT_REG_JABBER 0x0000000000000008ULL 145 #define RXN_INT_REG_MAXERR 0x0000000000000004ULL 146 #define RXN_INT_REG_CAREXT 0x0000000000000002ULL 147 #define RXN_INT_REG_MINERR 0x0000000000000001ULL 148 149 /* GMX Interrupt-Enable Registers */ 150 151 #define RXN_INT_EN_XXX_63_19 0xfffffffffff80000ULL 152 #define RXN_INT_EN_PHY_DUPX 0x0000000000040000ULL 153 #define RXN_INT_EN_PHY_SPD 0x0000000000020000ULL 154 #define RXN_INT_EN_PHY_LINK 0x0000000000010000ULL 155 #define RXN_INT_EN_IFGERR 0x0000000000008000ULL 156 #define RXN_INT_EN_COLDET 0x0000000000004000ULL 157 #define RXN_INT_EN_FALERR 0x0000000000002000ULL 158 #define RXN_INT_EN_RSVERR 0x0000000000001000ULL 159 #define RXN_INT_EN_PCTERR 0x0000000000000800ULL 160 #define RXN_INT_EN_OVRERR 0x0000000000000400ULL 161 #define RXN_INT_EN_NIBERR 0x0000000000000200ULL 162 #define RXN_INT_EN_SKPERR 0x0000000000000100ULL 163 #define RXN_INT_EN_RCVERR 0x0000000000000080ULL 164 #define RXN_INT_EN_LENERR 0x0000000000000040ULL 165 #define RXN_INT_EN_ALNERR 0x0000000000000020ULL 166 #define RXN_INT_EN_FCSERR 0x0000000000000010ULL 167 #define RXN_INT_EN_JABBER 0x0000000000000008ULL 168 #define RXN_INT_EN_MAXERR 0x0000000000000004ULL 169 #define RXN_INT_EN_CAREXT 0x0000000000000002ULL 170 #define RXN_INT_EN_MINERR 0x0000000000000001ULL 171 172 /* GMX Port Configuration Registers */ 173 174 #define PRTN_CFG_XXX_63_9 0xfffffffffffffe00ULL 175 #define PRTN_CFG_SPEED_MSB 0x0000000000000100ULL 176 #define PRTN_CFG_XXX_7_4 0x00000000000000f0ULL 177 #define PRTN_CFG_SLOTTIME 0x0000000000000008ULL 178 #define PRTN_CFG_DUPLEX 0x0000000000000004ULL 179 #define PRTN_CFG_SPEED 0x0000000000000002ULL 180 #define PRTN_CFG_EN 0x0000000000000001ULL 181 182 /* Frame Control Registers */ 183 184 #define RXN_FRM_CTL_XXX_63_11 0xfffffffffffff800ULL 185 #define RXN_FRM_CTL_NULL_DIS 0x0000000000000400ULL 186 #define RXN_FRM_CTL_PRE_ALIGN 0x0000000000000200ULL 187 #define RXN_FRM_CTL_PAD_LEN 0x0000000000000100ULL 188 #define RXN_FRM_CTL_VLAN_LEN 0x0000000000000080ULL 189 #define RXN_FRM_CTL_PRE_FREE 0x0000000000000040ULL 190 #define RXN_FRM_CTL_CTL_SMAC 0x0000000000000020ULL 191 #define RXN_FRM_CTL_CTL_MCST 0x0000000000000010ULL 192 #define RXN_FRM_CTL_CTL_BCK 0x0000000000000008ULL 193 #define RXN_FRM_CTL_CTL_DRP 0x0000000000000004ULL 194 #define RXN_FRM_CTL_PRE_STRP 0x0000000000000002ULL 195 #define RXN_FRM_CTL_PRE_CHK 0x0000000000000001ULL 196 197 /* Frame Check Registers */ 198 199 #define RXN_FRM_CKK_XXX_63_10 0xfffffffffffffc00ULL 200 #define RXN_FRM_CHK_NIBERR 0x0000000000000200ULL 201 #define RXN_FRM_CHK_SKPERR 0x0000000000000100ULL 202 #define RXN_FRM_CHK_RCVERR 0x0000000000000080ULL 203 #define RXN_FRM_CHK_LENERR 0x0000000000000040ULL 204 #define RXN_FRM_CHK_ALNERR 0x0000000000000020ULL 205 #define RXN_FRM_CHK_FCSERR 0x0000000000000010ULL 206 #define RXN_FRM_CHK_JABBER 0x0000000000000008ULL 207 #define RXN_FRM_CHK_MAXERR 0x0000000000000004ULL 208 #define RXN_FRM_CHK_CAREXT 0x0000000000000002ULL 209 #define RXN_FRM_CHK_MINERR 0x0000000000000001ULL 210 211 /* Frame Minimum-Length Registers */ 212 213 #define RXN_RRM_MIN_XXX_63_16 0xffffffffffff0000ULL 214 #define RXN_RRM_MIN_LEN 0x000000000000ffffULL 215 216 /* Frame Maximun-Length Registers */ 217 218 #define RXN_RRM_MAX_XXX_63_16 0xffffffffffff0000ULL 219 #define RXN_RRM_MAX_LEN 0x000000000000ffffULL 220 221 /* GMX Maximum Packet-Size Registers */ 222 223 #define RXN_JABBER_XXX_63_16 0xffffffffffff0000ULL 224 #define RXN_JABBER_CNT 0x000000000000ffffULL 225 226 /* GMX Packet Decision Registers */ 227 228 #define RXN_DECISION_XXX_63_5 0xffffffffffffffe0ULL 229 #define RXN_DECISION_CNT 0x000000000000001fULL 230 231 /* GMX User-Defined Data Skip Registers */ 232 233 #define RXN_UDD_SKP_XXX_63_9 0xfffffffffffffe00ULL 234 #define RXN_UDD_SKP_FCSSEL 0x0000000000000100ULL 235 #define RXN_UDD_SKP_XXX_7 0x0000000000000080ULL 236 #define RXN_UDD_SKP_LEN 0x000000000000007fULL 237 238 /* GMX RX Statistics Control Registers */ 239 240 #define RXN_STATS_CTL_XXX_63_1 0xfffffffffffffffeULL 241 #define RXN_STATS_CTL_RD_CLR 0x0000000000000001ULL 242 243 /* GMX Minimum Interface-Gap Cycles Registers */ 244 245 #define RXN_IFG_XXX_63_4 0xfffffffffffffff0ULL 246 #define RXN_IFG_IFG 0x000000000000000fULL 247 248 /* InBand Link Status Registers */ 249 250 #define RXN_RX_INBND_XXX_63_4 0xfffffffffffffff0ULL 251 #define RXN_RX_INBND_DUPLEX 0x0000000000000008ULL 252 #define RXN_RX_INBND_DUPLEX_SHIFT 3 253 #define RXN_RX_INBND_DUPLEX_HALF (0ULL << RXN_RX_INBND_DUPLEX_SHIFT) 254 #define RXN_RX_INBND_DUPLEX_FULL (1ULL << RXN_RX_INBND_DUPLEX_SHIFT) 255 #define RXN_RX_INBND_SPEED 0x0000000000000006ULL 256 #define RXN_RX_INBND_SPEED_SHIFT 1 257 #define RXN_RX_INBND_SPEED_2_5 (0ULL << RXN_RX_INBND_SPEED_SHIFT) 258 #define RXN_RX_INBND_SPEED_25 (1ULL << RXN_RX_INBND_SPEED_SHIFT) 259 #define RXN_RX_INBND_SPEED_125 (2ULL << RXN_RX_INBND_SPEED_SHIFT) 260 #define RXN_RX_INBND_SPEED_XXX_3 (3ULL << RXN_RX_INBND_SPEED_SHIFT) 261 #define RXN_RX_INBND_STATUS 0x0000000000000001ULL 262 263 /* GMX RX Good Packets Registers */ 264 265 #define RXN_STATS_PKTS_XXX_63_32 0xffffffff00000000ULL 266 #define RXN_STATS_PKTS_CNT 0x00000000ffffffffULL 267 268 /* GMX RX Good Packets Octet Registers */ 269 270 #define RXN_STATS_OCTS_XXX_63_48 0xffff000000000000ULL 271 #define RXN_STATS_OCTS_CNT 0x0000ffffffffffffULL 272 273 /* GMX RX Pause Packets Registers */ 274 275 #define RXN_STATS_PKTS_CTL_XXX_63_32 0xffffffff00000000ULL 276 #define RXN_STATS_PKTS_CTL_CNT 0x00000000ffffffffULL 277 278 /* GMX RX Pause Packets Octet Registers */ 279 280 #define RXN_STATS_OCTS_CTL_XXX_63_48 0xffff000000000000ULL 281 #define RXN_STATS_OCTS_CTL_CNT 0x0000ffffffffffffULL 282 283 /* GMX RX DMAC Packets Registers */ 284 285 #define RXN_STATS_PKTS_DMAC_XXX_63_32 0xffffffff00000000ULL 286 #define RXN_STATS_PKTS_DMAC_CNT 0x00000000ffffffffULL 287 288 /* GMX RX DMAC Packets Octet Registers */ 289 290 #define RXN_STATS_OCTS_DMAC_XXX_63_48 0xffff000000000000ULL 291 #define RXN_STATS_OCTS_DMAC_CNT 0x0000ffffffffffffULL 292 293 /* GMX RX Overflow Packets Registers */ 294 295 #define RXN_STATS_PKTS_DRP_XXX_63_48 0xffffffff00000000ULL 296 #define RXN_STATS_PKTS_DRP_CNT 0x00000000ffffffffULL 297 298 /* GMX RX Overflow Packets Octet Registers */ 299 300 #define RXN_STATS_OCTS_DRP_XXX_63_48 0xffff000000000000ULL 301 #define RXN_STATS_OCTS_DRP_CNT 0x0000ffffffffffffULL 302 303 /* GMX RX Bad Packets Registers */ 304 305 #define RXN_STATS_PKTS_BAD_XXX_63_48 0xffffffff00000000ULL 306 #define RXN_STATS_PKTS_BAD_CNT 0x00000000ffffffffULL 307 308 /* Address-Filtering Control Registers */ 309 310 #define RXN_ADR_CTL_XXX_63_4 0xfffffffffffffff0ULL 311 #define RXN_ADR_CTL_CAM_MODE 0x0000000000000008ULL 312 #define RXN_ADR_CTL_CAM_MODE_SHIFT 3 313 #define RXN_ADR_CTL_CAM_MODE_REJECT (0ULL << RXN_ADR_CTL_CAM_MODE_SHIFT) 314 #define RXN_ADR_CTL_CAM_MODE_ACCEPT (1ULL << RXN_ADR_CTL_CAM_MODE_SHIFT) 315 #define RXN_ADR_CTL_MCST 0x0000000000000006ULL 316 #define RXN_ADR_CTL_MCST_SHIFT 1 317 #define RXN_ADR_CTL_MCST_AFCAM (0ULL << RXN_ADR_CTL_MCST_SHIFT) 318 #define RXN_ADR_CTL_MCST_REJECT (1ULL << RXN_ADR_CTL_MCST_SHIFT) 319 #define RXN_ADR_CTL_MCST_ACCEPT (2ULL << RXN_ADR_CTL_MCST_SHIFT) 320 #define RXN_ADR_CTL_MCST_XXX_3 (3ULL << RXN_ADR_CTL_MCST_SHIFT) 321 #define RXN_ADR_CTL_BCST 0x0000000000000001ULL 322 323 /* Address-Filtering Control Enable Registers */ 324 325 #define RXN_ADR_CAM_EN_XXX_63_8 0xffffffffffffff00ULL 326 #define RXN_ADR_CAM_EN_EN 0x00000000000000ffULL 327 328 /* Address-Filtering CAM Control Registers */ 329 #define RXN_ADR_CAMN_ADR 0xffffffffffffffffULL 330 331 /* GMX TX Clock Generation Registers */ 332 333 #define TXN_CLK_XXX_63_6 0xffffffffffffffc0ULL 334 #define TXN_CLK_CLK_CNT 0x000000000000003fULL 335 336 /* TX Threshold Registers */ 337 338 #define TXN_THRESH_XXX_63_6 0xffffffffffffffc0ULL 339 #define TXN_THRESH_CNT 0x000000000000003fULL 340 341 /* TX Append Control Registers */ 342 343 #define TXN_APPEND_XXX_63_4 0xfffffffffffffff0ULL 344 #define TXN_APPEND_FORCE_FCS 0x0000000000000008ULL 345 #define TXN_APPEND_FCS 0x0000000000000004ULL 346 #define TXN_APPEND_PAD 0x0000000000000002ULL 347 #define TXN_APPEND_PREAMBLE 0x0000000000000001ULL 348 349 /* TX Slottime Counter Registers */ 350 351 #define TXN_SLOT_XXX_63_10 0xfffffffffffffc00ULL 352 #define TXN_SLOT_SLOT 0x00000000000003ffULL 353 354 /* TX Burst-Counter Registers */ 355 356 #define TXN_BURST_XXX_63_16 0xffffffffffff0000ULL 357 #define TXN_BURST_BURST 0x000000000000ffffULL 358 359 /* RGMII SMAC Registers */ 360 361 #define SMACN_XXX_63_48 0xffff000000000000ULL 362 #define SMACN_SMAC 0x0000ffffffffffffULL 363 364 /* TX Pause Packet Pause-Time Registers */ 365 366 #define TXN_PAUSE_PKT_TIME_XXX_63_16 0xffffffffffff0000ULL 367 #define TXN_PAUSE_PKT_TIME_TIME 0x000000000000ffffULL 368 369 /* RGMII TX Minimum-Size-Packet Registers */ 370 371 #define TXN_MIN_PKT_XXX_63_8 0xffffffffffffff00ULL 372 #define TXN_MIN_PKT_MIN_SIZE 0x00000000000000ffULL 373 374 /* TX Pause-Packet Transmission-Interval Registers */ 375 376 #define TXN_PAUSE_PKT_INTERVAL_XXX_63_16 0xffffffffffff0000ULL 377 #define TXN_PAUSE_PKT_INTERVAL_INTERVAL 0x000000000000ffffULL 378 379 /* TX Software-Pause Registers */ 380 381 #define TXN_SOFT_PAUSE_XXX_63_16 0xffffffffffff0000ULL 382 #define TXN_SOFT_PAUSE_TIME 0x000000000000ffffULL 383 384 /* TX Time-to-Backpressure Registers */ 385 386 #define TXN_PAUSE_TOGO_XXX_63_16 0xffffffffffff0000ULL 387 #define TXN_PAUSE_TOGO_TIME 0x000000000000ffffULL 388 389 /* TX Pause-Zero-Enable Registers */ 390 391 #define TXN_PAUSE_ZERO_XXX_63_1 0xfffffffffffffffeULL 392 #define TXN_PAUSE_ZERO_SEND 0x0000000000000001ULL 393 394 /* GMX TX Statistics Control Registers */ 395 396 #define TXN_STATS_CTL_XXX_63_1 0xfffffffffffffffeULL 397 #define TXN_STATS_CTL_RD_CLR 0x0000000000000001ULL 398 399 /* GMX TX Transmit Control Registers */ 400 401 #define TXN_CTL_XXX_63_2 0xfffffffffffffffcULL 402 #define TXN_CTL_XSDEF_EN 0x0000000000000002ULL 403 #define TXN_CTL_XSCOL_EN 0x0000000000000001ULL 404 405 /* Transmit Statistics Registers 0 */ 406 407 #define TXN_STAT0_XSDEF 0xffffffff00000000ULL 408 #define TXN_STAT0_XSCOL 0x00000000ffffffffULL 409 410 /* Transmit Statistics Registers 1 */ 411 412 #define TXN_STAT1_SCOL 0xffffffff00000000ULL 413 #define TXN_STAT1_MSCOL 0x00000000ffffffffULL 414 415 /* Transmit Statistics Registers 2 */ 416 417 #define TXN_STAT2_XXX_63_48 0xffff000000000000ULL 418 #define TXN_STAT2_OCTS 0x0000ffffffffffffULL 419 420 /* Transmit Statistics Registers 3 */ 421 422 #define TXN_STAT3_XXX_63_48 0xffffffff00000000ULL 423 #define TXN_STAT3_PKTS 0x00000000ffffffffULL 424 425 /* Transmit Statistics Registers 4 */ 426 427 #define TXN_STAT4_HIST1 0xffffffff00000000ULL 428 #define TXN_STAT4_HIST0 0x00000000ffffffffULL 429 430 /* Transmit Statistics Registers 5 */ 431 432 #define TXN_STAT5_HIST3 0xffffffff00000000ULL 433 #define TXN_STAT5_HIST2 0x00000000ffffffffULL 434 435 /* Transmit Statistics Registers 6 */ 436 437 #define TXN_STAT6_HIST5 0xffffffff00000000ULL 438 #define TXN_STAT6_HIST4 0x00000000ffffffffULL 439 440 /* Transmit Statistics Registers 7 */ 441 442 #define TXN_STAT7_HIST7 0xffffffff00000000ULL 443 #define TXN_STAT7_HIST6 0x00000000ffffffffULL 444 445 /* Transmit Statistics Registers 8 */ 446 447 #define TXN_STAT8_MCST 0xffffffff00000000ULL 448 #define TXN_STAT8_BCST 0x00000000ffffffffULL 449 450 /* Transmit Statistics Register 9 */ 451 452 #define TXN_STAT9_UNDFLW 0xffffffff00000000ULL 453 #define TXN_STAT9_CTL 0x00000000ffffffffULL 454 455 /* BMX BIST Results Register */ 456 457 #define BIST_XXX_63_10 0xfffffffffffffc00ULL 458 #define BIST_STATUS 0x00000000000003ffULL 459 460 /* RX Ports Register */ 461 462 #define RX_PRTS_XXX_63_3 0xfffffffffffffff8ULL 463 #define RX_PRTS_PRTS 0x0000000000000007ULL 464 465 /* RX FIFO Packet-Drop Registers */ 466 467 #define RX_BP_DROPN_XXX_63_6 0xffffffffffffffc0ULL 468 #define RX_BP_DROPN_MARK 0x000000000000003fULL 469 470 /* RX Backpressure On Registers */ 471 472 #define RX_BP_ONN_XXX_63_9 0xfffffffffffffe00ULL 473 #define RX_BP_ONN_MARK 0x00000000000001ffULL 474 475 /* RX Backpressure Off Registers */ 476 477 #define RX_BP_OFFN_XXX_63_6 0xffffffffffffffc0ULL 478 #define RX_BP_OFFN_MARK 0x000000000000003fULL 479 480 /* TX Ports Register */ 481 482 #define TX_PRTS_XXX_63_5 0xffffffffffffffe0ULL 483 #define TX_PRTS_PRTS 0x000000000000001fULL 484 485 /* TX Interframe Gap Register */ 486 487 #define TX_IFG_XXX_63_8 0xffffffffffffff00ULL 488 #define TX_IFG_IFG2 0x00000000000000f0ULL 489 #define TX_IFG_IFG1 0x000000000000000fULL 490 491 /* TX Jam Pattern Register */ 492 493 #define TX_JAM_XXX_63_8 0xffffffffffffff00ULL 494 #define TX_JAM_JAM 0x00000000000000ffULL 495 496 /* TX Collision Attempts Before Dropping Frame Register */ 497 498 #define TX_COL_ATTEMPT_XXX_63_5 0xffffffffffffffe0ULL 499 #define TX_COL_ATTEMPT_LIMIT 0x000000000000001fULL 500 501 /* TX Pause-Packet DMAC-Field Register */ 502 503 #define TX_PAUSE_PKT_DMAC_XXX_63_48 0xffff000000000000ULL 504 #define TX_PAUSE_PKT_DMAC_DMAC 0x0000ffffffffffffULL 505 506 /* TX Pause Packet Type Field Register */ 507 508 #define TX_PAUSE_PKT_TYPE_XXX_63_16 0xffffffffffff0000ULL 509 #define TX_PAUSE_PKT_TYPE_TYPE 0x000000000000ffffULL 510 511 /* TX Override Backpressure Register */ 512 513 #define TX_OVR_BP_XXX_63_12 0xfffffffffffff000ULL 514 #define TX_OVR_BP_XXX_11 0x0000000000000800ULL 515 #define TX_OVR_BP_EN 0x0000000000000700ULL 516 #define TX_OVR_BP_EN_SHIFT 8 517 #define TX_OVR_BP_XXX_7 0x0000000000000080ULL 518 #define TX_OVR_BP_BP 0x0000000000000070ULL 519 #define TX_OVR_BP_BP_SHIFT 4 520 #define TX_OVR_BP_XXX_3 0x0000000000000008ULL 521 #define TX_OVR_BP_IGN_FULL 0x0000000000000007ULL 522 #define TX_OVR_BP_IGN_FULL_SHIFT 0 523 524 /* TX Override Backpressure Register */ 525 526 #define TX_OVR_BP_XXX_63_12 0xfffffffffffff000ULL 527 #define TX_OVR_BP_XXX_11 0x0000000000000800ULL 528 #define TX_OVR_BP_EN 0x0000000000000700ULL 529 #define TX_OVR_BP_XXX_7 0x0000000000000080ULL 530 #define TX_OVR_BP_BP 0x0000000000000070ULL 531 #define TX_OVR_BP_XXX_3 0x0000000000000008ULL 532 #define TX_OVR_BP_IGN_FULL 0x0000000000000007ULL 533 534 /* TX Backpressure Status Register */ 535 536 #define TX_BP_SR_XXX_63_3 0xfffffffffffffff8ULL 537 #define TX_BP_SR_BP 0x0000000000000007ULL 538 539 /* TX Corrupt Packets Register */ 540 541 #define TX_CORRUPT_XXX_63_3 0xfffffffffffffff8ULL 542 #define TX_CORRUPT_CORRUPT 0x0000000000000007ULL 543 544 /* RX Port State Information Register */ 545 546 #define RX_PRT_INFO_XXX_63_19 0xfffffffffff80000ULL 547 #define RX_PRT_INFO_DROP 0x0000000000070000ULL 548 #define RX_PRT_INFO_XXX_15_3 0x000000000000fff8ULL 549 #define RX_PRT_INFO_COMMIT 0x0000000000000007ULL 550 551 /* TX LFSR Register */ 552 553 #define TX_LFSR_XXX_63_16 0xffffffffffff0000ULL 554 #define TX_LFSR_LFSR 0x000000000000ffffULL 555 556 /* TX Interrupt Register */ 557 558 #define TX_INT_REG_XXX_63_20 0xfffffffffff00000ULL 559 #define TX_INT_REG_XXX_19 0x0000000000080000ULL 560 #define TX_INT_REG_LATE_COL 0x0000000000070000ULL 561 #define TX_INT_REG_XXX_15 0x0000000000008000ULL 562 #define TX_INT_REG_XSDEF 0x0000000000007000ULL 563 #define TX_INT_REG_XXX_11 0x0000000000000800ULL 564 #define TX_INT_REG_XSCOL 0x0000000000000700ULL 565 #define TX_INT_REG_XXX_7_5 0x00000000000000e0ULL 566 #define TX_INT_REG_UNDFLW 0x000000000000001cULL 567 #define TX_INT_REG_XXX_1 0x0000000000000002ULL 568 #define TX_INT_REG_PKO_NXA 0x0000000000000001ULL 569 570 /* TX Interrupt Register */ 571 572 #define TX_INT_EN_XXX_63_20 0xfffffffffff00000ULL 573 #define TX_INT_EN_XXX_19 0x0000000000080000ULL 574 #define TX_INT_EN_LATE_COL 0x0000000000070000ULL 575 #define TX_INT_EN_XXX_15 0x0000000000008000ULL 576 #define TX_INT_EN_XSDEF 0x0000000000007000ULL 577 #define TX_INT_EN_XXX_11 0x0000000000000800ULL 578 #define TX_INT_EN_XSCOL 0x0000000000000700ULL 579 #define TX_INT_EN_XXX_7_5 0x00000000000000e0ULL 580 #define TX_INT_EN_UNDFLW 0x000000000000001cULL 581 #define TX_INT_EN_XXX_1 0x0000000000000002ULL 582 #define TX_INT_EN_PKO_NXA 0x0000000000000001ULL 583 584 /* Address-out-of-Range Error Register */ 585 586 #define NXA_ADR_XXX_63_6 0xffffffffffffffc0ULL 587 #define NXA_ADR_PRT 0x000000000000003fULL 588 589 /* GMX Miscellaneous Error Register */ 590 591 #define BAD_REG_XXX_63_31 0xffffffff80000000ULL 592 #define BAD_REG_INB_NXA 0x0000000078000000ULL 593 #define BAD_REG_STATOVR 0x0000000004000000ULL 594 #define BAD_REG_XXX_25 0x0000000002000000ULL 595 #define BAD_REG_LOSTSTAT 0x0000000001c00000ULL 596 #define BAD_REG_XXX_21_18 0x00000000003c0000ULL 597 #define BAD_REG_XXX_17_5 0x000000000003ffe0ULL 598 #define BAD_REG_OUT_OVR 0x000000000000001cULL 599 #define BAD_REG_XXX_1_0 0x0000000000000003ULL 600 601 /* GMX Backpressure Statistics Register */ 602 603 #define STAT_BP_XXX_63_17 0xfffffffffffe0000ULL 604 #define STAT_BP_BP 0x0000000000010000ULL 605 #define STAT_BP_CNT 0x000000000000ffffULL 606 607 /* Mode Change Mask Registers */ 608 609 #define TX_CLK_MSKN_XXX_63_1 0xfffffffffffffffeULL 610 #define TX_CLK_MSKN_MSK 0x0000000000000001ULL 611 612 /* GMX RX/TX Status Register */ 613 614 #define RX_TX_STATUS_XXX_63_7 0xffffffffffffff80ULL 615 #define RX_TX_STATUS_TX 0x0000000000000070ULL 616 #define RX_TX_STATUS_XXX_3 0x0000000000000008ULL 617 #define RX_TX_STATUS_RX 0x0000000000000007ULL 618 619 /* Interface Mode Register */ 620 621 #define INF_MODE_XXX_63_3 0xfffffffffffffff8ULL 622 #define INF_MODE_P0MII 0x0000000000000004ULL 623 #define INF_MODE_EN 0x0000000000000002ULL 624 #define INF_MODE_TYPE 0x0000000000000001ULL 625 626 /* Interface mode, applicable on CN68xx and CN7xxx (?) */ 627 #define INF_MODE_MODE 0x0000000000000070ULL 628 #define INF_MODE_MODE_SGMII 0x0000000000000020ULL 629 #define INF_MODE_MODE_XAUI 0x0000000000000030ULL 630 631 #define MIO_QLM_CFG(x) (0x0001180000001590ULL + (x)*8) 632 633 #define MIO_QLM_CFG_CFG 0x000000000000000fULL 634 635 /* -------------------------------------------------------------------------- */ 636 637 /* for bus_space(9) */ 638 639 #define GMX_PORT_NUNITS (3 * 16) 640 #define GMX_PORT_NUM(g, i) ((g) * 16 + (i)) 641 #define GMX_PORT_IFACE(port) ((port) / 16) 642 #define GMX_PORT_INDEX(port) ((port) % 16) 643 644 #define GMX_BLOCK_SIZE 0x8000000 645 646 #define GMX0_BASE_PORT0 0x0001180008000000ULL 647 #define GMX0_BASE_PORT1 0x0001180008000800ULL 648 #define GMX0_BASE_PORT2 0x0001180008001000ULL 649 #define GMX0_BASE_PORT_SIZE 0x00800 650 #define GMX0_BASE_IF0 0x0001180008000000ULL 651 #define GMX0_BASE_IF_SIZE(n) (GMX0_BASE_PORT_SIZE * (n)) 652 653 #define AGL_BASE 0x00011800e0000000ULL 654 #define AGL_SIZE 0x4000 655 656 #define AGL_GMX_PRT_CFG 0x0010 657 #define AGL_GMX_PRT_CFG_TX_IDLE 0x0000000000002000ULL 658 #define AGL_GMX_PRT_CFG_RX_IDLE 0x0000000000001000ULL 659 #define AGL_GMX_PRT_CFG_SPEED_MSB 0x0000000000000100ULL 660 #define AGL_GMX_PRT_CFG_BURST 0x0000000000000040ULL 661 #define AGL_GMX_PRT_CFG_TX_EN 0x0000000000000020ULL 662 #define AGL_GMX_PRT_CFG_RX_EN 0x0000000000000010ULL 663 #define AGL_GMX_PRT_CFG_SLOTTIME 0x0000000000000008ULL 664 #define AGL_GMX_PRT_CFG_DUPLEX 0x0000000000000004ULL 665 #define AGL_GMX_PRT_CFG_SPEED 0x0000000000000002ULL 666 #define AGL_GMX_PRT_CFG_EN 0x0000000000000001ULL 667 668 #define AGL_GMX_RX_FRM_CTL 0x0018 669 #define AGL_GMX_RX_FRM_CTL_PRE_ALIGN 0x0000000000000200ULL 670 #define AGL_GMX_RX_FRM_CTL_PAD_LEN 0x0000000000000100ULL 671 #define AGL_GMX_RX_FRM_CTL_VLAN_LEN 0x0000000000000080ULL 672 #define AGL_GMX_RX_FRM_CTL_PRE_FREE 0x0000000000000040ULL 673 #define AGL_GMX_RX_FRM_CTL_SMAC 0x0000000000000020ULL 674 #define AGL_GMX_RX_FRM_CTL_MCST 0x0000000000000010ULL 675 #define AGL_GMX_RX_FRM_CTL_BCK 0x0000000000000008ULL 676 #define AGL_GMX_RX_FRM_CTL_DRP 0x0000000000000004ULL 677 #define AGL_GMX_RX_FRM_CTL_PRE_STRP 0x0000000000000002ULL 678 #define AGL_GMX_RX_FRM_CTL_PRE_CHK 0x0000000000000001ULL 679 680 #define AGL_GMX_RX_FRM_MAX 0x0030 681 #define AGL_GMX_RX_JABBER 0x0038 682 683 #define AGL_GMX_TX_CLK 0x0208 684 #define AGL_GMX_TX_CLK_CLK_CNT_M 0x000000000000003fULL 685 #define AGL_GMX_TX_CLK_CLK_CNT_S 0 686 687 #define AGL_PRT_CTL(i) (0x2000 + (i) * 8) 688 #define AGL_PRT_CTL_DRV_BYP 0x8000000000000000ULL 689 #define AGL_PRT_CTL_CLK_SET_M 0x000000007f000000ULL 690 #define AGL_PRT_CTL_CLKRX_BYP 0x0000000000800000ULL 691 #define AGL_PRT_CTL_CLKRX_SET_M 0x00000000007f0000ULL 692 #define AGL_PRT_CTL_CLKTX_BYP 0x0000000000008000ULL 693 #define AGL_PRT_CTL_CLKTX_SET_M 0x0000000000007f00ULL 694 #define AGL_PRT_CTL_REFCLK_SEL_M 0x00000000000000c0ULL 695 #define AGL_PRT_CTL_DLLRST 0x0000000000000010ULL 696 #define AGL_PRT_CTL_COMP 0x0000000000000008ULL 697 #define AGL_PRT_CTL_ENABLE 0x0000000000000004ULL 698 #define AGL_PRT_CTL_CLKRST 0x0000000000000002ULL 699 #define AGL_PRT_CTL_MODE_M 0x0000000000000001ULL 700 #define AGL_PRT_CTL_MODE_RGMII 0x0000000000000000ULL 701 702 /* -------------------------------------------------------------------------- */ 703 704 /* Low-level SGMII link control */ 705 706 #define PCS_BASE(g, i) (0x00011800b0001000ULL + 0x8000000 * (g) + 0x400 * (i)) 707 #define PCS_SIZE 0x98 708 709 #define PCS_MR_CONTROL 0x00 710 #define PCS_MR_STATUS 0x08 711 #define PCS_LINK_TIMER_COUNT 0x40 712 #define PCS_MISC_CTL 0x78 713 714 #define PCS_MR_CONTROL_RES_16_63 0xffffffffffff0000ULL 715 #define PCS_MR_CONTROL_RESET 0x0000000000008000ULL 716 #define PCS_MR_CONTROL_LOOPBCK1 0x0000000000004000ULL 717 #define PCS_MR_CONTROL_SPDLSB 0x0000000000002000ULL 718 #define PCS_MR_CONTROL_AN_EN 0x0000000000001000ULL 719 #define PCS_MR_CONTROL_PWR_DN 0x0000000000000800ULL 720 #define PCS_MR_CONTROL_RES_10_10 0x0000000000000400ULL 721 #define PCS_MR_CONTROL_RST_AN 0x0000000000000200ULL 722 #define PCS_MR_CONTROL_DUPLEX 0x0000000000000100ULL 723 #define PCS_MR_CONTROL_COLTST 0x0000000000000080ULL 724 #define PCS_MR_CONTROL_SPDMSB 0x0000000000000040ULL 725 #define PCS_MR_CONTROL_UNI 0x0000000000000020ULL 726 #define PCS_MR_CONTROL_RES_0_4 0x000000000000001fULL 727 728 #define PCS_MR_STATUS_RES_16_63 0xffffffffffff0000ULL 729 #define PCS_MR_STATUS_HUN_T4 0x0000000000008000ULL 730 #define PCS_MR_STATUS_HUN_XFD 0x0000000000004000ULL 731 #define PCS_MR_STATUS_HUN_XHD 0x0000000000002000ULL 732 #define PCS_MR_STATUS_TEN_FD 0x0000000000001000ULL 733 #define PCS_MR_STATUS_TEN_HD 0x0000000000000800ULL 734 #define PCS_MR_STATUS_HUN_T2FD 0x0000000000000400ULL 735 #define PCS_MR_STATUS_HUN_T2HD 0x0000000000000200ULL 736 #define PCS_MR_STATUS_EXT_ST 0x0000000000000100ULL 737 #define PCS_MR_STATUS_RES_7_7 0x0000000000000080ULL 738 #define PCS_MR_STATUS_PRB_SUP 0x0000000000000040ULL 739 #define PCS_MR_STATUS_AN_CPT 0x0000000000000020ULL 740 #define PCS_MR_STATUS_RM_FLT 0x0000000000000010ULL 741 #define PCS_MR_STATUS_AN_ABIL 0x0000000000000008ULL 742 #define PCS_MR_STATUS_LNK_ST 0x0000000000000004ULL 743 #define PCS_MR_STATUS_RES_1_1 0x0000000000000002ULL 744 #define PCS_MR_STATUS_EXTND 0x0000000000000001ULL 745 746 #define PCS_LINK_TIMER_COUNT_MASK 0x000000000000ffffULL 747 748 #define PCS_MISC_CTL_SGMII 0x0000000000001000ULL 749 #define PCS_MISC_CTL_GMXENO 0x0000000000000800ULL 750 #define PCS_MISC_CTL_LOOPBCK2 0x0000000000000400ULL 751 #define PCS_MISC_CTL_MAC_PHY 0x0000000000000200ULL 752 #define PCS_MISC_CTL_MODE 0x0000000000000100ULL 753 #define PCS_MISC_CTL_AN_OVRD 0x0000000000000080ULL 754 #define PCS_MISC_CTL_SAMP_PT 0x000000000000007fULL 755 756 #endif /* _CN30XXGMXREG_H_ */ 757