1 // Copyright 2008 Dolphin Emulator Project
2 // Licensed under GPLv2+
3 // Refer to the license.txt file included.
4
5 // Additional copyrights go to Duddie (c) 2005 (duddie@walla.com)
6
7 #include "Core/DSP/DSPTables.h"
8
9 #include <algorithm>
10 #include <array>
11 #include <cstddef>
12 #include <cstdio>
13
14 #include "Common/CommonTypes.h"
15 #include "Common/Logging/Log.h"
16
17 #include "Core/DSP/Interpreter/DSPIntTables.h"
18
19 namespace DSP
20 {
21 // clang-format off
22 const std::array<DSPOPCTemplate, 214> s_opcodes =
23 {{
24 // # of parameters----+ {type, size, loc, lshift, mask} branch reads PC // instruction approximation
25 // name opcode mask size-V V param 1 param 2 param 3 extendable uncond. updates SR
26 {"NOP", 0x0000, 0xfffc, 1, 0, {}, false, false, false, false, false}, // no operation
27
28 {"DAR", 0x0004, 0xfffc, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arD--
29 {"IAR", 0x0008, 0xfffc, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arD++
30 {"SUBARN", 0x000c, 0xfffc, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arD -= $ixS
31 {"ADDARN", 0x0010, 0xfff0, 1, 2, {{P_REG, 1, 0, 0, 0x0003}, {P_REG04, 1, 0, 2, 0x000c}}, false, false, false, false, false}, // $arD += $ixS
32
33 {"HALT", 0x0021, 0xffff, 1, 0, {}, false, true, true, false, false}, // halt until reset
34
35 {"RETGE", 0x02d0, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if greater or equal
36 {"RETL", 0x02d1, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if less
37 {"RETG", 0x02d2, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if greater
38 {"RETLE", 0x02d3, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if less or equal
39 {"RETNZ", 0x02d4, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if not zero
40 {"RETZ", 0x02d5, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if zero
41 {"RETNC", 0x02d6, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if not carry
42 {"RETC", 0x02d7, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if carry
43 {"RETx8", 0x02d8, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if TODO
44 {"RETx9", 0x02d9, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if TODO
45 {"RETxA", 0x02da, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if TODO
46 {"RETxB", 0x02db, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if TODO
47 {"RETLNZ", 0x02dc, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if logic not zero
48 {"RETLZ", 0x02dd, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if logic zero
49 {"RETO", 0x02de, 0xffff, 1, 0, {}, false, true, false, true, false}, // return if overflow
50 {"RET", 0x02df, 0xffff, 1, 0, {}, false, true, true, false, false}, // unconditional return
51
52 {"RTI", 0x02ff, 0xffff, 1, 0, {}, false, true, true, false, false}, // return from interrupt
53
54 {"CALLGE", 0x02b0, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if greater or equal
55 {"CALLL", 0x02b1, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if less
56 {"CALLG", 0x02b2, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if greater
57 {"CALLLE", 0x02b3, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if less or equal
58 {"CALLNZ", 0x02b4, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if not zero
59 {"CALLZ", 0x02b5, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if zero
60 {"CALLNC", 0x02b6, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if not carry
61 {"CALLC", 0x02b7, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if carry
62 {"CALLx8", 0x02b8, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if TODO
63 {"CALLx9", 0x02b9, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if TODO
64 {"CALLxA", 0x02ba, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if TODO
65 {"CALLxB", 0x02bb, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if TODO
66 {"CALLLNZ", 0x02bc, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if logic not zero
67 {"CALLLZ", 0x02bd, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if logic zero
68 {"CALLO", 0x02be, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // call if overflow
69 {"CALL", 0x02bf, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true, false}, // unconditional call
70
71 {"IFGE", 0x0270, 0xffff, 1, 0, {}, false, true, false, true, false}, // if greater or equal
72 {"IFL", 0x0271, 0xffff, 1, 0, {}, false, true, false, true, false}, // if less
73 {"IFG", 0x0272, 0xffff, 1, 0, {}, false, true, false, true, false}, // if greater
74 {"IFLE", 0x0273, 0xffff, 1, 0, {}, false, true, false, true, false}, // if less or equal
75 {"IFNZ", 0x0274, 0xffff, 1, 0, {}, false, true, false, true, false}, // if not zero
76 {"IFZ", 0x0275, 0xffff, 1, 0, {}, false, true, false, true, false}, // if zero
77 {"IFNC", 0x0276, 0xffff, 1, 0, {}, false, true, false, true, false}, // if not carry
78 {"IFC", 0x0277, 0xffff, 1, 0, {}, false, true, false, true, false}, // if carry
79 {"IFx8", 0x0278, 0xffff, 1, 0, {}, false, true, false, true, false}, // if TODO
80 {"IFx9", 0x0279, 0xffff, 1, 0, {}, false, true, false, true, false}, // if TODO
81 {"IFxA", 0x027a, 0xffff, 1, 0, {}, false, true, false, true, false}, // if TODO
82 {"IFxB", 0x027b, 0xffff, 1, 0, {}, false, true, false, true, false}, // if TODO
83 {"IFLNZ", 0x027c, 0xffff, 1, 0, {}, false, true, false, true, false}, // if logic not zero
84 {"IFLZ", 0x027d, 0xffff, 1, 0, {}, false, true, false, true, false}, // if logic zero
85 {"IFO", 0x027e, 0xffff, 1, 0, {}, false, true, false, true, false}, // if overflow
86 {"IF", 0x027f, 0xffff, 1, 0, {}, false, true, true, true, false}, // what is this, I don't even...
87
88 {"JGE", 0x0290, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if greater or equal
89 {"JL", 0x0291, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if less
90 {"JG", 0x0292, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if greater
91 {"JLE", 0x0293, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if less or equal
92 {"JNZ", 0x0294, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if not zero
93 {"JZ", 0x0295, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if zero
94 {"JNC", 0x0296, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if not carry
95 {"JC", 0x0297, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if carry
96 {"JMPx8", 0x0298, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if TODO
97 {"JMPx9", 0x0299, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if TODO
98 {"JMPxA", 0x029a, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if TODO
99 {"JMPxB", 0x029b, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if TODO
100 {"JLNZ", 0x029c, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if logic not zero
101 {"JLZ", 0x029d, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if logic zero
102 {"JO", 0x029e, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, false, true, false}, // jump if overflow
103 {"JMP", 0x029f, 0xffff, 2, 1, {{P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true, false}, // unconditional jump
104
105 {"JRGE", 0x1700, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if greater or equal
106 {"JRL", 0x1701, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if less
107 {"JRG", 0x1702, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if greater
108 {"JRLE", 0x1703, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if less or equal
109 {"JRNZ", 0x1704, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if not zero
110 {"JRZ", 0x1705, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if zero
111 {"JRNC", 0x1706, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if not carry
112 {"JRC", 0x1707, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if carry
113 {"JMPRx8", 0x1708, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if TODO
114 {"JMPRx9", 0x1709, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if TODO
115 {"JMPRxA", 0x170a, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if TODO
116 {"JMPRxB", 0x170b, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if TODO
117 {"JRLNZ", 0x170c, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if logic not zero
118 {"JRLZ", 0x170d, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if logic zero
119 {"JRO", 0x170e, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, false, false}, // jump to $R if overflow
120 {"JMPR", 0x170f, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, true, false, false}, // jump to $R
121
122 {"CALLRGE", 0x1710, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if greater or equal
123 {"CALLRL", 0x1711, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if less
124 {"CALLRG", 0x1712, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if greater
125 {"CALLRLE", 0x1713, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if less or equal
126 {"CALLRNZ", 0x1714, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if not zero
127 {"CALLRZ", 0x1715, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if zero
128 {"CALLRNC", 0x1716, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if not carry
129 {"CALLRC", 0x1717, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if carry
130 {"CALLRx8", 0x1718, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if TODO
131 {"CALLRx9", 0x1719, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if TODO
132 {"CALLRxA", 0x171a, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if TODO
133 {"CALLRxB", 0x171b, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if TODO
134 {"CALLRLNZ", 0x171c, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if logic not zero
135 {"CALLRLZ", 0x171d, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if logic zero
136 {"CALLRO", 0x171e, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, false, true, false}, // call $R if overflow
137 {"CALLR", 0x171f, 0xff1f, 1, 1, {{P_REG, 1, 0, 5, 0x00e0}}, false, true, true, true, false}, // call $R
138
139 {"SBCLR", 0x1200, 0xff00, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false, false, false, false}, // $sr &= ~(I + 6)
140 {"SBSET", 0x1300, 0xff00, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false, false, false, false}, // $sr |= (I + 6)
141
142 {"LSL", 0x1400, 0xfec0, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, // $acR <<= I
143 {"LSR", 0x1440, 0xfec0, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, // $acR >>= I (shifting in zeros)
144 {"ASL", 0x1480, 0xfec0, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, // $acR <<= I
145 {"ASR", 0x14c0, 0xfec0, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false, false, true}, // $acR >>= I (shifting in sign bits)
146
147 // these two were discovered by ector
148 {"LSRN", 0x02ca, 0xffff, 1, 0, {}, false, false, false, false, true}, // $ac0 >>=/<<= $ac1.m[0-6]
149 {"ASRN", 0x02cb, 0xffff, 1, 0, {}, false, false, false, false, true}, // $ac0 >>=/<<= $ac1.m[0-6] (arithmetic)
150
151 {"LRI", 0x0080, 0xffe0, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, false}, // $D = I
152 {"LR", 0x00c0, 0xffe0, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_MEM, 2, 1, 0, 0xffff}}, false, false, false, true, false}, // $D = MEM[M]
153 {"SR", 0x00e0, 0xffe0, 2, 2, {{P_MEM, 2, 1, 0, 0xffff}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, true, false}, // MEM[M] = $S
154
155 {"MRR", 0x1c00, 0xfc00, 1, 2, {{P_REG, 1, 0, 5, 0x03e0}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, // $D = $S
156
157 {"SI", 0x1600, 0xff00, 2, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, false}, // MEM[M] = I
158
159 {"ADDIS", 0x0400, 0xfe00, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false, false, true}, // $acD.hm += I
160 {"CMPIS", 0x0600, 0xfe00, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false, false, true}, // FLAGS($acD - I)
161 {"LRIS", 0x0800, 0xf800, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_IMM, 1, 0, 0, 0x00ff}}, false, false, false, false, true}, // $(D+24) = I
162
163 {"ADDI", 0x0200, 0xfeff, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $acD.hm += I
164 {"XORI", 0x0220, 0xfeff, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $acD.m ^= I
165 {"ANDI", 0x0240, 0xfeff, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $acD.m &= I
166 {"ORI", 0x0260, 0xfeff, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $acD.m |= I
167 {"CMPI", 0x0280, 0xfeff, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // FLAGS(($acD.hm - I) | $acD.l)
168
169 {"ANDF", 0x02a0, 0xfeff, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $sr.LZ = ($acD.m & I) == 0 ? 1 : 0
170 {"ANDCF", 0x02c0, 0xfeff, 2, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_IMM, 2, 1, 0, 0xffff}}, false, false, false, true, true}, // $sr.LZ = ($acD.m & I) == I ? 1 : 0
171
172 {"ILRR", 0x0210, 0xfefc, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $acD.m = IMEM[$arS]
173 {"ILRRD", 0x0214, 0xfefc, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $acD.m = IMEM[$arS--]
174 {"ILRRI", 0x0218, 0xfefc, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $acD.m = IMEM[$arS++]
175 {"ILRRN", 0x021c, 0xfefc, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $acD.m = IMEM[$arS]; $arS += $ixS
176
177 // LOOPS
178 {"LOOP", 0x0040, 0xffe0, 1, 1, {{P_REG, 1, 0, 0, 0x001f}}, false, true, true, true, false}, // run next instruction $R times
179 {"BLOOP", 0x0060, 0xffe0, 2, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true, false}, // COMEFROM addr $R times
180 {"LOOPI", 0x1000, 0xff00, 1, 1, {{P_IMM, 1, 0, 0, 0x00ff}}, false, true, true, true, false}, // run next instruction I times
181 {"BLOOPI", 0x1100, 0xff00, 2, 2, {{P_IMM, 1, 0, 0, 0x00ff}, {P_ADDR_I, 2, 1, 0, 0xffff}}, false, true, true, true, false}, // COMEFROM addr I times
182
183 // load and store value pointed by indexing reg and increment; LRR/SRR variants
184 {"LRR", 0x1800, 0xff80, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, // $D = MEM[$arS]
185 {"LRRD", 0x1880, 0xff80, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, // $D = MEM[$arS--]
186 {"LRRI", 0x1900, 0xff80, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, // $D = MEM[$arS++]
187 {"LRRN", 0x1980, 0xff80, 1, 2, {{P_REG, 1, 0, 0, 0x001f}, {P_PRG, 1, 0, 5, 0x0060}}, false, false, false, false, false}, // $D = MEM[$arS]; $arS += $ixS
188
189 {"SRR", 0x1a00, 0xff80, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, // MEM[$arD] = $S
190 {"SRRD", 0x1a80, 0xff80, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, // MEM[$arD--] = $S
191 {"SRRI", 0x1b00, 0xff80, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, // MEM[$arD++] = $S
192 {"SRRN", 0x1b80, 0xff80, 1, 2, {{P_PRG, 1, 0, 5, 0x0060}, {P_REG, 1, 0, 0, 0x001f}}, false, false, false, false, false}, // MEM[$arD] = $S; $arD += $ixD
193
194 //2
195 {"LRS", 0x2000, 0xf800, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_MEM, 1, 0, 0, 0x00ff}}, false, false, false, false, false}, // $(D+24) = MEM[($cr[0-7] << 8) | I]
196 {"SRS", 0x2800, 0xf800, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG18, 1, 0, 8, 0x0700}}, false, false, false, false, false}, // MEM[($cr[0-7] << 8) | I] = $(S+24)
197
198 // opcodes that can be extended
199
200 //3 - main opcode defined by 9 bits, extension defined by last 7 bits!!
201 {"XORR", 0x3000, 0xfc80, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD.m ^= $axS.h
202 {"ANDR", 0x3400, 0xfc80, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD.m &= $axS.h
203 {"ORR", 0x3800, 0xfc80, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD.m |= $axS.h
204 {"ANDC", 0x3c00, 0xfe80, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.m &= $ac(1-D).m
205 {"ORC", 0x3e00, 0xfe80, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.m |= $ac(1-D).m
206 {"XORC", 0x3080, 0xfe80, 1, 2, {{P_ACCM, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.m ^= $ac(1-D).m
207 {"NOT", 0x3280, 0xfe80, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.m = ~$acD.m
208 {"LSRNRX", 0x3480, 0xfc80, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD >>=/<<= $axS.h[0-6]
209 {"ASRNRX", 0x3880, 0xfc80, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD >>=/<<= $axS.h[0-6] (arithmetic)
210 {"LSRNR", 0x3c80, 0xfe80, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD >>=/<<= $ac(1-D).m[0-6]
211 {"ASRNR", 0x3e80, 0xfe80, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD >>=/<<= $ac(1-D).m[0-6] (arithmetic)
212
213 //4
214 {"ADDR", 0x4000, 0xf800, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false, false, true}, // $acD += $(S+24)
215 {"ADDAX", 0x4800, 0xfc00, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD += $axS
216 {"ADD", 0x4c00, 0xfe00, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD += $ac(1-D)
217 {"ADDP", 0x4e00, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD += $prod
218
219 //5
220 {"SUBR", 0x5000, 0xf800, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false, false, true}, // $acD -= $(S+24)
221 {"SUBAX", 0x5800, 0xfc00, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD -= $axS
222 {"SUB", 0x5c00, 0xfe00, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD -= $ac(1-D)
223 {"SUBP", 0x5e00, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD -= $prod
224
225 //6
226 {"MOVR", 0x6000, 0xf800, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false, false, true}, // $acD.hm = $(S+24); $acD.l = 0
227 {"MOVAX", 0x6800, 0xfc00, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD = $axS
228 {"MOV", 0x6c00, 0xfe00, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD = $ax(1-D)
229 {"MOVP", 0x6e00, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD = $prod
230
231 //7
232 {"ADDAXL", 0x7000, 0xfc00, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0200}}, true, false, false, false, true}, // $acD += $axS.l
233 {"INCM", 0x7400, 0xfe00, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acsD++
234 {"INC", 0x7600, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD++
235 {"DECM", 0x7800, 0xfe00, 1, 1, {{P_ACCM, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acsD--
236 {"DEC", 0x7a00, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD--
237 {"NEG", 0x7c00, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD = -$acD
238 {"MOVNP", 0x7e00, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD = -$prod
239
240 //8
241 {"NX", 0x8000, 0xf700, 1, 0, {}, true, false, false, false, false}, // extendable nop
242 {"CLR", 0x8100, 0xf700, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $acD = 0
243 {"CMP", 0x8200, 0xff00, 1, 0, {}, true, false, false, false, true}, // FLAGS($ac0 - $ac1)
244 {"MULAXH", 0x8300, 0xff00, 1, 0, {}, true, false, false, false, true}, // $prod = $ax0.h * $ax0.h
245 {"CLRP", 0x8400, 0xff00, 1, 0, {}, true, false, false, false, true}, // $prod = 0
246 {"TSTPROD", 0x8500, 0xff00, 1, 0, {}, true, false, false, false, true}, // FLAGS($prod)
247 {"TSTAXH", 0x8600, 0xfe00, 1, 1, {{P_REG1A, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // FLAGS($axR.h)
248 {"M2", 0x8a00, 0xff00, 1, 0, {}, true, false, false, false, false}, // enable "$prod *= 2" after every multiplication
249 {"M0", 0x8b00, 0xff00, 1, 0, {}, true, false, false, false, false}, // disable "$prod *= 2" after every multiplication
250 {"CLR15", 0x8c00, 0xff00, 1, 0, {}, true, false, false, false, false}, // set normal multiplication
251 {"SET15", 0x8d00, 0xff00, 1, 0, {}, true, false, false, false, false}, // set unsigned multiplication in MUL
252 {"SET16", 0x8e00, 0xff00, 1, 0, {}, true, false, false, false, false}, // set 16 bit sign extension width
253 {"SET40", 0x8f00, 0xff00, 1, 0, {}, true, false, false, false, false}, // set 40 bit sign extension width
254
255 //9
256 {"MUL", 0x9000, 0xf700, 1, 2, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $prod = $axS.l * $axS.h
257 {"ASR16", 0x9100, 0xf700, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $acD >>= 16 (shifting in sign bits)
258 {"MULMVZ", 0x9200, 0xf600, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR.hm = $prod.hm; $acR.l = 0; $prod = $axS.l * $axS.h
259 {"MULAC", 0x9400, 0xf600, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR += $prod; $prod = $axS.l * $axS.h
260 {"MULMV", 0x9600, 0xf600, 1, 3, {{P_REG18, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR = $prod; $prod = $axS.l * $axS.h
261
262 //a-b
263 {"MULX", 0xa000, 0xe700, 1, 2, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}}, true, false, false, false, true}, // $prod = $ax0.S * $ax1.T
264 {"ABS", 0xa100, 0xf700, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $acD = abs($acD)
265 {"MULXMVZ", 0xa200, 0xe600, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR.hm = $prod.hm; $acR.l = 0; $prod = $ax0.S * $ax1.T
266 {"MULXAC", 0xa400, 0xe600, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR += $prod; $prod = $ax0.S * $ax1.T
267 {"MULXMV", 0xa600, 0xe600, 1, 3, {{P_REGM18, 1, 0, 11, 0x1000}, {P_REGM19, 1, 0, 10, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR = $prod; $prod = $ax0.S * $ax1.T
268 {"TST", 0xb100, 0xf700, 1, 1, {{P_ACC, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // FLAGS($acR)
269
270 //c-d
271 {"MULC", 0xc000, 0xe700, 1, 2, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $prod = $acS.m * $axS.h
272 {"CMPAR", 0xc100, 0xe700, 1, 2, {{P_ACC, 1, 0, 11, 0x0800}, {P_REG1A, 1, 0, 12, 0x1000}}, true, false, false, false, true}, // FLAGS($acS - axR.h)
273 {"MULCMVZ", 0xc200, 0xe600, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR.hm, $acR.l, $prod = $prod.hm, 0, $acS.m * $axS.h
274 {"MULCAC", 0xc400, 0xe600, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR, $prod = $acR + $prod, $acS.m * $axS.h
275 {"MULCMV", 0xc600, 0xe600, 1, 3, {{P_ACCM, 1, 0, 12, 0x1000}, {P_REG1A, 1, 0, 11, 0x0800}, {P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR, $prod = $prod, $acS.m * $axS.h
276
277 //e
278 {"MADDX", 0xe000, 0xfc00, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, // $prod += $ax0.S * $ax1.T
279 {"MSUBX", 0xe400, 0xfc00, 1, 2, {{P_REGM18, 1, 0, 8, 0x0200}, {P_REGM19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, // $prod -= $ax0.S * $ax1.T
280 {"MADDC", 0xe800, 0xfc00, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, // $prod += $acS.m * $axT.h
281 {"MSUBC", 0xec00, 0xfc00, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false, false, false, true}, // $prod -= $acS.m * $axT.h
282
283 //f
284 {"LSL16", 0xf000, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR <<= 16
285 {"MADD", 0xf200, 0xfe00, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $prod += $axS.l * $axS.h
286 {"LSR16", 0xf400, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acR >>= 16
287 {"MSUB", 0xf600, 0xfe00, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $prod -= $axS.l * $axS.h
288 {"ADDPAXZ", 0xf800, 0xfc00, 1, 2, {{P_ACC, 1, 0, 9, 0x0200}, {P_AX, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.hm = $prod.hm + $ax.h; $acD.l = 0
289 {"CLRL", 0xfc00, 0xfe00, 1, 1, {{P_ACCL, 1, 0, 11, 0x0800}}, true, false, false, false, true}, // $acR.l = 0
290 {"MOVPZ", 0xfe00, 0xfe00, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false, false, true}, // $acD.hm = $prod.hm; $acD.l = 0
291 }};
292
293 const DSPOPCTemplate cw =
294 {"CW", 0x0000, 0x0000, 1, 1, {{P_VAL, 2, 0, 0, 0xffff}}, false, false, false, false, false};
295
296 // extended opcodes
297 const std::array<DSPOPCTemplate, 25> s_opcodes_ext =
298 {{
299 {"XXX", 0x0000, 0x00fc, 1, 1, {{P_VAL, 1, 0, 0, 0x00ff}}, false, false, false, false, false}, // no operation
300
301 {"DR", 0x0004, 0x00fc, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arR--
302 {"IR", 0x0008, 0x00fc, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arR++
303 {"NR", 0x000c, 0x00fc, 1, 1, {{P_REG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $arR += $ixR
304 {"MV", 0x0010, 0x00f0, 1, 2, {{P_REG18, 1, 0, 2, 0x000c}, {P_REG1C, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $(D+24) = $(S+28)
305
306 {"S", 0x0020, 0x00e4, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false, false, false, false, false}, // MEM[$D++] = $(S+28)
307 {"SN", 0x0024, 0x00e4, 1, 2, {{P_PRG, 1, 0, 0, 0x0003}, {P_REG1C, 1, 0, 3, 0x0018}}, false, false, false, false, false}, // MEM[$D] = $(D+28); $D += $(D+4)
308
309 {"L", 0x0040, 0x00c4, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $(D+24) = MEM[$S++]
310 {"LN", 0x0044, 0x00c4, 1, 2, {{P_REG18, 1, 0, 3, 0x0038}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $(D+24) = MEM[$S]; $S += $(S+4)
311
312 {"LS", 0x0080, 0x00ce, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false, false, false, false}, // $(D+24) = MEM[$ar0++]; MEM[$ar3++] = $acS.m
313 {"SL", 0x0082, 0x00ce, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false, false, false, false}, // MEM[$ar0++] = $acS.m; $(D+24) = MEM[$ar3++]
314 {"LSN", 0x0084, 0x00ce, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false, false, false, false}, // $(D+24) = MEM[$ar0]; MEM[$ar3++] = $acS.m; $ar0 += $ix0
315 {"SLN", 0x0086, 0x00ce, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false, false, false, false}, // MEM[$ar0] = $acS.m; $(D+24) = MEM[$ar3++]; $ar0 += $ix0
316 {"LSM", 0x0088, 0x00ce, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false, false, false, false}, // $(D+24) = MEM[$ar0++]; MEM[$ar3] = $acS.m; $ar3 += $ix3
317 {"SLM", 0x008a, 0x00ce, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false, false, false, false}, // MEM[$ar0++] = $acS.m; $(D+24) = MEM[$ar3]; $ar3 += $ix3
318 {"LSNM", 0x008c, 0x00ce, 1, 2, {{P_REG18, 1, 0, 4, 0x0030}, {P_ACCM, 1, 0, 0, 0x0001}}, false, false, false, false, false}, // $(D+24) = MEM[$ar0]; MEM[$ar3] = $acS.m; $ar0 += $ix0; $ar3 += $ix3
319 {"SLNM", 0x008e, 0x00ce, 1, 2, {{P_ACCM, 1, 0, 0, 0x0001}, {P_REG18, 1, 0, 4, 0x0030}}, false, false, false, false, false}, // MEM[$ar0] = $acS.m; $(D+24) = MEM[$ar3]; $ar0 += $ix0; $ar3 += $ix3
320
321 {"LDAX", 0x00c3, 0x00cf, 1, 2, {{P_AX, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, false, false, false, false, false}, // $axR.h = MEM[$arS++]; $axR.l = MEM[$ar3++]
322 {"LDAXN", 0x00c7, 0x00cf, 1, 2, {{P_AX, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, false, false, false, false, false}, // $axR.h = MEM[$arS]; $axR.l = MEM[$ar3++]; $arS += $ixS
323 {"LDAXM", 0x00cb, 0x00cf, 1, 2, {{P_AX, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, false, false, false, false, false}, // $axR.h = MEM[$arS++]; $axR.l = MEM[$ar3]; $ar3 += $ix3
324 {"LDAXNM", 0x00cf, 0x00cf, 1, 2, {{P_AX, 1, 0, 4, 0x0010}, {P_PRG, 1, 0, 5, 0x0020}}, false, false, false, false, false}, // $axR.h = MEM[$arS]; $axR.l = MEM[$ar3]; $arS += $ixS; $ar3 += $ix3
325
326 {"LD", 0x00c0, 0x00cc, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $ax0.D = MEM[$arS++]; $ax1.R = MEM[$ar3++]
327 {"LDN", 0x00c4, 0x00cc, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $ax0.D = MEM[$arS]; $ax1.R = MEM[$ar3++]; $arS += $ixS
328 {"LDM", 0x00c8, 0x00cc, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $ax0.D = MEM[$arS++]; $ax1.R = MEM[$ar3]; $ar3 += $ix3
329 {"LDNM", 0x00cc, 0x00cc, 1, 3, {{P_REGM18, 1, 0, 4, 0x0020}, {P_REGM19, 1, 0, 3, 0x0010}, {P_PRG, 1, 0, 0, 0x0003}}, false, false, false, false, false}, // $ax0.D = MEM[$arS]; $ax1.R = MEM[$ar3]; $arS += $ixS; $ar3 += $ix3
330 }};
331
332 const std::array<pdlabel_t, 96> pdlabels =
333 {{
334 {0xffa0, "COEF_A1_0", "COEF_A1_0",},
335 {0xffa1, "COEF_A2_0", "COEF_A2_0",},
336 {0xffa2, "COEF_A1_1", "COEF_A1_1",},
337 {0xffa3, "COEF_A2_1", "COEF_A2_1",},
338 {0xffa4, "COEF_A1_2", "COEF_A1_2",},
339 {0xffa5, "COEF_A2_2", "COEF_A2_2",},
340 {0xffa6, "COEF_A1_3", "COEF_A1_3",},
341 {0xffa7, "COEF_A2_3", "COEF_A2_3",},
342 {0xffa8, "COEF_A1_4", "COEF_A1_4",},
343 {0xffa9, "COEF_A2_4", "COEF_A2_4",},
344 {0xffaa, "COEF_A1_5", "COEF_A1_5",},
345 {0xffab, "COEF_A2_5", "COEF_A2_5",},
346 {0xffac, "COEF_A1_6", "COEF_A1_6",},
347 {0xffad, "COEF_A2_6", "COEF_A2_6",},
348 {0xffae, "COEF_A1_7", "COEF_A1_7",},
349 {0xffaf, "COEF_A2_7", "COEF_A2_7",},
350
351 {0xffb0, "0xffb0", nullptr,},
352 {0xffb1, "0xffb1", nullptr,},
353 {0xffb2, "0xffb2", nullptr,},
354 {0xffb3, "0xffb3", nullptr,},
355 {0xffb4, "0xffb4", nullptr,},
356 {0xffb5, "0xffb5", nullptr,},
357 {0xffb6, "0xffb6", nullptr,},
358 {0xffb7, "0xffb7", nullptr,},
359 {0xffb8, "0xffb8", nullptr,},
360 {0xffb9, "0xffb9", nullptr,},
361 {0xffba, "0xffba", nullptr,},
362 {0xffbb, "0xffbb", nullptr,},
363 {0xffbc, "0xffbc", nullptr,},
364 {0xffbd, "0xffbd", nullptr,},
365 {0xffbe, "0xffbe", nullptr,},
366 {0xffbf, "0xffbf", nullptr,},
367
368 {0xffc0, "0xffc0", nullptr,},
369 {0xffc1, "0xffc1", nullptr,},
370 {0xffc2, "0xffc2", nullptr,},
371 {0xffc3, "0xffc3", nullptr,},
372 {0xffc4, "0xffc4", nullptr,},
373 {0xffc5, "0xffc5", nullptr,},
374 {0xffc6, "0xffc6", nullptr,},
375 {0xffc7, "0xffc7", nullptr,},
376 {0xffc8, "0xffc8", nullptr,},
377 {0xffc9, "DSCR", "DSP DMA Control Reg",},
378 {0xffca, "0xffca", nullptr,},
379 {0xffcb, "DSBL", "DSP DMA Block Length",},
380 {0xffcc, "0xffcc", nullptr,},
381 {0xffcd, "DSPA", "DSP DMA DMEM Address",},
382 {0xffce, "DSMAH", "DSP DMA Mem Address H",},
383 {0xffcf, "DSMAL", "DSP DMA Mem Address L",},
384
385 {0xffd0, "0xffd0",nullptr,},
386 {0xffd1, "SampleFormat", "SampleFormat",},
387 {0xffd2, "0xffd2",nullptr,},
388 {0xffd3, "UnkZelda", "Unk Zelda reads/writes from/to it",},
389 {0xffd4, "ACSAH", "Accelerator start address H",},
390 {0xffd5, "ACSAL", "Accelerator start address L",},
391 {0xffd6, "ACEAH", "Accelerator end address H",},
392 {0xffd7, "ACEAL", "Accelerator end address L",},
393 {0xffd8, "ACCAH", "Accelerator current address H",},
394 {0xffd9, "ACCAL", "Accelerator current address L",},
395 {0xffda, "pred_scale", "pred_scale",},
396 {0xffdb, "yn1", "yn1",},
397 {0xffdc, "yn2", "yn2",},
398 {0xffdd, "ARAM", "Direct Read from ARAM (uses ADPCM)",},
399 {0xffde, "GAIN", "Gain",},
400 {0xffdf, "0xffdf", nullptr,},
401
402 {0xffe0, "0xffe0",nullptr,},
403 {0xffe1, "0xffe1",nullptr,},
404 {0xffe2, "0xffe2",nullptr,},
405 {0xffe3, "0xffe3",nullptr,},
406 {0xffe4, "0xffe4",nullptr,},
407 {0xffe5, "0xffe5",nullptr,},
408 {0xffe6, "0xffe6",nullptr,},
409 {0xffe7, "0xffe7",nullptr,},
410 {0xffe8, "0xffe8",nullptr,},
411 {0xffe9, "0xffe9",nullptr,},
412 {0xffea, "0xffea",nullptr,},
413 {0xffeb, "0xffeb",nullptr,},
414 {0xffec, "0xffec",nullptr,},
415 {0xffed, "0xffed",nullptr,},
416 {0xffee, "0xffee",nullptr,},
417 {0xffef, "AMDM", "ARAM DMA Request Mask",},
418
419 {0xfff0, "0xfff0",nullptr,},
420 {0xfff1, "0xfff1",nullptr,},
421 {0xfff2, "0xfff2",nullptr,},
422 {0xfff3, "0xfff3",nullptr,},
423 {0xfff4, "0xfff4",nullptr,},
424 {0xfff5, "0xfff5",nullptr,},
425 {0xfff6, "0xfff6",nullptr,},
426 {0xfff7, "0xfff7",nullptr,},
427 {0xfff8, "0xfff8",nullptr,},
428 {0xfff9, "0xfff9",nullptr,},
429 {0xfffa, "0xfffa",nullptr,},
430 {0xfffb, "DIRQ", "DSP IRQ Request",},
431 {0xfffc, "DMBH", "DSP Mailbox H",},
432 {0xfffd, "DMBL", "DSP Mailbox L",},
433 {0xfffe, "CMBH", "CPU Mailbox H",},
434 {0xffff, "CMBL", "CPU Mailbox L",},
435 }};
436
437 const std::array<pdlabel_t, 36> regnames =
438 {{
439 {0x00, "AR0", "Addr Reg 00",},
440 {0x01, "AR1", "Addr Reg 01",},
441 {0x02, "AR2", "Addr Reg 02",},
442 {0x03, "AR3", "Addr Reg 03",},
443 {0x04, "IX0", "Index Reg 0",},
444 {0x05, "IX1", "Index Reg 1",},
445 {0x06, "IX2", "Index Reg 2",},
446 {0x07, "IX3", "Index Reg 3",},
447 {0x08, "WR0", "Wrapping Register 0",},
448 {0x09, "WR1", "Wrapping Register 1",},
449 {0x0a, "WR2", "Wrapping Register 2",},
450 {0x0b, "WR3", "Wrapping Register 3",},
451 {0x0c, "ST0", "Call stack",},
452 {0x0d, "ST1", "Data stack",},
453 {0x0e, "ST2", "Loop addr stack",},
454 {0x0f, "ST3", "Loop counter stack",},
455 {0x10, "AC0.H", "Accu High 0",},
456 {0x11, "AC1.H", "Accu High 1",},
457 {0x12, "CR", "Config Register",},
458 {0x13, "SR", "Special Register",},
459 {0x14, "PROD.L", "Prod L",},
460 {0x15, "PROD.M1", "Prod M1",},
461 {0x16, "PROD.H", "Prod H",},
462 {0x17, "PROD.M2", "Prod M2",},
463 {0x18, "AX0.L", "Extra Accu L 0",},
464 {0x19, "AX1.L", "Extra Accu L 1",},
465 {0x1a, "AX0.H", "Extra Accu H 0",},
466 {0x1b, "AX1.H", "Extra Accu H 1",},
467 {0x1c, "AC0.L", "Accu Low 0",},
468 {0x1d, "AC1.L", "Accu Low 1",},
469 {0x1e, "AC0.M", "Accu Mid 0",},
470 {0x1f, "AC1.M", "Accu Mid 1",},
471
472 // To resolve combined register names.
473 {0x20, "ACC0", "Accu Full 0",},
474 {0x21, "ACC1", "Accu Full 1",},
475 {0x22, "AX0", "Extra Accu 0",},
476 {0x23, "AX1", "Extra Accu 1",},
477 }};
478 // clang-format on
479
480 std::array<u16, WRITEBACK_LOG_SIZE> writeBackLog;
481 std::array<int, WRITEBACK_LOG_SIZE> writeBackLogIdx;
482
pdname(u16 val)483 const char* pdname(u16 val)
484 {
485 static char tmpstr[12]; // nasty
486
487 for (const pdlabel_t& pdlabel : pdlabels)
488 {
489 if (pdlabel.addr == val)
490 return pdlabel.name;
491 }
492
493 sprintf(tmpstr, "0x%04x", val);
494 return tmpstr;
495 }
496
pdregname(int val)497 const char* pdregname(int val)
498 {
499 return regnames[val].name;
500 }
501
pdregnamelong(int val)502 const char* pdregnamelong(int val)
503 {
504 return regnames[val].description;
505 }
506
507 namespace
508 {
509 constexpr size_t OPTABLE_SIZE = 0xffff + 1;
510 constexpr size_t EXT_OPTABLE_SIZE = 0xff + 1;
511 std::array<const DSPOPCTemplate*, OPTABLE_SIZE> s_op_table;
512 std::array<const DSPOPCTemplate*, EXT_OPTABLE_SIZE> s_ext_op_table;
513
514 template <size_t N>
FindByName(std::string_view name,const std::array<DSPOPCTemplate,N> & data)515 auto FindByName(std::string_view name, const std::array<DSPOPCTemplate, N>& data)
516 {
517 return std::find_if(data.cbegin(), data.cend(),
518 [&name](const auto& info) { return name == info.name; });
519 }
520 } // Anonymous namespace
521
FindOpInfoByOpcode(UDSPInstruction opcode)522 const DSPOPCTemplate* FindOpInfoByOpcode(UDSPInstruction opcode)
523 {
524 const auto iter = FindByOpcode(opcode, s_opcodes);
525 if (iter == s_opcodes.cend())
526 return nullptr;
527
528 return &*iter;
529 }
530
FindOpInfoByName(std::string_view name)531 const DSPOPCTemplate* FindOpInfoByName(std::string_view name)
532 {
533 const auto iter = FindByName(name, s_opcodes);
534 if (iter == s_opcodes.cend())
535 return nullptr;
536
537 return &*iter;
538 }
539
FindExtOpInfoByOpcode(UDSPInstruction opcode)540 const DSPOPCTemplate* FindExtOpInfoByOpcode(UDSPInstruction opcode)
541 {
542 const auto iter = FindByOpcode(opcode, s_opcodes_ext);
543 if (iter == s_opcodes_ext.cend())
544 return nullptr;
545
546 return &*iter;
547 }
548
FindExtOpInfoByName(std::string_view name)549 const DSPOPCTemplate* FindExtOpInfoByName(std::string_view name)
550 {
551 const auto iter = FindByName(name, s_opcodes_ext);
552 if (iter == s_opcodes_ext.cend())
553 return nullptr;
554
555 return &*iter;
556 }
557
GetOpTemplate(UDSPInstruction inst)558 const DSPOPCTemplate* GetOpTemplate(UDSPInstruction inst)
559 {
560 return s_op_table[inst];
561 }
562
GetExtOpTemplate(UDSPInstruction inst)563 const DSPOPCTemplate* GetExtOpTemplate(UDSPInstruction inst)
564 {
565 const bool has_seven_bit_extension = (inst >> 12) == 0x3;
566
567 if (has_seven_bit_extension)
568 return s_ext_op_table[inst & 0x7F];
569
570 return s_ext_op_table[inst & 0xFF];
571 }
572
573 // This function could use the above GetOpTemplate, but then we'd lose the
574 // nice property that it catches colliding op masks.
InitInstructionTable()575 void InitInstructionTable()
576 {
577 // ext op table
578 for (size_t i = 0; i < s_ext_op_table.size(); i++)
579 {
580 s_ext_op_table[i] = &cw;
581
582 const auto iter = FindByOpcode(static_cast<UDSPInstruction>(i), s_opcodes_ext);
583 if (iter == s_opcodes_ext.cend())
584 continue;
585
586 if (s_ext_op_table[i] == &cw)
587 {
588 s_ext_op_table[i] = &*iter;
589 }
590 else
591 {
592 // If the entry already in the table is a strict subset, allow it
593 if ((s_ext_op_table[i]->opcode_mask | iter->opcode_mask) != s_ext_op_table[i]->opcode_mask)
594 {
595 ERROR_LOG(DSPLLE, "opcode ext table place %zu already in use by %s when inserting %s", i,
596 s_ext_op_table[i]->name, iter->name);
597 }
598 }
599 }
600
601 // op table
602 s_op_table.fill(&cw);
603
604 for (size_t i = 0; i < s_op_table.size(); i++)
605 {
606 const auto iter = FindByOpcode(static_cast<UDSPInstruction>(i), s_opcodes);
607 if (iter == s_opcodes.cend())
608 continue;
609
610 if (s_op_table[i] == &cw)
611 s_op_table[i] = &*iter;
612 else
613 ERROR_LOG(DSPLLE, "opcode table place %zu already in use for %s", i, iter->name);
614 }
615
616 writeBackLogIdx.fill(-1);
617
618 // Ensure the interpreter tables are all set up, as JITs also rely on them.
619 Interpreter::InitInstructionTables();
620 }
621 } // namespace DSP
622