1 //****************************************************************************
2 //
3 // SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
4 // SPDX-License-Identifier: MIT
5 //
6 // Permission is hereby granted, free of charge, to any person obtaining a
7 // copy of this software and associated documentation files (the "Software"),
8 // to deal in the Software without restriction, including without limitation
9 // the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 // and/or sell copies of the Software, and to permit persons to whom the
11 // Software is furnished to do so, subject to the following conditions:
12 //
13 // The above copyright notice and this permission notice shall be included in
14 // all copies or substantial portions of the Software.
15 //
16 // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 // THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 // FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 // DEALINGS IN THE SOFTWARE.
23 //
24 // File: nvtiming.h
25 //
26 // Purpose: This file is the common header all nv timing library clients.
27 //
28 //*****************************************************************************
29
30 #ifndef __NVTIMING_H__
31 #define __NVTIMING_H__
32
33 #include "nvtypes.h"
34
35
36 #define abs_delta(a,b) ((a)>(b)?((a)-(b)):((b)-(a)))
37
38 //***********************
39 // The Timing Structure
40 //***********************
41 //
42 // Nvidia specific timing extras
43 typedef struct tagNVT_HDMIEXT
44 {
45 // in the case of stereo, the NVT_TIMING structure will hold the 2D
46 // instance of the timing parameters, and the stereo extension will
47 // contain the variants required to produce the stereo frame.
48 NvU8 StereoStructureType;
49 NvU8 SideBySideHalfDetail;
50 NvU16 VActiveSpace[2];
51 } NVT_HDMIEXT;
52 #define NVT_HDMI_3D_SUPPORTED_STRUCT_MASK(x) (1 << (x))
53 #define NVT_HDMI_3D_SUPPORTED_FRAMEPACK_MASK NVT_HDMI_3D_SUPPORTED_STRUCT_MASK(NVT_HDMI_VS_BYTE5_HDMI_3DS_FRAMEPACK)
54 #define NVT_HDMI_3D_SUPPORTED_FIELD_ALT_MASK NVT_HDMI_3D_SUPPORTED_STRUCT_MASK(NVT_HDMI_VS_BYTE5_HDMI_3DS_FIELD_ALT)
55 #define NVT_HDMI_3D_SUPPORTED_LINE_ALT_MASK NVT_HDMI_3D_SUPPORTED_STRUCT_MASK(NVT_HDMI_VS_BYTE5_HDMI_3DS_LINE_ALT)
56 #define NVT_HDMI_3D_SUPPORTED_SIDEBYSIDEFULL_MASK NVT_HDMI_3D_SUPPORTED_STRUCT_MASK(NVT_HDMI_VS_BYTE5_HDMI_3DS_SIDEBYSIDEFULL)
57 #define NVT_HDMI_3D_SUPPORTED_LDEPTH_MASK NVT_HDMI_3D_SUPPORTED_STRUCT_MASK(NVT_HDMI_VS_BYTE5_HDMI_3DS_LDEPTH)
58 #define NVT_HDMI_3D_SUPPORTED_LDEPTHGFX_MASK NVT_HDMI_3D_SUPPORTED_STRUCT_MASK(NVT_HDMI_VS_BYTE5_HDMI_3DS_LDEPTHGFX)
59 #define NVT_HDMI_3D_SUPPORTED_TOPBOTTOM_MASK NVT_HDMI_3D_SUPPORTED_STRUCT_MASK(NVT_HDMI_VS_BYTE5_HDMI_3DS_TOPBOTTOM)
60 #define NVT_HDMI_3D_SUPPORTED_SIDEBYSIDEHALF_MASK NVT_HDMI_3D_SUPPORTED_STRUCT_MASK(NVT_HDMI_VS_BYTE5_HDMI_3DS_SIDEBYSIDEHALF)
61 #define NVT_ALL_HDMI_3D_STRUCT_SUPPORTED_MASK (NVT_HDMI_3D_SUPPORTED_FRAMEPACK_MASK | NVT_HDMI_3D_SUPPORTED_TOPBOTTOM_MASK | NVT_HDMI_3D_SUPPORTED_SIDEBYSIDEHALF_MASK)
62
63 typedef union tagNVT_COLORDEPTH
64 {
65 NvU8 bpcs;
66 struct
67 {
68 NvU8 bpc6 : 1;
69 NvU8 bpc8 : 1;
70 NvU8 bpc10 : 1;
71 NvU8 bpc12 : 1;
72 NvU8 bpc14 : 1;
73 NvU8 bpc16 : 1;
74 NvU8 rsrvd1 : 1; // must be 0
75 NvU8 rsrvd2 : 1; // must be 0
76 } bpc;
77 } NVT_COLORDEPTH;
78
79 #define IS_BPC_SUPPORTED_COLORFORMAT(colorDepth) (!!((NvU8)(colorDepth)))
80 #define UPDATE_BPC_FOR_COLORFORMAT(colorFormat, b6bpc, b8bpc, b10bpc, b12bpc, b14bpc, b16bpc) \
81 if ((b6bpc)) ((colorFormat).bpc.bpc6 = 1); \
82 if ((b8bpc)) ((colorFormat).bpc.bpc8 = 1); \
83 if ((b10bpc)) ((colorFormat).bpc.bpc10 = 1); \
84 if ((b12bpc)) ((colorFormat).bpc.bpc12 = 1); \
85 if ((b14bpc)) ((colorFormat).bpc.bpc14 = 1); \
86 if ((b16bpc)) ((colorFormat).bpc.bpc16 = 1);
87
88 #define SET_BPC_FOR_COLORFORMAT(_colorFormat, _bpc) \
89 if ((_bpc) == NVT_EDID_VIDEOSIGNAL_BPC_6) \
90 ((_colorFormat).bpc.bpc6 = 1); \
91 else if ((_bpc) == NVT_EDID_VIDEOSIGNAL_BPC_8) \
92 ((_colorFormat).bpc.bpc8 = 1); \
93 else if ((_bpc) == NVT_EDID_VIDEOSIGNAL_BPC_10) \
94 ((_colorFormat).bpc.bpc10 = 1); \
95 else if ((_bpc) == NVT_EDID_VIDEOSIGNAL_BPC_12) \
96 ((_colorFormat).bpc.bpc12 = 1); \
97 else if ((_bpc) == NVT_EDID_VIDEOSIGNAL_BPC_16) ((_colorFormat).bpc.bpc16 = 1);
98
99 #define CLEAR_BPC_FOR_COLORFORMAT(_colorFormat, _bpc) \
100 if ((_bpc) == NVT_EDID_VIDEOSIGNAL_BPC_6) \
101 ((_colorFormat).bpc.bpc6 = 0); \
102 else if ((_bpc) == NVT_EDID_VIDEOSIGNAL_BPC_8) \
103 ((_colorFormat).bpc.bpc8 = 0); \
104 else if ((_bpc) == NVT_EDID_VIDEOSIGNAL_BPC_10) \
105 ((_colorFormat).bpc.bpc10 = 0); \
106 else if ((_bpc) == NVT_EDID_VIDEOSIGNAL_BPC_12) \
107 ((_colorFormat).bpc.bpc12 = 0); \
108 else if ((_bpc) == NVT_EDID_VIDEOSIGNAL_BPC_16) ((_colorFormat).bpc.bpc16 = 0);
109
110 #define NVT_COLORDEPTH_HIGHEST_BPC(_colorFormat) \
111 (_colorFormat).bpc.bpc16 ? NVT_EDID_VIDEOSIGNAL_BPC_16 : \
112 (_colorFormat).bpc.bpc12 ? NVT_EDID_VIDEOSIGNAL_BPC_12 : \
113 (_colorFormat).bpc.bpc10 ? NVT_EDID_VIDEOSIGNAL_BPC_10 : \
114 (_colorFormat).bpc.bpc8 ? NVT_EDID_VIDEOSIGNAL_BPC_8 : \
115 (_colorFormat).bpc.bpc6 ? NVT_EDID_VIDEOSIGNAL_BPC_6 : NVT_EDID_VIDEOSIGNAL_BPC_NOT_DEFINED
116
117 #define NVT_COLORDEPTH_LOWEREST_BPC(_colorFormat) \
118 (_colorFormat).bpc.bpc6 ? NVT_EDID_VIDEOSIGNAL_BPC_6 : \
119 (_colorFormat).bpc.bpc8 ? NVT_EDID_VIDEOSIGNAL_BPC_8 : \
120 (_colorFormat).bpc.bpc10 ? NVT_EDID_VIDEOSIGNAL_BPC_10 : \
121 (_colorFormat).bpc.bpc12 ? NVT_EDID_VIDEOSIGNAL_BPC_12 : \
122 (_colorFormat).bpc.bpc16 ? NVT_EDID_VIDEOSIGNAL_BPC_16 : NVT_EDID_VIDEOSIGNAL_BPC_NOT_DEFINED
123
124 typedef struct tagNVT_TIMINGEXT
125 {
126 NvU32 flag; // reserve for NV h/w based enhancement like double-scan.
127 NvU16 rr; // the logical refresh rate to present
128 NvU32 rrx1k; // the physical vertical refresh rate in 0.001Hz
129 NvU32 aspect; // the display aspect ratio Hi(aspect):horizontal-aspect, Low(aspect):vertical-aspect
130 //
131 // Bitmask of one-hot encoded possible pixel repetitions:
132 // 0x1: no pixel repetition (i.e., display each pixel once)
133 // 0x2: each pixel is displayed twice horizontally;
134 // 0x3: use either no pixel repetition or display each pixel twice
135 // ...
136 //
137 NvU16 rep;
138 NVT_COLORDEPTH rgb444; // each bit within is set if rgb444 supported on that bpc
139 NVT_COLORDEPTH yuv444; // each bit within is set if yuv444 supported on that bpc
140 NVT_COLORDEPTH yuv422; // each bit within is set if yuv422 supported on that bpc
141 NVT_COLORDEPTH yuv420; // each bit within is set if yuv420 supported on that bpc
142 NvU32 status; // the timing standard being used
143 NvU8 name[51]; // the name of the timing
144 }NVT_TIMINGEXT;
145 //
146 //
147 //The very basic timing structure based on the VESA standard:
148 //
149 // |<----------------------------htotal--------------------------->|
150 // ---------"active" video-------->|<-------blanking------>|<-----
151 // |<-------hvisible-------->|<-hb->|<-hfp->|<-hsw->|<-hbp->|<-hb->|
152 // ----------+-------------------------+ | | | | |
153 // A A | | | | | | |
154 // : : | | | | | | |
155 // : : | | | | | | |
156 // :verical| addressable video | | | | | |
157 // :visible| | | | | | |
158 // : : | | | | | | |
159 // : : | | | | | | |
160 // verical V | | | | | | |
161 // total --+-------------------------+ | | | | |
162 // : vb border | | | | |
163 // : -----------------------------------+ | | | |
164 // : vfp front porch | | | |
165 // : -------------------------------------------+ | | |
166 // : vsw sync width | | |
167 // : ---------------------------------------------------+ | |
168 // : vbp back porch | |
169 // : -----------------------------------------------------------+ |
170 // V vb border |
171 // --------------------------------------------------------------------------+
172 //
173 typedef struct tagNVT_TIMING
174 {
175 // VESA scan out timing parameters:
176 NvU16 HVisible; //horizontal visible
177 NvU16 HBorder; //horizontal border
178 NvU16 HFrontPorch; //horizontal front porch
179 NvU16 HSyncWidth; //horizontal sync width
180 NvU16 HTotal; //horizontal total
181 NvU8 HSyncPol; //horizontal sync polarity: 1-negative, 0-positive
182
183 NvU16 VVisible; //vertical visible
184 NvU16 VBorder; //vertical border
185 NvU16 VFrontPorch; //vertical front porch
186 NvU16 VSyncWidth; //vertical sync width
187 NvU16 VTotal; //vertical total
188 NvU8 VSyncPol; //vertical sync polarity: 1-negative, 0-positive
189
190 NvU16 interlaced; //1-interlaced, 0-progressive
191 NvU32 pclk; //pixel clock in 10KHz
192
193 //other timing related extras
194 NVT_TIMINGEXT etc;
195 }NVT_TIMING;
196
197 #define NVT_MAX_TOTAL_TIMING 128
198
199 //
200 // The below VSync/HSync Polarity definition have been inverted to match
201 // HW Display Class definition.
202 // timing related constants:
203 #define NVT_H_SYNC_POSITIVE 0
204 #define NVT_H_SYNC_NEGATIVE 1
205 #define NVT_H_SYNC_DEFAULT NVT_H_SYNC_NEGATIVE
206 //
207 #define NVT_V_SYNC_POSITIVE 0
208 #define NVT_V_SYNC_NEGATIVE 1
209 #define NVT_V_SYNC_DEFAULT NVT_V_SYNC_POSITIVE
210 //
211 #define NVT_PROGRESSIVE 0
212 #define NVT_INTERLACED 1
213 #define NVT_INTERLACED_EXTRA_VBLANK_ON_FIELD2 1
214 #define NVT_INTERLACED_NO_EXTRA_VBLANK_ON_FIELD2 2
215
216 // timing related macros:
217 #define NVT_FRAME_HEIGHT(_vvisible_, _interlaced_) ((_vvisible_) * ((_interlaced_ != 0) ? 2 : 1))
218
219 //*************************************
220 // The Timing Status encoded in
221 // NVT_TIMING::NVT_TIMINGEXT::status
222 //*************************************
223 //
224 // TIMING_STATUS has the following kinds of info:
225 //
226 // NVT_TIMING::NVT_TIMINGEXT::status
227 //
228 // +----+----+---------+----+----+------------------------------+---+---------------+---+----------------+
229 // bit31 bit30 bit29 bit22 bit21 bit20 bit16 bit15 bit8 bit7 bit0
230 // |native|cust|<-cta format->|Dual|<--------mismatch status-------->|<---timing type--->|<---timing seq#--->|
231 //
232 // 1. the monitor preferred timing flag and cust EDID entry flag
233 //
234 #define NVT_STATUS_TIMING_NATIVE_FLAG_MASK 0x80000000
235 #define NVT_STATUS_TIMING_NATIVE_FLAG_SHIFT 31
236 #define NVT_IS_NATIVE_TIMING(n) (((n)&NVT_STATUS_TIMING_NATIVE_FLAG_MASK)>>NVT_STATUS_TIMING_NATIVE_FLAG_SHIFT)
237 #define NVT_SET_NATIVE_TIMING_FLAG(n) ((n)|=1U<< NVT_STATUS_TIMING_NATIVE_FLAG_SHIFT)
238 #define NVT_PREFERRED_TIMING_MODE_MASK 0x2
239 //
240 #define NVT_STATUS_TIMING_CUST_ENTRY_MASK 0x40000000
241 #define NVT_STATUS_TIMING_CUST_ENTRY_SHIFT 30
242 #define NVT_IS_CUST_ENTRY(n) (((n)&NVT_STATUS_TIMING_CUST_ENTRY_MASK)>>NVT_STATUS_TIMING_CUST_ENTRY_SHIFT)
243 #define NVT_SET_CUST_ENTRY_FLAG(n) ((n)|=1<<NVT_STATUS_TIMING_CUST_ENTRY_SHIFT)
244 //
245 #define NVT_STATUS_TIMING_CEA_FORMAT_MASK 0x3FC00000
246 #define NVT_STATUS_TIMING_CEA_FORMAT_SHIFT 22
247 #define NVT_GET_CEA_FORMAT(n) (((n)&NVT_STATUS_TIMING_CEA_FORMAT_MASK)>>NVT_STATUS_TIMING_CEA_FORMAT_SHIFT)
248 #define NVT_SET_CEA_FORMAT(n,index) {(n)&=~NVT_STATUS_TIMING_CEA_FORMAT_MASK;(n)|=(index)<<NVT_STATUS_TIMING_CEA_FORMAT_SHIFT;}
249 //
250 //
251 // 2. CEA/DMT dual standard flag
252 //
253 #define NVT_STATUS_TIMING_CEA_DMT_MASK 0x00200000
254 #define NVT_STATUS_TIMING_CEA_DMT_SHIFT 21
255 #define NVT_IS_CEA_DMT_DUAL_STANDARD(n) (((n)&NVT_STATUS_TIMING_CEA_DMT_MASK)>>NVT_STATUS_TIMING_CEA_DMT_SHIFT)
256 #define NVT_SET_CEA_DMT_DUAL_STANDARD_FLAG(n) ((n)|=NVT_STATUS_TIMING_CEA_DMT_MASK)
257 //
258 //
259 // 3. the mismatch status
260 #define NVT_STATUS_TIMING_MISMATCH_MASK 0x001F0000
261 #define NVT_STATUS_TIMING_MISMATCH_SHIFT 16
262 #define NVT_STATUS_TIMING_MISMATCH_SIZE 0x1 //visible width and height don't match with the asked width/height
263 #define NVT_STATUS_TIMING_MISMATCH_RR 0x2 //the refresh rate doesn't match with the requested
264 #define NVT_STATUS_TIMING_MISMATCH_FORMAT 0x4 //other timing info doesn't match (i.e. progressive/interlaced, double, reduced-blanking etc...)
265 #define NVT_STATUS_TIMING_MISMATCH_ALIGNMENT 0x8 //the asking alignment doesn't match the spec
266 //
267 // macroes to set/get the timing mismatch status
268 #define NVT_SET_TIMING_STATUS_MISMATCH(m,n) ((m)|=(((n)<<NVT_STATUS_TIMING_MISMATCH_SHIFT)&NVT_STATUS_TIMING_MISMATCH_MASK))
269 #define NVT_GET_TIMING_STATUS_MATCH(n) (((n)&NVT_STATUS_TIMING_MISMATCH_MASK)>>NVT_STATUS_TIMING_MISMATCH_SHIFT)
270 //
271 //
272 // 4. the timing type
273 //
274 #define NVT_STATUS_TIMING_TYPE_MASK 0x0000FF00
275 #define NVT_STATUS_TIMING_TYPE_SHIFT 8
276 //
277 typedef enum NVT_TIMING_TYPE
278 {
279 NVT_TYPE_DMT = 1, // DMT
280 NVT_TYPE_GTF, // GTF
281 NVT_TYPE_ASPR, // wide aspect ratio timing, for legacy support only
282 NVT_TYPE_NTSC_TV, // NTSC TV timing. for legacy support only
283 NVT_TYPE_PAL_TV, // PAL TV timing, legacy support only
284 NVT_TYPE_CVT, // CVT timing
285 NVT_TYPE_CVT_RB, // CVT timing with reduced blanking
286 NVT_TYPE_CUST, // Customized timing
287 NVT_TYPE_EDID_DTD, // EDID detailed timing
288 NVT_TYPE_EDID_STD, // = 10 EDID standard timing
289 NVT_TYPE_EDID_EST, // EDID established timing
290 NVT_TYPE_EDID_CVT, // EDID defined CVT timing (EDID 1.4)
291 NVT_TYPE_EDID_861ST, // EDID defined CEA/EIA 861 timing (in the CTA861 extension)
292 NVT_TYPE_NV_PREDEFINED, // NV pre-defined timings (PsF timings)
293 NVT_TYPE_DMT_RB, // DMT timing with reduced blanking
294 NVT_TYPE_EDID_EXT_DTD, // EDID detailed timing in the extension
295 NVT_TYPE_SDTV, // SDTV timing (including NTSC, PAL etc)
296 NVT_TYPE_HDTV, // HDTV timing (480p,480i,720p, 1080i etc)
297 NVT_TYPE_SMPTE, // deprecated ? still used by drivers\unix\nvkms\src\nvkms-dpy.c
298 NVT_TYPE_EDID_VTB_EXT, // = 20 EDID defined VTB extension timing
299 NVT_TYPE_EDID_VTB_EXT_STD, // EDID defined VTB extension standard timing
300 NVT_TYPE_EDID_VTB_EXT_DTD, // EDID defined VTB extension detailed timing
301 NVT_TYPE_EDID_VTB_EXT_CVT, // EDID defined VTB extension cvt timing
302 NVT_TYPE_HDMI_STEREO, // EDID defined HDMI stereo timing
303 NVT_TYPE_DISPLAYID_1, // DisplayID Type 1 timing
304 NVT_TYPE_DISPLAYID_2, // DisplayID Type 2 timing
305 NVT_TYPE_HDMI_EXT, // EDID defined HDMI extended resolution timing (UHDTV - 4k, 8k etc.)
306 NVT_TYPE_CUST_AUTO, // Customized timing generated automatically by NVCPL
307 NVT_TYPE_CUST_MANUAL, // Customized timing entered manually by user
308 NVT_TYPE_CVT_RB_2, // = 30 CVT timing with reduced blanking V2
309 NVT_TYPE_DMT_RB_2, // DMT timing with reduced blanking V2
310 NVT_TYPE_DISPLAYID_7, // DisplayID 2.0 detailed timing - Type VII
311 NVT_TYPE_DISPLAYID_8, // DisplayID 2.0 enumerated timing - Type VIII
312 NVT_TYPE_DISPLAYID_9, // DisplayID 2.0 formula-based timing - Type IX
313 NVT_TYPE_DISPLAYID_10, // DisplayID 2.0 formula-based timing - Type X
314 NVT_TYPE_CVT_RB_3, // CVT timing with reduced blanking V3
315 NVT_TYPE_CTA861_DID_T7, // EDID defined CTA861 DisplayID Type VII timing (in the CTA861 extension)
316 NVT_TYPE_CTA861_DID_T8, // EDID defined CTA861 DisplayID Type VIII timing (in the CTA861 extension)
317 NVT_TYPE_CTA861_DID_T10 // EDID defined CTA861 DisplayID Type X timing (in the CTA861 extension)
318 }NVT_TIMING_TYPE;
319 //
320 // 5. the timing sequence number like the TV format and EIA861B predefined timing format
321 // **the numbers are chosen to match with the NV h/w format**
322 //
323 #define NVT_STATUS_TIMING_SEQ_MASK 0x000000FF
324 //
325 typedef enum NVT_TV_FORMAT
326 {
327 NVT_NTSC = 0,
328 NVT_NTSC_M = 0,
329 NVT_NTSC_J = 1,
330 NVT_PAL = 2,
331 NVT_PAL_M = 2,
332 NVT_PAL_A = 3,
333 NVT_PAL_N = 4,
334 NVT_PAL_NC = 5,
335 NVT_HD576I = 8,
336 NVT_HD480I,
337 NVT_HD480P,
338 NVT_HD576P,
339 NVT_HD720P,
340 NVT_HD1080I,
341 NVT_HD1080P,
342 NVT_HD720P50,
343 NVT_HD1080P24,
344 NVT_HD1080I50,
345 NVT_HD1080P50,
346 NVT_MAX_TV_FORMAT,
347 NVT_AUTO_SDTV_FORMAT = (NvU32)(-2), // Not supported in NvTiming_GetTvTiming
348 NVT_AUTO_HDTV_FORMAT = (NvU32)(-1),
349 }NVT_TV_FORMAT;
350
351 #define NVT_DEFAULT_HDTV_FMT NVT_HD1080I
352 //
353 // macros to set/get the timing type and seq number
354 //
355 #define NVT_DEF_TIMING_STATUS(type, seq) ((((type)<<NVT_STATUS_TIMING_TYPE_SHIFT)&NVT_STATUS_TIMING_TYPE_MASK) | ((seq)&NVT_STATUS_TIMING_SEQ_MASK))
356 #define NVT_SET_TIMING_STATUS_TYPE(n, type) (((n)&(~NVT_STATUS_TIMING_TYPE_MASK)) | ((type)<<NVT_STATUS_TIMING_TYPE_SHIFT))
357 #define NVT_GET_TIMING_STATUS_TYPE(n) ((n)&NVT_STATUS_TIMING_TYPE_MASK)>>NVT_STATUS_TIMING_TYPE_SHIFT
358 #define NVT_GET_TIMING_STATUS_SEQ(n) ((n)&NVT_STATUS_TIMING_SEQ_MASK)
359 //
360 //
361 //
362 // the timing type definitions
363 #define NVT_STATUS_DMT NVT_DEF_TIMING_STATUS(NVT_TYPE_DMT, 0) // DMT
364 #define NVT_STATUS_GTF NVT_DEF_TIMING_STATUS(NVT_TYPE_GTF, 0) // GTF
365 #define NVT_STATUS_ASPR NVT_DEF_TIMING_STATUS(NVT_TYPE_ASPR, 0) // ASPR
366 #define NVT_STATUS_NTSC_TV NVT_DEF_TIMING_STATUS(NVT_TYPE_NTSC_TV, 0) // TVN
367 #define NVT_STATUS_PAL_TV NVT_DEF_TIMING_STATUS(NVT_TYPE_PAL_TV, 0) // TVP
368 #define NVT_STATUS_CVT NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT, 0) // CVT timing with regular blanking
369 #define NVT_STATUS_CVT_RB NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT_RB, 0) // CVT_RB timing V1
370 #define NVT_STATUS_CVT_RB_2 NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT_RB_2, 0) // CVT_RB timing V2
371 #define NVT_STATUS_CVT_RB_3 NVT_DEF_TIMING_STATUS(NVT_TYPE_CVT_RB_3, 0) // CVT_RB timing V3
372 #define NVT_STATUS_CUST NVT_DEF_TIMING_STATUS(NVT_TYPE_CUST, 0) // Customized timing
373 #define NVT_STATUS_EDID_DTD NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_DTD, 0)
374 #define NVT_STATUS_EDID_STD NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_STD, 0)
375 #define NVT_STATUS_EDID_EST NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_EST, 0)
376 #define NVT_STATUS_EDID_CVT NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_CVT, 0)
377 #define NVT_STATUS_EDID_861ST NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_861ST, 0)
378 #define NVT_STATUS_DMT_RB NVT_DEF_TIMING_STATUS(NVT_TYPE_DMT_RB, 0)
379 #define NVT_STATUS_EDID_EXT_DTD NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_EXT_DTD, 0)
380 #define NVT_STATUS_SDTV_NTSC NVT_DEF_TIMING_STATUS(NVT_TYPE_SDTV, NVT_NTSC)
381 #define NVT_STATUS_SDTV_NTSC_M NVT_DEF_TIMING_STATUS(NVT_TYPE_SDTV, NVT_NTSC)
382 #define NVT_STATUS_SDTV_NTSC_J NVT_DEF_TIMING_STATUS(NVT_TYPE_SDTV, NVT_NTSC_J)
383 #define NVT_STATUS_SDTV_PAL NVT_DEF_TIMING_STATUS(NVT_TYPE_SDTV, NVT_PAL)
384 #define NVT_STATUS_SDTV_PAL_M NVT_DEF_TIMING_STATUS(NVT_TYPE_SDTV, NVT_PAL)
385 #define NVT_STATUS_SDTV_PAL_A NVT_DEF_TIMING_STATUS(NVT_TYPE_SDTV, NVT_PAL_A)
386 #define NVT_STATUS_SDTV_PAL_N NVT_DEF_TIMING_STATUS(NVT_TYPE_SDTV, NVT_PAL_N)
387 #define NVT_STATUS_SDTV_PAL_NC NVT_DEF_TIMING_STATUS(NVT_TYPE_SDTV, NVT_PAL_NC)
388 #define NVT_STATUS_HDTV_480I NVT_DEF_TIMING_STATUS(NVT_TYPE_HDTV, NVT_HD480I)
389 #define NVT_STATUS_HDTV_480P NVT_DEF_TIMING_STATUS(NVT_TYPE_HDTV, NVT_HD480P)
390 #define NVT_STATUS_HDTV_576I NVT_DEF_TIMING_STATUS(NVT_TYPE_HDTV, NVT_HD576I)
391 #define NVT_STATUS_HDTV_576P NVT_DEF_TIMING_STATUS(NVT_TYPE_HDTV, NVT_HD576P)
392 #define NVT_STATUS_HDTV_720P NVT_DEF_TIMING_STATUS(NVT_TYPE_HDTV, NVT_HD720P)
393 #define NVT_STATUS_HDTV_1080I NVT_DEF_TIMING_STATUS(NVT_TYPE_HDTV, NVT_HD1080I)
394 #define NVT_STATUS_HDTV_1080P NVT_DEF_TIMING_STATUS(NVT_TYPE_HDTV, NVT_HD1080P)
395 #define NVT_STATUS_HDTV_720P50 NVT_DEF_TIMING_STATUS(NVT_TYPE_HDTV, NVT_HD720P50)
396 #define NVT_STATUS_HDTV_1080P24 NVT_DEF_TIMING_STATUS(NVT_TYPE_HDTV, NVT_HD1080P24)
397 #define NVT_STATUS_HDTV_1080I50 NVT_DEF_TIMING_STATUS(NVT_TYPE_HDTV, NVT_HD1080I50)
398 #define NVT_STATUS_HDTV_1080P50 NVT_DEF_TIMING_STATUS(NVT_TYPE_HDTV, NVT_HD1080P50)
399 #define NVT_STATUS_EDID_VTB_EXT NVT_DEF_TIMING_STATUS(NVT_TYPE_VTB_EXT, 0)
400 #define NVT_STATUS_EDID_VTB_EXT_DTD NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_VTB_EXT_DTD, 0)
401 #define NVT_STATUS_EDID_VTB_EXT_CVT NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_VTB_EXT_CVT, 0)
402 #define NVT_STATUS_EDID_VTB_EXT_STD NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_VTB_EXT_STD, 0)
403 #define NVT_STATUS_HDMI_STEREO NVT_DEF_TIMING_STATUS(NVT_TYPE_HDMI_STEREO, 0)
404 #define NVT_STATUS_DISPLAYID_1 NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_1, 0)
405 #define NVT_STATUS_DISPLAYID_2 NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_2, 0)
406 #define NVT_STATUS_DISPLAYID_7 NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_7, 0)
407 #define NVT_STATUS_DISPLAYID_8 NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_8, 0)
408 #define NVT_STATUS_DISPLAYID_9 NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_9, 0)
409 #define NVT_STATUS_DISPLAYID_10 NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_10, 0)
410 #define NVT_STATUS_HDMI_EXT NVT_DEF_TIMING_STATUS(NVT_TYPE_HDMI_EXT, 0)
411 #define NVT_STATUS_CUST_AUTO NVT_DEF_TIMING_STATUS(NVT_TYPE_CUST_AUTO, 0)
412 #define NVT_STATUS_CUST_MANUAL NVT_DEF_TIMING_STATUS(NVT_TYPE_CUST_MANUAL, 0)
413
414 //
415 // adding the timing sequence (from the EDID) to the modeset status
416 #define NVT_STATUS_DTD1 NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_DTD, 1)
417 #define NVT_STATUS_EDID_DTDn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_DTD, n)
418 #define NVT_STATUS_EDID_STDn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_STD, n)
419 #define NVT_STATUS_EDID_ESTn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_EST, n)
420 #define NVT_STATUS_EDID_CVTn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_CVT, n)
421 #define NVT_STATUS_EDID_861STn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_861ST, n)
422 #define NVT_STATUS_EDID_EXT_DTDn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_EXT_DTD, n)
423 #define NVT_STATUS_CUSTn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CUST, n)
424 #define NVT_TYPE_NV_PREDEFINEDn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_NV_PREDEFINED, n)
425 #define NVT_STATUS_EDID_VTB_EXTn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_VTB_EXT, n)
426 #define NVT_STATUS_EDID_VTB_EXT_DTDn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_VTB_EXT_DTD, n)
427 #define NVT_STATUS_EDID_VTB_EXT_STDn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_VTB_EXT_STD, n)
428 #define NVT_STATUS_EDID_VTB_EXT_CVTn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_EDID_VTB_EXT_CVT, n)
429 #define NVT_STATUS_HDMI_STEREO_REQn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_HDMI_STEREO_REQ, n)
430 #define NVT_STATUS_DISPLAYID_1N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_1, n)
431 #define NVT_STATUS_DISPLAYID_2N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_2, n)
432 #define NVT_STATUS_DISPLAYID_7N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_7, n)
433 #define NVT_STATUS_DISPLAYID_8N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_8, n)
434 #define NVT_STATUS_DISPLAYID_9N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_9, n)
435 #define NVT_STATUS_DISPLAYID_10N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_DISPLAYID_10, n)
436 #define NVT_STATUS_HDMI_EXTn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_HDMI_EXT, n)
437 #define NVT_STATUS_CTA861_DID_T7N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T7, n)
438 #define NVT_STATUS_CTA861_DID_T8N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T8, n)
439 #define NVT_STATUS_CTA861_DID_T10N(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_DID_T10, n)
440 #define NVT_STATUS_CTA861_OVT_Tn(n) NVT_DEF_TIMING_STATUS(NVT_TYPE_CTA861_OVT, n)
441
442 //********************************
443 // CEA/EIA 861 related EDID info
444 //********************************
445 #define NVT_CEA861_REV_NONE 0
446 #define NVT_CEA861_REV_ORIGINAL 1
447 #define NVT_CEA861_REV_A 2
448 #define NVT_CEA861_REV_B 3
449 #define NVT_CEA861_REV_C 3
450 #define NVT_CEA861_REV_D 3
451 #define NVT_CEA861_REV_E 3
452 #define NVT_CEA861_REV_F 3
453 #define NVT_CTA861_REV_G 3
454 #define NVT_CTA861_REV_H 3
455 //
456 // max data after misc/basic_caps in EIA861EXTENSION
457 #define NVT_CEA861_MAX_PAYLOAD 123
458 //
459 // the basic info encoded in byte[3]
460 #define NVT_CEA861_CAP_UNDERSCAN 0x80 // DTV monitor supports underscan
461 #define NVT_CEA861_CAP_BASIC_AUDIO 0x40 // DTV monitor supports basic audio
462 #define NVT_CEA861_CAP_YCbCr_444 0x20 // DTV monitor supports YCbCr4:4:4
463 #define NVT_CEA861_CAP_YCbCr_422 0x10 // DTV monitor supports YCbCr4:2:2
464 //
465 #define NVT_CEA861_TOTAL_LT_MASK 0x0F //the max number of 18-byte detailed timing descriptor
466 //
467 //
468 #define NVT_CEA861_SHORT_DESCRIPTOR_SIZE_MASK 0x1F
469 #define NVT_CEA861_SHORT_DESCRIPTOR_TAG_MASK 0xE0
470 #define NVT_CEA861_SHORT_DESCRIPTOR_TAG_SHIFT 5
471 //
472 // the CTA Tag Codes
473 #define NVT_CEA861_TAG_RSVD 0 // reserved block
474 #define NVT_CEA861_TAG_NONE 0 // reserved block
475 #define NVT_CEA861_TAG_AUDIO 1 // Audio Data Block
476 #define NVT_CEA861_TAG_VIDEO 2 // Video Data Block
477 #define NVT_CEA861_TAG_VENDOR 3 // Vendor Specific Data Block
478 #define NVT_CEA861_TAG_SPEAKER_ALLOC 4 // Speaker Allocation Data Block
479 #define NVT_CEA861_TAG_VESA_DTC 5 // VESA DTC data block
480 #define NVT_CTA861_TAG_VIDEO_FORMAT 6 // Video Format Data Block in CTA861.6
481 #define NVT_CEA861_TAG_EXTENDED_FLAG 7 // use Extended Tag
482 //
483 // the extended tag codes when NVT_CEA861_TAG_EXTENDED_FLAG
484 #define NVT_CEA861_EXT_TAG_VIDEO_CAP 0 // Video Capability Data Block
485 #define NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_VIDEO 1 // Vendor-Specific Video Data Block
486 #define NVT_CEA861_EXT_TAG_VESA_VIDEO_DISPLAY_DEVICE 2 // VESA Video Display Device Information Data Block
487 #define NVT_CEA861_EXT_TAG_VESA_VIDEO 3 // Reserved for VESA Video Data BLock
488 #define NVT_CEA861_EXT_TAG_HDMI_VIDEO 4 // Reserved for HDMI Video Data Block
489 #define NVT_CEA861_EXT_TAG_COLORIMETRY 5 // Colorimetry Data Block
490 #define NVT_CEA861_EXT_TAG_HDR_STATIC_METADATA 6 // HDR Static Metadata Data Block CEA861.3 HDR extension for HDMI 2.0a
491 #define NVT_CTA861_EXT_TAG_HDR_DYNAMIC_METADATA 7 // CTA861-H HDR Dynamic Metadata Data Block
492 #define NVT_CTA861_EXT_TAG_NATIVE_VIDEO_RESOLUTION 8 // CTA861.6 Native Video Resolution Data Block
493 #define NVT_CTA861_EXT_TAG_VIDEO_RSVD_MIN 9 // 9...12 : Reserved for video-related blocks
494 #define NVT_CTA861_EXT_TAG_VIDEO_RSVD_MAX 12
495 #define NVT_CEA861_EXT_TAG_VIDEO_FORMAT_PREFERENCE 13 // CEA861F Video Format Preference Data Block
496 #define NVT_CEA861_EXT_TAG_YCBCR420_VIDEO 14 // CEA861F YCBCR 4:2:0 Video Data Block
497 #define NVT_CEA861_EXT_TAG_YCBCR420_CAP 15 // CEA861F YCBCR 4:2:0 Capability Map Data Block
498 #define NVT_CEA861_EXT_TAG_MISC_AUDIO 16 // CEA Miscellaneous Audio Fields
499 #define NVT_CEA861_EXT_TAG_VENDOR_SPECIFIC_AUDIO 17 // Vendor-Specific Audio Data Block
500 #define NVT_CTA861_EXT_TAG_HDMI_AUDIO 18 // Reserved for HDMI Audio Data Block
501 #define NVT_CTA861_EXT_TAG_ROOM_CONFIGURATION 19 // CTA861-H Room Configuration Data Block
502 #define NVT_CTA861_EXT_TAG_SPEACKER_LOCATION 20 // CTA861-H Speaker Location Data Block
503 #define NVT_CTA861_EXT_TAG_AUDIO_RSVD_MIN 21 // 21...31 : Reserved for audio-related blocks
504 #define NVT_CTA861_EXT_TAG_AUDIO_RSVD_MAX 31
505 #define NVT_CEA861_EXT_TAG_INFOFRAME 32 // Infoframe Data Block
506 #define NVT_CTA861_EXT_TAG_RSVD 33 // Reserved
507 #define NVT_CTA861_EXT_TAG_DID_TYPE_VII 34 // DisplayID Type VII Video Timing Data Block
508 #define NVT_CTA861_EXT_TAG_DID_TYPE_VIII 35 // DisplayID Type VIII Video Timing Data Block
509 #define NVT_CTA861_EXT_TAG_RSVD_MIN_1 36 // 36...41 : Reserved for general
510 #define NVT_CTA861_EXT_TAG_RSVD_MAX_1 41
511 #define NVT_CTA861_EXT_TAG_DID_TYPE_X 42 // DisplayID Type X Video Timing Data Block
512 #define NVT_CTA861_EXT_TAG_RSVD_MIN_2 43 // 43...119 : Reserved for general
513 #define NVT_CTA861_EXT_TAG_RSVD_MAX_2 119
514 #define NVT_CTA861_EXT_TAG_HF_EEODB 120 // HDMI Forum Edid Extension Override Data Block
515 #define NVT_CTA861_EXT_TAG_SCDB 121 // 0x79 == Tag for Sink Capability Data Block
516 #define NVT_CTA861_EXT_TAG_HDMI_RSVD_MIN 122 // 122...127 : Reserved for HDMI
517 #define NVT_CTA861_EXT_TAG_HDMI_RSVD_MAX 127
518 #define NVT_CTA861_EXT_TAG_RSVD_MIN_3 128 // 128...255 : Reserved for general
519 #define NVT_CTA861_EXT_TAG_RSVD_MAX_3 255
520 //
521 //the extended tag payload size; the size includes the extended tag code
522 #define NVT_CEA861_EXT_VIDEO_CAP_SD_SIZE 2
523 #define NVT_CEA861_EXT_COLORIMETRY_SD_SIZE 3
524 #define NVT_CTA861_EXT_HDR_STATIC_METADATA_SIZE 6
525 #define NVT_CTA861_EXT_SCDB_PAYLOAD_MAX_LENGTH NVT_CEA861_VSDB_PAYLOAD_MAX_LENGTH
526 //
527 //
528 #define NVT_CEA861_GET_SHORT_DESCRIPTOR_TAG(a) (((a)&NVT_CEA861_SHORT_DESCRIPTOR_TAG_MASK)>>NVT_CEA861_SHORT_DESCRIPTOR_TAG_SHIFT)
529 #define NVT_CEA861_GET_SHORT_DESCRIPTOR_SIZE(a) ((NvU32)((a)&NVT_CEA861_SHORT_DESCRIPTOR_SIZE_MASK))
530
531
532 //********************************
533 // VTB Extension related info
534 //********************************
535
536 #define NVT_VTB_REV_NONE 0
537 #define NVT_VTB_REV_A 1
538
539 #define NVT_VTB_MAX_PAYLOAD 122
540
541 //*************************
542 // short descriptor
543 //*************************
544 #define NVT_CEA861_SD_HEADER_SIZE 1
545 #define NVT_CEA861_SD_PAYLOAD_SIZE 31
546 #define NVT_CEA861_SD_TOTAL_SIZE (NVT_CEA861_SD_HEADER_SIZE + NVT_CEA861_SD_PAYLOAD_SIZE)
547
548 //*************************
549 // short video descriptor
550 //*************************
551 #define NVT_CEA861_VIDEO_SD_SIZE 1
552 // the max total short video descriptors possible; See CEA-861-E, section 7.5,
553 // "It is also possible to have more than one of a specific type of data block if necessary
554 // to include all of the descriptors needed to describe the sinks capabilities."
555 #define NVT_CEA861_VIDEO_MAX_DESCRIPTOR ((NVT_CEA861_MAX_PAYLOAD / NVT_CEA861_SD_TOTAL_SIZE) * (NVT_CEA861_SD_PAYLOAD_SIZE / NVT_CEA861_VIDEO_SD_SIZE) + \
556 (NVT_CEA861_MAX_PAYLOAD % NVT_CEA861_SD_TOTAL_SIZE - NVT_CEA861_SD_HEADER_SIZE) / NVT_CEA861_VIDEO_SD_SIZE)
557 #define NVT_CTA861_VIDEO_VIC_MASK 0xFF //the VIC mask of the short video descriptor
558 #define NVT_CTA861_7BIT_VIDEO_VIC_MASK 0x7F //the 7 bits VIC mask of the short video descriptor
559 #define NVT_CTA861_VIDEO_NATIVE_MASK 0x80 //the Native mask of the short video descriptor
560 #define NVT_HDMI_YUV_420_PCLK_SUPPORTED_MIN 59000 //the vale shall equal or larger than 590MHz to support YCbCr in HDMI2.1
561
562 // CTA-861G supports more SVDs which is over 0x7F index
563 // All value below 192 will be treated as 7 bit VIC. Value 128~192 shall be forbidden.
564 #define NVT_GET_CTA_8BIT_VIC(vic) (((vic) <= NVT_CTA861_7BIT_8BIT_SEPARATE_VALUE) ? ((vic) & NVT_CTA861_7BIT_VIDEO_VIC_MASK) : ((vic) & NVT_CTA861_VIDEO_VIC_MASK))
565 //
566
567 // According to CEA-861-E Spec.
568 // Note 3. A video timing with a vertical frequency that is an integer multiple
569 // of 6.00 Hz (i.e. 24.00, 30.00, 60.00, 120.00 or 240.00 Hz) is considered to
570 // be the same as a video timing with the equivalent detailed timing
571 // information but where the vertical frequency is adjusted by a factor of
572 // 1000/1001 (i.e., 24/1.001, 30/1.001, 60/1.001, 120/1.001 or 240/1.001).
573 // Excluding ceaIndex 1 640x480 which is a PC Mode.
574 #define NVT_CTA861_TIMING_FRR(_VID_, _RR_) ((_VID_) > 1 && ((_RR_) % 6) == 0)
575 #define NVT_CEA861_640X480P_59940HZ_4X3 1 // Video Identification Code: format 1
576 #define NVT_CEA861_720X480P_59940HZ_4X3 2 // Video Identification Code: format 2
577 #define NVT_CEA861_720X480P_59940HZ_16X9 3 // Video Identification Code: format 3
578 #define NVT_CEA861_1280X720P_59940HZ_16X9 4 // ...
579 #define NVT_CEA861_1920X1080I_59940HZ_16X9 5 // ...
580 #define NVT_CEA861_1440X480I_59940HZ_4X3 6 // ...
581 #define NVT_CEA861_1440X480I_59940HZ_16X9 7 // ...
582 #define NVT_CEA861_1440X240P_59940HZ_4X3 8 // ...
583 #define NVT_CEA861_1440X240P_59940HZ_16X9 9 // ...
584 #define NVT_CEA861_2880X480I_59940HZ_4X3 10 // ...
585 #define NVT_CEA861_2880X480I_59940HZ_16X9 11 // ...
586 #define NVT_CEA861_2880X240P_59940HZ_4X3 12 // ...
587 #define NVT_CEA861_2880X240P_59940HZ_16X9 13 // ...
588 #define NVT_CEA861_1440X480P_59940HZ_4X3 14 // ...
589 #define NVT_CEA861_1440X480P_59940HZ_16X9 15 // ...
590 #define NVT_CEA861_1920X1080P_59940HZ_16X9 16 // ...
591 #define NVT_CEA861_720X576P_50000HZ_4X3 17 // ...
592 #define NVT_CEA861_720X576P_50000HZ_16X9 18 // ...
593 #define NVT_CEA861_1280X720P_50000HZ_16X9 19 // ...
594 #define NVT_CEA861_1920X1080I_50000HZ_16X9 20 // ...
595 #define NVT_CEA861_1440X576I_50000HZ_4X3 21 // ...
596 #define NVT_CEA861_1440X576I_50000HZ_16X9 22 // ...
597 #define NVT_CEA861_1440X288P_50000HZ_4X3 23 // ...
598 #define NVT_CEA861_1440X288P_50000HZ_16X9 24 // ...
599 #define NVT_CEA861_2880X576I_50000HZ_4X3 25 // ...
600 #define NVT_CEA861_2880X576I_50000HZ_16X9 26 // ...
601 #define NVT_CEA861_2880X288P_50000HZ_4X3 27 // ...
602 #define NVT_CEA861_2880X288P_50000HZ_16X9 28 // ...
603 #define NVT_CEA861_1440X576P_50000HZ_4X3 29 // ...
604 #define NVT_CEA861_1440X576P_50000HZ_16X9 30 // ...
605 #define NVT_CEA861_1920X1080P_50000HZ_16X9 31 // ...
606 #define NVT_CEA861_1920X1080P_23976HZ_16X9 32 // ...
607 #define NVT_CEA861_1920X1080P_25000HZ_16X9 33 // ...
608 #define NVT_CEA861_1920X1080P_29970HZ_16X9 34 // ...
609 #define NVT_CEA861_2880X480P_59940HZ_4X3 35 // ...
610 #define NVT_CEA861_2880X480P_59940HZ_16X9 36 // ...
611 #define NVT_CEA861_2880X576P_50000HZ_4X3 37 // ...
612 #define NVT_CEA861_2880X576P_50000HZ_16X9 38 // ...
613 #define NVT_CEA861_1920X1250I_50000HZ_16X9 39 // ...
614 #define NVT_CEA861_1920X1080I_100000HZ_16X9 40 // ...
615 #define NVT_CEA861_1280X720P_100000HZ_16X9 41 // ...
616 #define NVT_CEA861_720X576P_100000HZ_4X3 42 // ...
617 #define NVT_CEA861_720X576P_100000HZ_16X9 43 // ...
618 #define NVT_CEA861_1440X576I_100000HZ_4X3 44 // ...
619 #define NVT_CEA861_1440X576I_100000HZ_16X9 45 // ...
620 #define NVT_CEA861_1920X1080I_119880HZ_16X9 46 // ...
621 #define NVT_CEA861_1280X720P_119880HZ_16X9 47 // ...
622 #define NVT_CEA861_720X480P_119880HZ_4X3 48 // ...
623 #define NVT_CEA861_720X480P_119880HZ_16X9 49 // ...
624 #define NVT_CEA861_1440X480I_119880HZ_4X3 50 // ...
625 #define NVT_CEA861_1440X480I_119880HZ_16X9 51 // ...
626 #define NVT_CEA861_720X576P_200000HZ_4X3 52 // ...
627 #define NVT_CEA861_720X576P_200000HZ_16X9 53 // ...
628 #define NVT_CEA861_1440X576I_200000HZ_4X3 54 // ...
629 #define NVT_CEA861_1440X576I_200000HZ_16X9 55 // ...
630 #define NVT_CEA861_720X480P_239760HZ_4X3 56 // ...
631 #define NVT_CEA861_720X480P_239760HZ_16X9 57 // ...
632 #define NVT_CEA861_1440X480I_239760HZ_4X3 58 // Video Identification Code: format 58
633 #define NVT_CEA861_1440X480I_239760HZ_16X9 59 // Video Identification Code: format 59
634 #define NVT_CEA861_1280X720P_23976HZ_16X9 60 // ...
635 #define NVT_CEA861_1280X720P_25000HZ_16X9 61 // ...
636 #define NVT_CEA861_1280X720P_29970HZ_16X9 62 // ...
637 #define NVT_CEA861_1920X1080P_119880HZ_16X9 63 // ...
638 #define NVT_CEA861_1920X1080P_100000HZ_16X9 64 // ...
639
640 // Following modes are from CEA-861F
641 #define NVT_CEA861_1280X720P_23980HZ_64X27 65 // Video Identification Code: format 65
642 #define NVT_CEA861_1280X720P_25000HZ_64X27 66 // Video Identification Code: format 66
643 #define NVT_CEA861_1280X720P_29970HZ_64X27 67 // Video Identification Code: format 67
644 #define NVT_CEA861_1280X720P_50000HZ_64X27 68
645 #define NVT_CEA861_1280X720P_59940HZ_64X27 69
646 #define NVT_CEA861_1280X720P_100000HZ_64X27 70
647 #define NVT_CEA861_1280X720P_119880HZ_64X27 71
648 #define NVT_CEA861_1920X1080P_23980HZ_64X27 72
649 #define NVT_CEA861_1920X1080P_25000HZ_64X27 73
650 #define NVT_CEA861_1920X1080P_29970HZ_64X27 74
651 #define NVT_CEA861_1920X1080P_50000HZ_64X27 75
652 #define NVT_CEA861_1920X1080P_59940HZ_64X27 76
653 #define NVT_CEA861_1920X1080P_100000HZ_64X27 77
654 #define NVT_CEA861_1920X1080P_119880HZ_64X27 78
655 #define NVT_CEA861_1680X720P_23980HZ_64X27 79
656 #define NVT_CEA861_1680X720P_25000HZ_64X27 80
657 #define NVT_CEA861_1680X720P_29970HZ_64X27 81
658 #define NVT_CEA861_1680X720P_50000HZ_64X27 82
659 #define NVT_CEA861_1680X720P_59940HZ_64X27 83
660 #define NVT_CEA861_1680X720P_100000HZ_64X27 84
661 #define NVT_CEA861_1680X720P_119880HZ_64X27 85
662 #define NVT_CEA861_2560X1080P_23980HZ_64X27 86
663 #define NVT_CEA861_2560X1080P_25000HZ_64X27 87
664 #define NVT_CEA861_2560X1080P_29970HZ_64X27 88
665 #define NVT_CEA861_2560X1080P_50000HZ_64X27 89
666 #define NVT_CEA861_2560X1080P_59940HZ_64X27 90
667 #define NVT_CEA861_2560X1080P_100000HZ_64X27 91
668 #define NVT_CEA861_2560X1080P_119880HZ_64X27 92
669 #define NVT_CEA861_3840X2160P_23980HZ_16X9 93
670 #define NVT_CEA861_3840X2160P_25000HZ_16X9 94
671 #define NVT_CEA861_3840X2160P_29970HZ_16X9 95
672 #define NVT_CEA861_3840X2160P_50000HZ_16X9 96
673 #define NVT_CEA861_3840X2160P_59940HZ_16X9 97
674 #define NVT_CEA861_4096X2160P_23980HZ_256X135 98
675 #define NVT_CEA861_4096X2160P_25000HZ_256X135 99
676 #define NVT_CEA861_4096X2160P_29970HZ_256X135 100
677 #define NVT_CEA861_4096X2160P_50000HZ_256X135 101
678 #define NVT_CEA861_4096X2160P_59940HZ_256X135 102
679 #define NVT_CEA861_4096X2160P_23980HZ_64X27 103
680 #define NVT_CEA861_4096X2160P_25000HZ_64X27 104
681 #define NVT_CEA861_4096X2160P_29970HZ_64X27 105
682 #define NVT_CEA861_4096X2160P_50000HZ_64X27 106
683 #define NVT_CEA861_4096X2160P_59940HZ_64X27 107
684
685 // Following modes are from CTA-861G
686 #define NVT_CTA861_1280X720P_47950HZ_16X9 108
687 #define NVT_CTA861_1280X720P_47950HZ_64x27 109
688 #define NVT_CTA861_1680X720P_47950HZ_64x27 110
689 #define NVT_CTA861_1920X1080P_47950HZ_16X9 111
690 #define NVT_CTA861_1920X1080P_47950HZ_64x27 112
691 #define NVT_CTA861_2560X1080P_47950HZ_64x27 113
692 #define NVT_CTA861_3840X2160P_47950HZ_16X9 114
693 #define NVT_CTA861_4096x2160p_47950HZ_256X135 115
694 #define NVT_CTA861_3840x2160p_47950HZ_64x276 116
695 #define NVT_CTA861_3840x2160p_100000HZ_16X9 117
696 #define NVT_CTA861_3840x2160p_119880HZ_16X9 118
697 #define NVT_CTA861_3840x2160p_100000HZ_64X276 119
698 #define NVT_CTA861_3840x2160p_119880HZ_64X276 120
699 #define NVT_CTA861_5120x2160p_23980HZ_64X276 121
700 #define NVT_CTA861_5120x2160p_25000HZ_64X276 122
701 #define NVT_CTA861_5120x2160p_29970HZ_64X276 123
702 #define NVT_CTA861_5120x2160p_47950Hz_64X276 124
703 #define NVT_CTA861_5120x2160p_50000HZ_64X276 125
704 #define NVT_CTA861_5120x2160p_59940HZ_64X276 126
705 #define NVT_CTA861_5120x2160p_100000HZ_64X276 127
706
707 #define NVT_CTA861_7BIT_8BIT_SEPARATE_VALUE 192
708
709 #define NVT_CTA861_5120x2160p_119880HZ_64X276 193
710 #define NVT_CTA861_7680x4320p_23980HZ_16X9 194
711 #define NVT_CTA861_7680x4320p_25000HZ_16X9 195
712 #define NVT_CTA861_7680x4320p_29970HZ_16X9 196
713 #define NVT_CTA861_7680x4320p_47950HZ_16X9 197
714 #define NVT_CTA861_7680x4320p_50000HZ_16X9 198
715 #define NVT_CTA861_7680x4320p_59940HZ_16X9 199
716 #define NVT_CTA861_7680x4320p_100000HZ_16X9 200
717 #define NVT_CTA861_7680x4320p_119880HZ_16X9 201
718 #define NVT_CTA861_7680x4320p_23980HZ_64X276 202
719 #define NVT_CTA861_7680x4320p_25000HZ_64X276 203
720 #define NVT_CTA861_7680x4320p_29970HZ_64X276 204
721 #define NVT_CTA861_7680x4320p_47950HZ_64X276 205
722 #define NVT_CTA861_7680x4320p_50000HZ_64X276 206
723 #define NVT_CTA861_7680x4320p_59940HZ_64X276 207
724 #define NVT_CTA861_7680x4320p_100000HZ_64X276 208
725 #define NVT_CTA861_7680x4320p_119880HZ_64X276 209
726 #define NVT_CTA861_10240x4320p_23980HZ_64X276 210
727 #define NVT_CTA861_10240x4320p_25000HZ_64X276 211
728 #define NVT_CTA861_10240x4320p_29970HZ_64X276 212
729 #define NVT_CTA861_10240x4320p_47950HZ_64X276 213
730 #define NVT_CTA861_10240x4320p_50000HZ_64X276 214
731 #define NVT_CTA861_10240x4320p_59940HZ_64X276 215
732 #define NVT_CTA861_10240x4320p_100000HZ_64X276 216
733 #define NVT_CTA861_10240x4320p_119880HZ_64X276 217
734 #define NVT_CTA861_4096x2160p_100000HZ_256X135 218
735 #define NVT_CTA861_4096x2160p_119880HZ_256X135 219
736
737 // When defining new CEA861 format:
738 // Search code base to update array of certain category of CEA formats, such as 720p, 1080i, etc...
739 // Ideally, it's better to define these groups in one module. However, they should not reside
740 // in this .h file, thus updating these groups in other file is still needed.
741 // example of the group: 720p: NVT_CEA861_1280X720P_59940HZ_16X9,
742 // NVT_CEA861_1280X720P_100000HZ_16X9,
743 // NVT_CEA861_1280X720P_119880HZ_16X9
744
745 // According to CEA-861-I Spec.
746 // Table 11 - Resoution Identification (RID)
747 #define NVT_CTA861_OVT_TIMING_FRR(_FLAG_, _RR_) (((_FLAG_) & (NVT_FLAG_CTA_OVT_TIMING)) != 0 && ((_RR_) % 6) == 0 && (_RR_) != 300)
748 #define NVT_CTA861_RID_NONE NVT_INFOFRAME_CTRL_DONTCARE
749 #define NVT_CTA861_RID_1280x720p_16x9 1
750 #define NVT_CTA861_RID_1280x720p_64x27 2
751 #define NVT_CTA861_RID_1680x720p_64x27 3
752 #define NVT_CTA861_RID_1920x1080p_16x9 4
753 #define NVT_CTA861_RID_1920x1080p_64x27 5
754 #define NVT_CTA861_RID_2560x1080p_64x27 6
755 #define NVT_CTA861_RID_3840x1080p_32x9 7
756 #define NVT_CTA861_RID_2560x1440p_16x9 8
757 #define NVT_CTA861_RID_3440x1440p_64x27 9
758 #define NVT_CTA861_RID_5120x1440p_32x9 10
759 #define NVT_CTA861_RID_3840x2160p_16x9 11
760 #define NVT_CTA861_RID_3840x2160p_64x27 12
761 #define NVT_CTA861_RID_5120x2160p_64x27 13
762 #define NVT_CTA861_RID_7680x2160p_32x9 14
763 #define NVT_CTA861_RID_5120x2880p_16x9 15
764 #define NVT_CTA861_RID_5120x2880p_64x27 16
765 #define NVT_CTA861_RID_6880x2880p_64x27 17
766 #define NVT_CTA861_RID_10240x2880p_32x9 18
767 #define NVT_CTA861_RID_7680x4320p_16x9 19
768 #define NVT_CTA861_RID_7680x4320p_64x27 20
769 #define NVT_CTA861_RID_10240x4320p_64x27 21
770 #define NVT_CTA861_RID_15360x4320p_32x9 22
771 #define NVT_CTA861_RID_11520x6480p_16x9 23
772 #define NVT_CTA861_RID_11520x6480p_64x27 24
773 #define NVT_CTA861_RID_15360x6480p_64x27 25
774 #define NVT_CTA861_RID_15360x8640p_16x9 26
775 #define NVT_CTA861_RID_15360x8640p_64x27 27
776 #define NVT_CTA861_RID_20480x8640p_64x27 28
777
778 // Table 12 - AVI InfoFrame Video Format Frame Rate
779 #define NVT_CTA861_FR_NO_DATA NVT_INFOFRAME_CTRL_DONTCARE
780 #define NVT_CTA861_FR_2398 1
781 #define NVT_CTA861_FR_2400 2
782 #define NVT_CTA861_FR_2500 3
783 #define NVT_CTA861_FR_2997 4
784 #define NVT_CTA861_FR_3000 5
785 #define NVT_CTA861_FR_4795 6
786 #define NVT_CTA861_FR_4800 7
787 #define NVT_CTA861_FR_5000 8
788 #define NVT_CTA861_FR_5994 9
789 #define NVT_CTA861_FR_6000 10
790 #define NVT_CTA861_FR_10000 11
791 #define NVT_CTA861_FR_11988 12
792 #define NVT_CTA861_FR_12000 13
793 #define NVT_CTA861_FR_14386 14
794 #define NVT_CTA861_FR_14400 15
795 #define NVT_CTA861_FR_20000 16
796 #define NVT_CTA861_FR_23976 17
797 #define NVT_CTA861_FR_24000 18
798 #define NVT_CTA861_FR_30000 19
799 #define NVT_CTA861_FR_35964 20
800 #define NVT_CTA861_FR_36000 21
801 #define NVT_CTA861_FR_40000 22
802 #define NVT_CTA861_FR_47952 23
803 #define NVT_CTA861_FR_48000 24
804
805 //*************************
806 // short audio descriptor
807 //*************************
808 #define NVT_CEA861_AUDIO_SD_SIZE sizeof(NVT_3BYTES)
809 // the max total short audio descriptors possible; See CEA-861-E, section 7.5 on repeated types
810 #define NVT_CEA861_AUDIO_MAX_DESCRIPTOR ((NVT_CEA861_MAX_PAYLOAD / NVT_CEA861_SD_TOTAL_SIZE) * (NVT_CEA861_SD_PAYLOAD_SIZE / NVT_CEA861_AUDIO_SD_SIZE) + \
811 (NVT_CEA861_MAX_PAYLOAD % NVT_CEA861_SD_TOTAL_SIZE - NVT_CEA861_SD_HEADER_SIZE) / NVT_CEA861_AUDIO_SD_SIZE)
812 //
813 // short audio descriptor - byte 1
814 #define NVT_CEA861_AUDIO_FORMAT_MASK 0x78 //the audio format mask of the CEA short
815 #define NVT_CEA861_AUDIO_FORMAT_SHIFT 3 //the audio format data shift
816 //
817 #define NVT_CEA861_AUDIO_FORMAT_RSVD 0 // short audio descriptor format - reserved
818 #define NVT_CEA861_AUDIO_FORMAT_LINEAR_PCM 1 // short audio descriptor format - Linear PCM (uncompressed)
819 #define NVT_CEA861_AUDIO_FORMAT_AC3 2 // short audio descriptor format - AC3
820 #define NVT_CEA861_AUDIO_FORMAT_MPEG1 3 // short audio descriptor format - MPEG1(layer 1&2)
821 #define NVT_CEA861_AUDIO_FORMAT_MP3 4 // short audio descriptor format - MP3(MPEG1 layer 3)
822 #define NVT_CEA861_AUDIO_FORMAT_MPEG2 5 // short audio descriptor format - MPEG2 (multichannel)
823 #define NVT_CEA861_AUDIO_FORMAT_AAC 6 // short audio descriptor format - AAC
824 #define NVT_CEA861_AUDIO_FORMAT_DTS 7 // short audio descriptor format - DTS
825 #define NVT_CEA861_AUDIO_FORMAT_ATRAC 8 // short audio descriptor format - ATRAC
826 #define NVT_CEA861_AUDIO_FORMAT_ONE_BIT 9 // short audio descriptor format - one bit audio
827 #define NVT_CEA861_AUDIO_FORMAT_DDP 10 // short audio descriptor format - dolby digital +
828 #define NVT_CEA861_AUDIO_FORMAT_DTS_HD 11 // short audio descriptor format - DTS_HD
829 #define NVT_CEA861_AUDIO_FORMAT_MAT 12 // short audio descriptor format - MAT(MLP)
830 #define NVT_CEA861_AUDIO_FORMAT_DST 13 // short audio descriptor format - DST
831 #define NVT_CEA861_AUDIO_FORMAT_WMA_PRO 14 // short audio descriptor format - WMA Pro
832 #define NVT_CEA861_AUDIO_FORMAT_RSVD15 15 // short audio descriptor format - reserved
833 //
834 #define NVT_CEA861_AUDIO_MAX_CHANNEL_MASK 7 // short audio descriptor format - Max Number of channels - 1
835 #define NVT_CEA861_AUDIO_MAX_CHANNEL_SHIFT 0 // short audio descriptor format shift
836 //
837 // short audio descriptor - byte 2
838 #define NVT_CEA861_AUDIO_SAMPLE_RATE_MASK 0x7F //the sample rate mask
839 #define NVT_CEA861_AUDIO_SAMPLE_RATE_SHIFT 0 //the sample rate shift
840 //
841 #define NVT_CEA861_AUDIO_SAMPLE_RATE_32KHZ 0x01 // short audio descriptor - sample rate : 32KHz
842 #define NVT_CEA861_AUDIO_SAMPLE_RATE_44KHZ 0x02 // short audio descriptor - sample rate : 44KHz
843 #define NVT_CEA861_AUDIO_SAMPLE_RATE_48KHZ 0x04 // short audio descriptor - sample rate : 48KHz
844 #define NVT_CEA861_AUDIO_SAMPLE_RATE_88KHZ 0x08 // short audio descriptor - sample rate : 88KHz
845 #define NVT_CEA861_AUDIO_SAMPLE_RATE_96KHZ 0x10 // short audio descriptor - sample rate : 96KHz
846 #define NVT_CEA861_AUDIO_SAMPLE_RATE_176KHZ 0x20 // short audio descriptor - sample rate : 176KHz
847 #define NVT_CEA861_AUDIO_SAMPLE_RATE_192KHZ 0x40 // short audio descriptor - sample rate : 192KHz
848 #define NVT_CEA861_AUDIO_SAMPLE_RATE_RSVD 0x80 // short audio descriptor - sample rate : reserved
849 //
850 // short audio descriptor - byte 3
851 #define NVT_CEA861_AUDIO_SAMPLE_DEPTH_MASK 0x07 // the uncompressed audio resolution mask
852 #define NVT_CEA861_AUDIO_SAMPLE_DEPTH_SHIFT 0 // the uncompressed audio resolution shift
853 //
854 #define NVT_CEA861_AUDIO_SAMPLE_SIZE_16BIT 0x01 // uncompressed (Linear PCM) audio A/D resolution - 16bit
855 #define NVT_CEA861_AUDIO_SAMPLE_SIZE_20BIT 0x02 // uncompressed (Linear PCM) audio A/D resolution - 20bit
856 #define NVT_CEA861_AUDIO_SAMPLE_SIZE_24BIT 0x04 // uncompressed (Linear PCM) audio A/D resolution - 24bit
857
858 //**************************
859 // speaker allocation data
860 //**************************
861 #define NVT_CEA861_SPEAKER_SD_SIZE sizeof(NVT_3BYTES)
862 // the max total short speaker descriptors possible; See CEA-861-E, section 7.5 on repeated types
863 #define NVT_CEA861_SPEAKER_MAX_DESCRIPTOR ((NVT_CEA861_MAX_PAYLOAD / NVT_CEA861_SD_TOTAL_SIZE) * (NVT_CEA861_SD_PAYLOAD_SIZE / NVT_CEA861_SPEAKER_SD_SIZE) + \
864 (NVT_CEA861_MAX_PAYLOAD % NVT_CEA861_SD_TOTAL_SIZE - NVT_CEA861_SD_HEADER_SIZE) / NVT_CEA861_SPEAKER_SD_SIZE)
865 #define NVT_CEA861_SPEAKER_ALLOC_MASK 0x7F // the speaker allocation mask
866 #define NVT_CEA861_SPEAKER_ALLOC_SHIFT 0 // the speaker allocation mask shift
867 //
868 #define NVT_CEA861_SPEAKER_ALLOC_FL_FR 0x01 // speaker allocation : Front Left + Front Right
869 #define NVT_CEA861_SPEAKER_ALLOC_LFE 0x02 // speaker allocation : Low Frequency Effect
870 #define NVT_CEA861_SPEAKER_ALLOC_FC 0x04 // speaker allocation : Front Center
871 #define NVT_CEA861_SPEAKER_ALLOC_RL_RR 0x08 // speaker allocation : Rear Left + Rear Right
872 #define NVT_CEA861_SPEAKER_ALLOC_RC 0x10 // speaker allocation : Rear Center
873 #define NVT_CEA861_SPEAKER_ALLOC_FLC_FRC 0x20 // speaker allocation : Front Left Center + Front Right Center
874 #define NVT_CEA861_SPEAKER_ALLOC_RLC_RRC 0x40 // speaker allocation : Rear Left Center + Rear Right Center
875
876 //***********************
877 // vendor specific data block (VSDB)
878 //***********************
879 #define NVT_CEA861_VSDB_HEADER_SIZE 4
880 #define NVT_CEA861_VSDB_PAYLOAD_MAX_LENGTH 28 // max allowed vendor specific data block payload (in byte)
881 #define NVT_CEA861_HDMI_IEEE_ID 0x0C03
882 #define NVT_CEA861_HDMI_LLC_IEEE_ID NVT_CEA861_HDMI_IEEE_ID
883 #define NVT_CEA861_NVDA_IEEE_ID 0x44B
884 #define NVT_CEA861_HDMI_FORUM_IEEE_ID 0xC45DD8
885 #define NVT_CEA861_MSFT_IEEE_ID 0xCA125C
886
887 #define NVT_CEA861_VSDB_MAX_BLOCKS 4 // NOTE: The maximum number of VSDB blocks should be:
888 // (NVT_CEA861_MAX_PAYLOAD / (NVT_CEA861_VSDB_HEADER_SIZE + 1)) (assume at least 1 byte of payload)
889 // As of Sept 2013, there are 3 different VSDBs defined in the spec. Hence allocating space for all 24
890 // is overkill. As a tradeoff, we define this limit as 4 for now. If required, this should be increased later.
891
892 typedef struct VSDB_DATA
893 {
894 NvU32 ieee_id;
895 NvU32 vendor_data_size; // size of data copied to vendor_data (excludes ieee_id from frame)
896 NvU8 vendor_data[NVT_CEA861_VSDB_PAYLOAD_MAX_LENGTH];
897 } VSDB_DATA;
898
899 //*******************************
900 // vendor specific video data block (VSVDB)
901 //*******************************
902 #define NVT_CEA861_VSVDB_MAX_BLOCKS 2 // Dolby Vision, HDR10+ VSVDBs
903 #define NVT_CEA861_DV_IEEE_ID 0x00D046
904 #define NVT_CEA861_HDR10PLUS_IEEE_ID 0x90848B
905 #define NVT_CEA861_VSVDB_PAYLOAD_MAX_LENGTH 25 // max allowed vendor specific video data block payload (in byte)
906 #define NVT_CEA861_VSVDB_VERSION_MASK 0xE0 // vsdb version mask
907 #define NVT_CEA861_VSVDB_VERSION_MASK_SHIFT 5 // vsdb version shift mask
908
909 typedef struct VSVDB_DATA
910 {
911 NvU32 ieee_id;
912 NvU32 vendor_data_size; // size of data copied to vendor_data (excludes ieee_id from frame)
913 NvU8 vendor_data[NVT_CEA861_VSVDB_PAYLOAD_MAX_LENGTH];
914 } VSVDB_DATA;
915
916 //*******************************
917 // Video Format Data Block (VFDB)
918 //*******************************
919
920 #define NVT_CTA861_VF_MAX_BLOCKS 4
921 #define NVT_CTA861_VF_MAX_DESCRIPTORS 30
922
923 #define NVT_CTA861_VF_RID_MASK 0x3F
924
925 typedef struct tagNVT_RID_CODES
926 {
927 NvU16 HVisible; // horizontal visible
928 NvU8 HSyncPol; // horizontal sync polarity: 1-negative, 0-positive
929 NvU16 VVisible; // vertical visible
930 NvU8 VSyncPol; // vertical sync polarity: 1-negative, 0-positive
931 NvU16 interlaced; // 1-interlaced, 0-progressive
932 NvU32 aspect; // the display aspect ratio Hi(aspect):horizontal-aspect, Low(aspect):vertical-aspect
933 NvU8 rid; // Resolution Identification (RID)
934 } NVT_RID_CODES;
935
936 #pragma pack(1)
937 typedef struct tagVFD_ONE_BYTE
938 {
939 NvU8 rid : 6;
940 NvU8 fr24 : 1;
941 NvU8 bfr50 : 1;
942 } VFD_ONE_BYTE;
943
944 typedef struct tagVFD_TWO_BYTE
945 {
946 VFD_ONE_BYTE in_onebyte;
947 NvU8 frRate : 6;
948 NvU8 fr144 : 1;
949 NvU8 bfr60 : 1;
950 } VFD_TWO_BYTE;
951
952 typedef struct tagVFD_THREE_BYTE
953 {
954 VFD_TWO_BYTE in_twobyte;
955 NvU8 fr48 : 1;
956 NvU8 f31_37 : 7;
957 } VFD_THREE_BYTE;
958
959 typedef struct tagVFD_FOUR_BYTE
960 {
961 VFD_THREE_BYTE in_threebyte;
962 NvU8 f40_47;
963 } VFD_FOUR_BYTE;
964
965 typedef struct tagVFDB_DATA
966 {
967 struct {
968 NvU8 vfd_len : 2;
969 NvU8 f22_25 : 4;
970 NvU8 ntsc : 1;
971 NvU8 y420 : 1;
972 } info;
973
974 NvU8 total_vfd;
975 NvU8 video_format_desc[NVT_CTA861_VF_MAX_DESCRIPTORS];
976 } VFDB_DATA;
977
978 typedef struct tagNVT_DV_STATIC_METADATA_TYPE0
979 {
980 // first byte
981 NvU8 supports_YUV422_12bit : 1;
982 NvU8 supports_2160p60hz : 1;
983 NvU8 supports_global_dimming : 1;
984 NvU8 reserved_1 : 2;
985 NvU8 VSVDB_version : 3;
986
987 // second- fourth byte
988 NvU8 cc_red_y_3_0 : 4;
989 NvU8 cc_red_x_3_0 : 4;
990 NvU8 cc_red_x_11_4 : 8;
991 NvU8 cc_red_y_11_4 : 8;
992
993 NvU8 cc_green_y_3_0 : 4;
994 NvU8 cc_green_x_3_0 : 4;
995 NvU8 cc_green_x_11_4 : 8;
996 NvU8 cc_green_y_11_4 : 8;
997
998 NvU8 cc_blue_y_3_0 : 4;
999 NvU8 cc_blue_x_3_0 : 4;
1000 NvU8 cc_blue_x_11_4 : 8;
1001 NvU8 cc_blue_y_11_4 : 8;
1002
1003 NvU8 cc_white_y_3_0 : 4;
1004 NvU8 cc_white_x_3_0 : 4;
1005 NvU8 cc_white_x_11_4 : 8;
1006 NvU8 cc_white_y_11_4 : 8;
1007
1008 NvU8 target_max_pq_3_0 : 4;
1009 NvU8 target_min_pq_3_0 : 4;
1010 NvU8 target_min_pq_11_4 : 8;
1011 NvU8 target_max_pq_11_4 : 8;
1012
1013 NvU8 dm_version_minor : 4;
1014 NvU8 dm_version_major : 4;
1015
1016 NvU8 reserved_2 : 8;
1017 NvU8 reserved_3 : 8;
1018 NvU8 reserved_4 : 8;
1019 NvU8 reserved_5 : 8;
1020 } NVT_DV_STATIC_METADATA_TYPE0;
1021
1022 typedef struct tagNVT_DV_STATIC_METADATA_TYPE1
1023 {
1024 // first byte
1025 NvU8 supports_YUV422_12bit : 1;
1026 NvU8 supports_2160p60hz : 1;
1027 NvU8 dm_version : 3;
1028 NvU8 VSVDB_version : 3;
1029
1030 // second byte
1031 NvU8 supports_global_dimming : 1;
1032 NvU8 target_max_luminance : 7;
1033
1034 // third byte
1035 NvU8 colorimetry : 1;
1036 NvU8 target_min_luminance : 7;
1037
1038 //fourth byte
1039 NvU8 reserved : 8;
1040 //fith to tenth byte
1041 NvU8 cc_red_x : 8;
1042 NvU8 cc_red_y : 8;
1043 NvU8 cc_green_x : 8;
1044 NvU8 cc_green_y : 8;
1045 NvU8 cc_blue_x : 8;
1046 NvU8 cc_blue_y : 8;
1047 } NVT_DV_STATIC_METADATA_TYPE1;
1048
1049 typedef struct tagNVT_DV_STATIC_METADATA_TYPE1_1
1050 {
1051 // first byte
1052 NvU8 supports_YUV422_12bit : 1;
1053 NvU8 supports_2160p60hz : 1;
1054 NvU8 dm_version : 3;
1055 NvU8 VSVDB_version : 3;
1056
1057 // second byte
1058 NvU8 supports_global_dimming : 1;
1059 NvU8 target_max_luminance : 7;
1060
1061 // third byte
1062 NvU8 colorimetry : 1;
1063 NvU8 target_min_luminance : 7;
1064
1065 //fourth byte
1066 NvU8 interface_supported_by_sink : 2;
1067 NvU8 unique_By : 3;
1068 NvU8 unique_Bx : 3;
1069
1070 //fifth byte
1071 NvU8 unique_Ry_bit_0 : 1;
1072 NvU8 unique_Gx : 7;
1073
1074 //sixth byte
1075 NvU8 unique_Ry_bit_1 : 1;
1076 NvU8 unique_Gy : 7;
1077
1078 //seventh byte
1079 NvU8 unique_Rx : 5;
1080 NvU8 unique_Ry_bit_2_to_4 : 3;
1081
1082 } NVT_DV_STATIC_METADATA_TYPE1_1;
1083
1084 typedef struct tagNVT_DV_STATIC_METADATA_TYPE2
1085 {
1086 // first byte
1087 NvU8 supports_YUV422_12bit : 1;
1088 NvU8 supports_backlight_control : 1;
1089 NvU8 dm_version : 3;
1090 NvU8 VSVDB_version : 3;
1091
1092 // second byte
1093 NvU8 reserved : 2;
1094 NvU8 supports_global_dimming : 1;
1095 NvU8 target_min_luminance : 5;
1096
1097 // third byte
1098 NvU8 interface_supported_by_sink : 2;
1099 NvU8 parity : 1;
1100 NvU8 target_max_luminance : 5;
1101
1102 //fourth byte
1103 NvU8 supports_10b_12b_444_bit1 : 1;
1104 NvU8 unique_Gx : 7;
1105
1106 //fifth byte
1107 NvU8 supports_10b_12b_444_bit0 : 1;
1108 NvU8 unique_Gy : 7;
1109
1110 //sixth byte
1111 NvU8 unique_Bx : 3;
1112 NvU8 unique_Rx : 5;
1113
1114 //seventh byte
1115 NvU8 unique_By : 3;
1116 NvU8 unique_Ry : 5;
1117
1118 } NVT_DV_STATIC_METADATA_TYPE2;
1119
1120 typedef struct tagNVT_HDR10PLUS_INFO
1121 {
1122 // first byte
1123 NvU8 application_version : 2;
1124 NvU8 full_frame_peak_luminance_index : 2;
1125 NvU8 peak_luminance_index : 4;
1126 } NVT_HDR10PLUS_INFO;
1127 #pragma pack()
1128
1129 //***************************
1130 // colorimetry data block
1131 //***************************
1132 //
1133 // Colorimetry capabilities - byte 3
1134 #define NVT_CEA861_COLORIMETRY_MASK 0xFF // the colorimetry cap mask
1135 #define NVT_CEA861_COLORIMETRY_SHIFT 0 // the colorimetry cap shift
1136
1137 #define NVT_CEA861_COLORIMETRY_NO_DATA 0x00
1138 #define NVT_CEA861_COLORIMETRY_xvYCC_601 0x01 // xvYCC601 capable
1139 #define NVT_CEA861_COLORIMETRY_xvYCC_709 0x02 // xvYCC709 capable
1140 #define NVT_CEA861_COLORIMETRY_sYCC_601 0x04 // sYCC601 capable
1141 #define NVT_CEA861_COLORIMETRY_AdobeYCC_601 0x08 // AdobeYCC601 capable
1142 #define NVT_CEA861_COLORIMETRY_AdobeRGB 0x10 // AdobeRGB capable
1143 #define NVT_CEA861_COLORIMETRY_BT2020cYCC 0x20 // BT2020 cYCbCr (constant luminance) capable
1144 #define NVT_CEA861_COLORIMETRY_BT2020YCC 0x40 // BT2020 Y'CbCr capable
1145 #define NVT_CEA861_COLORIMETRY_BT2020RGB 0x80 // BT2020 RGB capable
1146 // Colorimetry capabilities - byte 4
1147 #define NVT_CEA861_COLORIMETRY_defaultRGB 0x10 // based on the default chromaticity in Basic Display Parameters and Feature Block
1148 #define NVT_CEA861_COLORIMETRY_sRGB 0x20 // IEC 61966-2-1
1149 #define NVT_CEA861_COLORIMETRY_ICtCp 0x40 // ITU-R BT.2100 ICtCp
1150 #define NVT_CEA861_COLORIMETRY_ST2113RGB 0x80 // SMPTE ST 2113 R'G'B'
1151 //
1152 // gamut-related metadata capabilities - byte 4
1153 #define NVT_CEA861_GAMUT_METADATA_MASK 0x8F // the colorimetry or gamut-related metadata block mask
1154 #define NVT_CEA861_GAMUT_METADATA_SHIFT 0 // the metadata block shift
1155 //
1156 #define NVT_CEA861_GAMUT_METADATA_MD0 0x01 // MD0
1157 #define NVT_CEA861_GAMUT_METADATA_MD1 0x02 // MD1
1158 #define NVT_CEA861_GAMUT_METADATA_MD2 0x04 // MD2
1159 #define NVT_CEA861_GAMUT_METADATA_MD3 0x08 // MD2
1160
1161 //***************************
1162 // HDR static metadata data block
1163 //***************************
1164 //
1165 typedef struct tagNVT_5BYTES
1166 {
1167 NvU8 byte1;
1168 NvU8 byte2;
1169 NvU8 byte3;
1170 NvU8 byte4;
1171 NvU8 byte5;
1172 } NVT_5BYTES;
1173
1174 // Supported Electro-Optical Transfer Function - byte 3
1175 #define NVT_CEA861_EOTF_MASK 0x3F // the EOTF cap mask
1176 #define NVT_CEA861_EOTF_SHIFT 0 // the EOTF cap shift
1177 //
1178 #define NVT_CEA861_EOTF_GAMMA_SDR 0x01 // ET_0 Traditional gamma - SDR Luminance Range
1179 #define NVT_CEA861_EOTF_GAMMA_HDR 0x02 // ET_1 Traditional gamma - HDR Luminance Range
1180 #define NVT_CEA861_EOTF_SMPTE_ST2084 0x04 // ET_2 SMPTE ST2084 EOTF (a.k.a PQ - Perceptual Quantizer EOTF)
1181 #define NVT_CEA861_EOTF_FUTURE 0x08 // ET_3 Future EOTF
1182
1183 //
1184 // Supported Static Metadata Descriptor - byte 4
1185 #define NVT_CEA861_STATIC_METADATA_DESCRIPTOR_MASK 0x01 // the supported static metadata descriptor block mask
1186 #define NVT_CEA861_STATIC_METADATA_SHIFT 0 // the metadata block shift
1187 //
1188 #define NVT_CEA861_STATIC_METADATA_SM0 0x00 // Static Metadata Type 1
1189
1190 //
1191 // Desired Content Max Luminance data - byte 5
1192 #define NVT_CEA861_MAX_CLL_MASK 0xFF // the desired content max luminance level (MaxCLL) data block mask
1193 #define NVT_CEA861_MAX_CLL_SHIFT 0 // the metadata block shift
1194
1195 // Desired Content Max Frame-Average Luminance data - byte 6
1196 #define NVT_CEA861_MAX_FALL_MASK 0xFF // the desired content max frame-average luminance (MaxFALL) data block mask
1197 #define NVT_CEA861_MAX_FALL_SHIFT 0 // the metadata block shift
1198
1199 // Desired Content Min Luminance data - byte 7
1200 #define NVT_CEA861_MIN_CLL_MASK 0xFF // the desired content min luminance level (MinCLL) data block mask
1201 #define NVT_CEA861_MIN_CLL_SHIFT 0 // the metadata block shift
1202
1203 //***************************
1204 // video capability data block
1205 //***************************
1206 //
1207 #define NVT_CEA861_VIDEO_CAPABILITY_MASK 0x7F // the video capability data block mask
1208 #define NVT_CEA861_VIDEO_CAPABILITY_SHIFT 0 // the video capability data block shift
1209 //
1210 #define NVT_CEA861_VIDEO_CAPABILITY_S_CE0 0x01 // S_CE0
1211 #define NVT_CEA861_VIDEO_CAPABILITY_S_CE1 0x02 // S_CE1
1212 #define NVT_CEA861_VIDEO_CAPABILITY_S_IT0 0x04 // S_IT0
1213 #define NVT_CEA861_VIDEO_CAPABILITY_S_IT1 0x08 // S_IT1
1214 #define NVT_CEA861_VIDEO_CAPABILITY_S_PT0 0x10 // S_PT0
1215 #define NVT_CEA861_VIDEO_CAPABILITY_S_PT1 0x20 // S_PT1
1216 #define NVT_CEA861_VIDEO_CAPABILITY_S_QS 0x40 // S_QS
1217
1218 //**************************
1219 // EDID 861 Extension Info
1220 //**************************
1221 typedef struct tagNVT_3BYTES
1222 {
1223 NvU8 byte1;
1224 NvU8 byte2;
1225 NvU8 byte3;
1226 } NVT_3BYTES;
1227
1228 //***********************
1229 // VCDB specific data
1230 //***********************
1231 #define NVT_CEA861_VCDB_QS_MASK 0x40 // quantization range selectable mask
1232 #define NVT_CEA861_VCDB_QS_SHIFT 6 // quantization range selectable shift
1233
1234 #define NVT_CEA861_VCDB_S_PT_MASK 0x30 // PT over/underscan behavior mask
1235 #define NVT_CEA861_VCDB_S_PT_SHIFT 4 // PT over/underscan behavior shift
1236 #define NVT_CEA861_VCDB_S_PT_NO_DATA 0x00
1237 #define NVT_CEA861_VCDB_S_PT_ALWAYS_OVERSCAN 0x01
1238 #define NVT_CEA861_VCDB_S_PT_ALWAYS_UNDERSCAN 0x02
1239 #define NVT_CEA861_VCDB_S_PT_OVER_OR_UNDERSCAN 0x03
1240
1241 #define NVT_CEA861_VCDB_S_IT_MASK 0x0C // IT over/underscan behavior mask
1242 #define NVT_CEA861_VCDB_S_IT_SHIFT 2 // IT over/underscan behavior shift
1243 #define NVT_CEA861_VCDB_S_IT_NOT_SUPPORTED 0x00
1244 #define NVT_CEA861_VCDB_S_IT_ALWAYS_OVERSCAN 0x01
1245 #define NVT_CEA861_VCDB_S_IT_ALWAYS_UNDERSCAN 0x02
1246 #define NVT_CEA861_VCDB_S_IT_OVER_OR_UNDERSCAN 0x03
1247
1248 #define NVT_CEA861_VCDB_S_CE_MASK 0x03 // CE over/underscan behavior mask
1249 #define NVT_CEA861_VCDB_S_CE_SHIFT 0 // CE over/underscan behavior shift
1250 #define NVT_CEA861_VCDB_S_CE_NOT_SUPPORTED 0x00
1251 #define NVT_CEA861_VCDB_S_CE_ALWAYS_OVERSCAN 0x01
1252 #define NVT_CEA861_VCDB_S_CE_ALWAYS_UNDERSCAN 0x02
1253 #define NVT_CEA861_VCDB_S_CE_OVER_OR_UNDERSCAN 0x03
1254
1255 //
1256 typedef struct tagNVT_2BYTES
1257 {
1258 NvU8 byte1;
1259 NvU8 byte2;
1260 } NVT_2BYTES;
1261
1262 #pragma pack(1)
1263 #define NVT_CTA861_DID_MAX_DATA_BLOCK 4
1264 //***********************
1265 // DisplayID VII Video Timing Data Block (T7VDB)
1266 //***********************
1267 #define NVT_CTA861_DID_TYPE7_DESCRIPTORS_MIN 1
1268 #define NVT_CTA861_DID_TYPE7_DESCRIPTORS_MAX 1
1269 #define NVT_CTA861_DID_TYPE7_DESCRIPTORS_LENGTH 20
1270
1271 typedef struct tagDID_TYPE7_DATA
1272 {
1273 struct {
1274 NvU8 revision : 3;
1275 NvU8 dsc_pt : 1;
1276 NvU8 t7_m : 3;
1277 NvU8 F37 : 1;
1278 } version;
1279
1280 NvU8 total_descriptors;
1281 NvU8 payload[29]; // t7_m=0 so only 20byte used
1282 } DID_TYPE7_DATA;
1283
1284 //***********************
1285 // DisplayID VIII Video Timing Data Block (T8VDB)
1286 //***********************
1287 #define NVT_CTA861_DID_TYPE8_ONE_BYTE_DESCRIPTOR 1
1288 #define NVT_CTA861_DID_TYPE8_TWO_BYTE_DESCRIPTOR 2
1289 #define NVT_CTA861_DID_TYPE8_DESCRIPTORS_MIN 1
1290 #define NVT_CTA861_DID_TYPE8_ONE_BYTE_DESCRIPTORS_MAX 28
1291 #define NVT_CTA861_DID_TYPE8_TWO_BYTE_DESCRIPTORS_MAX 14
1292
1293 typedef struct tagDID_TYPE8_DATA
1294 {
1295 struct {
1296 NvU8 revision : 3;
1297 NvU8 tcs : 1;
1298 NvU8 F34 : 1;
1299 NvU8 t8y420 : 1;
1300 NvU8 code_type : 2;
1301 } version;
1302
1303 NvU8 total_descriptors;
1304 NvU8 payload[NVT_CTA861_DID_TYPE8_ONE_BYTE_DESCRIPTORS_MAX]; // used one_byte descriptor length
1305 } DID_TYPE8_DATA;
1306
1307 //***********************
1308 // DisplayID X Video Timing Data Block (T10VDB)
1309 //***********************
1310 #define NVT_CTA861_DID_TYPE10_DESCRIPTORS_MIN 1
1311 #define NVT_CTA861_DID_TYPE10_DESCRIPTORS_MAX 4
1312
1313 typedef struct tagDID_TYPE10_DATA
1314 {
1315 struct {
1316 NvU8 revision : 3;
1317 NvU8 F33 : 1;
1318 NvU8 t10_m : 3;
1319 NvU8 F37 : 1;
1320 } version;
1321
1322 NvU8 total_descriptors;
1323 NvU8 payload[28]; // given the 7bytes * 4 space
1324 } DID_TYPE10_DATA;
1325
1326 //***********************
1327 // Native Video Resolution Data Block (NVRDB)
1328 //***********************
1329 typedef struct tagNATIVE_VIDEO_RESOLUTION_DATA
1330 {
1331 NvU8 native_svr;
1332
1333 struct {
1334 NvU8 img_size : 1;
1335 NvU8 f41 : 1;
1336 NvU8 f42 : 1;
1337 NvU8 f43 : 1;
1338 NvU8 f44 : 1;
1339 NvU8 f45 : 1;
1340 NvU8 f46 : 1;
1341 NvU8 sz_prec : 1;
1342 } option;
1343
1344 NvU8 image_size[4];
1345 } NATIVE_VIDEO_RESOLUTION_DATA;
1346
1347 #pragma pack()
1348
1349 // See CEA-861E, Table 42, 43 Extended Tags; indicates that the corresponding CEA extended data block value is valid,
1350 // e.g. if colorimetry is set, then NVT_EDID_CEA861_INFO::colorimetry is valid
1351 typedef struct tagNVT_VALID_EXTENDED_BLOCKS
1352 {
1353 NvU32 VCDB : 1;
1354 NvU32 VSVD : 1;
1355 NvU32 colorimetry : 1;
1356 NvU32 H14B_VSDB : 1;
1357 NvU32 H20_HF_VSDB : 1;
1358 NvU32 y420cmdb : 1;
1359 NvU32 hdr_static_metadata : 1;
1360 NvU32 dv_static_metadata : 1;
1361 NvU32 hdr10Plus : 1;
1362 NvU32 SCDB : 1;
1363 NvU32 HF_EEODB : 1;
1364 NvU32 nvda_vsdb : 1;
1365 NvU32 msft_vsdb : 1;
1366 NvU32 NVRDB : 1;
1367 } NVT_VALID_EXTENDED_BLOCKS;
1368
1369 //*************************
1370 // extended data blocks
1371 //*************************
1372 #define NVT_CEA861_SD_EXT_HEADER_SIZE 1
1373
1374 #define NVT_CEA861_Y420VDB_SD_SIZE 1
1375
1376 // Max number of YUV420 VDBs for each VDB block is 30 per CTA-861-G spec sec. 7.5.10
1377 // Accomodate 2 blocks
1378 #define NVT_CEA861_Y420VDB_MAX_DESCRIPTOR 60
1379
1380 #define NVT_CEA861_Y420CMDB_SD_SIZE 1
1381
1382 // Max number of YUV420 SVDs for each VDB block is 30 per CTA-861-G spec sec. 7.5.11
1383 // Accomodate 2 blocks
1384 #define NVT_CEA861_Y420CMDB_MAX_DESCRIPTOR 60
1385 #define NVT_CEA861_VFPDB_SD_SIZE 1
1386 #define NVT_CEA861_VFPDB_MAX_DESCRIPTOR 16 // NOTE: Limiting to 16 to not allocate too much space. The maximum descriptor should be:
1387 // ((NVT_CEA861_MAX_PAYLOAD / NVT_CEA861_SD_TOTAL_SIZE) * (NVT_CEA861_SD_PAYLOAD_SIZE / NVT_CEA861_VFPDB_SD_SIZE) +
1388 // (NVT_CEA861_MAX_PAYLOAD % NVT_CEA861_SD_TOTAL_SIZE - NVT_CEA861_SD_HEADER_SIZE - NVT_CEA861_SD_EXT_HEADER_SIZE) / NVT_CEA861_VFPDB_SD_SIZE)
1389
1390 typedef enum tagNVT_CTA861_ORIGIN
1391 {
1392 FROM_CTA861_EXTENSION,
1393 FROM_DISPLAYID_13_DATA_BLOCK,
1394 FROM_DISPLAYID_20_DATA_BLOCK,
1395 } NVT_CTA861_ORIGIN;
1396
1397 //
1398 typedef struct tagEDID_CEA861_INFO
1399 {
1400 NvU8 revision;
1401 NvU8 basic_caps;
1402
1403 // short video descriptor
1404 NvU8 total_svd;
1405 NvU8 video[NVT_CEA861_VIDEO_MAX_DESCRIPTOR];
1406
1407 // short audio descriptor
1408 NvU8 total_sad;
1409 NVT_3BYTES audio[NVT_CEA861_AUDIO_MAX_DESCRIPTOR];
1410
1411 // speaker allocation data
1412 NvU8 total_ssd;
1413 NVT_3BYTES speaker[NVT_CEA861_SPEAKER_MAX_DESCRIPTOR];
1414
1415 // vendor specific data
1416 NvU8 total_vsdb;
1417 VSDB_DATA vsdb[NVT_CEA861_VSDB_MAX_BLOCKS];
1418
1419 // vendor specific video data
1420 NvU8 total_vsvdb;
1421 VSVDB_DATA vsvdb[NVT_CEA861_VSVDB_MAX_BLOCKS];
1422
1423 // video format data
1424 NvU8 total_vfdb;
1425 VFDB_DATA vfdb[NVT_CTA861_VF_MAX_BLOCKS];
1426
1427 // indicates which of the extended data blocks below contain valid data excluding extended blocks with total count
1428 NVT_VALID_EXTENDED_BLOCKS valid;
1429 // extended data blocks
1430 NVT_2BYTES colorimetry; // Colorimetry Data Block
1431 NvU8 video_capability; // Video Capability Block
1432
1433 // HDR Static Metadata Data Block. See CEA-861.3 HDR Static Metadata Extensions, Section 4.2
1434 NVT_5BYTES hdr_static_metadata;
1435
1436 // VFPDB extended block. See CEA861-H, Section 7.5.12 Video Format Preference Data Block
1437 NvU8 total_svr;
1438 NvU8 svr_vfpdb[NVT_CEA861_VFPDB_MAX_DESCRIPTOR]; // svr of preferred video formats
1439
1440 // NVRDB extended block. see CTA861.6, Section 7.5.18 Native Video Resolution Data Block
1441 NATIVE_VIDEO_RESOLUTION_DATA native_video_resolution_db;
1442
1443 // Y420VDB extended block. See CEA861-F, Section 7.5.10 YCBCR 4:2:0 Video Data Block
1444 NvU8 total_y420vdb;
1445 NvU8 svd_y420vdb[NVT_CEA861_Y420VDB_MAX_DESCRIPTOR]; // svd of video formats that only support YCbCr 4:2:0
1446
1447 // Y420CMDB extended block. See CEA861-F, Section 7.5.11 YCBCR 4:2:0 Capability Map Data Block
1448 NvU8 total_y420cmdb;
1449 NvU8 map_y420cmdb[NVT_CEA861_Y420CMDB_MAX_DESCRIPTOR]; // bit map to svd in video[] that also supports YCbCr 4:2:0
1450
1451 // NVT_EDID_CEA861_INFO::vsvdb.SCDB = 1 in case hfscdb is exposed by sink.
1452 NvU32 hfscdbSize;
1453 NvU8 hfscdb[NVT_CTA861_EXT_SCDB_PAYLOAD_MAX_LENGTH];
1454
1455 // DID Type VII Video extended block, see 7.5.17.1 in CTA861-H
1456 NvU8 total_did_type7db;
1457 DID_TYPE7_DATA did_type7_data_block[NVT_CTA861_DID_MAX_DATA_BLOCK];
1458
1459 // DID Type VIII Video extended block, see 7.5.17.2 in CTA861-H
1460 NvU8 total_did_type8db;
1461 DID_TYPE8_DATA did_type8_data_block[NVT_CTA861_DID_MAX_DATA_BLOCK];
1462
1463 // DID Type X Video extended block, see 7.5.17.3 in CTA861-H
1464 NvU8 total_did_type10db;
1465 DID_TYPE10_DATA did_type10_data_block[NVT_CTA861_DID_MAX_DATA_BLOCK];
1466
1467 NvU8 hfeeodb; // HDMI Forum Edid Extension Override Data Block.
1468 } NVT_EDID_CEA861_INFO;
1469
1470
1471 //*******************
1472 // Parsed DisplayID Information
1473 //*******************
1474 #define NVT_DISPLAYID_SECTION_MAX_SIZE 251
1475 #define NVT_DISPLAYID_SECTION_HEADER_LEN 5
1476 #define NVT_DISPLAYID_DATABLOCK_MAX_PAYLOAD_LEN 248
1477 #define NVT_DISPLAYID_DATABLOCK_HEADER_LEN 3
1478
1479 #define NVT_DISPLAYID_PRODUCT_STRING_MAX_LEN 233
1480 #define NVT_DISPLAYID_COLOR_MAX_WHITEPOINTS 5
1481 #define NVT_DISPLAYID_COLOR_MAX_PRIMARIES 3
1482 #define NVT_DISPLAYID_RANGE_LIMITS_MAX_COUNT 2
1483 #define NVT_DISPLAYID_DISPLAY_INTERFACE_FEATURES_MAX_ADDITIONAL_SUPPORTED_COLORSPACE_EOTF 7
1484
1485 typedef enum tagNVT_SINGLE_TILE_BEHAVIOR
1486 {
1487 NVT_SINGLE_TILE_BEHAVIOR_OTHER = 0,
1488 NVT_SINGLE_TILE_BEHAVIOR_SOURCE_DRIVEN,
1489 NVT_SINGLE_TILE_BEHAVIOR_SCALE,
1490 NVT_SINGLE_TILE_BEHAVIOR_CLONE
1491 } NVT_SINGLE_TILE_BEHAVIOR;
1492
1493 typedef enum tagNVT_MULTI_TILE_BEHAVIOR
1494 {
1495 NVT_MULTI_TILE_BEHAVIOR_OTHER = 0,
1496 NVT_MULTI_TILE_BEHAVIOR_SOURCE_DRIVEN
1497 } NVT_MULTI_TILE_BEHAVIOR;
1498
1499 typedef struct _tagNVT_TILEDDISPLAY_TOPOLOGY_ID
1500 {
1501 NvU32 vendor_id;
1502 NvU16 product_id;
1503 NvU32 serial_number;
1504 } NVT_TILEDDISPLAY_TOPOLOGY_ID;
1505
1506 typedef struct _tagNVT_COLOR_POINT
1507 {
1508 NvU16 x;
1509 NvU16 y;
1510 } NVT_COLOR_POINT;
1511
1512 typedef struct _tagNVT_DISPLAYID_RANGE_LIMITS
1513 {
1514 NvU32 revision;
1515 NvU32 pclk_min;
1516 NvU32 pclk_max;
1517 NvU8 hfreq_min;
1518 NvU8 hfreq_max;
1519 NvU16 hblank_min;
1520 NvU8 vfreq_min;
1521 NvU16 vfreq_max;
1522 NvU16 vblank_min;
1523 NvU8 interlaced : 1;
1524 NvU8 cvt : 1;
1525 NvU8 cvt_reduced : 1;
1526 NvU8 dfd : 1;
1527 NvU8 seamless_dynamic_video_timing_change : 1;
1528 } NVT_DISPLAYID_RANGE_LIMITS;
1529
1530 #define NVT_DID_MAX_EXT_PAYLOAD 122
1531
1532 typedef struct _tagNVT_DISPLAYID_INFO
1533 {
1534 // Top Level Header Information
1535 NvU8 version;
1536 NvU8 product_type;
1537
1538 // Product Identification (0 or 1 Blocks Allowed)
1539 NvU32 vendor_id;
1540 NvU16 product_id;
1541 NvU32 serial_number;
1542 NvU8 week;
1543 NvU8 year;
1544 NvU8 product_string[NVT_DISPLAYID_PRODUCT_STRING_MAX_LEN + 1];
1545
1546 // Display Parameters
1547 NvU16 horiz_size;
1548 NvU16 vert_size;
1549 NvU16 horiz_pixels;
1550 NvU16 vert_pixels;
1551 NvU8 support_audio : 1;
1552 NvU8 separate_audio : 1;
1553 NvU8 audio_override : 1;
1554 NvU8 power_management : 1;
1555 NvU8 fixed_timing : 1;
1556 NvU8 fixed_pixel_format : 1;
1557 NvU8 rsvd4 : 1;
1558 NvU8 deinterlace : 1;
1559 NvU16 gamma;
1560 NvU8 aspect_ratio;
1561 NvU8 depth_overall : 4;
1562 NvU8 depth_native : 4;
1563
1564 // Color Characteristics
1565 NvU8 total_white_points;
1566 NvU8 total_primaries : 3;
1567 NvU8 temporal : 1;
1568 NVT_COLOR_POINT white_points[NVT_DISPLAYID_COLOR_MAX_WHITEPOINTS];
1569 NVT_COLOR_POINT primaries[NVT_DISPLAYID_COLOR_MAX_PRIMARIES];
1570
1571 // Range Limits
1572 NvU8 rl_num;
1573 NVT_DISPLAYID_RANGE_LIMITS range_limits[NVT_DISPLAYID_RANGE_LIMITS_MAX_COUNT];
1574
1575 // Display Data
1576 NvU8 tech_type;
1577 NvU8 device_op_mode : 4;
1578 NvU8 support_backlight : 1;
1579 NvU8 support_intensity : 1;
1580 NvU8 rsvd1 : 2;
1581 NvU16 horiz_pixel_count;
1582 NvU16 vert_pixel_count;
1583 NvU8 orientation : 2;
1584 NvU8 rotation : 2;
1585 NvU8 zero_pixel : 2;
1586 NvU8 scan_direction : 2;
1587 NvU8 subpixel_info;
1588 NvU8 horiz_pitch;
1589 NvU8 vert_pitch;
1590 NvU8 rsvd2 : 4;
1591 NvU8 color_bit_depth : 4;
1592 NvU8 white_to_black : 1;
1593 NvU8 response_time : 7;
1594
1595 // Power Settings
1596 NvU8 t1_min : 4;
1597 NvU8 t1_max : 4;
1598 NvU8 t2_max;
1599 NvU8 t3_max;
1600 NvU8 t4_min;
1601 NvU8 t5_min;
1602 NvU8 t6_min;
1603
1604 union
1605 {
1606 struct
1607 {
1608 NvU8 rsvd : 3;
1609 NvU8 color_map : 1;
1610 NvU8 support_2_8v : 1;
1611 NvU8 support_12v : 1;
1612 NvU8 support_5v : 1;
1613 NvU8 support_3_3v : 1;
1614 NvU8 rsvd2 : 5;
1615 NvU8 DE_mode : 1;
1616 NvU8 polarity : 1;
1617 NvU8 data_strobe : 1;
1618 } lvds;
1619
1620 struct
1621 {
1622 NvU8 rsvd : 5;
1623 NvU8 DE_mode : 1;
1624 NvU8 polarity : 1;
1625 NvU8 data_strobe : 1;
1626 } proprietary;
1627 } u2;
1628
1629 // Stereo Interface
1630 NvU8 stereo_code;
1631 union
1632 {
1633 struct
1634 {
1635 NvU8 stereo_polarity;
1636 } field_sequential;
1637
1638 struct
1639 {
1640 NvU8 view_identity;
1641 } side_by_side;
1642
1643 struct
1644 {
1645 NvU8 interleave_pattern[8];
1646 } pixel_interleaved;
1647
1648 struct
1649 {
1650 NvU8 rsvd : 5;
1651 NvU8 mirroring : 2;
1652 NvU8 polarity : 1;
1653 } left_right_separate;
1654
1655 struct
1656 {
1657 NvU8 num_views;
1658 NvU8 code;
1659 } multiview;
1660 } u3;
1661
1662 NvU32 tiled_display_revision;
1663 struct
1664 {
1665 NvBool bSingleEnclosure;
1666 NvBool bHasBezelInfo;
1667 NVT_SINGLE_TILE_BEHAVIOR single_tile_behavior;
1668 NVT_MULTI_TILE_BEHAVIOR multi_tile_behavior;
1669 } tile_capability;
1670
1671 struct
1672 {
1673 NvU32 row;
1674 NvU32 col;
1675 } tile_topology;
1676
1677 struct
1678 {
1679 NvU32 x;
1680 NvU32 y;
1681 } tile_location;
1682
1683 struct
1684 {
1685 NvU32 width;
1686 NvU32 height;
1687 } native_resolution;
1688
1689 struct
1690 {
1691 NvU32 pixel_density;
1692 NvU32 top;
1693 NvU32 bottom;
1694 NvU32 right;
1695 NvU32 left;
1696 } bezel_info;
1697
1698 NVT_TILEDDISPLAY_TOPOLOGY_ID tile_topology_id;
1699 NvU8 cea_data_block_present;
1700
1701 NvU8 supported_displayId2_0;
1702 union
1703 {
1704 // Display Interface
1705 struct
1706 {
1707 NvU8 interface_type : 4;
1708 union
1709 {
1710 NvU8 analog_subtype : 4;
1711 NvU8 digital_num_links : 4;
1712 } u1;
1713
1714 NvU8 interface_version;
1715
1716 struct
1717 {
1718 NvU8 rsvd : 2;
1719 NvU8 support_16b : 1;
1720 NvU8 support_14b : 1;
1721 NvU8 support_12b : 1;
1722 NvU8 support_10b : 1;
1723 NvU8 support_8b : 1;
1724 NvU8 support_6b : 1;
1725 } rgb_depth;
1726
1727 struct
1728 {
1729 NvU8 rsvd : 2;
1730 NvU8 support_16b : 1;
1731 NvU8 support_14b : 1;
1732 NvU8 support_12b : 1;
1733 NvU8 support_10b : 1;
1734 NvU8 support_8b : 1;
1735 NvU8 support_6b : 1;
1736 } ycbcr444_depth;
1737
1738 struct
1739 {
1740 NvU8 rsvd : 3;
1741 NvU8 support_16b : 1;
1742 NvU8 support_14b : 1;
1743 NvU8 support_12b : 1;
1744 NvU8 support_10b : 1;
1745 NvU8 support_8b : 1;
1746 } ycbcr422_depth;
1747
1748 NvU8 content_protection;
1749 NvU8 content_protection_version;
1750 NvU8 spread_spectrum : 2;
1751 NvU8 rsvd3 : 2;
1752 NvU8 spread_percent : 4;
1753
1754 } display_interface;
1755
1756 //display interface features for DID2.0
1757 struct
1758 {
1759 struct
1760 {
1761 NvU8 rsvd : 2;
1762 NvU8 support_16b : 1;
1763 NvU8 support_14b : 1;
1764 NvU8 support_12b : 1;
1765 NvU8 support_10b : 1;
1766 NvU8 support_8b : 1;
1767 NvU8 support_6b : 1;
1768 } rgb_depth;
1769
1770 struct
1771 {
1772 NvU8 rsvd : 2;
1773 NvU8 support_16b : 1;
1774 NvU8 support_14b : 1;
1775 NvU8 support_12b : 1;
1776 NvU8 support_10b : 1;
1777 NvU8 support_8b : 1;
1778 NvU8 support_6b : 1;
1779 } ycbcr444_depth;
1780
1781 struct
1782 {
1783 NvU8 rsvd : 3;
1784 NvU8 support_16b : 1;
1785 NvU8 support_14b : 1;
1786 NvU8 support_12b : 1;
1787 NvU8 support_10b : 1;
1788 NvU8 support_8b : 1;
1789 } ycbcr422_depth;
1790
1791 struct
1792 {
1793 NvU8 rsvd : 3;
1794 NvU8 support_16b : 1;
1795 NvU8 support_14b : 1;
1796 NvU8 support_12b : 1;
1797 NvU8 support_10b : 1;
1798 NvU8 support_8b : 1;
1799 } ycbcr420_depth;
1800
1801 // based on the DID2.0 spec. minimum pixel rate at which the Sink device shall support YCbCr 4:2:0 encoding
1802 NvU8 minimum_pixel_rate_ycbcr420;
1803
1804 struct
1805 {
1806 NvU8 support_32khz : 1;
1807 NvU8 support_44_1khz : 1;
1808 NvU8 support_48khz : 1;
1809 NvU8 rsvd : 5;
1810 } audio_capability;
1811
1812 struct
1813 {
1814 NvU8 rsvd : 1;
1815 NvU8 support_colorspace_bt2020_eotf_smpte_st2084: 1;
1816 NvU8 support_colorspace_bt2020_eotf_bt2020 : 1;
1817 NvU8 support_colorspace_dci_p3_eotf_dci_p3 : 1;
1818 NvU8 support_colorspace_adobe_rgb_eotf_adobe_rgb: 1;
1819 NvU8 support_colorspace_bt709_eotf_bt1886 : 1;
1820 NvU8 support_colorspace_bt601_eotf_bt601 : 1;
1821 NvU8 support_colorspace_srgb_eotf_srgb : 1;
1822 } colorspace_eotf_combination_1;
1823
1824 struct
1825 {
1826 NvU8 rsvd : 8;
1827 } colorspace_eotf_combination_2;
1828
1829 struct
1830 {
1831 NvU8 rsvd : 5;
1832 NvU8 total : 3;
1833 } total_additional_colorspace_eotf;
1834
1835 struct
1836 {
1837 NvU8 support_colorspace : 4;
1838 NvU8 support_eotf : 4;
1839 } additional_colorspace_eotf[NVT_DISPLAYID_DISPLAY_INTERFACE_FEATURES_MAX_ADDITIONAL_SUPPORTED_COLORSPACE_EOTF];
1840 } display_interface_features;
1841 } u4;
1842
1843 } NVT_DISPLAYID_INFO;
1844
1845 //***********************************
1846 // EDID 18-byte display descriptors
1847 //***********************************
1848 //
1849 //
1850 //*** (Tag = 0xFF) ***/
1851 // Display Product Serial Number
1852 #define NVT_EDID_LDD_PAYLOAD_SIZE 13
1853 typedef struct tagNVT_EDID_DD_SERIAL_NUMBER
1854 {
1855 NvU8 str[NVT_EDID_LDD_PAYLOAD_SIZE];
1856 NvU8 padding[16 - NVT_EDID_LDD_PAYLOAD_SIZE];
1857 } NVT_EDID_DD_SERIAL_NUMBER;
1858 //
1859 //
1860 //
1861 //*** (Tag = 0xFE) ***/
1862 // Alphanumeric Data String (ASCII)
1863 typedef struct tagNVT_EDID_DD_DATA_STRING
1864 {
1865 NvU8 str[NVT_EDID_LDD_PAYLOAD_SIZE];
1866 NvU8 padding[16 - NVT_EDID_LDD_PAYLOAD_SIZE];
1867 } NVT_EDID_DD_DATA_STRING;
1868 //
1869 //
1870 //
1871 //*** (Tag = 0xFD) ***/
1872 // Display Range Limit
1873 //
1874 typedef struct tagNVT_EDID_DD_RANGE_GTF2
1875 {
1876 NvU8 C;
1877 NvU8 K;
1878 NvU8 J;
1879 NvU16 M;
1880 } NVT_EDID_DD_RANGE_GTF2;
1881
1882 typedef struct tagNVT_EDID_DD_RANGE_CVT
1883 {
1884 NvU16 max_active_pixels_per_line;
1885
1886 NvU8 pixel_clock_adjustment : 2; // this is in 0.25Hz, subtract from max_pixel_clock
1887 // the whole number part (if existing) gets subtracted
1888 // from max_pclk_MHz right away
1889 NvU8 aspect_supported : 5;
1890
1891 NvU8 aspect_preferred : 3;
1892 NvU8 blanking_support : 2;
1893 NvU8 reserved1 : 3;
1894
1895 NvU8 scaling_support : 4;
1896 NvU8 reserved2 : 4;
1897
1898 NvU8 preferred_refresh_rate;
1899 } NVT_EDID_DD_RANGE_CVT;
1900
1901 typedef struct tagNVT_EDID_DD_RANGE_LIMIT
1902 {
1903 NvU16 min_v_rate;
1904 NvU16 max_v_rate;
1905 NvU16 min_h_rate;
1906 NvU16 max_h_rate;
1907 NvU16 max_pclk_MHz;
1908 NvU8 timing_support; // indicates 2nd GTF / CVT support
1909 union
1910 {
1911 // if timing_support = 0x02
1912 NVT_EDID_DD_RANGE_GTF2 gtf2;
1913
1914 // if timing_support = 0x04
1915 NVT_EDID_DD_RANGE_CVT cvt;
1916 }u;
1917 } NVT_EDID_DD_RANGE_LIMIT;
1918
1919 typedef struct tagNVT_EDID_RANGE_LIMIT
1920 {
1921 NvU32 min_v_rate_hzx1k;
1922 NvU32 max_v_rate_hzx1k;
1923 NvU32 min_h_rate_hz;
1924 NvU32 max_h_rate_hz;
1925 NvU32 max_pclk_10khz;
1926 } NVT_EDID_RANGE_LIMIT;
1927
1928 // timing support
1929 #define NVT_EDID_RANGE_SUPPORT_GTF2 0x02
1930 #define NVT_EDID_RANGE_SUPPORT_CVT 0x04
1931
1932 // supported aspect ratios
1933 #define NVT_EDID_CVT_ASPECT_SUPPORT_MAX 5
1934
1935 #define NVT_EDID_CVT_ASPECT_SUPPORT_4X3 0x10
1936 #define NVT_EDID_CVT_ASPECT_SUPPORT_16X9 0x08
1937 #define NVT_EDID_CVT_ASPECT_SUPPORT_16X10 0x04
1938 #define NVT_EDID_CVT_ASPECT_SUPPORT_5X4 0x02
1939 #define NVT_EDID_CVT_ASPECT_SUPPORT_15X9 0x01
1940
1941 // preferred aspect ratios
1942 #define NVT_EDID_CVT_ASPECT_PREFER_4X3 0x00
1943 #define NVT_EDID_CVT_ASPECT_PREFER_16X9 0x01
1944 #define NVT_EDID_CVT_ASPECT_PREFER_16X10 0x02
1945 #define NVT_EDID_CVT_ASPECT_PREFER_5X4 0x03
1946 #define NVT_EDID_CVT_ASPECT_PREFER_15X9 0x04
1947
1948 // cvt blanking support
1949 #define NVT_EDID_CVT_BLANKING_STANDARD 0x01
1950 #define NVT_EDID_CVT_BLANKING_REDUCED 0x02
1951
1952 // scaling support
1953 #define NVT_EDID_CVT_SCALING_HOR_SHRINK 0x08
1954 #define NVT_EDID_CVT_SCALING_HOR_STRETCH 0x04
1955 #define NVT_EDID_CVT_SCALING_VER_SHRINK 0x02
1956 #define NVT_EDID_CVT_SCALING_VER_STRETCH 0x01
1957
1958 //
1959 //
1960 //
1961 //*** (Tag = 0xFC) ***/
1962 // Display Product Name
1963 typedef struct tagNVT_EDID_DD_PRODUCT_NAME
1964 {
1965 NvU8 str[NVT_EDID_LDD_PAYLOAD_SIZE];
1966 NvU8 padding[16 - NVT_EDID_LDD_PAYLOAD_SIZE];
1967 } NVT_EDID_DD_PRODUCT_NAME;
1968 //
1969 //
1970 //
1971 //*** (Tag = 0xFB) ***/
1972 // the 18-byte display descriptors
1973 // Display Color Point Data
1974 typedef struct tagNVT_EDID_DD_COLOR_POINT
1975 {
1976 NvU8 wp1_index;
1977 NvU16 wp1_x;
1978 NvU16 wp1_y;
1979 NvU16 wp1_gamma;
1980 NvU8 wp2_index;
1981 NvU16 wp2_x;
1982 NvU16 wp2_y;
1983 NvU16 wp2_gamma;
1984 } NVT_EDID_DD_COLOR_POINT;
1985 //
1986 //
1987 //
1988 //*** (Tag = 0xFA) ***/
1989 // Standard Timing Identifications
1990 #define NVT_EDID_DD_STI_NUM 6
1991
1992 typedef struct tagNVT_EDID_DD_STD_TIMING
1993 {
1994 NvU16 descriptor[NVT_EDID_DD_STI_NUM];
1995 } NVT_EDID_DD_STD_TIMING;
1996 //
1997 //
1998 //
1999 //*** (Tag = 0xF9) ***/
2000 // Display Color Management Data (DCM)
2001 typedef struct tagNVT_EDID_DD_COLOR_MANAGEMENT_DATA
2002 {
2003 NvU16 red_a3;
2004 NvU16 red_a2;
2005 NvU16 green_a3;
2006 NvU16 green_a2;
2007 NvU16 blue_a3;
2008 NvU16 blue_a2;
2009 } NVT_EDID_DD_COLOR_MANAGEMENT_DATA;
2010 //
2011 //
2012 //
2013 //*** (Tag = 0xF8) ***/
2014 // CVT 3 Byte Timing Code
2015 #define NVT_EDID_DD_MAX_CVT3_PER_DESCRITPOR 4
2016
2017 typedef struct tagEDID_DD_CVT_3BYTE_BLOCK
2018 {
2019 NvU16 addressable_lines : 14;
2020 NvU8 aspect_ratio : 2;
2021 NvU8 reserved0 : 1;
2022 NvU8 preferred_vert_rates : 2;
2023 NvU8 supported_vert_rates : 5;
2024
2025 } NVT_EDID_DD_CVT_3BYTE_BLOCK;
2026
2027 typedef struct tagNVT_EDID_DD_CVT_3BYTE
2028 {
2029 NVT_EDID_DD_CVT_3BYTE_BLOCK block[NVT_EDID_DD_MAX_CVT3_PER_DESCRITPOR];
2030 } NVT_EDID_DD_CVT_3BYTE;
2031
2032 #define NVT_EDID_CVT3_ASPECT_4X3 0x00
2033 #define NVT_EDID_CVT3_ASPECT_16X9 0x01
2034 #define NVT_EDID_CVT3_ASPECT_16X10 0x02
2035 #define NVT_EDID_CVT3_ASPECT_15X9 0x03
2036
2037 #define NVT_EDID_CVT3_PREFFERED_RATE_50HZ 0x00
2038 #define NVT_EDID_CVT3_PREFFERED_RATE_60HZ 0x01
2039 #define NVT_EDID_CVT3_PREFFERED_RATE_75HZ 0x02
2040 #define NVT_EDID_CVT3_PREFFERED_RATE_85HZ 0x03
2041
2042 #define NVT_EDID_CVT3_SUPPORTED_RATE_50HZ 0x10
2043 #define NVT_EDID_CVT3_SUPPORTED_RATE_60HZ 0x08
2044 #define NVT_EDID_CVT3_SUPPORTED_RATE_75HZ 0x04
2045 #define NVT_EDID_CVT3_SUPPORTED_RATE_85HZ 0x02
2046 #define NVT_EDID_CVT3_SUPPORTED_RATE_60HZ_REDUCED_BLANKING 0x01
2047 //
2048 //
2049 //
2050 //*** (Tag = 0xF7) ***/
2051 // Established Timings III
2052 //
2053 #define NVT_EDID_DD_EST_TIMING3_NUM 6
2054
2055 typedef struct tagNVT_EDID_DD_EST_TIMING3
2056 {
2057 NvU8 revision;
2058 NvU8 data[NVT_EDID_DD_EST_TIMING3_NUM];
2059 } NVT_EDID_DD_EST_TIMING3;
2060 //
2061 //
2062 //
2063 //*** (Tag = 0x10) ***/
2064 // Dummy Descriptor Definition
2065 typedef struct tagNVT_EDID_DD_DUMMY_DESCRIPTOR
2066 {
2067 NvU8 data[13];
2068 } NVT_EDID_DD_DUMMY_DESCRIPTOR;
2069 //
2070 //
2071 //
2072 //*** (Tag = 0x00 to 0x0F) ***/
2073 // Manufacturer Special Data
2074 typedef struct tagNVT_EDID_DD_MANUF_DATA
2075 {
2076 NvU8 data[13];
2077 } NVT_EDID_DD_MANUF_DATA;
2078 //
2079 //
2080 //
2081 // the translated generic 18-byte long descriptor
2082 typedef struct tagNVT_EDID_18BYTE_DESCRIPTOR
2083 {
2084 NvU8 tag;
2085 union
2086 {
2087 NVT_EDID_DD_SERIAL_NUMBER serial_number;
2088 NVT_EDID_DD_DATA_STRING data_str;
2089 NVT_EDID_DD_RANGE_LIMIT range_limit;
2090 NVT_EDID_DD_PRODUCT_NAME product_name;
2091 NVT_EDID_DD_COLOR_POINT color_point;
2092 NVT_EDID_DD_STD_TIMING std_timing;
2093 NVT_EDID_DD_COLOR_MANAGEMENT_DATA color_man;
2094 NVT_EDID_DD_CVT_3BYTE cvt;
2095 NVT_EDID_DD_EST_TIMING3 est3;
2096 NVT_EDID_DD_DUMMY_DESCRIPTOR dummy;
2097 NVT_EDID_DD_MANUF_DATA manuf_data;
2098 } u;
2099 } NVT_EDID_18BYTE_DESCRIPTOR;
2100 //
2101 //
2102 // Display Descriptor Tags
2103 #define NVT_EDID_DISPLAY_DESCRIPTOR_DPSN 0xFF // display product serial number
2104 #define NVT_EDID_DISPLAY_DESCRIPTOR_ADS 0xFE // alphanumeric data string (ASCII)
2105 #define NVT_EDID_DISPLAY_DESCRIPTOR_DRL 0xFD // display range limit
2106 #define NVT_EDID_DISPLAY_DESCRITPOR_DPN 0xFC // display product name
2107 #define NVT_EDID_DISPLAY_DESCRIPTOR_CPD 0xFB // color point data
2108 #define NVT_EDID_DISPLAY_DESCRIPTOR_STI 0xFA // standard timing identification
2109 #define NVT_EDID_DISPLAY_DESCRIPTOR_DCM 0xF9 // display color management
2110 #define NVT_EDID_DISPLAY_DESCRIPTOR_CVT 0xF8 // CVT 3-byte timing code
2111 #define NVT_EDID_DISPLAY_DESCRIPTOR_ESTIII 0xF7 // establishied timing III
2112 #define NVT_EDID_DISPLAY_DESCRIPTOR_DUMMY 0x10 // dummy descriptor
2113
2114 //*******************
2115 // Raw EDID offsets and info
2116 //*******************
2117 //
2118 // Byte 14, video input definition
2119 //
2120 #define NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_MASK 0x0F // dvi/hdmi/dp
2121 #define NVT_EDID_VIDEO_COLOR_BIT_DEPTH_MASK 0x70 // bpc support
2122 #define NVT_EDID_VIDEO_INPUT_DEFINITION_DIGITAL_MASK 0x80 // digital/analog
2123 //
2124 #define NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_SHIFT 0
2125 #define NVT_EDID_VIDEO_COLOR_BIT_DEPTH_SHIFT 4
2126 #define NVT_EDID_VIDEO_INPUT_DEFINITION_DIGITAL_SHIFT 7
2127 //
2128 #define NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_UNDEFINED 0
2129 #define NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_DVI_SUPPORTED 1
2130 #define NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_A_SUPPORTED 2
2131 #define NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_HDMI_B_SUPPORTED 3
2132 #define NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_MDDI_SUPPORTED 4
2133 #define NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_DISPLAYPORT_SUPPORTED 5
2134 //#define NVT_EDID_DIGITAL_VIDEO_INTERFACE_STANDARD_RESERVED 6 - 15
2135 #define NVT_EDID_VIDEO_COLOR_BIT_DEPTH_UNDEFINED 0
2136 #define NVT_EDID_VIDEO_COLOR_BIT_DEPTH_6BPC 1
2137 #define NVT_EDID_VIDEO_COLOR_BIT_DEPTH_8BPC 2
2138 #define NVT_EDID_VIDEO_COLOR_BIT_DEPTH_10BPC 3
2139 #define NVT_EDID_VIDEO_COLOR_BIT_DEPTH_12BPC 4
2140 #define NVT_EDID_VIDEO_COLOR_BIT_DEPTH_14BPC 5
2141 #define NVT_EDID_VIDEO_COLOR_BIT_DEPTH_16BPC 6
2142 //#define NVT_EDID_VIDEO_COLOR_BIT_DEPTH_RESERVED 7
2143 #define NVT_EDID_VIDEO_INPUT_DEFINITION_DIGITAL 0x01
2144 //
2145 // Byte 18, feature support
2146 //
2147 #define NVT_EDID_OTHER_FEATURES_MASK 0x07 // sRGB space, preferred timing, continuous freq.
2148 #define NVT_EDID_DISPLAY_COLOR_TYPE_MASK 0x18 // for analog, see byte 14, bit 7
2149 #define NVT_EDID_DISPLAY_COLOR_ENCODING_MASK 0x18 // for digital
2150 #define NVT_EDID_DISPLAY_POWER_MANAGEMENT_MASK 0xE0 // standby/suspend/active off
2151 //
2152 #define NVT_EDID_OTHER_FEATURES_SHIFT 0
2153 #define NVT_EDID_DISPLAY_COLOR_TYPE_SHIFT 3
2154 #define NVT_EDID_DISPLAY_COLOR_ENCODING_SHIFT 3
2155 #define NVT_EDID_DISPLAY_POWER_MANAGEMENT_SHIFT 5
2156 //
2157 #define NVT_EDID_OTHER_FEATURES_USES_CONTINUOUS_FREQ (1 << 0)
2158 #define NVT_EDID_OTHER_FEATURES_PTM_INCLUDE_NATIVE (1 << 1)
2159 #define NVT_EDID_OTHER_FEATURES_SRGB_DEFAULT_COLORSPACE (1 << 2)
2160 //
2161 #define NVT_EDID_DISPLAY_COLOR_TYPE_MONOCHROME 0
2162 #define NVT_EDID_DISPLAY_COLOR_TYPE_RGB 1
2163 #define NVT_EDID_DISPLAY_COLOR_TYPE_NON_RGB 2
2164 #define NVT_EDID_DISPLAY_COLOR_TYPE_UNDEFINED 3
2165 //
2166 #define NVT_EDID_DISPLAY_COLOR_ENCODING_YCBCR_444 (1 << 0) // RGB is always supported
2167 #define NVT_EDID_DISPLAY_COLOR_ENCODING_YCBCR_422 (1 << 1) // RGB is always supported
2168 //
2169 #define NVT_EDID_DISPLAY_POWER_MANAGEMENT_SUPPORTS_ACTIVE_OFF (1 << 0)
2170 #define NVT_EDID_DISPLAY_POWER_MANAGEMENT_SUPPORTS_SUSPENDED_MODE (1 << 1)
2171 #define NVT_EDID_DISPLAY_POWER_MANAGEMENT_SUPPORTS_STANDBY_MODE (1 << 2)
2172 //
2173 // edid offsets
2174 //
2175 #define NVT_EDID_VIDEO_INPUT_DEFINITION 0x14
2176 #define NVT_EDID_FEATURE_SUPPORT 0x18
2177
2178
2179 //*******************
2180 // Parsed EDID info
2181 //*******************
2182 //
2183 #define NVT_EDID_MAX_LONG_DISPLAY_DESCRIPTOR 4
2184 #define NVT_EDID_MAX_STANDARD_TIMINGS 8
2185 #define NVT_EDID_MAX_TOTAL_TIMING NVT_MAX_TOTAL_TIMING
2186 #define NVT_EDID_VER_1_1 0x101
2187 #define NVT_EDID_VER_1_2 0x102
2188 #define NVT_EDID_VER_1_3 0x103
2189 #define NVT_EDID_VER_1_4 0x104
2190 //
2191 // byte 0x14, Digital
2192 // bits 0-3
2193 #define NVT_EDID_VIDEOSIGNAL_INTERFACE_NOT_DEFINED 0x0
2194 #define NVT_EDID_VIDEOSIGNAL_INTERFACE_DVI 0x1
2195 #define NVT_EDID_VIDEOSIGNAL_INTERFACE_HDMI_A 0x2
2196 #define NVT_EDID_VIDEOSIGNAL_INTERFACE_HDMI_B 0x3
2197 #define NVT_EDID_VIDEOSIGNAL_INTERFACE_MDDI 0x4
2198 #define NVT_EDID_VIDEOSIGNAL_INTERFACE_DP 0x5
2199 // bits 4-6; these are translated values. See NvTiming_ParseEDIDInfo()
2200 #define NVT_EDID_VIDEOSIGNAL_BPC_NOT_DEFINED 0
2201 #define NVT_EDID_VIDEOSIGNAL_BPC_6 6
2202 #define NVT_EDID_VIDEOSIGNAL_BPC_8 8
2203 #define NVT_EDID_VIDEOSIGNAL_BPC_10 10
2204 #define NVT_EDID_VIDEOSIGNAL_BPC_12 12
2205 #define NVT_EDID_VIDEOSIGNAL_BPC_14 14
2206 #define NVT_EDID_VIDEOSIGNAL_BPC_16 16
2207 //
2208 // byte 0x18, edid 1.3
2209 // bits 3-4
2210 #define NVT_EDID_FEATURESUPPORT_COLOR_MONOCHROME 0x0 /* Monochrome/grayscale display */
2211 #define NVT_EDID_FEATURESUPPORT_COLOR_RGB 0x1 /* R/G/B color display */
2212 #define NVT_EDID_FEATURESUPPORT_COLOR_MULTICOLOR 0x2 /* non R/G/B multicolor displays e.g. R/G/Y */
2213 #define NVT_EDID_FEATURESUPPORT_COLOR_UNDEFINED 0x3 /* Undefined */
2214 //
2215 // byte 0x18, edid 1.4
2216 // bits 3-4
2217 #define NVT_EDID_FEATURESUPPORT_COLOR_ENCODING_RBG 0x0 /* RGB always supported */
2218 #define NVT_EDID_FEATURESUPPORT_COLOR_ENCODING_YCRCB444 0x1 /* RGB + 444 */
2219 #define NVT_EDID_FEATURESUPPORT_COLOR_ENCODING_YCRCB422 0x2 /* RGB + 422 */
2220 #define NVT_EDID_FEATURESUPPORT_COLOR_ENCODING_YCRCB 0x3 /* RGB + 444 + 422 supported */
2221 //
2222 //
2223 // structure used internally to map support for HDMI 3D modes.
2224 #define MAX_EDID_ADDRESSABLE_3D_VICS 16
2225 #define MAX_3D_VICS_RESERVED_FOR_MANDATORY 8
2226 #define MAX_3D_VICS_SUPPORTED (MAX_EDID_ADDRESSABLE_3D_VICS + MAX_3D_VICS_RESERVED_FOR_MANDATORY)
2227
2228 //Constants given by Dolby to be appended for chromaticity information
2229 #define NVT_DOLBY_CHROMATICITY_MSB_BX 0x20
2230 #define NVT_DOLBY_CHROMATICITY_MSB_BY 0x08
2231 #define NVT_DOLBY_CHROMATICITY_MSB_GX 0x00
2232 #define NVT_DOLBY_CHROMATICITY_MSB_GY 0x80
2233 #define NVT_DOLBY_CHROMATICITY_MSB_RX 0xA0
2234 #define NVT_DOLBY_CHROMATICITY_MSB_RY 0x40
2235
2236 typedef struct _HDMI3DDetails
2237 {
2238 NvU8 Vic;
2239 NvU16 StereoStructureMask;
2240 NvU8 SideBySideHalfDetail;
2241 } HDMI3DDETAILS;
2242
2243 typedef struct _SupportMap
2244 {
2245 HDMI3DDETAILS map[MAX_3D_VICS_SUPPORTED];
2246 NvU32 total;
2247 } HDMI3DSUPPORTMAP;
2248
2249 typedef struct tagNVT_EXT_TIMING
2250 {
2251 NVT_TIMING timing;
2252 NVT_HDMIEXT HDMI3D;
2253 } NVT_EXT_TIMING;
2254
2255 typedef struct _NVDA_VSDB_PARSED_INFO
2256 {
2257 NvBool valid;
2258 NvU8 vsdbVersion;
2259
2260 // these fields are specified in version 1 of the NVDA VSDB
2261 union
2262 {
2263 struct
2264 {
2265 NvBool supportsVrr;
2266 NvU8 minRefreshRate;
2267 } v1;
2268 } vrrData;
2269
2270 } NVDA_VSDB_PARSED_INFO;
2271
2272 typedef enum _MSFT_VSDB_DESKTOP_USAGE
2273 {
2274 MSFT_VSDB_NOT_USABLE_BY_DESKTOP = 0,
2275 MSFT_VSDB_USABLE_BY_DESKTOP = 1
2276 } MSFT_VSDB_DESKTOP_USAGE;
2277
2278 typedef enum _MSFT_VSDB_THIRD_PARTY_USAGE
2279 {
2280 MSFT_VSDB_NOT_USABLE_BY_THIRD_PARTY = 0,
2281 MSFT_VSDB_USABLE_BY_THIRD_PARTY = 1
2282 } MSFT_VSDB_THIRD_PARTY_USAGE;
2283
2284 typedef enum _MSFT_VSDB_PRIMARY_USE_CASE
2285 {
2286 MSFT_VSDB_FOR_UNDEFINED = 0,
2287 MSFT_VSDB_FOR_TEST_EQUIPMENT = 0x1,
2288 MSFT_VSDB_FOR_GENERIC_DISPLAY = 0x2,
2289 MSFT_VSDB_FOR_TELEVISION_DISPLAY = 0x3,
2290 MSFT_VSDB_FOR_DESKTOP_PRODUCTIVITY_DISPLAY = 0x4,
2291 MSFT_VSDB_FOR_DESKTOP_GAMING_DISPLAY = 0x5,
2292 MSFT_VSDB_FOR_PRESENTATION_DISPLAY = 0x6,
2293 MSFT_VSDB_FOR_VIRTUAL_REALITY_HEADSETS = 0x7,
2294 MSFT_VSDB_FOR_AUGMENTED_REALITY = 0x8,
2295 MSFT_VSDB_FOR_VIDEO_WALL_DISPLAY = 0x10,
2296 MSFT_VSDB_FOR_MEDICAL_IMAGING_DISPLAY = 0x11,
2297 MSFT_VSDB_FOR_DEDICATED_GAMING_DISPLAY = 0x12,
2298 MSFT_VSDB_FOR_DEDICATED_VIDEO_MONITOR_DISPLAY = 0x13,
2299 MSFT_VSDB_FOR_ACCESSORY_DISPLAY = 0X14
2300 } MSFT_VSDB_PRIMARY_USE_CASE;
2301
2302 #define MSFT_VSDB_CONTAINER_ID_SIZE (16)
2303 #define MSFT_VSDB_MAX_VERSION_SUPPORT (3)
2304
2305 typedef struct _MSFT_VSDB_PARSED_INFO
2306 {
2307 NvBool valid;
2308 NvU8 version;
2309
2310 MSFT_VSDB_DESKTOP_USAGE desktopUsage;
2311 MSFT_VSDB_THIRD_PARTY_USAGE thirdPartyUsage;
2312 MSFT_VSDB_PRIMARY_USE_CASE primaryUseCase;
2313 NvU8 containerId[MSFT_VSDB_CONTAINER_ID_SIZE];
2314
2315 } MSFT_VSDB_PARSED_INFO;
2316
2317 typedef struct tagNVT_HDMI_LLC_INFO
2318 {
2319 // A.B.C.D address
2320 NvU8 addrA;
2321 NvU8 addrB;
2322 NvU8 addrC;
2323 NvU8 addrD;
2324
2325 NvU8 supports_AI : 1;
2326 NvU8 dc_48_bit : 1;
2327 NvU8 dc_36_bit : 1;
2328 NvU8 dc_30_bit : 1;
2329 NvU8 dc_y444 : 1;
2330 NvU8 dual_dvi : 1;
2331 NvU8 max_tmds_clock;
2332 NvU8 effective_tmds_clock;
2333 NvU8 latency_field_present : 1;
2334 NvU8 i_latency_field_present : 1;
2335 NvU8 hdmi_video_present : 1;
2336 NvU8 cnc3 : 1;
2337 NvU8 cnc2 : 1;
2338 NvU8 cnc1 : 1;
2339 NvU8 cnc0 : 1;
2340 NvU8 video_latency;
2341 NvU8 audio_latency;
2342 NvU8 interlaced_video_latency;
2343 NvU8 interlaced_audio_latency;
2344 NvU8 threeD_present : 1;
2345 NvU8 threeD_multi_present : 2;
2346 NvU8 image_size : 2;
2347 NvU8 hdmi_vic_len : 3;
2348 NvU8 hdmi_3d_len : 5;
2349 // for now ignoring the other extensions
2350 // ....
2351 } NVT_HDMI_LLC_INFO;
2352
2353 typedef struct tagNVT_HDMI_FORUM_INFO
2354 {
2355 NvU8 max_TMDS_char_rate;
2356
2357 NvU8 threeD_Osd_Disparity : 1;
2358 NvU8 dual_view : 1;
2359 NvU8 independent_View : 1;
2360 NvU8 lte_340Mcsc_scramble : 1;
2361 NvU8 ccbpci : 1;
2362 NvU8 cable_status : 1;
2363 NvU8 rr_capable : 1;
2364 NvU8 scdc_present : 1;
2365
2366 NvU8 dc_30bit_420 : 1;
2367 NvU8 dc_36bit_420 : 1;
2368 NvU8 dc_48bit_420 : 1;
2369 NvU8 uhd_vic : 1;
2370 NvU8 max_FRL_Rate : 4;
2371
2372 NvU8 fapa_start_location : 1;
2373 NvU8 allm : 1;
2374 NvU8 fva : 1;
2375 NvU8 cnmvrr : 1;
2376 NvU8 cinemaVrr : 1;
2377 NvU8 m_delta : 1;
2378 NvU8 qms : 1;
2379 NvU8 fapa_end_extended : 1;
2380
2381 NvU16 vrr_min : 6;
2382 NvU16 vrr_max : 10;
2383
2384 NvU8 qms_tfr_min : 1;
2385 NvU8 qms_tfr_max : 1;
2386 NvU16 dsc_MaxSlices : 6;
2387 NvU16 dsc_MaxPclkPerSliceMHz : 10;
2388
2389 NvU8 dsc_10bpc : 1;
2390 NvU8 dsc_12bpc : 1;
2391 NvU8 dsc_16bpc : 1;
2392 NvU8 dsc_All_bpp : 1;
2393 NvU8 dsc_Max_FRL_Rate : 4;
2394
2395 NvU8 dsc_Native_420 : 1;
2396 NvU8 dsc_1p2 : 1;
2397 NvU8 rsvd_2 : 6;
2398
2399 NvU8 dsc_totalChunkKBytes : 7; // = 1 + EDID reported DSC_TotalChunkKBytes
2400 NvU8 rsvd_3 : 1;
2401
2402 } NVT_HDMI_FORUM_INFO;
2403
2404 typedef struct tagNVT_HDR_STATIC_METADATA
2405 {
2406 struct
2407 {
2408 NvU8 trad_gamma_sdr_eotf : 1;
2409 NvU8 trad_gamma_hdr_eotf : 1;
2410 NvU8 smpte_st_2084_eotf : 1;
2411 NvU8 future_eotf : 1;
2412 } supported_eotf;
2413
2414 NvU8 static_metadata_type; // set to 1 if the sink support for static meta data type 1
2415 NvU8 max_cll; // maximum luminance level value
2416 NvU8 max_fall; // maximum fram-average luminance
2417 NvU8 min_cll; // minimum luminance level value
2418
2419 }NVT_HDR_STATIC_METADATA;
2420
2421 typedef struct tagNVT_DV_STATIC_METADATA
2422 {
2423 NvU32 ieee_id : 24;
2424 NvU32 VSVDB_version : 3;
2425 NvU32 dm_version : 8;
2426 NvU32 supports_2160p60hz : 1;
2427 NvU32 supports_YUV422_12bit : 1;
2428 NvU32 supports_global_dimming : 1;
2429 NvU32 colorimetry : 1;
2430 NvU32 target_min_luminance : 12;
2431 NvU32 target_max_luminance : 12;
2432 NvU32 cc_red_x : 12;
2433 NvU32 cc_red_y : 12;
2434 NvU32 cc_green_x : 12;
2435 NvU32 cc_green_y : 12;
2436 NvU32 cc_blue_x : 12;
2437 NvU32 cc_blue_y : 12;
2438 NvU32 cc_white_x : 12;
2439 NvU32 cc_white_y : 12;
2440 NvU32 supports_backlight_control : 2;
2441 NvU32 backlt_min_luma : 2;
2442 NvU32 interface_supported_by_sink : 2;
2443 NvU32 supports_10b_12b_444 : 2;
2444 NvU32 parity : 1;
2445 }NVT_DV_STATIC_METADATA;
2446
2447 //***********************************
2448 // parsed DisplayID 2.0 definitions
2449 //***********************************
2450 #define NVT_DISPLAYID_2_0_PRODUCT_STRING_MAX_LEN 236
2451
2452 // the basic info encoded in byte[3]
2453 #define NVT_DISPLAY_2_0_CAP_BASIC_AUDIO 0x40 // DTV monitor supports basic audio
2454 #define NVT_DISPLAY_2_0_CAP_YCbCr_444 0x20 // DTV monitor supports YCbCr4:4:4
2455 #define NVT_DISPLAY_2_0_CAP_YCbCr_422 0x10 // DTV monitor supports YCbCr4:2:2
2456
2457 // vendor specific
2458 #define NVT_VESA_VENDOR_SPECIFIC_IEEE_ID 0x3A0292
2459 #define NVT_VESA_VENDOR_SPECIFIC_LENGTH 7
2460
2461 #define NVT_VESA_ORG_VSDB_DATA_TYPE_MASK 0x07
2462 #define NVT_VESA_ORG_VSDB_COLOR_SPACE_AND_EOTF_MASK 0x80
2463 #define NVT_VESA_ORG_VSDB_COLOR_SPACE_AND_EOTF_SHIFT 7
2464 #define NVT_VESA_ORG_VSDB_PIXELS_OVERLAPPING_MASK 0x0F
2465 #define NVT_VESA_ORG_VSDB_MULTI_SST_MODE_MASK 0x60
2466 #define NVT_VESA_ORG_VSDB_MULTI_SST_MODE_SHIFT 5
2467 #define NVT_VESA_ORG_VSDB_PASS_THROUGH_INTEGER_MASK 0x3F
2468 #define NVT_VESA_ORG_VSDB_PASS_THROUGH_FRACTIOINAL_MASK 0x0F
2469
2470 // adaptive-sync
2471 #define NVT_ADAPTIVE_SYNC_DESCRIPTOR_MAX_COUNT 0x04
2472
2473 typedef enum _tagNVT_DISPLAYID_PRODUCT_PRIMARY_USE_CASE
2474 {
2475 PRODUCT_PRIMARY_USE_TEST_EQUIPMENT = 1,
2476 PRODUCT_PRIMARY_USE_GENERIC_DISPLAY = 2,
2477 PRODUCT_PRIMARY_USE_TELEVISION = 3,
2478 PRODUCT_PRIMARY_USE_DESKTOP_PRODUCTIVITY = 4,
2479 PRODUCT_PRIMARY_USE_DESKTOP_GAMING = 5,
2480 PRODUCT_PRIMARY_USE_PRESENTATION = 6,
2481 PRODUCT_PRIMARY_USE_HEAD_MOUNT_VIRTUAL_REALITY = 7,
2482 PRODUCT_PRIMARY_USE_HEAD_MOUNT_AUGMENTED_REALITY = 8,
2483 } NVT_DISPLAYID_PRODUCT_PRIMARY_USE_CASE;
2484
2485 typedef enum _tagNVT_DISPLAYID_SCAN_ORIENTATION
2486 {
2487 SCAN_ORIENTATION_LRTB = 0,
2488 SCAN_ORIENTATION_RLTB = 1,
2489 SCAN_ORIENTATION_TBRL = 2,
2490 SCAN_ORIENTATION_BTRL = 3,
2491 SCAN_ORIENTATION_RLBT = 4,
2492 SCAN_ORIENTATION_LRBT = 5,
2493 SCAN_ORIENTATION_BTLR = 6,
2494 SCAN_ORIENTATION_TBLR = 7,
2495 } NVT_DISPLAYID_SCAN_ORIENTATION;
2496
2497 typedef enum _tagNVT_DISPLAYID_INTERFACE_EOTF
2498 {
2499 INTERFACE_EOTF_NOT_DEFINED = 0x0,
2500 INTERFACE_EOTF_SRGB = 0x1,
2501 INTERFACE_EOTF_BT601 = 0x2,
2502 INTERFACE_EOTF_BT1886 = 0x3,
2503 INTERFACE_EOTF_ADOBE_RGB = 0x4,
2504 INTERFACE_EOTF_DCI_P3 = 0x5,
2505 INTERFACE_EOTF_BT2020 = 0x6,
2506 INTERFACE_EOTF_NATIVE_GAMMA = 0x7,
2507 INTERFACE_EOTF_SMPTE_ST2084 = 0x8,
2508 INTERFACE_EOTF_HYBRID_LOG = 0x9,
2509 INTERFACE_EOTF_CUSTOM = 0x10,
2510 } NVT_DISPLAYID_INTERFACE_EOTF;
2511
2512 typedef enum _tagNVT_DISPLAYID_INTERFACE_COLOR_SPACE
2513 {
2514 INTERFACE_COLOR_SPACE_NOT_DEFINED = 0x0,
2515 INTERFACE_COLOR_SPACE_SRGB = 0x1,
2516 INTERFACE_COLOR_SPACE_BT601 = 0x2,
2517 INTERFACE_COLOR_SPACE_BT709 = 0x3,
2518 INTERFACE_COLOR_SPACE_ADOBE_RGB = 0x4,
2519 INTERFACE_COLOR_SPACE_DCI_P3 = 0x5,
2520 INTERFACE_COLOR_SPACE_BT2020 = 0x6,
2521 INTERFACE_COLOR_SPACE_CUSTOM = 0x7,
2522 } NVT_DISPLAYID_INTERFACE_COLOR_SPACE;
2523
2524 typedef enum _tagNVT_DISPLAYID_DEVICE_TECHNOLOGY
2525 {
2526 DEVICE_TECHNOLOGY_NOT_SPECIFIED,
2527 DEVICE_TECHNOLOGY_LCD,
2528 DEVICE_TECHNOLOGY_OLED,
2529 } NVT_DISPLAYID_DEVICE_TECHNOLOGY;
2530
2531 typedef struct _tagNVT_DISPLAYID_TILED_DISPLAY_TOPOLOGY
2532 {
2533 NvU32 revision;
2534
2535 struct
2536 {
2537 NvBool bSingleEnclosure;
2538 NvBool bHasBezelInfo;
2539 NVT_SINGLE_TILE_BEHAVIOR single_tile_behavior;
2540 NVT_MULTI_TILE_BEHAVIOR multi_tile_behavior;
2541 } capability;
2542
2543 struct
2544 {
2545 NvU32 row;
2546 NvU32 col;
2547 } topology;
2548
2549 struct
2550 {
2551 NvU32 x;
2552 NvU32 y;
2553 } location;
2554
2555 struct
2556 {
2557 NvU32 width;
2558 NvU32 height;
2559 } native_resolution;
2560
2561 struct
2562 {
2563 NvU32 top; // Top bezel in pixels
2564 NvU32 bottom; // Bottom bezel in pixels
2565 NvU32 right; // Right bezel in pixels
2566 NvU32 left; // Left bezel in pixels
2567 } bezel_info;
2568
2569 NVT_TILEDDISPLAY_TOPOLOGY_ID tile_topology_id;
2570 } NVT_DISPLAYID_TILED_DISPLAY_TOPOLOGY;
2571
2572 typedef struct _tagNVT_DISPLAYID_CONTAINERID
2573 {
2574 NvU32 revision;
2575 NvU32 data1;
2576 NvU16 data2;
2577 NvU16 data3;
2578 NvU16 data4;
2579 NvU8 data5[6];
2580 } NVT_DISPLAYID_CONTAINERID;
2581
2582 typedef struct _tagNVT_DISPLAYID_INTERFACE_FEATURES
2583 {
2584 NvU32 revision;
2585
2586 NVT_COLORDEPTH rgb444; // each bit within is set if rgb444 supported on that bpc
2587 NVT_COLORDEPTH yuv444; // each bit within is set if yuv444 supported on that bpc
2588 NVT_COLORDEPTH yuv422; // each bit within is set if yuv422 supported on that bpc
2589 NVT_COLORDEPTH yuv420; // each bit within is set if yuv420 supported on that bpc
2590
2591 NvU32 yuv420_min_pclk;
2592
2593 struct
2594 {
2595 NvU8 support_32khz : 1;
2596 NvU8 support_44_1khz : 1;
2597 NvU8 support_48khz : 1;
2598 NvU8 rsvd : 5;
2599 } audio_capability;
2600
2601 NvU32 combination_count;
2602 struct
2603 {
2604 NVT_DISPLAYID_INTERFACE_EOTF eotf;
2605 NVT_DISPLAYID_INTERFACE_COLOR_SPACE color_space;
2606 } colorspace_eotf_combination[NVT_DISPLAYID_DISPLAY_INTERFACE_FEATURES_MAX_ADDITIONAL_SUPPORTED_COLORSPACE_EOTF + 1];
2607
2608 } NVT_DISPLAYID_INTERFACE_FEATURES;
2609
2610 typedef struct _tagNVT_DISPLAYID_PRODUCT_IDENTITY
2611 {
2612 NvU32 revision;
2613 NvU32 vendor_id;
2614 NvU16 product_id;
2615 NvU32 serial_number;
2616 NvU16 week;
2617 NvU16 year;
2618 NvU8 product_string[NVT_DISPLAYID_2_0_PRODUCT_STRING_MAX_LEN + 1];
2619 } NVT_DISPLAYID_PRODUCT_IDENTITY;
2620
2621 typedef enum _tagNVT_COLOR_MAP_STANDARD
2622 {
2623 COLOR_MAP_CIE_1931,
2624 COLOR_MAP_CIE_1976,
2625 } NVT_COLOR_MAP_STANDARD;
2626
2627 typedef enum _tagNVT_AUDIO_SPEAKER_INTEGRATED
2628 {
2629 AUDIO_SPEAKER_INTEGRATED_SUPPORTED = 0,
2630 AUDIO_SPEAKER_INTEGRATED_NOT_SUPPORTED = 1,
2631 } NVT_AUDIO_SPEAKER_INTEGRATED;
2632
2633 typedef enum _tagNVT_NATIVE_LUMINANCE_INFO
2634 {
2635 NATIVE_LUMINANCE_INFO_MIN_GURANTEE_VALUE = 0,
2636 NATIVE_LUMINANCE_INFO_SOURCE_DEVICE_GUIDANCE = 1,
2637 } NVT_NATIVE_LUMINANCE_INFO;
2638
2639 typedef struct _tagNVT_DISPLAYID_DISPLAY_PARAMETERS
2640 {
2641 NvU32 revision;
2642 NvU32 h_image_size_micro_meter;
2643 NvU32 v_image_size_micro_meter;
2644 NvU16 h_pixels;
2645 NvU16 v_pixels;
2646 NVT_DISPLAYID_SCAN_ORIENTATION scan_orientation;
2647 NVT_COLOR_MAP_STANDARD color_map_standard;
2648 NVT_COLOR_POINT primaries[3];
2649 NVT_COLOR_POINT white;
2650 NVT_NATIVE_LUMINANCE_INFO native_luminance_info;
2651 NvU16 native_max_luminance_full_coverage;
2652 NvU16 native_max_luminance_10_percent_rect_coverage;
2653 NvU16 native_min_luminance;
2654 NVT_COLORDEPTH native_color_depth;
2655 NvU16 gamma_x100;
2656 NVT_DISPLAYID_DEVICE_TECHNOLOGY device_technology;
2657 NvBool device_theme_Preference;
2658 NvBool audio_speakers_integrated;
2659 } NVT_DISPLAYID_DISPLAY_PARAMETERS;
2660
2661 typedef struct _tagNVT_DISPLAYID_ADAPTIVE_SYNC
2662 {
2663 union
2664 {
2665 NvU8 operation_range_info;
2666 struct
2667 {
2668 NvU8 adaptive_sync_range : 1;
2669 NvU8 duration_inc_flicker_perf : 1;
2670 NvU8 modes : 2;
2671 NvU8 seamless_not_support : 1;
2672 NvU8 duration_dec_flicker_perf : 1;
2673 NvU8 reserved : 2;
2674 } information;
2675 } u;
2676
2677 NvU8 max_duration_inc;
2678 NvU8 min_rr;
2679 NvU16 max_rr;
2680 NvU8 max_duration_dec;
2681 } NVT_DISPLAYID_ADAPTIVE_SYNC;
2682
2683 typedef struct _tagVESA_VSDB_PARSED_INFO
2684 {
2685 struct
2686 {
2687 NvU8 type : 3;
2688 NvU8 reserved : 4;
2689 NvU8 color_space_and_eotf : 1;
2690 } data_struct_type;
2691
2692 struct
2693 {
2694 NvU8 pixels_overlapping_count : 4;
2695 NvU8 reserved_0 : 1;
2696 NvU8 multi_sst : 2;
2697 NvU8 reserved_1 : 1;
2698 } overlapping;
2699
2700 struct
2701 {
2702 NvU8 pass_through_integer_dsc : 6;
2703 NvU8 reserved : 2;
2704 } pass_through_integer;
2705
2706 struct
2707 {
2708 NvU8 pass_through_fraction_dsc : 4;
2709 NvU8 reserved : 4;
2710 } pass_through_fractional;
2711 } VESA_VSDB_PARSED_INFO;
2712
2713 typedef struct _tagNVT_DISPLAYID_VENDOR_SPECIFIC
2714 {
2715 NVT_HDMI_LLC_INFO hdmiLlc;
2716 NVT_HDMI_FORUM_INFO hfvs;
2717 NVDA_VSDB_PARSED_INFO nvVsdb;
2718 MSFT_VSDB_PARSED_INFO msftVsdb;
2719 VESA_VSDB_PARSED_INFO vesaVsdb;
2720 } NVT_DISPLAYID_VENDOR_SPECIFIC;
2721
2722 typedef struct _tagNVT_DISPLAYID_CTA
2723 {
2724 NVT_EDID_CEA861_INFO cta861_info;
2725 NVT_HDR_STATIC_METADATA hdrInfo;
2726 NVT_DV_STATIC_METADATA dvInfo;
2727 NVT_HDR10PLUS_INFO hdr10PlusInfo;
2728 } NVT_DISPLAYID_CTA;
2729
2730 typedef struct _tagNVT_DISPLAYID_BRIGHTNESS_LUMINANCE_RANGE
2731 {
2732 NvU32 revision;
2733 NvU16 min_sdr_luminance;
2734 NvU16 max_sdr_luminance;
2735 NvU16 max_boost_sdr_luminance;
2736 } NVT_DISPLAYID_BRIGHTNESS_LUMINANCE_RANGE;
2737
2738 typedef struct _tagNVT_VALID_DATA_BLOCKS
2739 {
2740 NvBool product_id_present;
2741 NvBool parameters_present;
2742 NvBool type7Timing_present;
2743 NvBool type8Timing_present;
2744 NvBool type9Timing_present;
2745 NvBool dynamic_range_limit_present;
2746 NvBool interface_feature_present;
2747 NvBool stereo_interface_present;
2748 NvBool tiled_display_present;
2749 NvBool container_id_present;
2750 NvBool type10Timing_present;
2751 NvBool adaptive_sync_present;
2752 NvBool arvr_hmd_present;
2753 NvBool arvr_layer_present;
2754 NvBool brightness_luminance_range_present;
2755 NvBool vendor_specific_present;
2756 NvBool cta_data_present;
2757 } NVT_VALID_DATA_BLOCKS;
2758
2759 #define NVT_DISPLAYID_MAX_TOTAL_TIMING NVT_MAX_TOTAL_TIMING
2760 typedef struct _tagNVT_DISPLAYID_2_0_INFO
2761 {
2762 NvU8 revision;
2763 NvU8 version;
2764
2765 // support audio/yuv444/yuv422 color for CTA861 compatible
2766 NvU8 basic_caps;
2767
2768 // the all extensions that may appear following the base section
2769 NvU32 extension_count;
2770
2771 // this displayID20 is EDID extension or not
2772 NvBool as_edid_extension;
2773
2774 // data blocks present or not
2775 NVT_VALID_DATA_BLOCKS valid_data_blocks;
2776
2777 NVT_DISPLAYID_PRODUCT_PRIMARY_USE_CASE primary_use_case;
2778
2779 // Product Identification Data Block (Mandatory)
2780 NVT_DISPLAYID_PRODUCT_IDENTITY product_identity;
2781
2782 // Display Parameter Data Block (Mandatory for Display Use)
2783 NVT_DISPLAYID_DISPLAY_PARAMETERS display_param;
2784
2785 // Detailed Timing Data Block (Mandatory for Display Use)
2786 NvU32 total_timings;
2787 NVT_TIMING timing[NVT_DISPLAYID_MAX_TOTAL_TIMING];
2788
2789 // Enumerated Timing Code Data Block (Not Mandatory)
2790
2791 // Formula-based Timing Data Block (Not Mandatory)
2792
2793 // Dynamic Video Timing Range Limits Data Block (Not Mandatory)
2794 NVT_DISPLAYID_RANGE_LIMITS range_limits;
2795
2796 // Display Interface Features Data Block (Mandatory)
2797 NVT_DISPLAYID_INTERFACE_FEATURES interface_features;
2798
2799 // Stereo Display Interface Data Block (Not Mandatory)
2800
2801 // Tiled Display Topology Data Block (Not Mandatory)
2802 NVT_DISPLAYID_TILED_DISPLAY_TOPOLOGY tile_topo;
2803
2804 // ContainerID Data Block (Mandatory for Multi-function Device)
2805 NVT_DISPLAYID_CONTAINERID container_id;
2806
2807 // Adaptive-Sync Data Block (Mandatory for display device supports Adaptive-Sync)
2808 NvU32 total_adaptive_sync_descriptor;
2809 NVT_DISPLAYID_ADAPTIVE_SYNC adaptive_sync_descriptor[NVT_ADAPTIVE_SYNC_DESCRIPTOR_MAX_COUNT];
2810
2811 // Brightness Luminance Range Data Block (Mandatory for display device supports Nits based brightness control)
2812 NVT_DISPLAYID_BRIGHTNESS_LUMINANCE_RANGE luminance_ranges;
2813
2814 // Vendor-specific Data Block (Not Mandatory)
2815 NVT_DISPLAYID_VENDOR_SPECIFIC vendor_specific;
2816
2817 // CTA DisplayID Data Block (Not Mandatory)
2818 NVT_DISPLAYID_CTA cta;
2819 } NVT_DISPLAYID_2_0_INFO;
2820
2821 #define NVT_EDID_PRIMARY_COLOR_FP2INT_FACTOR 1024 // Per EDID 1.4, 10bit color primary is encoded in floating point as (bit9/2 + bit8/4 + bi7/8 + ... + bit0)
2822 typedef struct tagNVT_EDID_INFO
2823 {
2824 // generic edid info
2825 NvU32 version;
2826 NvU16 manuf_id;
2827 NvU16 manuf_id_hi;
2828 NvU8 manuf_name[4];
2829 NvU16 product_id;
2830 NvU32 serial_number;
2831 NvU8 week;
2832 NvU16 year;
2833
2834 // the interface info
2835 struct
2836 {
2837 union
2838 {
2839 struct
2840 {
2841 NvU8 serrations : 1;
2842 NvU8 sync_type : 3;
2843 NvU8 video_setup : 1;
2844 NvU8 vp_p : 2;
2845 } analog;
2846 struct
2847 {
2848 NvU8 video_interface : 4;
2849 NvU8 bpc : 5;
2850 } digital;
2851 NvU8 analog_data : 7;
2852 } u;
2853 NvU8 isDigital : 1;
2854 } input;
2855
2856 // the screen size info
2857 NvU8 screen_size_x; // horizontal screen size in cm
2858 NvU8 screen_size_y; // verical screen size in cm
2859 NvU16 screen_aspect_x; // aspect ratio
2860 NvU16 screen_aspect_y; // aspect ratio
2861
2862 // display transfer characteristics
2863 NvU16 gamma;
2864
2865 // features support
2866 union
2867 {
2868 NvU8 feature;
2869 struct
2870 {
2871 NvU8 support_gtf : 1;
2872 NvU8 preferred_timing_is_native : 1; // should be "Preferred_timing_is_dtd1". To be exact, "Native" is referenced as the native HDTV timing by CEA861 extension block
2873 NvU8 default_colorspace_srgb : 1;
2874 NvU8 color_type : 2;
2875 NvU8 support_active_off : 1;
2876 NvU8 support_suspend : 1;
2877 NvU8 support_standby : 1;
2878
2879 } feature_ver_1_3;
2880 struct
2881 {
2882 NvU8 continuous_frequency : 1;
2883 NvU8 preferred_timing_is_native : 1; // should be "Preferred_timing_is_dtd1". To be exact, "Native" is referenced as the native HDTV timing by CEA861 extension block
2884 NvU8 default_colorspace_srgb : 1;
2885 NvU8 color_type : 2;
2886 NvU8 support_active_off : 1;
2887 NvU8 support_suspend : 1;
2888 NvU8 support_standby : 1;
2889 } feature_ver_1_4_analog;
2890 struct
2891 {
2892 NvU8 continuous_frequency : 1;
2893 NvU8 preferred_timing_is_native : 1; // should be "Preferred_timing_is_dtd1". To be exact, "Native" is referenced as the native HDTV timing by CEA861 extension block
2894 NvU8 default_colorspace_srgb : 1;
2895 NvU8 support_ycrcb_444 : 1;
2896 NvU8 support_ycrcb_422 : 1;
2897 NvU8 support_active_off : 1;
2898 NvU8 support_suspend : 1;
2899 NvU8 support_standby : 1;
2900 } feature_ver_1_4_digital;
2901 }u;
2902
2903 // chromaticity coordinates
2904 NvU16 cc_red_x;
2905 NvU16 cc_red_y;
2906 NvU16 cc_green_x;
2907 NvU16 cc_green_y;
2908 NvU16 cc_blue_x;
2909 NvU16 cc_blue_y;
2910 NvU16 cc_white_x;
2911 NvU16 cc_white_y;
2912
2913 // established timings 1 and 2
2914 NvU16 established_timings_1_2;
2915
2916 // Manufacturer reserved timings
2917 NvU16 manufReservedTimings;
2918
2919 // standard timings
2920 NvU16 standard_timings[NVT_EDID_MAX_STANDARD_TIMINGS];
2921
2922 // 18-bytes display descriptor info
2923 NVT_EDID_18BYTE_DESCRIPTOR ldd[NVT_EDID_MAX_LONG_DISPLAY_DESCRIPTOR];
2924
2925 // the parse timing
2926 NVT_TIMING timing[NVT_EDID_MAX_TOTAL_TIMING];
2927
2928 // Note: This contains the timing after validation.
2929 NvU32 total_timings;
2930
2931 // This contains the count timing that were invalidated because they don't meet
2932 // some policies (PClk, etc).
2933 NvU32 total_invalidTimings;
2934
2935 // indicates support for HDMI 1.4+ 3D stereo modes are present
2936 NvU32 HDMI3DSupported;
2937
2938 HDMI3DSUPPORTMAP Hdmi3Dsupport;
2939
2940 // Data parsed from NVDA VSDB - Variable Refresh Rate Monitor capabilities
2941 NVDA_VSDB_PARSED_INFO nvdaVsdbInfo;
2942
2943 // Data parsed from MSFT VSDB - HMD and Specialized (Direct display) Monitor capabilities
2944 MSFT_VSDB_PARSED_INFO msftVsdbInfo;
2945
2946 // HDR capability information from the HDR Metadata Data Block
2947 NVT_HDR_STATIC_METADATA hdr_static_metadata_info;
2948
2949 // DV capability information from the DV Metadata Data Block
2950 NVT_DV_STATIC_METADATA dv_static_metadata_info;
2951
2952 // HDR10+ capability information from the HDR10+ LLC VSVDB
2953 NVT_HDR10PLUS_INFO hdr10PlusInfo;
2954
2955 // HDMI LLC info
2956 NVT_HDMI_LLC_INFO hdmiLlcInfo;
2957
2958 // HDMI 2.0 information
2959 NVT_HDMI_FORUM_INFO hdmiForumInfo;
2960 // deprecating the following, please use hdmiForumInfo;
2961 struct
2962 {
2963 NvU8 max_TMDS_char_rate;
2964 NvU8 lte_340Mcsc_scramble :1;
2965 NvU8 rr_capable :1;
2966 NvU8 SCDC_present :1;
2967 } hdmi_2_0_info;
2968
2969 // the total edid extension(s) attached to the basic block
2970 NvU32 total_extensions;
2971 // the total displayid2 extension(s) attached to the basic block.
2972 NvU32 total_did2_extensions;
2973
2974 NvU8 checksum;
2975 NvU8 checksum_ok;
2976
2977 // extension info
2978 NVT_EDID_CEA861_INFO ext861;
2979
2980 // for the 2nd CEA/EIA861 extension
2981 // note: "ext861" should really be an array but since it requires massive name change and it's hard
2982 // to find more than one 861 extension in the real world, I made a trade off like this for now.
2983 NVT_EDID_CEA861_INFO ext861_2;
2984
2985 NVT_DISPLAYID_INFO ext_displayid;
2986 NVT_DISPLAYID_2_0_INFO ext_displayid20;
2987 } NVT_EDID_INFO;
2988
2989 typedef enum
2990 {
2991 NVT_PROTOCOL_UNKNOWN = 0,
2992 NVT_PROTOCOL_DP = 1,
2993 NVT_PROTOCOL_HDMI = 2,
2994 NVT_PROTOCOL_DVI = 3,
2995 } NVT_PROTOCOL;
2996
2997 // the display interface/connector claimed by the EDID
2998 #define NVT_EDID_INPUT_DIGITAL_UNDEFINED 0x00 // undefined digital interface
2999 #define NVT_EDID_INPUT_DVI 0x01
3000 #define NVT_EDID_INPUT_HDMI_TYPE_A 0x02
3001 #define NVT_EDID_INPUT_HDMI_TYPE_B 0x03
3002 #define NVT_EDID_INPUT_MDDI 0x04
3003 #define NVT_EDID_INPUT_DISPLAY_PORT 0x05
3004
3005
3006 // the EDID extension TAG
3007 #define NVT_EDID_EXTENSION_CTA 0x02 // CTA 861 series extensions
3008 #define NVT_EDID_EXTENSION_VTB 0x10 // video timing block extension
3009 #define NVT_EDID_EXTENSION_DI 0x40 // display information extension
3010 #define NVT_EDID_EXTENSION_LS 0x50 // localized string extension
3011 #define NVT_EDID_EXTENSION_DPVL 0x60 // digital packet video link extension
3012 #define NVT_EDID_EXTENSION_DISPLAYID 0x70 // display id
3013 #define NVT_EDID_EXTENSION_BM 0xF0 // extension block map
3014 #define NVT_EDID_EXTENSION_OEM 0xFF // extension defined by the display manufacturer
3015
3016 //************************************
3017 // Audio and Video Infoframe Control
3018 //************************************
3019 //
3020 // the control info for generating infoframe data
3021 #define NVT_INFOFRAME_CTRL_DONTCARE 0xFF
3022 //
3023 typedef struct tagNVT_VIDEO_INFOFRAME_CTRL
3024 {
3025 NvU8 color_space;
3026 NvU8 active_format_info_present;
3027 NvU8 bar_info;
3028 NvU8 scan_info;
3029 NvU8 colorimetry;
3030 NvU8 pic_aspect_ratio;
3031 NvU8 active_format_aspect_ratio;
3032 NvU8 it_content;
3033 NvU8 it_content_type;
3034 NvU8 extended_colorimetry;
3035 NvU8 rgb_quantization_range;
3036 NvU8 nonuniform_scaling;
3037 NvU8 video_format_id;
3038 NvU8 pixel_repeat;
3039 NvU16 top_bar;
3040 NvU16 bottom_bar;
3041 NvU16 left_bar;
3042 NvU16 right_bar;
3043 NvU8 addition_colorimetry_ext;
3044 NvU8 frame_rate;
3045 NvU8 rid;
3046 }NVT_VIDEO_INFOFRAME_CTRL;
3047
3048 //
3049 typedef struct tagNVT_AUDIO_INFOFRAME_CTRL
3050 {
3051 NvU8 coding_type;
3052 NvU8 channel_count;
3053 NvU8 sample_rate;
3054 NvU8 sample_depth;
3055 NvU8 speaker_placement;
3056 NvU8 level_shift;
3057 NvU8 down_mix_inhibit;
3058 }NVT_AUDIO_INFOFRAME_CTRL;
3059
3060 typedef struct tagNVT_VENDOR_SPECIFIC_INFOFRAME_CTRL
3061 {
3062 NvU8 Enable;
3063 NvU8 HDMIRevision;
3064 NvU8 HDMIFormat;
3065 NvU8 HDMI_VIC;
3066 NvBool ALLMEnable;
3067 NvU8 ThreeDStruc;
3068 NvU8 ThreeDDetail;
3069 NvU8 MetadataPresent;
3070 NvU8 MetadataType;
3071 NvU8 Metadata[8]; // type determines length
3072
3073 } NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL;
3074 #define NVT_3D_METADTATA_TYPE_PARALAX 0x00
3075 #define NVT_3D_METADTATA_PARALAX_LEN 0x08
3076
3077 #define NVT_EXTENDED_METADATA_PACKET_INFOFRAME_VER_HDMI21 0x0
3078 #define NVT_EXTENDED_METADATA_PACKET_INFOFRAME_VER_HDMI21A 0x1
3079 typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL
3080 {
3081 NvU32 version; // See #define NVT_EXTENDED_METADATA_PACKET_INFOFRAME_VER
3082 NvU32 EnableVRR;
3083 NvU32 ITTiming;
3084 NvU32 BaseVFP;
3085 NvU32 ReducedBlanking;
3086 NvU32 BaseRefreshRate;
3087 NvU32 EnableQMS;
3088 NvU32 NextTFR;
3089 NvU32 Sync;
3090 NvU32 MConst;
3091 } NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL;
3092
3093 typedef struct tagNVT_ADAPTIVE_SYNC_SDP_CTRL
3094 {
3095 NvU32 minVTotal;
3096 NvU32 targetRefreshRate;
3097 NvU32 srCoastingVTotal;
3098 NvBool bFixedVTotal;
3099 NvBool bRefreshRateDivider;
3100 }NVT_ADAPTIVE_SYNC_SDP_CTRL;
3101
3102 //***********************************
3103 // the actual Auido/Video Infoframe
3104 //***********************************
3105 //
3106 // info frame type code
3107 #define NVT_INFOFRAME_TYPE_VENDOR_SPECIFIC 1
3108 #define NVT_INFOFRAME_TYPE_VIDEO 2
3109 #define NVT_INFOFRAME_TYPE_SOURCE_PRODUCT_DESCRIPTION 3
3110 #define NVT_INFOFRAME_TYPE_AUDIO 4
3111 #define NVT_INFOFRAME_TYPE_MPEG_SOURCE 5
3112 #define NVT_INFOFRAME_TYPE_SELF_REFRESH 6
3113 #define NVT_INFOFRAME_TYPE_DYNAMIC_RANGE_MASTERING 7
3114 #define NVT_INFOFRAME_TYPE_EXTENDED_METADATA_PACKET 8
3115 //
3116 //
3117 typedef struct tagNVT_INFOFRAME_HEADER
3118 {
3119 NvU8 type;
3120 NvU8 version;
3121 NvU8 length;
3122 }NVT_INFOFRAME_HEADER;
3123
3124 typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME_HEADER
3125 {
3126 NvU8 type;
3127 NvU8 firstLast;
3128 NvU8 sequenceIndex;
3129 } NVT_EXTENDED_METADATA_PACKET_INFOFRAME_HEADER;
3130
3131 #define NVT_EMP_HEADER_FIRST 0x80
3132 #define NVT_EMP_HEADER_LAST 0x40
3133 #define NVT_EMP_HEADER_FIRST_LAST 0xC0
3134
3135 // SPD Infoframe
3136 typedef struct tagNVT_SPD_INFOFRAME_PAYLOAD
3137 {
3138 NvU8 vendorBytes[8];
3139 NvU8 productBytes[16];
3140
3141 NvU8 sourceInformation;
3142
3143 } NVT_SPD_INFOFRAME_PAYLOAD;
3144
3145 typedef struct tagNVT_SPD_INFOFRAME
3146 {
3147 NVT_INFOFRAME_HEADER Header;
3148 NVT_SPD_INFOFRAME_PAYLOAD Data;
3149 } NVT_SPD_INFOFRAME;
3150
3151 // the video infoframe version 1-3 structure
3152 typedef struct tagNVT_VIDEO_INFOFRAME
3153 {
3154 NvU8 type;
3155 NvU8 version;
3156 NvU8 length;
3157
3158 // byte 1~5
3159 NvU8 byte1;
3160 NvU8 byte2;
3161 NvU8 byte3;
3162 NvU8 byte4;
3163 NvU8 byte5;
3164
3165 // byte 6~13
3166 NvU8 top_bar_low;
3167 NvU8 top_bar_high;
3168 NvU8 bottom_bar_low;
3169 NvU8 bottom_bar_high;
3170 NvU8 left_bar_low;
3171 NvU8 left_bar_high;
3172 NvU8 right_bar_low;
3173 NvU8 right_bar_high;
3174
3175 // byte 14~15
3176 NvU8 byte14;
3177 NvU8 byte15;
3178 }NVT_VIDEO_INFOFRAME;
3179 //
3180 #define NVT_VIDEO_INFOFRAME_VERSION_1 1
3181 #define NVT_VIDEO_INFOFRAME_VERSION_2 2
3182 #define NVT_VIDEO_INFOFRAME_VERSION_3 3
3183 #define NVT_VIDEO_INFOFRAME_VERSION_4 4
3184 //
3185 #define NVT_VIDEO_INFOFRAME_BYTE1_S1S0_MASK 0x03
3186 #define NVT_VIDEO_INFOFRAME_BYTE1_S1S0_SHIFT 0
3187 #define NVT_VIDEO_INFOFRAME_BYTE1_S1S0_NO_DATA 0
3188 #define NVT_VIDEO_INFOFRAME_BYTE1_S1S0_OVERSCANNED 1
3189 #define NVT_VIDEO_INFOFRAME_BYTE1_S1S0_UNDERSCANNED 2
3190 #define NVT_VIDEO_INFOFRAME_BYTE1_S1S0_FUTURE 3
3191 //
3192 #define NVT_VIDEO_INFOFRAME_BYTE1_B1B0_MASK 0x0C
3193 #define NVT_VIDEO_INFOFRAME_BYTE1_B1B0_SHIFT 2
3194 #define NVT_VIDEO_INFOFRAME_BYTE1_B1B0_NOT_VALID 0
3195 #define NVT_VIDEO_INFOFRAME_BYTE1_B1B0_VERT_VALID 1
3196 #define NVT_VIDEO_INFOFRAME_BYTE1_B1B0_HORIZ_VALID 2
3197 #define NVT_VIDEO_INFOFRAME_BYTE1_B1B0_H_V_VALID 3
3198 //
3199 #define NVT_VIDEO_INFOFRAME_BYTE1_A0_MASK 0x10 // active format info present
3200 #define NVT_VIDEO_INFOFRAME_BYTE1_A0_SHIFT 4 // active format info present
3201 #define NVT_VIDEO_INFOFRAME_BYTE1_A0_NO_DATA 0
3202 #define NVT_VIDEO_INFOFRAME_BYTE1_A0_VALID 1
3203 //
3204 // CTA-861G new requirement - DD changed this policy
3205 #define NVT_VIDEO_INFOFRAME_BYTE1_Y2_MASK 8
3206 #define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_MASK 0xE0
3207 #define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_SHIFT 0x5
3208 #define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_RGB 0
3209 #define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr422 1
3210 #define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr444 2
3211 #define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_YCbCr420 3
3212 #define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_FUTURE 3 // nvlEscape still uses this line 4266
3213 #define NVT_VIDEO_INFOFRAME_BYTE1_Y2Y1Y0_IDODEFINED 7
3214 // CEA-861-F - Unix still used this one
3215 #define NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_MASK 0x60
3216 #define NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_SHIFT 0x5
3217 #define NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_RGB 0
3218 #define NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_YCbCr422 1
3219 #define NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_YCbCr444 2
3220 #define NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_YCbCr420 3
3221 #define NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_FUTURE 3 // nvlEscape still uses this lline 4266
3222 //
3223 #define NVT_VIDEO_INFOFRAME_BYTE1_RESERVED_MASK 0x80 // for Inforframe V1 / V2
3224 #define NVT_VIDEO_INFOFRAME_BYTE1_RESERVED_SHIFT 7
3225 //
3226 #define NVT_VIDEO_INFOFRAME_BYTE2_R3R2R1R0_MASK 0x0F // active format aspect ratio
3227 #define NVT_VIDEO_INFOFRAME_BYTE2_R3R2R1R0_SHIFT 0
3228 #define NVT_VIDEO_INFOFRAME_BYTE2_R3R2R1R0_SAME_AS_M1M0 8
3229 #define NVT_VIDEO_INFOFRAME_BYTE2_R3R2R1R0_4X3_CENTER 9
3230 #define NVT_VIDEO_INFOFRAME_BYTE2_R3R2R1R0_16X9_CENTER 10
3231 #define NVT_VIDEO_INFOFRAME_BYTE2_R3R2R1R0_14x9_CENTER 11
3232 //
3233 #define NVT_VIDEO_INFOFRAME_BYTE2_M1M0_MASK 0x30 // picture aspect ratio
3234 #define NVT_VIDEO_INFOFRAME_BYTE2_M1M0_SHIFT 4 // picture aspect ratio
3235 #define NVT_VIDEO_INFOFRAME_BYTE2_M1M0_NO_DATA 0
3236 #define NVT_VIDEO_INFOFRAME_BYTE2_M1M0_4X3 1
3237 #define NVT_VIDEO_INFOFRAME_BYTE2_M1M0_16X9 2
3238 #define NVT_VIDEO_INFOFRAME_BYTE2_M1M0_FUTURE 3
3239 //
3240 #define NVT_VIDEO_INFOFRAME_BYTE2_C1C0_MASK 0xC0 // colorimetry
3241 #define NVT_VIDEO_INFOFRAME_BYTE2_C1C0_SHIFT 6
3242 #define NVT_VIDEO_INFOFRAME_BYTE2_C1C0_NO_DATA 0
3243 #define NVT_VIDEO_INFOFRAME_BYTE2_C1C0_SMPTE170M_ITU601 1
3244 #define NVT_VIDEO_INFOFRAME_BYTE2_C1C0_ITU709 2
3245 #define NVT_VIDEO_INFOFRAME_BYTE2_C1C0_EXT_COLORIMETRY 3
3246 //
3247 #define NVT_VIDEO_INFOFRAME_BYTE3_SC_MASK 0x03 // non-uniform scaling
3248 #define NVT_VIDEO_INFOFRAME_BYTE3_SC_SHIFT 0
3249 #define NVT_VIDEO_INFOFRAME_BYTE3_SC_NONE 0
3250 #define NVT_VIDEO_INFOFRAME_BYTE3_SC_HORIZ_SCALED 1
3251 #define NVT_VIDEO_INFOFRAME_BYTE3_SC_VERT_SCALED 2
3252 #define NVT_VIDEO_INFOFRAME_BYTE3_SC_H_V_SCALED 3
3253 //
3254 #define NVT_VIDEO_INFOFRAME_BYTE3_Q1Q0_MASK 0x0C // quantization
3255 #define NVT_VIDEO_INFOFRAME_BYTE3_Q1Q0_SHIFT 2
3256 #define NVT_VIDEO_INFOFRAME_BYTE3_Q1Q0_DEFAULT 0
3257 #define NVT_VIDEO_INFOFRAME_BYTE3_Q1Q0_LIMITED_RANGE 1
3258 #define NVT_VIDEO_INFOFRAME_BYTE3_Q1Q0_FULL_RANGE 2
3259 #define NVT_VIDEO_INFOFRAME_BYTE3_Q1Q0_RESERVED 3
3260 //
3261 #define NVT_VIDEO_INFOFRAME_BYTE3_EC_MASK 0x70 // extended colorimetry
3262 #define NVT_VIDEO_INFOFRAME_BYTE3_EC_SHIFT 4
3263 #define NVT_VIDEO_INFOFRAME_BYTE3_EC_xvYCC_601 0
3264 #define NVT_VIDEO_INFOFRAME_BYTE3_EC_xvYCC_709 1
3265 #define NVT_VIDEO_INFOFRAME_BYTE3_EC_sYCC_601 2
3266 #define NVT_VIDEO_INFOFRAME_BYTE3_EC_AdobeYCC_601 3
3267 #define NVT_VIDEO_INFOFRAME_BYTE3_EC_AdobeRGB 4
3268 #define NVT_VIDEO_INFOFRAME_BYTE3_EC_BT2020cYCC 5 // CEA-861-F define it as "ITU-R BT.2020 YcCbcCrc" at Table 12
3269 #define NVT_VIDEO_INFOFRAME_BYTE3_EC_BT2020RGBYCC 6 // CEA-861-F define it as "ITU-R BT.2020 YcCbCr" at Table 12
3270 #define NVT_VIDEO_INFOFRAME_BYTE3_EC_RESERVED7 7 // CEA-861-F define it as "Reserved" at Table 12
3271 #define NVT_VIDEO_INFOFRAME_BYTE3_EC_AdditionalColorExt 7 // CTA-861-G define it as "Additional Colorimtry Ext Info Valid" at Table_13
3272 //
3273 #define NVT_VIDEO_INFOFRAME_BYTE3_ITC_MASK 0x80 // IT content
3274 #define NVT_VIDEO_INFOFRAME_BYTE3_ITC_SHIFT 7
3275 #define NVT_VIDEO_INFOFRAME_BYTE3_ITC_NO_DATA 0
3276 #define NVT_VIDEO_INFOFRAME_BYTE3_ITC_IT_CONTENT 1
3277 //
3278 #define NVT_VIDEO_INFOFRAME_BYTE3_RESERVED_V1_MASK 0x60 // reserved
3279 #define NVT_VIDEO_INFOFRAME_BYTE3_RESERVED_V1_SHIFT 5
3280 //
3281 #define NVT_VIDEO_INFOFRAME_BYTE4_VIC_MASK 0xFF // video identification code
3282 #define NVT_VIDEO_INFOFRAME_BYTE4_VIC_SHIFT 0
3283 #define NVT_VIDEO_INFOFRAME_BYTE4_VIC7 0x80
3284 //
3285 #define NVT_VIDEO_INFOFRAME_BYTE4_RESERVED_V3_MASK 0x00
3286 #define NVT_VIDEO_INFOFRAME_BYTE4_RESERVED_V3_SHIFT 0
3287 #define NVT_VIDEO_INFOFRAME_BYTE4_RESERVED_V2_MASK 0x80
3288 #define NVT_VIDEO_INFOFRAME_BYTE4_RESERVED_V2_SHIFT 7
3289 #define NVT_VIDEO_INFOFRAME_BYTE4_RESERVED_V1_MASK 0xFF
3290 #define NVT_VIDEO_INFOFRAME_BYTE4_RESERVED_V1_SHIFT 0
3291 //
3292 #define NVT_VIDEO_INFOFRAME_BYTE5_PR_MASK 0x0F // pixel repetitions
3293 #define NVT_VIDEO_INFOFRAME_BYTE5_PR_SHIFT 0
3294 #define NVT_VIDEO_INFOFRAME_BYTE5_PR_NO_PEP 0
3295 #define NVT_VIDEO_INFOFRAME_BYTE5_PR_2X 1
3296 #define NVT_VIDEO_INFOFRAME_BYTE5_PR_3X 2
3297 #define NVT_VIDEO_INFOFRAME_BYTE5_PR_4X 3
3298 #define NVT_VIDEO_INFOFRAME_BYTE5_PR_5X 4
3299 #define NVT_VIDEO_INFOFRAME_BYTE5_PR_6X 5
3300 #define NVT_VIDEO_INFOFRAME_BYTE5_PR_7X 6
3301 #define NVT_VIDEO_INFOFRAME_BYTE5_PR_8X 7
3302 #define NVT_VIDEO_INFOFRAME_BYTE5_PR_9X 8
3303 #define NVT_VIDEO_INFOFRAME_BYTE5_PR_10X 9
3304 //
3305 #define NVT_VIDEO_INFOFRAME_BYTE5_CN1CN0_MASK 0x30 // Content Information
3306 #define NVT_VIDEO_INFOFRAME_BYTE5_CN1CN0_SHIFT 4
3307 #define NVT_VIDEO_INFOFRAME_BYTE5_CN1CN0_NODATA 0 // ITC = 0
3308 #define NVT_VIDEO_INFOFRAME_BYTE5_CN1CN0_GRAPHICS 0 // ITC = 1
3309 #define NVT_VIDEO_INFOFRAME_BYTE5_CN1CN0_PHOTO 1 // ITC = don't care
3310 #define NVT_VIDEO_INFOFRAME_BYTE5_CN1CN0_CINEMA 2 // ITC = don't care
3311 #define NVT_VIDEO_INFOFRAME_BYTE5_CN1CN0_GAME 3 // ITC = don't care
3312
3313 #define NVT_VIDEO_INFOFRAME_BYTE5_YQ1YQ0_MASK 0xC0 // YCC quantization
3314 #define NVT_VIDEO_INFOFRAME_BYTE5_YQ1YQ0_SHIFT 6
3315 #define NVT_VIDEO_INFOFRAME_BYTE5_YQ1YQ0_LIMITED_RANGE 1
3316 #define NVT_VIDEO_INFOFRAME_BYTE5_YQ1YQ0_FULL_RANGE 2
3317 #define NVT_VIDEO_INFOFRAME_BYTE5_YQ1YQ0_RESERVED3 3
3318 #define NVT_VIDEO_INFOFRAME_BYTE5_YQ1YQ0_RESERVED4 4
3319 //
3320 #define NVT_VIDEO_INFOFRAME_BYTE5_YQ_MASK 0xc0 // content type
3321 #define NVT_VIDEO_INFOFRAME_BYTE5_YQ_SHIFT 6
3322 #define NVT_VIDEO_INFOFRAME_BYTE5_YQ_LIMITED 0
3323 #define NVT_VIDEO_INFOFRAME_BYTE5_YQ_FULL 1
3324 #define NVT_VIDEO_INFOFRAME_BYTE5_YQ_RSVD1 2
3325 #define NVT_VIDEO_INFOFRAME_BYTE5_YQ_RSVD2 3
3326 //
3327 #define NVT_VIDEO_INFOFRAME_BYTE5_RESERVED_V2_MASK 0x00
3328 #define NVT_VIDEO_INFOFRAME_BYTE5_RESERVED_V2_SHIFT 0
3329 #define NVT_VIDEO_INFOFRAME_BYTE5_RESERVED_V1_MASK 0xFF
3330 #define NVT_VIDEO_INFOFRAME_BYTE5_RESERVED_V1_SHIFT 0
3331 //
3332 #define NVT_VIDEO_INFOFRAME_BYTE14_FR0_FR3_MASK 0x0F
3333 #define NVT_VIDEO_INFOFRAME_BYTE14_FR0_FR3_SHIFT 0
3334 #define NVT_VIDEO_INFOFRAME_BYTE14_FR0_FR3_NODATA 0
3335 #define NVT_VIDEO_INFOFRAME_BYTE14_FR4_ONE_BIT_MASK 0x10
3336 #define NVT_VIDEO_INFOFRAME_BYTE15_FR4_MASK 0x40
3337 #define NVT_VIDEO_INFOFRAME_BYTE15_FR4_NODATA 0
3338 #define NVT_VIDEO_INFOFRAME_BYTE15_FR4_SHIFT 2
3339 //
3340 #define NVT_VIDEO_INFOFRAME_BYTE15_RID_MASK 0x3F
3341 #define NVT_VIDEO_INFOFRAME_BYTE15_RID_SHIFT 0
3342 #define NVT_VIDEO_INFOFRAME_BYTE15_RID_NODATA 0
3343 //
3344 #define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_MASK 0xF0
3345 #define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_SHIFT 4
3346 #define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_P3D65RGB 0
3347 #define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_P3DCIRGB 1
3348 #define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_BT2100_ICtCp 2
3349 #define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_sRGB 3
3350 #define NVT_VIDEO_INFOFRAME_BYTE14_ACE0_3_defaultRGB 4
3351 //
3352 #define NVT_VIDEO_INFOFRAME_CONTENT_VIDEO 0
3353 #define NVT_VIDEO_INFOFRAME_CONTENT_GRAPHICS 1
3354 #define NVT_VIDEO_INFOFRAME_CONTENT_PHOTO 2
3355 #define NVT_VIDEO_INFOFRAME_CONTENT_CINEMA 3
3356 #define NVT_VIDEO_INFOFRAME_CONTENT_GAME 4
3357 #define NVT_VIDEO_INFOFRAME_CONTENT_LAST 4
3358
3359 #pragma pack(1)
3360 typedef struct
3361 {
3362 // byte 1
3363 struct
3364 {
3365 NvU8 scanInfo : 2;
3366 NvU8 barInfo : 2;
3367 NvU8 activeFormatInfoPresent : 1;
3368 NvU8 colorSpace : 2;
3369 NvU8 rsvd_bits_byte1 : 1;
3370 } byte1;
3371
3372 // byte 2
3373 struct
3374 {
3375 NvU8 activeFormatAspectRatio : 4;
3376 NvU8 picAspectRatio : 2;
3377 NvU8 colorimetry : 2;
3378 } byte2;
3379
3380 // byte 3
3381 struct
3382 {
3383 NvU8 nonuniformScaling : 2;
3384 NvU8 rgbQuantizationRange : 2;
3385 NvU8 extendedColorimetry : 3;
3386 NvU8 itContent : 1;
3387 } byte3;
3388
3389 // byte 4
3390 struct
3391 {
3392 NvU8 vic : 7;
3393 NvU8 rsvd_bits_byte4 : 1;
3394 } byte4;
3395
3396 // byte 5
3397 struct
3398 {
3399 NvU8 pixelRepeat : 4;
3400 NvU8 contentTypes : 2;
3401 NvU8 yccQuantizationRange : 2;
3402 } byte5;
3403
3404 NvU16 topBar;
3405 NvU16 bottomBar;
3406 NvU16 leftBar;
3407 NvU16 rightBar;
3408
3409 // byte 14~15
3410 struct
3411 {
3412 NvU8 fr_low : 4;
3413 NvU8 ace : 4;
3414 } byte14;
3415
3416 struct
3417 {
3418 NvU8 rid : 6;
3419 NvU8 fr_hi : 1;
3420 NvU8 rsvd_bits_byte15 : 1;
3421 }byte15;
3422 } NVT_VIDEO_INFOFRAME_OVERRIDE;
3423 #pragma pack()
3424
3425 typedef struct
3426 {
3427 NvU32 vic : 8;
3428 NvU32 pixelRepeat : 5;
3429 NvU32 colorSpace : 3;
3430 NvU32 colorimetry : 3;
3431 NvU32 extendedColorimetry : 4;
3432 NvU32 rgbQuantizationRange : 3;
3433 NvU32 yccQuantizationRange : 3;
3434 NvU32 itContent : 2;
3435 NvU32 contentTypes : 3;
3436 NvU32 scanInfo : 3;
3437 NvU32 activeFormatInfoPresent : 2;
3438 NvU32 activeFormatAspectRatio : 5;
3439 NvU32 picAspectRatio : 3;
3440 NvU32 nonuniformScaling : 3;
3441 NvU32 barInfo : 3;
3442 NvU32 top_bar : 17;
3443 NvU32 bottom_bar : 17;
3444 NvU32 left_bar : 17;
3445 NvU32 right_bar : 17;
3446 NvU32 Future17 : 2;
3447 NvU32 Future47 : 2;
3448 } NVT_INFOFRAME_VIDEO;
3449
3450
3451 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE1_S1S0_MASK 0x3
3452 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE1_B1B0_MASK 0x3
3453 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE1_A0_MASK 0x1 // active format info present
3454 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE1_Y1Y0_MASK 0x3
3455 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE1_Y2Y1Y0_MASK 0x7
3456 //
3457 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE2_R3R2R1R0_MASK 0xF // active format aspect ratio
3458 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE2_M1M0_MASK 0x3 // picture aspect ratio
3459 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE2_C1C0_MASK 0x3 // colorimetry
3460 //
3461 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE3_SC_MASK 0x3 // non-uniform scaling
3462 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE3_Q1Q0_MASK 0x3 // quantization
3463 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE3_EC_MASK 0x7 // extended colorimetry
3464 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE3_ITC_MASK 0x1 // IT content
3465 //
3466 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE4_VIC_MASK 0x7F // video identification code
3467 //
3468 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE5_PR_MASK 0xF // pixel repetitions
3469 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE5_CN1CN0_MASK 0x3
3470 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE5_YQ1YQ0_MASK 0x3 // YCC quantization
3471 //
3472 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE14_FR0FR3_MASK 0xF // Frame rate 0-3 bits in Byte14
3473 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE14_ACE0ACE3_MASK 0xF // Additional Colorimetry Extension
3474 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE15_RID0RID5_MASK 0x3F // Resolution Identification
3475 #define NVT_VIDEO_INFOFRAME_OVERRIDE_BYTE15_FR4_MASK 0x1 // Frame rate 4th bit in Byte 15
3476
3477 // audio infoframe structure
3478 typedef struct tagNVT_AUDIO_INFOFRAME
3479 {
3480 NvU8 type;
3481 NvU8 version;
3482 NvU8 length;
3483
3484 // byte 1~5
3485 NvU8 byte1;
3486 NvU8 byte2;
3487 NvU8 byte3;
3488 NvU8 byte4;
3489 NvU8 byte5;
3490
3491 // byte 6~10
3492 NvU8 rsvd_byte6;
3493 NvU8 rsvd_byte7;
3494 NvU8 rsvd_byte8;
3495 NvU8 rsvd_byte9;
3496 NvU8 rsvd_byte10;
3497
3498 }NVT_AUDIO_INFOFRAME;
3499
3500 // self refresh infoframe structure. See SR spec.
3501 typedef struct tagNVT_SR_INFOFRAME
3502 {
3503 NvU8 type;
3504 NvU8 version;
3505 NvU8 length;
3506
3507 NvU8 data;
3508
3509 }NVT_SR_INFOFRAME;
3510
3511 //
3512 #define NVT_AUDIO_INFOFRAME_VERSION_1 1
3513 //
3514 #define NVT_AUDIO_INFOFRAME_BYTE1_CC_MASK 0x07
3515 #define NVT_AUDIO_INFOFRAME_BYTE1_CC_SHIFT 0
3516 #define NVT_AUDIO_INFOFRAME_BYTE1_CC_REF_HEADER 0
3517 #define NVT_AUDIO_INFOFRAME_BYTE1_CC_2CH 1
3518 #define NVT_AUDIO_INFOFRAME_BYTE1_CC_DO_NOT_USE 2
3519 #define NVT_AUDIO_INFOFRAME_BYTE1_CC_4CH 3
3520 #define NVT_AUDIO_INFOFRAME_BYTE1_CC_5CH 4
3521 #define NVT_AUDIO_INFOFRAME_BYTE1_CC_6CH 5
3522 #define NVT_AUDIO_INFOFRAME_BYTE1_CC_7CH 6
3523 #define NVT_AUDIO_INFOFRAME_BYTE1_CC_8CH 7
3524 //
3525 #define NVT_AUDIO_INFOFRAME_BYTE1_RESERVED_MASK 0x08
3526 #define NVT_AUDIO_INFOFRAME_BYTE1_RESERVED_SHIFT 3
3527 //
3528 #define NVT_AUDIO_INFOFRAME_BYTE1_CT_MASK 0xF0
3529 #define NVT_AUDIO_INFOFRAME_BYTE1_CT_SHIFT 4
3530 #define NVT_AUDIO_INFOFRAME_BYTE1_CT_REF_HEADER 0
3531 #define NVT_AUDIO_INFOFRAME_BYTE1_CT_PCM 1
3532 #define NVT_AUDIO_INFOFRAME_BYTE1_CT_DO_NOT_USE 2
3533 #define NVT_AUDIO_INFOFRAME_BYTE1_CT_MPEG1 3
3534 #define NVT_AUDIO_INFOFRAME_BYTE1_CT_MP3 4
3535 #define NVT_AUDIO_INFOFRAME_BYTE1_CT_MPEG2 5
3536 #define NVT_AUDIO_INFOFRAME_BYTE1_CT_AAC 6
3537 #define NVT_AUDIO_INFOFRAME_BYTE1_CT_DTS 7
3538 #define NVT_AUDIO_INFOFRAME_BYTE1_CT_USE_CODING_EXTENSION_TYPE 15
3539 //
3540 #define NVT_AUDIO_INFOFRAME_BYTE2_SS_MASK 0x3
3541 #define NVT_AUDIO_INFOFRAME_BYTE2_SS_SHIFT 0
3542 #define NVT_AUDIO_INFOFRAME_BYTE2_SS_REF_HEADER 0
3543 #define NVT_AUDIO_INFOFRAME_BYTE2_SS_16BIT 1
3544 #define NVT_AUDIO_INFOFRAME_BYTE2_SS_20BIT 2
3545 #define NVT_AUDIO_INFOFRAME_BYTE2_SS_24BIT 3
3546 //
3547 #define NVT_AUDIO_INFOFRAME_BYTE2_SF_MASK 0x1C
3548 #define NVT_AUDIO_INFOFRAME_BYTE2_SF_SHIFT 2
3549 #define NVT_AUDIO_INFOFRAME_BYTE2_SF_HEADER 0
3550 #define NVT_AUDIO_INFOFRAME_BYTE2_SF_32KHz 1
3551 #define NVT_AUDIO_INFOFRAME_BYTE2_SF_44KHz 2
3552 #define NVT_AUDIO_INFOFRAME_BYTE2_SF_48KHz 3
3553 #define NVT_AUDIO_INFOFRAME_BYTE2_SF_88KHz 4
3554 #define NVT_AUDIO_INFOFRAME_BYTE2_SF_96KHz 5
3555 #define NVT_AUDIO_INFOFRAME_BYTE2_SF_176KHz 6
3556 #define NVT_AUDIO_INFOFRAME_BYTE2_SF_192KHz 7
3557 //
3558 #define NVT_AUDIO_INFOFRAME_BYTE2_RESERVED_MASK 0xE0
3559 #define NVT_AUDIO_INFOFRAME_BYTE2_RESERVED_SHIFT 5
3560 //
3561 #define NVT_AUDIO_INFOFRAME_BYTE3_CXT_MASK 0x1F
3562 #define NVT_AUDIO_INFOFRAME_BYTE3_CXT_SHIFT 0
3563 #define NVT_AUDIO_INFOFRAME_BYTE3_CXT_RESERVE31 31
3564 //
3565 #define NVT_AUDIO_INFOFRAME_BYTE3_RESERVED_MASK 0xE0
3566 #define NVT_AUDIO_INFOFRAME_BYTE3_RESERVED_SHIFT 5
3567 //
3568 #define NVT_AUDIO_INFOFRAME_BYTE4_CA_MASK 0xFF
3569 #define NVT_AUDIO_INFOFRAME_BYTE4_CA_SHIFT 0
3570 #define NVT_AUDIO_INFOFRAME_BYTE4_CA_FRW_FLW_RR_RL_FC_LFE_FR_FL 49
3571 //
3572 #define NVT_AUDIO_INFOFRAME_BYTE5_LFEPBL_MASK 0x03
3573 #define NVT_AUDIO_INFOFRAME_BYTE5_LFEPBL_SHIFT 0
3574 #define NVT_AUDIO_INFOFRAME_BYTE5_LFEPBL_NO_DATA 0
3575 #define NVT_AUDIO_INFOFRAME_BYTE5_LFEPBL_0DB 1
3576 #define NVT_AUDIO_INFOFRAME_BYTE5_LFEPBL_PLUS10DB 2
3577 #define NVT_AUDIO_INFOFRAME_BYTE5_LFEPBL_RESERVED03 3
3578 //
3579 #define NVT_AUDIO_INFOFRAME_BYTE5_RESERVED_MASK 0x4
3580 #define NVT_AUDIO_INFOFRAME_BYTE5_RESERVED_SHIFT 2
3581 //
3582 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_MASK 0x78
3583 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_SHIFT 3
3584 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_0dB 0
3585 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_1dB 1
3586 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_2dB 2
3587 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_3dB 3
3588 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_4dB 4
3589 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_5dB 5
3590 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_6dB 6
3591 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_7dB 7
3592 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_8dB 8
3593 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_9dB 9
3594 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_10dB 10
3595 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_11dB 11
3596 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_12dB 12
3597 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_13dB 13
3598 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_14dB 14
3599 #define NVT_AUDIO_INFOFRAME_BYTE5_LSV_15dB 15
3600 //
3601 #define NVT_AUDIO_INFOFRAME_BYTE5_DM_INH_MASK 0x80
3602 #define NVT_AUDIO_INFOFRAME_BYTE5_DM_INH_SHIFT 7
3603 #define NVT_AUDIO_INFOFRAME_BYTE5_DM_INH_PERMITTED 0
3604 #define NVT_AUDIO_INFOFRAME_BYTE5_DM_INH_PROHIBITED 1
3605 //
3606 #define NVT_AUDIO_INFOFRAME_BYTE6_RESERVED_MASK 0xFF
3607 #define NVT_AUDIO_INFOFRAME_BYTE6_RESERVED_SHIFT 0
3608 //
3609 //
3610 #define NVT_AUDIO_INFOFRAME_BYTE7_RESERVED_MASK 0xFF
3611 #define NVT_AUDIO_INFOFRAME_BYTE7_RESERVED_SHIFT 0
3612 //
3613 ///
3614 #define NVT_AUDIO_INFOFRAME_BYTE8_RESERVED_MASK 0xFF
3615 #define NVT_AUDIO_INFOFRAME_BYTE8_RESERVED_SHIFT 0
3616 //
3617 //
3618 #define NVT_AUDIO_INFOFRAME_BYTE9_RESERVED_MASK 0xFF
3619 #define NVT_AUDIO_INFOFRAME_BYTE9_RESERVED_SHIFT 0
3620 //
3621 //
3622 #define NVT_AUDIO_INFOFRAME_BYTE10_RESERVED_MASK 0xFF
3623 #define NVT_AUDIO_INFOFRAME_BYTE10_RESERVED_SHIFT 0
3624 //
3625
3626 typedef struct
3627 {
3628 // byte 1
3629 struct
3630 {
3631 NvU8 channelCount : 3;
3632 NvU8 rsvd_bits_byte1 : 1;
3633 NvU8 codingType : 4;
3634 } byte1;
3635
3636 // byte 2
3637 struct
3638 {
3639 NvU8 sampleSize : 2;
3640 NvU8 sampleRate : 3;
3641 NvU8 rsvd_bits_byte2 : 3;
3642 } byte2;
3643
3644
3645 // byte 3
3646 struct
3647 {
3648 NvU8 codingExtensionType : 5;
3649 NvU8 rsvd_bits_byte3 : 3;
3650 } byte3;
3651
3652 // byte 4
3653 NvU8 speakerPlacement;
3654
3655 // byte 5
3656 struct
3657 {
3658 NvU8 lfePlaybackLevel : 2;
3659 NvU8 rsvd_bits_byte5 : 1;
3660 NvU8 levelShift : 4;
3661 NvU8 downmixInhibit : 1;
3662 } byte5;
3663
3664 // byte 6~10
3665 NvU8 rsvd_byte6;
3666 NvU8 rsvd_byte7;
3667 NvU8 rsvd_byte8;
3668 NvU8 rsvd_byte9;
3669 NvU8 rsvd_byte10;
3670 } NVT_AUDIO_INFOFRAME_OVERRIDE;
3671
3672 typedef struct
3673 {
3674 NvU32 codingType : 5;
3675 NvU32 codingExtensionType : 6;
3676 NvU32 sampleSize : 3;
3677 NvU32 sampleRate : 4;
3678 NvU32 channelCount : 4;
3679 NvU32 speakerPlacement : 9;
3680 NvU32 downmixInhibit : 2;
3681 NvU32 lfePlaybackLevel : 3;
3682 NvU32 levelShift : 5;
3683 NvU32 Future12 : 2;
3684 NvU32 Future2x : 4;
3685 NvU32 Future3x : 4;
3686 NvU32 Future52 : 2;
3687 NvU32 Future6 : 9;
3688 NvU32 Future7 : 9;
3689 NvU32 Future8 : 9;
3690 NvU32 Future9 : 9;
3691 NvU32 Future10 : 9;
3692 } NVT_INFOFRAME_AUDIO;
3693
3694 #define NVT_AUDIO_INFOFRAME_OVERRIDE_BYTE1_CC_MASK 0x07
3695 #define NVT_AUDIO_INFOFRAME_OVERRIDE_BYTE1_CT_MASK 0x0F
3696 #define NVT_AUDIO_INFOFRAME_OVERRIDE_BYTE2_SS_MASK 0x03
3697 #define NVT_AUDIO_INFOFRAME_OVERRIDE_BYTE2_SF_MASK 0x03
3698 #define NVT_AUDIO_INFOFRAME_OVERRIDE_BYTE3_CXT_MASK 0x1F
3699 #define NVT_AUDIO_INFOFRAME_OVERRIDE_BYTE4_CA_MASK 0xFF
3700 #define NVT_AUDIO_INFOFRAME_OVERRIDE_BYTE5_LFEPBL_MASK 0x03
3701 #define NVT_AUDIO_INFOFRAME_OVERRIDE_BYTE5_LSV_MASK 0x0F
3702 #define NVT_AUDIO_INFOFRAME_OVERRIDE_BYTE5_DM_INH_MASK 0x01
3703
3704 //
3705 // HDMI 1.3a GCP, ColorDepth
3706 //
3707 #define NVT_HDMI_COLOR_DEPTH_DEFAULT 0x0
3708 #define NVT_HDMI_COLOR_DEPTH_RSVD1 0x1
3709 #define NVT_HDMI_COLOR_DEPTH_RSVD2 0x2
3710 #define NVT_HDMI_COLOR_DEPTH_RSVD3 0x3
3711 #define NVT_HDMI_COLOR_DEPTH_24 0x4
3712 #define NVT_HDMI_COLOR_DEPTH_30 0x5
3713 #define NVT_HDMI_COLOR_DEPTH_36 0x6
3714 #define NVT_HDMI_COLOR_DEPTH_48 0x7
3715 #define NVT_HDMI_COLOR_DEPTH_RSVD8 0x8
3716 #define NVT_HDMI_COLOR_DEPTH_RSVD9 0x9
3717 #define NVT_HDMI_COLOR_DEPTH_RSVD10 0xA
3718 #define NVT_HDMI_COLOR_DEPTH_RSVD11 0xB
3719 #define NVT_HDMI_COLOR_DEPTH_RSVD12 0xC
3720 #define NVT_HDMI_COLOR_DEPTH_RSVD13 0xD
3721 #define NVT_HDMI_COLOR_DEPTH_RSVD14 0xE
3722 #define NVT_HDMI_COLOR_DEPTH_RSVD15 0xF
3723
3724 // HDMI 1.3a GCP, PixelPacking Phase
3725 #define NVT_HDMI_PIXELPACKING_PHASE4 0x0
3726 #define NVT_HDMI_PIXELPACKING_PHASE1 0x1
3727 #define NVT_HDMI_PIXELPACKING_PHASE2 0x2
3728 #define NVT_HDMI_PIXELPACKING_PHASE3 0x3
3729 #define NVT_HDMI_PIXELPACKING_RSVD4 0x4
3730 #define NVT_HDMI_PIXELPACKING_RSVD5 0x5
3731 #define NVT_HDMI_PIXELPACKING_RSVD6 0x6
3732 #define NVT_HDMI_PIXELPACKING_RSVD7 0x7
3733 #define NVT_HDMI_PIXELPACKING_RSVD8 0x8
3734 #define NVT_HDMI_PIXELPACKING_RSVD9 0x9
3735 #define NVT_HDMI_PIXELPACKING_RSVD10 0xA
3736 #define NVT_HDMI_PIXELPACKING_RSVD11 0xB
3737 #define NVT_HDMI_PIXELPACKING_RSVD12 0xC
3738 #define NVT_HDMI_PIXELPACKING_RSVD13 0xD
3739 #define NVT_HDMI_PIXELPACKING_RSVD14 0xE
3740 #define NVT_HDMI_PIXELPACKING_RSVD15 0xF
3741
3742 #define NVT_HDMI_RESET_DEFAULT_PIXELPACKING_PHASE 0x0
3743 #define NVT_HDMI_SET_DEFAULT_PIXELPACKING_PHASE 0x1
3744
3745 #define NVT_HDMI_GCP_SB1_CD_SHIFT 0
3746 #define NVT_HDMI_GCP_SB1_PP_SHIFT 4
3747
3748
3749 // Vendor specific info frame (HDMI 1.4 specific)
3750 typedef struct tagNVT_VENDOR_SPECIFIC_INFOFRAME_PAYLOAD
3751 {
3752 // byte 1~5
3753 NvU8 byte1;
3754 NvU8 byte2;
3755 NvU8 byte3;
3756 NvU8 byte4;
3757 NvU8 byte5;
3758 NvU8 optionalBytes[22];
3759 }NVT_VENDOR_SPECIFIC_INFOFRAME_PAYLOAD;
3760 typedef struct tagNVT_VENDOR_SPECIFIC_INFOFRAME
3761 {
3762 NVT_INFOFRAME_HEADER Header;
3763 NVT_VENDOR_SPECIFIC_INFOFRAME_PAYLOAD Data;
3764 } NVT_VENDOR_SPECIFIC_INFOFRAME;
3765 //
3766 #define NVT_HDMI_VS_INFOFRAME_VERSION_1 1
3767
3768 #define NVT_HDMI_VS_HB0_MASK 0xFF
3769 #define NVT_HDMI_VS_HB0_SHIFT 0x00
3770 #define NVT_HDMI_VS_HB0_VALUE 0x01
3771
3772 #define NVT_HDMI_VS_HB1_MASK 0xFF
3773 #define NVT_HDMI_VS_HB1_SHIFT 0x00
3774 #define NVT_HDMI_VS_HB1_VALUE 0x01
3775
3776 #define NVT_HDMI_VS_HB2_MASK 0xFF
3777 #define NVT_HDMI_VS_HB2_SHIFT 0x00
3778 #define NVT_HDMI_VS_HB2_VALUE 0x06
3779
3780 #define NVT_HDMI_VS_BYTE1_OUI_MASK 0xff
3781 #define NVT_HDMI_VS_BYTE1_OUI_SHIFT 0x00
3782 #define NVT_HDMI_VS_BYTE1_OUI_VER_1_4 0x03
3783 #define NVT_HDMI_VS_BYTE1_OUI_VER_2_0 0xD8
3784
3785 #define NVT_HDMI_VS_BYTE2_OUI_MASK 0xff
3786 #define NVT_HDMI_VS_BYTE2_OUI_SHIFT 0x00
3787 #define NVT_HDMI_VS_BYTE2_OUI_VER_1_4 0x0C
3788 #define NVT_HDMI_VS_BYTE2_OUI_VER_2_0 0x5D
3789
3790 #define NVT_HDMI_VS_BYTE3_OUI_MASK 0xff
3791 #define NVT_HDMI_VS_BYTE3_OUI_SHIFT 0x00
3792 #define NVT_HDMI_VS_BYTE3_OUI_VER_1_4 0x00
3793 #define NVT_HDMI_VS_BYTE3_OUI_VER_2_0 0xC4
3794
3795 //
3796 #define NVT_HDMI_VS_BYTE4_RSVD_MASK 0x1f
3797 #define NVT_HDMI_VS_BYTE4_RSVD_SHIFT 0x00
3798 #define NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_MASK 0xe0
3799 #define NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_SHIFT 0x05
3800 #define NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_NONE 0x00
3801 #define NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_EXT 0x01
3802 #define NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_3D 0x02
3803 // 0x03-0x07 reserved
3804 //
3805 #define NVT_HDMI_VS_BYTE5_HDMI_VIC_MASK 0xff // HDMI_VID_FMT = HDMI_VID_FMT_EXT
3806 #define NVT_HDMI_VS_BYTE5_HDMI_VIC_SHIFT 0x00
3807 #define NVT_HDMI_VS_BYTE5_HDMI_VIC_NA 0xfe
3808 #define NVT_HDMI_VS_BYTE5_HDMI_VIC_RSVD 0x00
3809 #define NVT_HDMI_VS_BYTE5_HDMI_VIC_4Kx2Kx30Hz 0x01
3810 #define NVT_HDMI_VS_BYTE5_HDMI_VIC_4Kx2Kx25Hz 0x02
3811 #define NVT_HDMI_VS_BYTE5_HDMI_VIC_4Kx2Kx24Hz 0x03
3812 #define NVT_HDMI_VS_BYTE5_HDMI_VIC_4Kx2Kx24Hz_SMPTE 0x04
3813 // 0x05-0xff reserved
3814 //
3815 #define NVT_HDMI_VS_BYTE5_HDMI_RSVD_MASK 0x07 // HDMI_VID_FMT = HDMI_VID_FMT_3D
3816 #define NVT_HDMI_VS_BYTE5_HDMI_RSVD_SHIFT 0x00
3817 #define NVT_HDMI_VS_BYTE5_3D_META_PRESENT_MASK 0x01
3818 #define NVT_HDMI_VS_BYTE5_3D_META_PRESENT_SHIFT 0x03
3819 #define NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_NOTPRES 0x00 // HDMI Metadata is not present
3820 #define NVT_HDMI_VS_BYTE5_HDMI_META_PRESENT_PRES 0x01 // HDMI Metadata is present
3821 #define NVT_HDMI_VS_BYTE5_ALLM_MODE_MASK 0x02 // ALLM is field of length 1 bit at Bit Number 1
3822 #define NVT_HDMI_VS_BYTE5_ALLM_MODE_DIS 0x00
3823 #define NVT_HDMI_VS_BYTE5_ALLM_MODE_EN 0x01
3824 #define NVT_HDMI_VS_BYTE5_ALLM_MODE_SHIFT 0x01 // ALLM is byte5 bit position 1, so shift 1 bit
3825 #define NVT_HDMI_VS_BYTE5_HDMI_3DS_MASK 0xf0
3826 #define NVT_HDMI_VS_BYTE5_HDMI_3DS_SHIFT 0x04
3827 #define NVT_HDMI_VS_BYTE5_HDMI_3DS_NA 0xfe
3828 #define NVT_HDMI_VS_BYTE5_HDMI_3DS_FRAMEPACK 0x00
3829 #define NVT_HDMI_VS_BYTE5_HDMI_3DS_FIELD_ALT 0x01
3830 #define NVT_HDMI_VS_BYTE5_HDMI_3DS_LINE_ALT 0x02
3831 #define NVT_HDMI_VS_BYTE5_HDMI_3DS_SIDEBYSIDEFULL 0x03
3832 #define NVT_HDMI_VS_BYTE5_HDMI_3DS_LDEPTH 0x04
3833 #define NVT_HDMI_VS_BYTE5_HDMI_3DS_LDEPTHGFX 0x05
3834 #define NVT_HDMI_VS_BYTE5_HDMI_3DS_TOPBOTTOM 0x06
3835 //0x06-0x07 reserved
3836 #define NVT_HDMI_VS_BYTE5_HDMI_3DS_SIDEBYSIDEHALF 0x08
3837 //0x09-0x0f reserved
3838 //
3839 // bytes 6-21 are optional depending on the 3D mode & the presence/abcense of metadata
3840 #define NVT_HDMI_VS_BYTE_OPT1_HDMI_RSVD_MASK 0x0f // HDMI_VID_FMT = HDMI_VID_FMT_3D
3841 #define NVT_HDMI_VS_BYTE_OPT1_HDMI_RSVD_SHIFT 0x00
3842 #define NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_MASK 0xf0
3843 #define NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SHIFT 0x04
3844 #define NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_NA 0xfe // Extended data is not applicable
3845 #define NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SSH 0x01 // Horizontal subsampling 1.4a defines a single subsampling vs 1.4s 4.
3846 #define NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SSH_H_OL_OR 0x00 // Horizontal subsampling Odd Left Odd Right
3847 #define NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SSH_H_OL_ER 0x01 // Horizontal subsampling Odd Left Even Right
3848 #define NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SSH_H_EL_OR 0x02 // Horizontal subsampling Even Left Odd Right
3849 #define NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SSH_H_EL_ER 0x03 // Horizontal subsampling Even Left Even Right
3850 #define NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SSH_Q_OL_OR 0x04 // Quincunx matrix Odd Left Odd Right
3851 #define NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SSH_Q_OL_ER 0x05 // Quincunx matrix Odd Left Even Right
3852 #define NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SSH_Q_EL_OR 0x06 // Quincunx matrix Even Left Odd Right
3853 #define NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_SSH_Q_EL_ER 0x07 // Quincunx matrix Even Left Even Right
3854 //0x08-0x0f reserved
3855 #define NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_MASK 0xf0 // HDMI_VID_FMT = HDMI_VID_FMT_3D; HDMI_3D_META_PRESENT = 1
3856 #define NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_SHIFT 0x04 //
3857 #define NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_NONE 0x00 // length of no metadata
3858 #define NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_LEN_PARALLAX 0x08 // length of paralax data
3859
3860 #define NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_MASK 0x0f // HDMI_VID_FMT = HDMI_VID_FMT_3D
3861 #define NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_SHIFT 0x00
3862 #define NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_PARALLAX 0x00 // parallax metadata in the frame
3863 #define NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_NA 0xfe // no metadata in the frame
3864
3865 #define NVT_HDMI_VS_BYTENv_RSVD_MASK 0xff // if last byte of infoframe, will move depending on HDMI_VID_FMT, 3D metadata present, 3D_Metadata type.
3866 #define NVT_HDMI_VS_BYTENv_RSVD_SHIFT 0x00
3867 #define NVT_HDMI_VS_BYTENv_RSVD 0x00
3868
3869
3870 // Extended Metadata Packet (HDMI 2.1 specific)
3871 typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME_PAYLOAD
3872 {
3873 // byte 1~7
3874 NvU8 byte1;
3875 NvU8 byte2;
3876 NvU8 byte3;
3877 NvU8 byte4;
3878 NvU8 byte5;
3879 NvU8 byte6;
3880 NvU8 byte7;
3881
3882 NvU8 metadataBytes[21];
3883 } NVT_EXTENDED_METADATA_PACKET_INFOFRAME_PAYLOAD;
3884
3885 typedef struct tagNVT_EXTENDED_METADATA_PACKET_INFOFRAME
3886 {
3887 NVT_EXTENDED_METADATA_PACKET_INFOFRAME_HEADER Header;
3888 NVT_EXTENDED_METADATA_PACKET_INFOFRAME_PAYLOAD Data;
3889 } NVT_EXTENDED_METADATA_PACKET_INFOFRAME;
3890
3891 #define NVT_HDMI_EMP_BYTE1_RSVD_MASK 0x01
3892 #define NVT_HDMI_EMP_BYTE1_RSVD_SHIFT 0
3893
3894 #define NVT_HDMI_EMP_BYTE1_SYNC_MASK 0x02
3895 #define NVT_HDMI_EMP_BYTE1_SYNC_SHIFT 1
3896 #define NVT_HDMI_EMP_BYTE1_SYNC_DISABLE 0
3897 #define NVT_HDMI_EMP_BYTE1_SYNC_ENABLE 1
3898
3899 #define NVT_HDMI_EMP_BYTE1_VFR_MASK 0x04
3900 #define NVT_HDMI_EMP_BYTE1_VFR_SHIFT 2
3901 #define NVT_HDMI_EMP_BYTE1_VFR_DISABLE 0
3902 #define NVT_HDMI_EMP_BYTE1_VFR_ENABLE 1
3903
3904 #define NVT_HDMI_EMP_BYTE1_AFR_MASK 0x08
3905 #define NVT_HDMI_EMP_BYTE1_AFR_SHIFT 3
3906 #define NVT_HDMI_EMP_BYTE1_AFR_DISABLE 0
3907 #define NVT_HDMI_EMP_BYTE1_AFR_ENABLE 1
3908
3909 #define NVT_HDMI_EMP_BYTE1_DS_TYPE_MASK 0x30
3910 #define NVT_HDMI_EMP_BYTE1_DS_TYPE_SHIFT 4
3911 #define NVT_HDMI_EMP_BYTE1_DS_TYPE_PERIODIC_PSEUDO_STATIC 0
3912 #define NVT_HDMI_EMP_BYTE1_DS_TYPE_PERIODIC_DYNAMIC 1
3913 #define NVT_HDMI_EMP_BYTE1_DS_TYPE_UNIQUE 2
3914 #define NVT_HDMI_EMP_BYTE1_DS_TYPE_RSVD 3
3915
3916 #define NVT_HDMI_EMP_BYTE1_END_MASK 0x40
3917 #define NVT_HDMI_EMP_BYTE1_END_SHIFT 6
3918 #define NVT_HDMI_EMP_BYTE1_END_DISABLE 0
3919 #define NVT_HDMI_EMP_BYTE1_END_ENABLE 1
3920
3921 #define NVT_HDMI_EMP_BYTE1_NEW_MASK 0x80
3922 #define NVT_HDMI_EMP_BYTE1_NEW_SHIFT 7
3923 #define NVT_HDMI_EMP_BYTE1_NEW_DISABLE 0
3924 #define NVT_HDMI_EMP_BYTE1_NEW_ENABLE 1
3925
3926 #define NVT_HDMI_EMP_BYTE2_RSVD_MASK 0xff
3927 #define NVT_HDMI_EMP_BYTE2_RSVD_SHIFT 0
3928
3929 #define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_MASK 0xff
3930 #define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_SHIFT 0
3931 #define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_VENDOR_SPECIFIC 0
3932 #define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_SPEC_DEFINED 1
3933 #define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_CTA_DEFINED 2
3934 #define NVT_HDMI_EMP_BYTE3_ORGANIZATION_ID_VESA_DEFINED 3
3935
3936 #define NVT_HDMI_EMP_BYTE4_DATA_SET_TAG_MSB_MASK 0xff
3937 #define NVT_HDMI_EMP_BYTE4_DATA_SET_TAG_MSB_SHIFT 0
3938
3939 #define NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_MASK 0xff
3940 #define NVT_HDMI_EMP_BYTE5_DATA_SET_TAG_LSB_SHIFT 0
3941
3942 #define NVT_HDMI_EMP_BYTE6_DATA_SET_LENGTH_MSB_MASK 0xff
3943 #define NVT_HDMI_EMP_BYTE6_DATA_SET_LENGTH_MSB_SHIFT 0
3944
3945 #define NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_MASK 0xff
3946 #define NVT_HDMI_EMP_BYTE7_DATA_SET_LENGTH_LSB_SHIFT 0
3947
3948 #define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_MASK 0x01
3949 #define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_SHIFT 0
3950 #define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_DISABLE 0
3951 #define NVT_HDMI_EMP_BYTE8_MD0_VRR_EN_ENABLE 1
3952 #define NVT_HDMI_EMP_BYTE8_MD0_M_CONST_MASK 0x02
3953 #define NVT_HDMI_EMP_BYTE8_MD0_M_CONST_SHIFT 1
3954 #define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_MASK 0x04
3955 #define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_SHIFT 2
3956 #define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_DISABLE 0
3957 #define NVT_HDMI_EMP_BYTE8_MD0_QMS_EN_ENABLE 1
3958
3959 #define NVT_HDMI_EMP_BYTE8_MD1_BASE_VFRONT_MASK 0xff
3960 #define NVT_HDMI_EMP_BYTE8_MD1_BASE_VFRONT_SHIFT 0
3961
3962 #define NVT_HDMI_EMP_BYTE8_MD2_RB_MASK 0x04
3963 #define NVT_HDMI_EMP_BYTE8_MD2_RB_SHIFT 2
3964 #define NVT_HDMI_EMP_BYTE8_MD2_RB_DISABLE 0
3965 #define NVT_HDMI_EMP_BYTE8_MD2_RB_ENABLE 1
3966
3967 #define NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_MASK 0xf8
3968 #define NVT_HDMI_EMP_BYTE8_MD2_NEXT_TFR_SHIFT 3
3969
3970 #define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_MASK 0x03
3971 #define NVT_HDMI_EMP_BYTE8_MD2_BASE_RR_MSB_SHIFT 0
3972
3973 #define NVT_HDMI_EMP_BYTE8_MD3_BASE_RR_LSB_MASK 0xff
3974 #define NVT_HDMI_EMP_BYTE8_MD3_BASE_RR_LSB_SHIFT 0
3975
3976 #define NVT_DP_ADAPTIVE_SYNC_SDP_PACKET_TYPE 0x22
3977 #define NVT_DP_ADAPTIVE_SYNC_SDP_VERSION 0x2
3978 #define NVT_DP_ADAPTIVE_SYNC_SDP_LENGTH 0x9
3979 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_MASK 0x3
3980 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_SHIFT 0
3981 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_AVT_VARIABLE 0
3982 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_AVT_FIXED 1
3983 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_FAVT_TARGET_NOT_REACHED 2
3984 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_VARIABLE_FRAME_RATE_FAVT_TARGET_REACHED 3
3985
3986 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_MASK 0x4
3987 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_SHIFT 2
3988 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_SOURCE_SINK_SYNC_ENABLED 0
3989 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_SOURCE_SINK_SYNC_DISABLED 1
3990
3991 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_MASK 0x8
3992 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_SHIFT 3
3993 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_NO_UPDATE 0
3994 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_DISABLE_PR_ACTIVE_RFB_UPDATE_UPDATE 1
3995
3996 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_RSVD_MASK 0xf0
3997 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB0_RSVD_SHIFT 4
3998
3999 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_LSB_MASK 0xff
4000 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_LSB_SHIFT 0
4001
4002 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB2_MIN_VTOTAL_MSB_MASK 0xff
4003 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB2_MIN_VTOTAL_MSB_SHIFT 0
4004
4005 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_MASK 0xff
4006 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB3_TARGET_RR_LSB_SHIFT 0
4007
4008 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_MASK 0x01
4009 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_MSB_SHIFT 0
4010
4011 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_RSVD_MASK 0x1c
4012 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_RSVD_SHIFT 2
4013
4014 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_MASK 0x20
4015 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_SHIFT 5
4016 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_DISABLE 0
4017 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_TARGET_RR_DIVIDER_ENABLE 1
4018
4019 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_MASK 0x40
4020 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_SHIFT 6
4021 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_DISABLE 0
4022 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_INC_ENABLE 1
4023
4024 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_MASK 0x80
4025 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_SHIFT 7
4026 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_DISABLE 0
4027 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB4_SUCCESSIVE_FRAME_DEC_ENABLE 1
4028
4029 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB5_DURATION_INCREASE_CONSTRAINT_LSB_MASK 0xff
4030 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB5_DURATION_INCREASE_CONSTRAINT_LSB_SHIFT 0
4031
4032 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB6_DURATION_INCREASE_CONSTRAINT_MSB_MASK 0xff
4033 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB6_DURATION_INCREASE_CONSTRAINT_MSB_SHIFT 0
4034
4035 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB7_PR_COASTING_VTOTAL_LSB_MASK 0xff
4036 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB7_PR_COASTING_VTOTAL_LSB_SHIFT 0
4037
4038 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB8_PR_COASTING_VTOTAL_MSB_MASK 0xff
4039 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB8_PR_COASTING_VTOTAL_MSB_SHIFT 0
4040
4041 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_BYTE2_MASK 0xff
4042 #define NVT_DP_ADAPTIVE_SYNC_SDP_DB1_MIN_VTOTAL_BYTE2_SHIFT 0
4043
4044 typedef struct tagNVT_ADAPTIVE_SYNC_SDP_HEADER
4045 {
4046 NvU8 hb0;
4047 NvU8 type;
4048 NvU8 version;
4049 NvU8 length;
4050 }NVT_ADAPTIVE_SYNC_SDP_HEADER;
4051
4052 typedef struct tagNVT_ADAPTIVE_SYNC_SDP_PAYLOAD
4053 {
4054 NvU8 db0; // operatingMode
4055 NvU8 db1; // minVTotalLSB
4056 NvU8 db2; // minVTotalMSB
4057 NvU8 db3; // targetRefreshRateLSB
4058 NvU8 db4; // targetRefreshRateMSB, rsvd, targetRRDivider, frameInc/Dec Config
4059 NvU8 db5; // frameDurationIncMs
4060 NvU8 db6; // frameDurationDecreaseMs
4061 NvU8 db7; // coastingVTotalPrLSB
4062 NvU8 db8; // coastingVTotalPrMSB
4063
4064 NvU8 rsvd[23];
4065 }NVT_ADAPTIVE_SYNC_SDP_PAYLOAD;
4066
4067 typedef struct tagADAPTIVE_SYNC_SDP
4068 {
4069 NVT_ADAPTIVE_SYNC_SDP_HEADER header;
4070 NVT_ADAPTIVE_SYNC_SDP_PAYLOAD payload;
4071 }NVT_ADAPTIVE_SYNC_SDP;
4072
4073 // the Vendor-Specific-Data-Block header
4074 typedef struct tagNVT_CEA861_VSDB_HEADER
4075 {
4076 // byte 0
4077 NvU32 length : 5;
4078 NvU32 vendorSpecificTag : 3;
4079 // byte 1-3
4080 NvU32 ieee_id : 24;
4081
4082 } NVT_CEA861_VSDB_HEADER;
4083
4084 // HDMI LLC Vendor-Specific data block
4085 // from HDMI 1.4 spec (superset of VSDB from HDMI 1.3a spec)
4086 typedef struct tagNVT_CEA861_LATENCY
4087 {
4088 NvU8 Video_Latency;
4089 NvU8 Audio_Latency;
4090
4091 } NVT_CEA861_LATENCY;
4092
4093 typedef struct tagNVT_HDMI_VIDEO
4094 {
4095 NvU8 Rsvd_1 : 3;
4096 NvU8 ImageSize : 2;
4097 NvU8 ThreeD_Multi_Present : 2;
4098 NvU8 ThreeD_Present : 1;
4099 NvU8 HDMI_3D_Len : 5;
4100 NvU8 HDMI_VIC_Len : 3;
4101 } NVT_HDMI_VIDEO;
4102
4103 typedef struct tagNVT_HDMI_VIC_LIST
4104 {
4105 NvU8 HDMI_VIC[1]; // note: list length is actually specified in HDMI_VIC_Len
4106 } NVT_HDMI_VIC_LIST;
4107
4108 typedef struct tagNVT_3D_STRUCT_ALL
4109 {
4110 NvU8 ThreeDStructALL0_FramePacking : 1;
4111 NvU8 ThreeDStructALL1_FieldAlt : 1;
4112 NvU8 ThreeDStructALL2_LineAlt : 1;
4113 NvU8 ThreeDStructALL3_SSFull : 1;
4114 NvU8 ThreeDStructALL4_LDepth : 1;
4115 NvU8 ThreeDStructALL5_LDepthGFX : 1;
4116 NvU8 ThreeDStructALL6_TopBottom : 1;
4117 NvU8 ThreeDStructALL7 : 1;
4118 NvU8 ThreeDStructALL8_SSHalf : 1;
4119 NvU8 Rsvd_1 : 7;
4120 } NVT_3D_STRUCT_ALL;
4121
4122 typedef struct tagNVT_3D_MULTI_LIST
4123 {
4124 NvU8 ThreeD_Structure : 4;
4125 NvU8 TwoD_VIC_order : 4;
4126 NvU8 Rsvd_2 : 4;
4127 NvU8 ThreeD_Detail : 4;
4128 } NVT_3D_MULTI_LIST;
4129
4130 #define NVT_3D_DETAILS_ALL 0x00
4131 #define NVT_3D_DETAILS_ALL_HORIZONTAL 0x01
4132 #define NVT_3D_DETAILS_HORIZONTAL_ODD_LEFT_ODD_RIGHT 0x02
4133 #define NVT_3D_DETAILS_HORIZONTAL_ODD_LEFT_EVEN_RIGHT 0x03
4134 #define NVT_3D_DETAILS_HORIZONTAL_EVEN_LEFT_ODD_RIGHT 0x04
4135 #define NVT_3D_DETAILS_HORIZONTAL_EVEN_LEFT_EVEN_RIGHT 0x05
4136 #define NVT_3D_DETAILS_ALL_QUINCUNX 0x06
4137 #define NVT_3D_DETAILS_QUINCUNX_ODD_LEFT_ODD_RIGHT 0x07
4138 #define NVT_3D_DETAILS_QUINCUNX_ODD_LEFT_EVEN_RIGHT 0x08
4139 #define NVT_3D_DETAILS_QUINCUNX_EVEN_LEFT_ODD_RIGHT 0x09
4140 #define NVT_3D_DETAILS_QUINCUNX_EVEN_LEFT_EVEN_RIGHT 0x0a
4141
4142 typedef struct tagNVT_HDMI_LLC_VSDB_PAYLOAD
4143 {
4144 // 1st byte
4145 NvU8 B : 4;
4146 NvU8 A : 4;
4147 // 2nd byte
4148 NvU8 D : 4;
4149 NvU8 C : 4;
4150 // 3rd byte
4151 NvU8 DVI_Dual : 1;
4152 NvU8 Rsvd_3 : 2;
4153 NvU8 DC_Y444 : 1;
4154 NvU8 DC_30bit : 1;
4155 NvU8 DC_36bit : 1;
4156 NvU8 DC_48bit : 1;
4157 NvU8 Supports_AI : 1;
4158 // 4th byte
4159 NvU8 Max_TMDS_Clock;
4160 // 5th byte
4161 NvU8 CNC0 : 1;
4162 NvU8 CNC1 : 1;
4163 NvU8 CNC2 : 1;
4164 NvU8 CNC3 : 1;
4165 NvU8 Rsvd_5 : 1;
4166 NvU8 HDMI_Video_present : 1;
4167 NvU8 I_Latency_Fields_Present : 1;
4168 NvU8 Latency_Fields_Present : 1;
4169
4170 // the rest of the frame may contain optional data as defined
4171 // in the NVT_CEA861_LATENCY, HDMI_VIDEO, HDMI_VIC, NVT_3D_STRUCT_ALL & 3D_MULTI_LIST structures
4172 // and as specified by the corresponding control bits
4173 NvU8 Data[NVT_CEA861_VSDB_PAYLOAD_MAX_LENGTH - 5];
4174
4175 } NVT_HDMI_LLC_VSDB_PAYLOAD;
4176
4177 // HDMI LLC Vendor Specific Data Block
4178 typedef struct tagNVT_HDMI_LLC_DATA
4179 {
4180 NVT_CEA861_VSDB_HEADER header;
4181 NVT_HDMI_LLC_VSDB_PAYLOAD payload;
4182 } NVT_HDMI_LLC_DATA;
4183
4184 typedef struct tagNVT_NVDA_VSDB_PAYLOAD
4185 {
4186 NvU8 opcode; // Nvidia specific opcode - please refer to VRR monitor spec v5
4187 NvU8 vrrMinRefreshRate; // Minimum refresh rate supported by this monitor
4188 } NVT_NVDA_VSDB_PAYLOAD;
4189
4190 // NVIDIA Vendor Specific Data Block
4191 typedef struct tagNVT_NVDA_VSDB_DATA
4192 {
4193 NVT_CEA861_VSDB_HEADER header;
4194 NVT_NVDA_VSDB_PAYLOAD payload;
4195 } NVT_NVDA_VSDB_DATA;
4196
4197 typedef struct _NVT_MSFT_VSDB_PAYLOAD
4198 {
4199 NvU8 version;
4200 NvU8 primaryUseCase : 5;
4201 NvU8 thirdPartyUsage : 1;
4202 NvU8 desktopUsage : 1;
4203 NvU8 reserved : 1;
4204 NvU8 containerId[MSFT_VSDB_CONTAINER_ID_SIZE];
4205 } NVT_MSFT_VSDB_PAYLOAD;
4206
4207 typedef struct _NVT_MSFT_VSDB_DATA
4208 {
4209 NVT_CEA861_VSDB_HEADER header;
4210 NVT_MSFT_VSDB_PAYLOAD payload;
4211 } NVT_MSFT_VSDB_DATA;
4212
4213 #define NVT_MSFT_VSDB_BLOCK_SIZE (sizeof(NVT_MSFT_VSDB_DATA))
4214
4215 typedef struct tagNVT_HDMI_FORUM_VSDB_PAYLOAD
4216 {
4217 // first byte
4218 NvU8 Version;
4219 // second byte
4220 NvU8 Max_TMDS_Character_Rate;
4221 // third byte
4222 NvU8 ThreeD_Osd_Disparity : 1;
4223 NvU8 Dual_View : 1;
4224 NvU8 Independent_View : 1;
4225 NvU8 Lte_340mcsc_Scramble : 1;
4226 NvU8 CCBPCI : 1;
4227 NvU8 CABLE_STATUS : 1;
4228 NvU8 RR_Capable : 1;
4229 NvU8 SCDC_Present : 1;
4230 // fourth byte
4231 NvU8 DC_30bit_420 : 1;
4232 NvU8 DC_36bit_420 : 1;
4233 NvU8 DC_48bit_420 : 1;
4234 NvU8 UHD_VIC : 1;
4235 NvU8 Max_FRL_Rate : 4;
4236 // fifth byte
4237 NvU8 FAPA_start_location : 1;
4238 NvU8 ALLM : 1;
4239 NvU8 FVA : 1;
4240 NvU8 CNMVRR : 1;
4241 NvU8 CinemaVRR : 1;
4242 NvU8 M_delta : 1;
4243 NvU8 QMS : 1;
4244 NvU8 FAPA_End_Extended : 1;
4245
4246 // sixth byte
4247 NvU8 VRR_min : 6;
4248 NvU8 VRR_max_high : 2;
4249 // seventh byte
4250 NvU8 VRR_max_low : 8;
4251 // eighth byte
4252 NvU8 DSC_10bpc : 1;
4253 NvU8 DSC_12bpc : 1;
4254 NvU8 DSC_16bpc : 1;
4255 NvU8 DSC_All_bpp : 1;
4256 NvU8 QMS_TFR_min : 1;
4257 NvU8 QMS_TFR_max : 1;
4258 NvU8 DSC_Native_420 : 1;
4259 NvU8 DSC_1p2 : 1;
4260 // ninth byte
4261 NvU8 DSC_MaxSlices : 4;
4262 NvU8 DSC_Max_FRL_Rate : 4;
4263 // tenth byte
4264 NvU8 DSC_totalChunkKBytes : 6;
4265 NvU8 Rsvd_4 : 2;
4266 } NVT_HDMI_FORUM_VSDB_PAYLOAD;
4267
4268 // HDMI Forum Vendor Specific Data Block
4269 typedef struct tagNVT_HDMI_FORUM_DATA
4270 {
4271 NVT_CEA861_VSDB_HEADER header;
4272 NVT_HDMI_FORUM_VSDB_PAYLOAD payload;
4273 } NVT_HDMI_FORUM_DATA;
4274
4275 //
4276 //
4277 // Video Capability Data Block (VCDB)
4278 typedef struct _NV_ESC_MONITOR_CAPS_VCDB
4279 {
4280 NvU8 quantizationRangeYcc : 1;
4281 NvU8 quantizationRangeRgb : 1;
4282 NvU8 scanInfoPreferredVideoFormat : 2;
4283 NvU8 scanInfoITVideoFormats : 2;
4284 NvU8 scanInfoCEVideoFormats : 2;
4285 } NVT_HDMI_VCDB_DATA;
4286
4287 //
4288 //
4289 //***********************************************************
4290 // Dynamic Range and Mastering Infoframe (HDR)
4291 //***********************************************************
4292 //
4293 typedef struct tagNVT_HDR_INFOFRAME_MASTERING_DATA
4294 {
4295 NvU16 displayPrimary_x0; //!< x coordinate of color primary 0 (e.g. Red) of mastering display ([0x0000-0xC350] = [0.0 - 1.0])
4296 NvU16 displayPrimary_y0; //!< y coordinate of color primary 0 (e.g. Red) of mastering display ([0x0000-0xC350] = [0.0 - 1.0])
4297
4298 NvU16 displayPrimary_x1; //!< x coordinate of color primary 1 (e.g. Green) of mastering display ([0x0000-0xC350] = [0.0 - 1.0])
4299 NvU16 displayPrimary_y1; //!< y coordinate of color primary 1 (e.g. Green) of mastering display ([0x0000-0xC350] = [0.0 - 1.0])
4300
4301 NvU16 displayPrimary_x2; //!< x coordinate of color primary 2 (e.g. Blue) of mastering display ([0x0000-0xC350] = [0.0 - 1.0])
4302 NvU16 displayPrimary_y2; //!< y coordinate of color primary 2 (e.g. Blue) of mastering display ([0x0000-0xC350] = [0.0 - 1.0])
4303
4304 NvU16 displayWhitePoint_x; //!< x coordinate of white point of mastering display ([0x0000-0xC350] = [0.0 - 1.0])
4305 NvU16 displayWhitePoint_y; //!< y coordinate of white point of mastering display ([0x0000-0xC350] = [0.0 - 1.0])
4306
4307 NvU16 max_display_mastering_luminance; //!< Maximum display mastering luminance ([0x0001-0xFFFF] = [1.0 - 65535.0] cd/m^2)
4308 NvU16 min_display_mastering_luminance; //!< Minimum display mastering luminance ([0x0001-0xFFFF] = [1.0 - 6.55350] cd/m^2)
4309
4310 NvU16 max_content_light_level; //!< Maximum Content Light level (MaxCLL) ([0x0001-0xFFFF] = [1.0 - 65535.0] cd/m^2)
4311 NvU16 max_frame_average_light_level; //!< Maximum Frame-Average Light Level (MaxFALL) ([0x0001-0xFFFF] = [1.0 - 65535.0] cd/m^2)
4312 } NVT_HDR_INFOFRAME_MASTERING_DATA;
4313
4314 #define NVT_CEA861_HDR_INFOFRAME_EOTF_SDR_GAMMA 0 //SDR Luminance Range
4315 #define NVT_CEA861_HDR_INFOFRAME_EOTF_HDR_GAMMA 1 //HDR Luminance Range
4316 #define NVT_CEA861_HDR_INFOFRAME_EOTF_ST2084 2
4317 #define NVT_CEA861_HDR_INFOFRAME_EOTF_Future 3
4318 #define NVT_CEA861_STATIC_METADATA_TYPE1_PRIMARY_COLOR_NORMALIZE_FACTOR 0xC350 // Per CEA-861.3 spec
4319
4320 typedef struct tagNVT_HDR_INFOFRAME_PAYLOAD
4321 {
4322 //byte 1
4323 NvU8 eotf : 3;
4324 NvU8 f13_17 : 5; // These bits are reserved for future use
4325 //byte 2
4326 NvU8 static_metadata_desc_id : 3;
4327 NvU8 f23_27 : 5; // These bits are reserved for future use
4328
4329 NVT_HDR_INFOFRAME_MASTERING_DATA type1;
4330 } NVT_HDR_INFOFRAME_PAYLOAD;
4331
4332 #pragma pack(1)
4333 typedef struct tagNVT_HDR_INFOFRAME
4334 {
4335 NVT_INFOFRAME_HEADER header;
4336 NVT_HDR_INFOFRAME_PAYLOAD payload;
4337 } NVT_HDR_INFOFRAME;
4338 #pragma pack()
4339
4340 //
4341 //
4342 //***********************************************************
4343 // Gamut Metadata Range and Vertices structures
4344 //***********************************************************
4345 //
4346 // GBD structure formats
4347 //
4348 #define NVT_GAMUT_FORMAT_VERTICES 0
4349 #define NVT_GAMUT_FORMAT_RANGE 1
4350
4351 typedef struct tagNVT_GAMUT_HEADER
4352 {
4353 NvU8 type:8;
4354
4355 // byte 1
4356 NvU8 AGSNum:4;
4357 NvU8 GBD_profile:3;
4358 NvU8 Next_Field:1;
4359
4360 // byte 2
4361 NvU8 CGSNum:4;
4362 NvU8 Packet_Seq:2;
4363 NvU8 Rsvd:1;
4364 NvU8 No_Cmt_GBD:1;
4365
4366 } NVT_GAMUT_HEADER;
4367
4368 typedef struct tagNVT_GAMUT_METADATA_RANGE_8BIT{
4369
4370 // Header
4371 NvU8 GBD_Color_Space:3;
4372 NvU8 GBD_Color_Precision:2;
4373 NvU8 Rsvd:2;
4374 NvU8 Format_Flag:1;
4375
4376 // Packaged data
4377 NvU8 Min_Red_Data:8;
4378 NvU8 Max_Red_Data:8;
4379 NvU8 Min_Green_Data:8;
4380 NvU8 Max_Green_Data:8;
4381 NvU8 Min_Blue_Data:8;
4382 NvU8 Max_Blue_Data:8;
4383 } NVT_GAMUT_METADATA_RANGE_8BIT;
4384
4385 typedef struct tagNVT_GAMUT_METADATA_RANGE_10BIT{
4386
4387 // Header
4388 NvU8 GBD_Color_Space:3;
4389 NvU8 GBD_Color_Precision:2;
4390 NvU8 Rsvd:2;
4391 NvU8 Format_Flag:1;
4392
4393 // Packaged data
4394 NvU8 Min_Red_Data_HI:8;
4395
4396 NvU8 Max_Red_Data_HI:6;
4397 NvU8 Min_Red_Data_LO:2;
4398
4399 NvU8 Min_Green_Data_HI:4;
4400 NvU8 Max_Red_Data_LO:4;
4401
4402 NvU8 Max_Green_Data_HI:2;
4403 NvU8 Min_Green_Data_LO:6;
4404
4405 NvU8 Max_Green_Data_LO:8;
4406
4407 NvU8 Min_Blue_Data_HI:8;
4408
4409 NvU8 Max_Blue_Data_HI:6;
4410 NvU8 Min_Blue_Data_LO:2;
4411
4412 NvU8 Data_Rsvd:4;
4413 NvU8 Max_Blue_Data_LO:4;
4414
4415 } NVT_GAMUT_METADATA_RANGE_10BIT;
4416
4417 typedef struct tagNVT_GAMUT_METADATA_RANGE_12BIT{
4418
4419 // Header
4420 NvU8 GBD_Color_Space:3;
4421 NvU8 GBD_Color_Precision:2;
4422 NvU8 Rsvd:2;
4423 NvU8 Format_Flag:1;
4424
4425 // Packaged data
4426 NvU8 Min_Red_Data_HI:8;
4427
4428 NvU8 Max_Red_Data_HI:4;
4429 NvU8 Min_Red_Data_LO:4;
4430
4431 NvU8 Max_Red_Data_LO:8;
4432
4433 NvU8 Min_Green_Data_HI:8;
4434
4435 NvU8 Max_Green_Data_HI:4;
4436 NvU8 Min_Green_Data_LO:4;
4437
4438 NvU8 Max_Green_Data_LO:8;
4439
4440 NvU8 Min_Blue_Data_HI:8;
4441
4442 NvU8 Max_Blue_Data_HI:4;
4443 NvU8 Min_Blue_Data_LO:4;
4444
4445 NvU8 Max_Blue_Data_LO:8;
4446
4447 } NVT_GAMUT_METADATA_RANGE_12BIT;
4448
4449 typedef struct tagNVT_GAMUT_METADATA_VERTICES_8BIT
4450 {
4451 // Header
4452 NvU8 GBD_Color_Space:3;
4453 NvU8 GBD_Color_Precision:2;
4454 NvU8 Rsvd:1;
4455 NvU8 Facet_Mode:1; // Must be set to 0
4456 NvU8 Format_Flag:1; // Must be set to 0
4457 NvU8 Number_Vertices_H:8; // Must be set to 0
4458 NvU8 Number_Vertices_L:8; // Must be set to 4
4459
4460 // Packaged data
4461 NvU8 Black_Y_R;
4462 NvU8 Black_Cb_G;
4463 NvU8 Black_Cr_B;
4464 NvU8 Red_Y_R;
4465 NvU8 Red_Cb_G;
4466 NvU8 Red_Cr_B;
4467 NvU8 Green_Y_R;
4468 NvU8 Green_Cb_G;
4469 NvU8 Green_Cr_B;
4470 NvU8 Blue_Y_R;
4471 NvU8 Blue_Cb_G;
4472 NvU8 Blue_Cr_B;
4473 } NVT_GAMUT_METADATA_VERTICES_8BIT;
4474
4475 typedef struct tagNVT_GAMUT_METADATA_VERTICES_10BIT
4476 {
4477 // Header
4478 NvU8 GBD_Color_Space:3;
4479 NvU8 GBD_Color_Precision:2;
4480 NvU8 Rsvd:1;
4481 NvU8 Facet_Mode:1; // Must be set to 0
4482 NvU8 Format_Flag:1; // Must be set to 0
4483 NvU8 Number_Vertices_H:8; // Must be set to 0
4484 NvU8 Number_Vertices_L:8; // Must be set to 4
4485
4486 // Packaged data
4487 NvU8 Black_Y_R_HI;
4488
4489 NvU8 Black_Cb_G_HI:6;
4490 NvU8 Black_Y_R_LO:2;
4491
4492 NvU8 Black_Cr_B_HI:4;
4493 NvU8 Black_Cb_G_LO:4;
4494
4495 NvU8 Red_Y_R_HI:2;
4496 NvU8 Black_Cr_B_LO:6;
4497
4498 NvU8 Red_Y_R_LO;
4499
4500 NvU8 Red_Cb_G_HI;
4501
4502 NvU8 Red_Cr_B_HI:6;
4503 NvU8 Red_Cb_G_LO:2;
4504
4505 NvU8 Green_Y_R_HI:4;
4506 NvU8 Red_Cr_B_LO:4;
4507
4508 NvU8 Green_Cb_G_HI:2;
4509 NvU8 Green_Y_R_LO:6;
4510
4511 NvU8 Green_Cb_G_LO;
4512
4513 NvU8 Green_Cr_B_HI;
4514
4515 NvU8 Blue_Y_R_HI:6;
4516 NvU8 Green_Cr_B_LO:2;
4517
4518 NvU8 Blue_Cb_G_HI:4;
4519 NvU8 Blue_Y_R_LO:4;
4520
4521 NvU8 Blue_Cr_B_HI:2;
4522 NvU8 Blue_Cb_G_LO:6;
4523
4524 NvU8 Blue_Cr_B_LO;
4525 } NVT_GAMUT_METADATA_VERTICES_10BIT;
4526
4527 typedef struct tagNVT_GAMUT_METADATA_VERTICES_12BIT
4528 {
4529 // Header
4530 NvU8 GBD_Color_Space:3;
4531 NvU8 GBD_Color_Precision:2;
4532 NvU8 Rsvd:1;
4533 NvU8 Facet_Mode:1; // Must be set to 0
4534 NvU8 Format_Flag:1; // Must be set to 0
4535 NvU8 Number_Vertices_H:8; // Must be set to 0
4536 NvU8 Number_Vertices_L:8; // Must be set to 4
4537
4538 // Packaged data
4539 NvU8 Black_Y_R_HI;
4540
4541 NvU8 Black_Cb_G_HI:4;
4542 NvU8 Black_Y_R_LO:4;
4543
4544 NvU8 Black_Cb_G_LO;
4545
4546 NvU8 Black_Cr_B_HI;
4547
4548 NvU8 Red_Y_R_HI:4;
4549 NvU8 Black_Cr_B_LO:4;
4550
4551 NvU8 Red_Y_R_LO;
4552
4553 NvU8 Red_Cb_G_HI;
4554
4555 NvU8 Red_Cr_B_HI:4;
4556 NvU8 Red_Cb_G_LO:4;
4557
4558 NvU8 Red_Cr_B_LO;
4559
4560 NvU8 Green_Y_R_HI;
4561
4562 NvU8 Green_Cb_G_HI:4;
4563 NvU8 Green_Y_R_LO:4;
4564
4565 NvU8 Green_Cb_G_LO;
4566
4567 NvU8 Green_Cr_B_HI;
4568
4569 NvU8 Blue_Y_R_HI:4;
4570 NvU8 Green_Cr_B_LO:4;
4571
4572 NvU8 Blue_Y_R_LO;
4573
4574 NvU8 Blue_Cb_G_HI;
4575
4576 NvU8 Blue_Cr_B_HI:4;
4577 NvU8 Blue_Cb_G_LO:4;
4578
4579 NvU8 Blue_Cr_B_LO;
4580 } NVT_GAMUT_METADATA_VERTICES_12BIT;
4581
4582 typedef struct tagNVT_GAMUT_METADATA
4583 {
4584 NVT_GAMUT_HEADER header;
4585
4586 union
4587 {
4588 NVT_GAMUT_METADATA_RANGE_8BIT range8Bit;
4589 NVT_GAMUT_METADATA_RANGE_10BIT range10Bit;
4590 NVT_GAMUT_METADATA_RANGE_12BIT range12Bit;
4591 NVT_GAMUT_METADATA_VERTICES_8BIT vertices8bit;
4592 NVT_GAMUT_METADATA_VERTICES_10BIT vertices10bit;
4593 NVT_GAMUT_METADATA_VERTICES_12BIT vertices12bit;
4594 }payload;
4595
4596 }NVT_GAMUT_METADATA;
4597 //
4598 //***********************************
4599 // Display Port Configuration Data
4600 //***********************************
4601 //
4602 // DPCD field offset
4603 #define NVT_DPCD_ADDRESS_RECEIVER_CAPABILITY_FIELD 0x00000
4604 #define NVT_DPCD_ADDRESS_LINK_CONFIG_FIELD 0x00100
4605 #define NVT_DPCD_ADDRESS_MSTM_CTRL_FIELD 0x00111 //DPMST Control MST <-> ST
4606 #define NVT_DPCD_ADDRESS_MSTM_BRANCH_DEVICE 0x001A1
4607 #define NVT_DPCD_ADDRESS_LINK_SINK_STATUS_FIELD 0x00200
4608 #define NVT_DPCD_ADDRESS_VENDOR_SPECIFIC_SOURCE_DEVICE 0x00300
4609 #define NVT_DPCD_ADDRESS_VENDOR_SPECIFIC_SINK_DEVICE 0x00400
4610 #define NVT_DPCD_ADDRESS_VENDOR_SPECIFIC_BRANCH_DEVICE 0x00500
4611 #define NVT_DPCD_ADDRESS_SINK_CTRL_FIELD 0x00600
4612 #define NVT_DPCD_ADDRESS_DOWN_REQ_BUFFER_FIELD 0x01000
4613 #define NVT_DPCD_ADDRESS_UP_REP_BUFFER_FIELD 0x01200
4614 #define NVT_DPCD_ADDRESS_DOWN_REP_BUFFER_FIELD 0x01400
4615 #define NVT_DPCD_ADDRESS_UP_REQ_BUFFER_FIELD 0x01600
4616 #define NVT_DPCD_ADDRESS_DEVICE_SERVICE_IRQ_VECTOR_ESI0 0x02003
4617 #define NVT_DPCD_ADDRESS_DP_TUNNELING_DEVICE_IEEE_OUI 0xE0000
4618 #define NVT_DPCD_ADDRESS_DP_TUNNELING_DEVICE_ID_STRING 0xE0003
4619 #define NVT_DPCD_ADDRESS_DP_TUNNELING_CAPS_SUPPORT_FIELD 0xE000D
4620 #define NVT_DPCD_ADDRESS_DP_IN_ADAPTER_INFO_FIELD 0xE000E
4621 #define NVT_DPCD_ADDRESS_USB4_DRIVER_ID_FIELD 0xE000F
4622 #define NVT_DPCD_ADDRESS_USB4_ROUTER_TOPOLOGY_ID_FIELD 0xE001B
4623
4624 //
4625 // Raw DPCD data format - Receiver Capability Field // 00000h - 000FFh
4626 typedef struct tagNVT_DPCD_RECEIVER_CAP
4627 {
4628 NvU8 rev; // 00000h
4629 NvU8 max_link_rate; // 00001h
4630 NvU8 max_lane_count; // 00002h
4631 NvU8 max_downspread; // 00003h
4632 NvU8 norp; // 00004h
4633 NvU8 downstream_port_present; // 00005h
4634 NvU8 main_link_ch_coding; // 00006h
4635 NvU8 down_stream_port_count; // 00007h
4636 NvU8 receive_port0_cap_0; // 00008h
4637 NvU8 receive_port0_cap_1; // 00009h
4638 NvU8 receive_port1_cap_0; // 0000Ah
4639 NvU8 receive_port1_cap_1; // 0000Bh
4640 NvU8 reserved_0[0x7F - 0xC + 1]; // 0000Ch - 0007Fh
4641 NvU8 down_strm_port0_cap[0x8F - 0x80 + 1]; // 00080h - 0008Fh
4642 //NvU8 reserved_1[0xFF - 0x90 + 1]; // 00090h - 000FFh
4643 }NVT_DPCD_RECEIVER_CAP;
4644
4645 //
4646 // Raw DPCD data format - Link Configuration Field // 00100h - 001FFh
4647 typedef struct tagNVT_DPCD_LINK_CFG
4648 {
4649 NvU8 link_bw_set; // 00100h
4650 NvU8 lane_count_set; // 00101h
4651 NvU8 training_pattern_set; // 00102h
4652 NvU8 training_lane0_set; // 00103h
4653 NvU8 training_lane1_set; // 00104h
4654 NvU8 training_lane2_set; // 00105h
4655 NvU8 training_lane3_set; // 00106h
4656 NvU8 downspread_ctrl; // 00107h
4657 NvU8 main_link_ch_coding_set; // 00108h
4658 NvU8 reserved_0[0x110 - 0x109 + 1]; // 00110h - 00109h
4659 NvU8 mstm_ctrl; // 00111h
4660 // NvU8 reserved_0[0x1FF - 0x111 + 1];
4661 }NVT_DPCD_LINK_CFG;
4662 //
4663 // Raw DPCD data format - Link/Sink Status Field // 00200h - 002FFh
4664 typedef struct tagNVT_DPCD_LINK_SINK_STATUS
4665 {
4666 NvU8 sink_count; // 00200h
4667 NvU8 device_service_irq_vector; // 00201h
4668 NvU8 lane0_1_status; // 00202h
4669 NvU8 lane2_3_status; // 00203h
4670 NvU8 lane_align_status_update; // 00204h
4671 NvU8 sink_status; // 00205h
4672 NvU8 adjust_req_lane0_1; // 00206h
4673 NvU8 adjust_req_lane2_3; // 00207h
4674 NvU8 training_score_lane0; // 00208h
4675 NvU8 training_score_lane1; // 00209h
4676 NvU8 training_score_lane2; // 0020Ah
4677 NvU8 training_score_lane3; // 0020Bh
4678 NvU8 reserved_0[0x20F - 0x20C + 1]; // 0020Fh - 0020Ch
4679 NvU16 sym_err_count_lane0; // 00210h - 00211h
4680 NvU16 sym_err_count_lane1; // 00212h - 00213h
4681 NvU16 sym_err_count_lane2; // 00214h - 00215h
4682 NvU16 sym_err_count_lane3; // 00217h - 00216h
4683 NvU8 test_req; // 00218h
4684 NvU8 test_link_rate; // 00219h
4685 NvU8 reserved_1[0x21F - 0x21A + 1]; // 0021Fh - 0021Ah
4686 NvU8 test_lane_count; // 00220h
4687 NvU8 test_pattern; // 00221h
4688 NvU16 test_h_total; // 00222h - 00223h
4689 NvU16 test_v_total; // 00224h - 00225h
4690 NvU16 test_h_start; // 00226h - 00227h
4691 NvU16 test_v_start; // 00228h - 00229h
4692 NvU16 test_hsync; // 0022Ah - 0022Bh
4693 NvU16 test_vsync; // 0022Ch - 0022Dh
4694 NvU16 test_h_width; // 0022Eh - 0022Fh
4695 NvU16 test_v_height; // 00230h - 00231h
4696 NvU16 test_misc; // 00232h - 00233h
4697 NvU8 test_refresh_rate_numerator; // 00234h
4698 NvU8 reserved_2[0x23F - 0x235 + 1]; // 00235h - 0023Fh
4699 NvU16 test_crc_R_Cr; // 00240h - 00241h
4700 NvU16 test_crc_G_Y; // 00242h - 00243h
4701 NvU16 test_crc_B_Cb; // 00244h - 00245h
4702 NvU8 test_sink_misc; // 00246h
4703 NvU8 reserved_3[0x25F - 0x247 + 1]; // 00247h - 0025fh
4704 NvU8 test_response; // 00260h
4705 NvU8 test_edid_checksum; // 00261h
4706 NvU8 reserved_4[0x26F - 0x262 + 1]; // 00262h - 0026Fh
4707 NvU8 test_sink; // 00270h
4708 //NvU8 reserved_5[0x27F - 0x271 + 1]; // 00271h - 0027Fh
4709 //NvU8 reserved_6[0x2FF - 0x280 + 1]; // 00280h - 002FFh
4710 }NVT_DPCD_LINK_SINK_STATUS;
4711
4712 #define NV_DPCD_DONGLE_NVIDIA_OUI 0x00044B
4713
4714 //
4715 // Raw DPCD data format - Vendor-Specific Field for Source Device // 00300h - 003FFh
4716 // Raw DPCD data format - Vendor-Specific Field for Sink Device // 00400h - 004FFh
4717 // Raw DPCD data format - Vendor-Specific Field for Branch Device // 00500h - 005FFh
4718 typedef struct tagNVT_DPCD_VENDOR_SPECIFIC_FIELD
4719 {
4720 NvU8 ieee_oui7_0; // 00300h
4721 NvU8 ieee_oui15_8; // 00301h
4722 NvU8 ieee_oui23_16; // 00302h
4723 //NvU8 reserved[0x3FF - 0x303 + 1]; // 003FFh - 00303h
4724 }NVT_DPCD_VENDOR_SPECIFIC_FIELD;
4725 //
4726 // Raw DPCD data format - Dongle Specific Field
4727 typedef struct tagNVT_DPCD_DONGLE_SPECIFIC_FIELD
4728 {
4729 NvU8 vendor_b0; // 00300h
4730 NvU8 vendor_b1; // 00301h
4731 NvU8 vendor_b2; // 00302h
4732 NvU8 model[6]; // 00303h - 00308h
4733 NvU8 chipIDVersion; // 00309h
4734 //NvU8 reserved[0x3FF - 0x30A + 1]; // 0030Ah - 005FFh
4735 }NVT_DPCD_DONGLE_SPECIFIC_FIELD;
4736 //
4737 // Raw DPCD data format - DualDP Specific Field
4738 typedef struct tagNVT_DPCD_DUALDP_SPECIFIC_FIELD
4739 {
4740 NvU8 vendor_b0; // 00300h
4741 NvU8 vendor_b1; // 00301h
4742 NvU8 vendor_b2; // 00302h
4743 NvU8 model[6]; // 00303h - 00308h
4744 NvU8 chipd_id_version; // 00309h
4745 NvU8 reserved_1[0x3AF - 0x30A + 1]; // 0030Ah - 003AFh
4746 NvU8 dual_dp_cap; // 003B0h
4747 NvU8 dual_dp_base_addr[3]; // 003B1h - 003B3h
4748 //NvU8 reserved_2[0x3FF - 0x3B4 + 1]; // 003B4h - 003FFh
4749 }NVT_DPCD_DUALDP_SPECIFIC_FIELD;
4750
4751 //
4752 // Raw DPCD data format - Sink Control Field // 00600h - 006FFh
4753 typedef struct tagNVT_DPCD_SINK_CTRL_FIELD
4754 {
4755 NvU8 set_power; // 00600h
4756 //NvU8 reserved[0x6FF - 0x601 + 1]; // 00601h - 006FFh
4757 }NVT_DPCD_SINK_CTRL_FIELD;
4758 //
4759 // The entire DPCD data block
4760 typedef struct tagNVT_DPCD
4761 {
4762 NVT_DPCD_RECEIVER_CAP receiver_cap;
4763 NVT_DPCD_LINK_CFG link_cfg;
4764 NVT_DPCD_LINK_SINK_STATUS link_status;
4765 NVT_DPCD_VENDOR_SPECIFIC_FIELD vsp_source_device;
4766 NVT_DPCD_VENDOR_SPECIFIC_FIELD vsp_sink_device;
4767 NVT_DPCD_VENDOR_SPECIFIC_FIELD vsp_branch_device;
4768 NVT_DPCD_SINK_CTRL_FIELD sink_ctrl;
4769 }NVT_DPCD;
4770 //
4771 //
4772 // Parsed DPCD info
4773 //
4774 //
4775 #define NVT_DPCD_REV_10 NVT_DPCD_DPCD_REV_10 // DPCD revision 1.0
4776 #define NVT_DPCD_REV_11 NVT_DPCD_DPCD_REV_11 // DPCD revision 1.1
4777 #define NVT_DPCD_REV_12 NVT_DPCD_DPCD_REV_12 // DPCD revision 1.2
4778 #define NVT_DPCD_RECEIVER_MAX_DOWNSTREAM_PORT 16 // the max downstream port possible per device
4779 #define NVT_DPCD_RECEIVER_DOWNSTREAM_PORT_TYPE_DP NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_TYPE_DISPLAYPORT // Display Port
4780 #define NVT_DPCD_RECEIVER_DOWNSTREAM_PORT_TYPE_VGA NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_TYPE_VGA // analog VGA or analog video over DVI-I
4781 #define NVT_DPCD_RECEIVER_DOWNSTREAM_PORT_TYPE_DVI NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_TYPE_DVI // DVI
4782 #define NVT_DPCD_RECEIVER_DOWNSTREAM_PORT_TYPE_HDMI NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_TYPE_HDMI // HDMI
4783 #define NVT_DPCD_RECEIVER_DOWNSTREAM_PORT_TYPE_OTHERS NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_TYPE_NO_EDID // the downstream port type will have no EDID in sink device such as Composite/SVideo.
4784 #define NVT_DPCD_RECEIVER_DOWNSTREAM_PORT_TYPE_DP_PP NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_TYPE_DISPLAYPORT_PP // Display Port++
4785 #define NVT_DPCD_LINK_RATE_1_62_GBPS NVT_DPCD_LINK_BW_SET_LINK_BW_SET_1_62GPBS_PER_LANE // 1.62Gbps per lane
4786 #define NVT_DPCD_LINK_RATE_2_70_GBPS NVT_DPCD_LINK_BW_SET_LINK_BW_SET_2_70GPBS_PER_LANE // 2.70Gbps per lane
4787 #define NVT_DPCD_LINK_RATE_5_40_GBPS NVT_DPCD_LINK_BW_SET_LINK_BW_SET_5_40GPBS_PER_LANE // 5.40Gbps per lane
4788 #define NVT_DPCD_LINK_RATE_8_10_GBPS NVT_DPCD_LINK_BW_SET_LINK_BW_SET_8_10GPBS_PER_LANE // 5.40Gbps per lane
4789 #define NVT_DPCD_LINK_RATE_FACTOR_IN_10KHZ_MBPS 2700 // e.g. NVT_DPCD_LINK_RATE_1_62_GBPS * 0.27Gbps per lane (in 10KHz)
4790 #define NVT_DPCD_LANE_COUNT_1 NVT_DPCD_LANE_COUNT_SET_LANE_COUNT_SET_1_LANE
4791 #define NVT_DPCD_LANE_COUNT_2 NVT_DPCD_LANE_COUNT_SET_LANE_COUNT_SET_2_LANES
4792 #define NVT_DPCD_LANE_COUNT_4 NVT_DPCD_LANE_COUNT_SET_LANE_COUNT_SET_4_LANES
4793 #define NVT_DPCD_LANE_COUNT_8 8
4794
4795 // note: the values of NVT_COLOR_FORMAT_* are fixed in order to match the equivalent NV classes
4796 typedef enum _NVT_COLOR_FORMAT
4797 {
4798 NVT_COLOR_FORMAT_RGB = 0,
4799 NVT_COLOR_FORMAT_YCbCr422 = 1,
4800 NVT_COLOR_FORMAT_YCbCr444 = 2,
4801 NVT_COLOR_FORMAT_YCbCr420 = 3,
4802 NVT_COLOR_FORMAT_Y = 4,
4803 NVT_COLOR_FORMAT_RAW = 5,
4804 NVT_COLOR_FORMAT_INVALID = 0xFF
4805 } NVT_COLOR_FORMAT;
4806
4807 typedef enum
4808 {
4809 NVT_COLOR_RANGE_FULL = 0,
4810 NVT_COLOR_RANGE_LIMITED = 1
4811 } NVT_COLOR_RANGE;
4812
4813 // note: the values of NVT_COLORIMETRY_* are fixed in order to match the equivalent NV classes
4814 typedef enum
4815 {
4816 NVT_COLORIMETRY_RGB = 0,
4817 NVT_COLORIMETRY_YUV_601 = 1,
4818 NVT_COLORIMETRY_YUV_709 = 2,
4819 NVT_COLORIMETRY_EXTENDED = 3,
4820 NVT_COLORIMETRY_XVYCC_601 = 4,
4821 NVT_COLORIMETRY_XVYCC_709 = 5,
4822 NVT_COLORIMETRY_ADOBERGB = 6,
4823 NVT_COLORIMETRY_BT2020cYCC = 7,
4824 NVT_COLORIMETRY_BT2020YCC = 8,
4825 NVT_COLORIMETRY_BT2020RGB = 9,
4826 NVT_COLORIMETRY_INVALID = 0xFF
4827 } NVT_COLORIMETRY;
4828
4829 #define NVT_DPCD_BPC_DEFAULT 0x00
4830 #define NVT_DPCD_BPC_6 0x01
4831 #define NVT_DPCD_BPC_8 0x02
4832 #define NVT_DPCD_BPC_10 0x03
4833 #define NVT_DPCD_BPC_12 0x04
4834 #define NVT_DPCD_BPC_16 0x05
4835
4836 #define NVT_DPCD_AUTOMATED_TEST 0x02
4837 #define NVT_DPCD_CP_IRQ 0x04
4838
4839 #define NVT_DPCD_LANES_2_3_TRAINED 0x77
4840 #define NVT_DPCD_LANE_1_TRAINED 0x07
4841 #define NVT_DPCD_LANE_0_TRAINED 0x07
4842 #define NVT_DPCD_INTERLANE_ALIGN_DONE 0x1
4843
4844 #define NVT_DPCD_LANE_1_STATUS 7:4
4845 #define NVT_DPCD_LANE_0_STATUS 3:0
4846 #define NVT_DPCD_ADDRESS_LANE_STATUS 0x00202
4847
4848 #define NVT_DPCD_TEST_REQ_LINK_TRAINING 0x01
4849 #define NVT_DPCD_TEST_REQ_TEST_PATTERN 0x02
4850 #define NVT_DPCD_TEST_REQ_EDID_READ 0x04
4851 #define NVT_DPCD_TEST_REQ_PHY_TEST_PATTERN 0x08
4852
4853 #define NVT_DPCD_TEST_ACK 0x01
4854 #define NVT_DPCD_TEST_NAK 0x02
4855 #define NVT_DPCD_TEST_EDID_CHECKSUM_WRITE 0x04
4856
4857 #define NVT_DPCD_TEST_MISC_COLOR_FORMAT 2:1
4858 #define NVT_DPCD_TEST_MISC_DYNAMIC_RANGE 3:3
4859 #define NVT_DPCD_TEST_MISC_YCbCr_COEFFICIENT 4:4
4860 #define NVT_DPCD_TEST_MISC_BIT_DEPTH 7:5
4861
4862 #define NVT_DPCD_TEST_EDID_CHECKSUM_ADDRESS 0x261
4863 #define NVT_DPCD_TEST_RESPONSE_ADDRESS 0x260
4864 #define NVT_EDID_CHECKSUM_BYTE 127
4865
4866 #define NVT_DPCD_POWER_STATE_NORMAL 0x01
4867 #define NVT_DPCD_POWER_STATE_POWER_DOWN 0x02
4868
4869 // *******************
4870 // ** DPCD 1.1 Spec **
4871 // *******************
4872
4873 // 0x000h DPCD_REV
4874 #define NVT_DPCD_DPCD_REV 0x000
4875 #define NVT_DPCD_DPCD_REV_MINOR_VER 3:0
4876 #define NVT_DPCD_DPCD_REV_MAJOR_VER 7:4
4877 #define NVT_DPCD_DPCD_REV_10 0x10
4878 #define NVT_DPCD_DPCD_REV_11 0x11
4879 #define NVT_DPCD_DPCD_REV_12 0x12
4880
4881 // 0x001h MAX_LINK_RATE
4882 #define NVT_DPCD_MAX_LINK_RATE 0x001
4883 #define NVT_DPCD_MAX_LINK_RATE_MAX_LINK_RATE 7:0
4884 #define NVT_DPCD_MAX_LINK_RATE_MAX_LINK_RATE_1_62GPS_PER_LANE 0x06
4885 #define NVT_DPCD_MAX_LINK_RATE_MAX_LINK_RATE_2_70GPS_PER_LANE 0x0A
4886 #define NVT_DPCD_MAX_LINK_RATE_MAX_LINK_RATE_5_40GPS_PER_LANE 0x14
4887 #define NVT_DPCD_MAX_LINK_RATE_MAX_LINK_RATE_8_10GPS_PER_LANE 0x1E
4888
4889 // 0x002h - MAX_LANE_COUNT
4890 #define NVT_DPCD_MAX_LANE_COUNT 0x002
4891 #define NVT_DPCD_MAX_LANE_COUNT_MAX_LANE_COUNT 4:0
4892 #define NVT_DPCD_MAX_LANE_COUNT_RSVD 6:5
4893 #define NVT_DPCD_MAX_LANE_COUNT_ENHANCED_FRAME_CAP 7:7
4894
4895 // 0x003h - MAX_DOWNSPREAD
4896 #define NVT_DPCD_MAX_DOWNSPREAD 0x003
4897 #define NVT_DPCD_MAX_DOWNSPREAD_MAX_DOWNSPREAD 0:0
4898 #define NVT_DPCD_MAX_DOWNSPREAD_MAX_DOWNSPREAD_NO 0
4899 #define NVT_DPCD_MAX_DOWNSPREAD_MAX_DOWNSPREAD_YES 1
4900 #define NVT_DPCD_MAX_DOWNSPREAD_RSVD 5:1
4901 #define NVT_DPCD_MAX_DOWNSPREAD_NO_AUX_HANDSHAKE_LINK_TRAINING 6:6
4902 #define NVT_DPCD_MAX_DOWNSPREAD_RSVD_2 7:7
4903
4904 // 0x004h - NORP
4905 #define NVT_DPCD_NORP 0x004
4906 #define NVT_DPCD_NORP_NUMBER_OF_RECEIVER_PORT_SUBTRACT_ONE 0:0
4907 #define NVT_DPCD_NORP_RSVD 7:1
4908
4909 // 0x005 - DOWNSTREAMPORT_PRESENT
4910 #define NVT_DPCD_DOWNSTREAMPORT_PRESENT 0x005
4911 #define NVT_DPCD_DOWNSTREAMPORT_PRESENT_DWN_STRM_PORT_PRESENT 0:0
4912 #define NVT_DPCD_DOWNSTREAMPORT_PRESENT_DWN_STRM_PORT_TYPE 2:1
4913 #define NVT_DPCD_DOWNSTREAMPORT_PRESENT_DWN_STRM_PORT_TYPE_DISPLAYPORT 0
4914 #define NVT_DPCD_DOWNSTREAMPORT_PRESENT_DWN_STRM_PORT_TYPE_VGA 1
4915 #define NVT_DPCD_DOWNSTREAMPORT_PRESENT_DWN_STRM_PORT_TYPE_DVI_HDMI 2
4916 #define NVT_DPCD_DOWNSTREAMPORT_PRESENT_DWN_STRM_PORT_TYPE_OTHERS 3
4917 #define NVT_DPCD_DOWNSTREAMPORT_PRESENT_FORMAT_CONVERSION 3:3
4918 #define NVT_DPCD_DOWNSTREAMPORT_PRESENT_RSVD 7:4
4919
4920 // 0x006 - MAIN_LINK_CHANNEL_CODING
4921 #define NVT_DPCD_MAIN_LINK_CHANNEL_CODING 0x006
4922 #define NVT_DPCD_MAIN_LINK_CHANNEL_CODING_ANSI8B_10B 0:0
4923 #define NVT_DPCD_MAIN_LINK_CHANNEL_CODING_RSVD 7:1
4924
4925 // 0x007 - DOWN_STREAM_PORT_COUNT
4926 #define NVT_DPCD_DOWN_STREAM_PORT_COUNT 0x007
4927 #define NVT_DPCD_DOWN_STREAM_PORT_COUNT_DWN_STRM_PORT_COUNT 3:0
4928 #define NVT_DPCD_DOWN_STREAM_PORT_COUNT_RSVD 6:4
4929 #define NVT_DPCD_DOWN_STREAM_PORT_COUNT_OUI_SUPPORT 7:7
4930 #define NVT_DPCD_DOWN_STREAM_PORT_COUNT_OUI_SUPPORT_YES 1
4931 #define NVT_DPCD_DOWN_STREAM_PORT_COUNT_OUI_SUPPORT_NO 0
4932
4933 // 0x008h - RECEIVE_PORT0_CAP_0
4934 #define NVT_DPCD_RECEIVE_PORT0_CAP_0 0x008
4935 #define NVT_DPCD_RECEIVE_PORT0_CAP_0_RSVD 0:0
4936 #define NVT_DPCD_RECEIVE_PORT0_CAP_0_LOCAL_EDID_PRESENT 1:1
4937 #define NVT_DPCD_RECEIVE_PORT0_CAP_0_LOCAL_EDID_PRESENT_YES 1
4938 #define NVT_DPCD_RECEIVE_PORT0_CAP_0_LOCAL_EDID_PRESENT_NO 0
4939 #define NVT_DPCD_RECEIVE_PORT0_CAP_0_ASSOCIATED_TO_PRECEDING_PORT 2:2
4940 #define NVT_DPCD_RECEIVE_PORT0_CAP_0_ASSOCIATED_TO_PRECEDING_PORT_YES 1
4941 #define NVT_DPCD_RECEIVE_PORT0_CAP_0_ASSOCIATED_TO_PRECEDING_PORT_NO 0
4942 #define NVT_DPCD_RECEIVE_PORT0_CAP_0_RSVD_2 7:3
4943
4944 // 0x009h - RECEIVE_PORT0_CAP_1
4945 #define NVT_DPCD_RECEIVE_PORT0_CAP_1 0x009
4946 #define NVT_DPCD_RECEIVE_PORT0_CAP_1_BUFFER_SIZE 7:0
4947
4948 // 0x00Ah - RECEIVE_PORT1_CAP_0
4949 #define NVT_DPCD_RECEIVE_PORT1_CAP_0 0x00A
4950 #define NVT_DPCD_RECEIVE_PORT1_CAP_0_RSVD 0:0
4951 #define NVT_DPCD_RECEIVE_PORT1_CAP_0_LOCAL_EDID_PRESENT 1:1
4952 #define NVT_DPCD_RECEIVE_PORT1_CAP_0_LOCAL_EDID_PRESENT_YES 1
4953 #define NVT_DPCD_RECEIVE_PORT1_CAP_0_LOCAL_EDID_PRESENT_NO 0
4954 #define NVT_DPCD_RECEIVE_PORT1_CAP_0_ASSOCIATED_TO_PRECEDING_PORT 2:2
4955 #define NVT_DPCD_RECEIVE_PORT1_CAP_0_ASSOCIATED_TO_PRECEDING_PORT_YES 1
4956 #define NVT_DPCD_RECEIVE_PORT1_CAP_0_ASSOCIATED_TO_PRECEDING_PORT_NO 0
4957 #define NVT_DPCD_RECEIVE_PORT1_CAP_0_RSVD_2 7:3
4958
4959 // 0x00Bh - RECEIVE_PORT1_CAP_1
4960 #define NVT_DPCD_RECEIVE_PORT1_CAP_1 0x00B
4961 #define NVT_DPCD_RECEIVE_PORT1_CAP_1_BUFFER_SIZE 7:0
4962
4963 // 0x021h - MST_CAP
4964 #define NVT_DPCD_MSTM_CAP 0x021
4965 #define NVT_DPCD_MSTM_CAP_MST_CAP 0:0
4966 #define NVT_DPCD_MSTM_CAP_MST_CAP_NO 0
4967 #define NVT_DPCD_MSTM_CAP_MST_CAP_YES 1
4968
4969 // 0x080h ~ 0x08Fh - DWN_STRM_PORT0_CAP
4970 #define NVT_DPCD_DWN_STRM_PORT0_CAP 0x080
4971 #define NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_TYPE 2:0
4972 #define NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_TYPE_DISPLAYPORT 0
4973 #define NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_TYPE_VGA 1
4974 #define NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_TYPE_DVI 2
4975 #define NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_TYPE_HDMI 3
4976 #define NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_TYPE_NO_EDID 4
4977 #define NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_TYPE_DISPLAYPORT_PP 5 //Defined in Post DP 1.2 draft
4978 #define NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_HPD 3:3
4979 #define NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_HPD_AWARE_YES 1
4980 #define NVT_DPCD_DWN_STRM_PORT0_CAP_DWN_STRM_PORT0_HPD_AWARE_NO 0
4981 #define NVT_DPCD_DWN_STRM_PORT0_CAP_RSVD 7:4
4982
4983 // 0x100h - LINK_BW_SET
4984 #define NVT_DPCD_LINK_BW_SET 0x100
4985 #define NVT_DPCD_LINK_BW_SET_LINK_BW_SET 7:0
4986 #define NVT_DPCD_LINK_BW_SET_LINK_BW_SET_1_62GPBS_PER_LANE 0x06
4987 #define NVT_DPCD_LINK_BW_SET_LINK_BW_SET_2_70GPBS_PER_LANE 0x0A
4988 #define NVT_DPCD_LINK_BW_SET_LINK_BW_SET_5_40GPBS_PER_LANE 0x14
4989 #define NVT_DPCD_LINK_BW_SET_LINK_BW_SET_8_10GPBS_PER_LANE 0x1E
4990
4991 // 0x101h - LANE_COUNT_SET
4992 #define NVT_DPCD_LANE_COUNT_SET 0x101
4993 #define NVT_DPCD_LANE_COUNT_SET_LANE_COUNT_SET 4:0
4994 #define NVT_DPCD_LANE_COUNT_SET_LANE_COUNT_SET_1_LANE 1
4995 #define NVT_DPCD_LANE_COUNT_SET_LANE_COUNT_SET_2_LANES 2
4996 #define NVT_DPCD_LANE_COUNT_SET_LANE_COUNT_SET_4_LANES 4
4997 #define NVT_DPCD_LANE_COUNT_SET_RSVD 6:5
4998 #define NVT_DPCD_LANE_COUNT_SET_ENHANCED_FRAME_EN 7:7
4999 #define NVT_DPCD_LANE_COUNT_SET_ENHANCED_FRAME_EN_YES 1
5000 #define NVT_DPCD_LANE_COUNT_SET_ENHANCED_FRAME_EN_NO 0
5001
5002 // 0x102h - TRAINING_PATTERN_SET
5003 #define NVT_DPCD_TRAINING_PATTERN_SET 0x102
5004 #define NVT_DPCD_TRAINING_PATTERN_SET_TRAINING_PATTERN_SET 1:0
5005 #define NVT_DPCD_TRAINING_PATTERN_SET_TRAINING_PATTERN_SET_NOT_IN_PROGRESS 0
5006 #define NVT_DPCD_TRAINING_PATTERN_SET_TRAINING_PATTERN_SET_PATTERN_1 1
5007 #define NVT_DPCD_TRAINING_PATTERN_SET_TRAINING_PATTERN_SET_PATTERN_2 2
5008 #define NVT_DPCD_TRAINING_PATTERN_SET_TRAINING_PATTERN_SET_RSVD 3
5009 #define NVT_DPCD_TRAINING_PATTERN_SET_LINK_QUAL_PATTERN_SET 3:2
5010 #define NVT_DPCD_TRAINING_PATTERN_SET_LINK_QUAL_PATTERN_SET_NOT_TRANSMITTED 0
5011 #define NVT_DPCD_TRAINING_PATTERN_SET_LINK_QUAL_PATTERN_SET_D10_2 1
5012 #define NVT_DPCD_TRAINING_PATTERN_SET_LINK_QUAL_PATTERN_SET_SERMPT 2
5013 #define NVT_DPCD_TRAINING_PATTERN_SET_LINK_QUAL_PATTERN_SET_PRBS7 3
5014 #define NVT_DPCD_TRAINING_PATTERN_SET_RECOVERED_CLOCK_OUT_EN 4:4
5015 #define NVT_DPCD_TRAINING_PATTERN_SET_RECOVERED_CLOCK_OUT_EN_NO 0
5016 #define NVT_DPCD_TRAINING_PATTERN_SET_RECOVERED_CLOCK_OUT_EN_YES 1
5017 #define NVT_DPCD_TRAINING_PATTERN_SET_SCRAMBLING_DISABLE 5:5
5018 #define NVT_DPCD_TRAINING_PATTERN_SET_SCRAMBLING_DISABLE_NO 0
5019 #define NVT_DPCD_TRAINING_PATTERN_SET_SCRAMBLING_DISABLE_YES 1
5020 #define NVT_DPCD_TRAINING_PATTERN_SET_SYMBOL_ERROR_COUNT_SEL 7:6
5021 #define NVT_DPCD_TRAINING_PATTERN_SET_SYMBOL_ERROR_COUNT_SEL_DIS_ERROR 0
5022 #define NVT_DPCD_TRAINING_PATTERN_SET_SYMBOL_ERROR_COUNT_SEL_D_ERROR 1
5023 #define NVT_DPCD_TRAINING_PATTERN_SET_SYMBOL_ERROR_COUNT_SEL_IS_ERROR 2
5024 #define NVT_DPCD_TRAINING_PATTERN_SET_SYMBOL_ERROR_COUNT_SEL_RSVD 3
5025
5026 // 0x103h ~ 0x106h - TRAINING_LANE?_SET
5027 #define NVT_DPCD_TRAINING_LANE0_SET 0x103
5028 #define NVT_DPCD_TRAINING_LANE1_SET 0x104
5029 #define NVT_DPCD_TRAINING_LANE2_SET 0x105
5030 #define NVT_DPCD_TRAINING_LANE3_SET 0x106
5031 #define NVT_DPCD_TRAINING_LANE0_SET_VOLTAGE_SWING_SET 1:0
5032 #define NVT_DPCD_TRAINING_LANE0_SET_VOLTAGE_SWING_SET_TP1_VS_L0 0
5033 #define NVT_DPCD_TRAINING_LANE0_SET_VOLTAGE_SWING_SET_TP1_VS_L1 1
5034 #define NVT_DPCD_TRAINING_LANE0_SET_VOLTAGE_SWING_SET_TP1_VS_L2 2
5035 #define NVT_DPCD_TRAINING_LANE0_SET_VOLTAGE_SWING_SET_TP1_VS_L3 3
5036 #define NVT_DPCD_TRAINING_LANE0_SET_MAX_SWING_REACHED 2:2
5037 #define NVT_DPCD_TRAINING_LANE0_SET_MAX_SWING_REACHED_NO 0
5038 #define NVT_DPCD_TRAINING_LANE0_SET_MAX_SWING_REACHED_YES 1
5039 #define NVT_DPCD_TRAINING_LANE0_SET_PRE_EMPHASIS_SET 4:3
5040 #define NVT_DPCD_TRAINING_LANE0_SET_PRE_EMPHASIS_SET_TP2_PE_NONE 0
5041 #define NVT_DPCD_TRAINING_LANE0_SET_PRE_EMPHASIS_SET_TP2_PE_L1 1
5042 #define NVT_DPCD_TRAINING_LANE0_SET_PRE_EMPHASIS_SET_TP2_PE_L2 2
5043 #define NVT_DPCD_TRAINING_LANE0_SET_PRE_EMPHASIS_SET_TP2_PE_L3 3
5044 #define NVT_DPCD_TRAINING_LANE0_SET_MAX_PRE_EMPHASIS_REACHED 5:5
5045 #define NVT_DPCD_TRAINING_LANE0_SET_MAX_PRE_EMPHASIS_REACHED_NO 0
5046 #define NVT_DPCD_TRAINING_LANE0_SET_MAX_PRE_EMPHASIS_REACHED_YES 1
5047 #define NVT_DPCD_TRAINING_LANE0_SET_RSVD 7:6
5048
5049 // 0x107h - DOWNSPREAD_CTRL
5050 #define NVT_DPCD_DOWNSPREAD_CTRL 0x107
5051 #define NVT_DPCD_DOWNSPREAD_CTRL_RSVD 3:0
5052 #define NVT_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP 4:4
5053 #define NVT_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_NO 0
5054 #define NVT_DPCD_DOWNSPREAD_CTRL_SPREAD_AMP_YES 1
5055 #define NVT_DPCD_DOWNSPREAD_CTRL_RSVD_2 7:5
5056
5057 // 0x108h - MAIN_LINK_CHANNEL_CODING_SET
5058 #define NVT_DPCD_MAIN_LINK_CHANNEL_CODING_SET 0x108
5059 #define NVT_DPCD_MAIN_LINK_CHANNEL_CODING_SET_SET_ANSI8B10B 0:0
5060 #define NVT_DPCD_MAIN_LINK_CHANNEL_CODING_SET_RSVD 7:1
5061
5062 // 0x111h - MSTM_CTRL
5063 #define NVT_DPCD_MSTM_CTRL 0x111
5064 #define NVT_DPCD_MSTM_CTRL_MST_EN 0:0
5065 #define NVT_DPCD_MSTM_CTRL_MST_EN_NO 0
5066 #define NVT_DPCD_MSTM_CTRL_MST_EN_YES 1
5067 #define NVT_DPCD_MSTM_CTRL_UP_REQ_EN 1:1
5068 #define NVT_DPCD_MSTM_CTRL_UP_REQ_EN_NO 0
5069 #define NVT_DPCD_MSTM_CTRL_UP_REQ_EN_YES 1
5070 #define NVT_DPCD_MSTM_CTRL_UPSTREAM_IS_SRC 2:2
5071 #define NVT_DPCD_MSTM_CTRL_UPSTREAM_IS_SRC_NO 0
5072 #define NVT_DPCD_MSTM_CTRL_UPSTREAM_IS_SRC_YES 1
5073 #define NVT_DPCD_MSTM_CTRL_MST_RSVD 7:3
5074
5075 // 0x1A1h - BRANCH_DEVICE_CTRL
5076 #define NVT_DPCD_BRANCH_DEVICE_CTRL 0x1A1
5077 #define NVT_DPCD_BRANCH_DEVICE_CTRL_HPD_NOTIF_TYPE 0:0
5078 #define NVT_DPCD_BRANCH_DEVICE_CTRL_HPD_NOTIF_TYPE_LONG_HPD_PULSE 0
5079 #define NVT_DPCD_BRANCH_DEVICE_CTRL_HPD_NOTIF_TYPE_SHORT_IRQ_PULSE 1
5080 #define NVT_DPCD_BRANCH_DEVICE_CTRL_RSVD 7:1
5081
5082 #define NVT_DPCD_PAYLOAD_ALLOCATE_SET 0x1C0
5083 #define NVT_DPCD_PAYLOAD_ALLOCATE_SET_VC_ID 6:0
5084
5085 #define NVT_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT 0x1C1
5086 #define NVT_DPCD_PAYLOAD_ALLOCATE_START_TIME_SLOT_FIELD 5:0
5087
5088 #define NVT_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0x1C2
5089 #define NVT_DPCD_PAYLOAD_ALLOCATE_TIME_SLOT_COUNT_FIELD 5:0
5090
5091 // 0x200h - SINK_COUNT
5092 #define NVT_DPCD_SINK_COUNT 0x200
5093 #define NVT_DPCD_SINK_COUNT_SINK_COUNT 5:0
5094 #define NVT_DPCD_SINK_COUNT_CP_READY 6:6
5095 #define NVT_DPCD_SINK_COUNT_RSVD 7:7
5096
5097 // 0x201h - DEVICE_SERVICE_IRQ_VECTOR
5098 #define NVT_DPCD_DEVICE_SERVICE_IRQ_VECTOR 0x201
5099 #define NVT_DPCD_DEVICE_SERVICE_IRQ_VECTOR_RSVD_REMOTE_CTRL_CMD_PENDING 0:0
5100 #define NVT_DPCD_DEVICE_SERVICE_IRQ_VECTOR_AUTOMATED_TEST_REQUEST 1:1
5101 #define NVT_DPCD_DEVICE_SERVICE_IRQ_VECTOR_CP_IRQ 2:2
5102 #define NVT_DPCD_DEVICE_SERVICE_IRQ_VECTOR_MCCS_IRQ 3:3
5103 #define NVT_DPCD_DEVICE_SERVICE_IRQ_VECTOR_DOWN_REP_MSG_READY 4:4
5104 #define NVT_DPCD_DEVICE_SERVICE_IRQ_VECTOR_UP_REQ_MSG_READY 5:5
5105 #define NVT_DPCD_DEVICE_SERVICE_IRQ_VECTOR_SINK_SPECIFIC_IRQ 6:6
5106 #define NVT_DPCD_DEVICE_SERVICE_IRQ_VECTOR_RSVD_2 7:7
5107
5108 // 0x202h ~ 0x203h - LANE0_1_STATUS
5109 #define NVT_DPCD_LANE0_1_STATUS 0x202
5110 #define NVT_DPCD_LANE2_3_STATUS 0x203
5111 #define NVT_DPCD_LANE0_1_STATUS_LANE0_CR_DONE 0:0
5112 #define NVT_DPCD_LANE0_1_STATUS_LANE0_CHANNEL_EQ_DONE 1:1
5113 #define NVT_DPCD_LANE0_1_STATUS_LANE0_SYMBOL_LOCKED 2:2
5114 #define NVT_DPCD_LANE0_1_STATUS_RSVD 3:3
5115 #define NVT_DPCD_LANE0_1_STATUS_LANE1_CR_DONE 4:4
5116 #define NVT_DPCD_LANE0_1_STATUS_LANE1_CHANNEL_EQ_DONE 5:5
5117 #define NVT_DPCD_LANE0_1_STATUS_LANE1_SYMBOL_LOCKED 6:6
5118 #define NVT_DPCD_LANE0_1_STATUS_RSVD_2 7:7
5119
5120 // 0x204h - LANE_ALIGN_STATUS_UPDATED
5121 // Temporary until Linux/Apple change their code.
5122 #define NVT_DPCD_LANE_ALIGN_STAUTS_UPDATED NVT_DPCD_LANE_ALIGN_STATUS_UPDATED
5123 #define NVT_DPCD_LANE_ALIGN_STATUS_UPDATED 0x204
5124 #define NVT_DPCD_LANE_ALIGN_STATUS_UPDATED_INTERLANE_ALIGN_DONE 0:0
5125 #define NVT_DPCD_LANE_ALIGN_STATUS_UPDATED_RSVD 5:1
5126 #define NVT_DPCD_LANE_ALIGN_STATUS_UPDATED_DOWNSTREAM_PORT_STATUS_CHANGED 6:6
5127 #define NVT_DPCD_LANE_ALIGN_STATUS_UPDATED_LINK_STATUS_UPDATED 7:7
5128
5129 // 0x205 - SINK_STATUS
5130 #define NVT_DPCD_SINK_STATUS 0x205
5131 #define NVT_DPCD_SINK_STATUS_RECEIVE_PORT_0_STATUS 0:0
5132 #define NVT_DPCD_SINK_STATUS_RECEIVE_PORT_0_STATUS_OUT_OF_SYNC 0
5133 #define NVT_DPCD_SINK_STATUS_RECEIVE_PORT_0_STATUS_IN_SYNC 1
5134 #define NVT_DPCD_SINK_STATUS_RECEIVE_PORT_1_STATUS 1:1
5135 #define NVT_DPCD_SINK_STATUS_RECEIVE_PORT_1_STATUS_OUT_OF_SYNC 0
5136 #define NVT_DPCD_SINK_STATUS_RECEIVE_PORT_1_STATUS_IN_SYNC 1
5137 #define NVT_DPCD_SINK_STATUS_RSVD 7:2
5138
5139 // 0x206h ~ 0x207h - ADJUST_REQUEST_LANE0_1
5140 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1 0x206
5141 #define NVT_DPCD_ADJUST_REQUEST_LANE2_3 0x207
5142 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_VOLTAGE_SWING_LANE0 1:0
5143 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_VOLTAGE_SWING_LANE0_LEVEL_0 0
5144 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_VOLTAGE_SWING_LANE0_LEVEL_1 1
5145 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_VOLTAGE_SWING_LANE0_LEVEL_2 2
5146 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_VOLTAGE_SWING_LANE0_LEVEL_3 3
5147 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_PRE_EMPHASIS_LANE0 3:2
5148 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_PRE_EMPHASIS_LANE0_LEVEL_0 0
5149 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_PRE_EMPHASIS_LANE0_LEVEL_1 1
5150 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_PRE_EMPHASIS_LANE0_LEVEL_2 2
5151 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_PRE_EMPHASIS_LANE0_LEVEL_3 3
5152 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_VOLTAGE_SWING_LANE1 5:4
5153 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_VOLTAGE_SWING_LANE1_LEVEL_0 0
5154 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_VOLTAGE_SWING_LANE1_LEVEL_1 1
5155 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_VOLTAGE_SWING_LANE1_LEVEL_2 2
5156 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_VOLTAGE_SWING_LANE1_LEVEL_3 3
5157 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_PRE_EMPHASIS_LANE1 7:6
5158 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_PRE_EMPHASIS_LANE1_LEVEL_0 0
5159 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_PRE_EMPHASIS_LANE1_LEVEL_1 1
5160 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_PRE_EMPHASIS_LANE1_LEVEL_2 2
5161 #define NVT_DPCD_ADJUST_REQUEST_LANE0_1_PRE_EMPHASIS_LANE1_LEVEL_3 3
5162
5163 // 0x208h ~ 0x20Bh TRAINING_SCORE_LANE0~3
5164 #define NVT_DPCD_TRAINING_SCORE_LANE0 0x208
5165 #define NVT_DPCD_TRAINING_SCORE_LANE1 0x209
5166 #define NVT_DPCD_TRAINING_SCORE_LANE2 0x20A
5167 #define NVT_DPCD_TRAINING_SCORE_LANE3 0x20B
5168
5169 // 0x210h ~ 0x217h SYMBOL_ERROR_COUNT_LANE0 (16bit)
5170 #define NVT_DPCD_SYMBOL_ERROR_COUNT_LANE0_LO 0x210
5171 #define NVT_DPCD_SYMBOL_ERROR_COUNT_LANE0_HI 0x211
5172 #define NVT_DPCD_SYMBOL_ERROR_COUNT_LANE1_LO 0x212
5173 #define NVT_DPCD_SYMBOL_ERROR_COUNT_LANE1_HI 0x213
5174 #define NVT_DPCD_SYMBOL_ERROR_COUNT_LANE2_LO 0x214
5175 #define NVT_DPCD_SYMBOL_ERROR_COUNT_LANE2_HI 0x215
5176 #define NVT_DPCD_SYMBOL_ERROR_COUNT_LANE3_LO 0x216
5177 #define NVT_DPCD_SYMBOL_ERROR_COUNT_LANE3_HI 0x217
5178 #define NVT_DPCD_SYMBOL_ERROR_COUNT_LANE0_ERROR_COUNT_LO 7:0
5179 #define NVT_DPCD_SYMBOL_ERROR_COUNT_LANE0_ERROR_COUNT_HI 6:0
5180 #define NVT_DPCD_SYMBOL_ERROR_COUNT_LANE0_ERROR_COUNT_VALID 7:7
5181
5182 // 0x218h TEST_REQUEST
5183 #define NVT_DPCD_TEST_REQUEST 0x218
5184 #define NVT_DPCD_TEST_REQUEST_TEST_LINK_TRAINING 0:0
5185 #define NVT_DPCD_TEST_REQUEST_TEST_PATTERN 1:1
5186 #define NVT_DPCD_TEST_REQUEST_TEST_EDID_READ 2:2
5187 #define NVT_DPCD_TEST_REQUEST_PHY_TEST_PATTERN 3:3
5188 #define NVT_DPCD_TEST_REQUEST_RSVD 7:4
5189
5190 // 0x219h TEST_LINK_RATE
5191 #define NVT_DPCD_TEST_LINK_RATE 0x219
5192
5193 // 0x220h TEST_LANE_COUNT
5194 #define NVT_DPCD_TEST_LANE_COUNT 0x220
5195 #define NVT_DPCD_TEST_LANE_COUNT_TEST_LANE_COUNT 4:0
5196 #define NVT_DPCD_TEST_LANE_COUNT_TEST_LANE_COUNT_ONE_LANE 1
5197 #define NVT_DPCD_TEST_LANE_COUNT_TEST_LANE_COUNT_TWO_LANES 2
5198 #define NVT_DPCD_TEST_LANE_COUNT_TEST_LANE_COUNT_FOUR_LANES 4
5199 #define NVT_DPCD_TEST_LANE_COUNT_RSVD 7:5
5200
5201 // 0x221h TEST_PATTERN
5202 #define NVT_DPCD_TEST_PATTERN 0x221
5203 #define NVT_DPCD_TEST_PATTERN_NO_TEST_PATTERN_TRANSMITTED 0
5204 #define NVT_DPCD_TEST_PATTERN_COLOR_RAMPS 1
5205 #define NVT_DPCD_TEST_PATTERN_BLACK_AND_WHITE_VERTICAL_LINES 2
5206 #define NVT_DPCD_TEST_PATTERN_COLOR_SQUARE 3
5207
5208 // 0x222h ~ 0x223h TEST_H_TOTAL
5209 #define NVT_DPCD_TEST_H_TOTAL_HI 0x222
5210 #define NVT_DPCD_TEST_H_TOTAL_LO 0x223
5211
5212 // 0x224h ~ 0x225h TEST_V_TOTAL
5213 #define NVT_DPCD_TEST_V_TOTAL_HI 0x224
5214 #define NVT_DPCD_TEST_V_TOTAL_LO 0x225
5215
5216 // 0x226h ~ 0x227h TEST_H_START
5217 #define NVT_DPCD_TEST_H_START_HI 0x226
5218 #define NVT_DPCD_TEST_H_START_LO 0x227
5219
5220 // 0x228h ~ 0x229h TEST_V_START
5221 #define NVT_DPCD_TEST_V_START_HI 0x228
5222 #define NVT_DPCD_TEST_V_START_LO 0x229
5223
5224 // 0x22Ah ~ 0x22Bh TEST_HSYNC
5225 #define NVT_DPCD_TEST_HSYNC_HI 0x22A
5226 #define NVT_DPCD_TEST_HSYNC_LO 0x22B
5227 #define NVT_DPCD_TEST_HSYNC_HI_TEST_HSYNC_WIDTH_14_8 6:0
5228 #define NVT_DPCD_TEST_HSYNC_HI_TEST_HSYNC_POLARITY 7:7
5229
5230 // 0x22Ch ~ 0x22Dh TEST_VSYNC
5231 #define NVT_DPCD_TEST_VSYNC_HI 0x22C
5232 #define NVT_DPCD_TEST_VSYNC_LO 0x22D
5233 #define NVT_DPCD_TEST_VSYNC_HI_TEST_VSYNC_WIDTH_14_8 6:0
5234 #define NVT_DPCD_TEST_VSYNC_HI_TEST_VSYNC_POLARITY 7:7
5235
5236 // 0x22Eh ~ 0x22Fh TEST_H_WIDTH
5237 #define NVT_DPCD_TEST_H_WIDTH_HI 0x22E
5238 #define NVT_DPCD_TEST_H_WIDTH_LO 0x22F
5239
5240 // 0x230h ~ 0x231h TEST_V_WIDTH
5241 #define NVT_DPCD_TEST_V_HEIGHT_HI 0x230
5242 #define NVT_DPCD_TEST_V_HEIGHT_LO 0x231
5243
5244 // 0x232h ~ 0x233h TEST_MISC
5245 #define NVT_DPCD_TEST_MISC_LO 0x232
5246 #define NVT_DPCD_TEST_MISC_LO_TEST_SYNCHRONOUS_CLOCK 0:0
5247 #define NVT_DPCD_TEST_MISC_LO_TEST_SYNCHRONOUS_CLOCK_ASYNC 0
5248 #define NVT_DPCD_TEST_MISC_LO_TEST_SYNCHRONOUS_CLOCK_SYNC 1
5249 #define NVT_DPCD_TEST_MISC_LO_TEST_COLOR_FORMAT 2:1
5250 #define NVT_DPCD_TEST_MISC_LO_TEST_COLOR_FORMAT_RGB 0
5251 #define NVT_DPCD_TEST_MISC_LO_TEST_COLOR_FORMAT_YCbCr422 1
5252 #define NVT_DPCD_TEST_MISC_LO_TEST_COLOR_FORMAT_YCbCr444 2
5253 #define NVT_DPCD_TEST_MISC_LO_TEST_COLOR_FORMAT_RSVD 3
5254 #define NVT_DPCD_TEST_MISC_LO_TEST_DYNAMIC_RANGE 3:3
5255 #define NVT_DPCD_TEST_MISC_LO_TEST_DYNAMIC_RANGE_VESA 0
5256 #define NVT_DPCD_TEST_MISC_LO_TEST_DYNAMIC_RANGE_CEA 1
5257 #define NVT_DPCD_TEST_MISC_LO_TEST_YCBCR_COEFFICIENTS 4:4
5258 #define NVT_DPCD_TEST_MISC_LO_TEST_YCBCR_COEFFICIENTS_ITU601 0
5259 #define NVT_DPCD_TEST_MISC_LO_TEST_YCBCR_COEFFICIENTS_ITU709 1
5260 #define NVT_DPCD_TEST_MISC_LO_TEST_BIT_DEPTH 7:5
5261 #define NVT_DPCD_TEST_MISC_LO_TEST_BIT_DEPTH_6BPC 0
5262 #define NVT_DPCD_TEST_MISC_LO_TEST_BIT_DEPTH_8BPC 1
5263 #define NVT_DPCD_TEST_MISC_LO_TEST_BIT_DEPTH_10BPC 2
5264 #define NVT_DPCD_TEST_MISC_LO_TEST_BIT_DEPTH_12BPC 3
5265 #define NVT_DPCD_TEST_MISC_LO_TEST_BIT_DEPTH_16BPC 4
5266 #define NVT_DPCD_TEST_MISC_HI 0x233
5267 #define NVT_DPCD_TEST_MISC_HI_TEST_REFRESH_DENOMINATOR 0:0
5268 #define NVT_DPCD_TEST_MISC_HI_TEST_REFRESH_DENOMINATOR_1 0
5269 #define NVT_DPCD_TEST_MISC_HI_TEST_REFRESH_DENOMINATOR_1001 1
5270 #define NVT_DPCD_TEST_MISC_HI_TEST_INTERLACED 1:1
5271 #define NVT_DPCD_TEST_MISC_HI_TEST_INTERLACED_NO 0
5272 #define NVT_DPCD_TEST_MISC_HI_TEST_INTERLACED_YES 1
5273 #define NVT_DPCD_TEST_MISC_HI_TEST_INTERLACED_RSVD 7:2
5274
5275 // 0x234h TEST_REFRESH_RATE_NUMERATOR
5276 #define NVT_DPCD_TEST_REFRESH_RATE_NUMERATOR 0x234
5277
5278 // 0x240h ~ 0x241h TEST_CRC_R_Cr
5279 #define NVT_DPCD_TEST_CRC_R_Cr_LO 0x240
5280 #define NVT_DPCD_TEST_CRC_R_Cr_HI 0x241
5281
5282 // 0x242h ~ 0x243h TEST_CRC_G_Y
5283 #define NVT_DPCD_TEST_CRC_G_Y_LO 0x242
5284 #define NVT_DPCD_TEST_CRC_G_Y_HI 0x243
5285
5286 // 0x244h ~ 0x245h TEST_CRC_B_Cb
5287 #define NVT_DPCD_TEST_CRC_B_Cb_LO 0x244
5288 #define NVT_DPCD_TEST_CRC_B_Cb_HI 0x245
5289
5290 // 0x246h TEST_SINC_MISC
5291 #define NVT_DPCD_TEST_SINK_MISC 0x246
5292 #define NVT_DPCD_TEST_SINK_MISC_TEST_CRC_COUNT 3:0
5293 #define NVT_DPCD_TEST_SINK_MISC_TEST_CRC_SUPPORTED 5:5
5294 #define NVT_DPCD_TEST_SINK_MISC_TEST_CRC_SUPPORTED_NO 0
5295 #define NVT_DPCD_TEST_SINK_MISC_TEST_CRC_SUPPORTED_YES 1
5296 #define NVT_DPCD_TEST_SINK_MISC_RSVD 7:6
5297
5298 // 0x248h PHY_TEST_PATTERN
5299 #define NVT_DPCD_PHY_TEST_PATTERN 0x248
5300 #define NVT_DPCD_PHY_TEST_PATTERN_PHY_TEST_PATTERN_SEL 1:0
5301 #define NVT_DPCD_PHY_TEST_PATTERN_PHY_TEST_PATTERN_SEL_NO_TEST_PATTERN 0
5302 #define NVT_DPCD_PHY_TEST_PATTERN_PHY_TEST_PATTERN_SEL_D10_2 1
5303 #define NVT_DPCD_PHY_TEST_PATTERN_PHY_TEST_PATTERN_SEL_SEMC 2
5304 #define NVT_DPCD_PHY_TEST_PATTERN_PHY_TEST_PATTERN_SEL_PRBS7 3
5305 #define NVT_DPCD_PHY_TEST_PATTERN_RSVD 7:2
5306
5307 // 0x260h TEST_RESPONSE
5308 #define NVT_DPCD_TEST_RESPONSE 0x260
5309 #define NVT_DPCD_TEST_RESPONSE_TEST_ACK 0:0
5310 #define NVT_DPCD_TEST_RESPONSE_TEST_ACK_KEEP_TEST_REQ 0
5311 #define NVT_DPCD_TEST_RESPONSE_TEST_ACK_CLEAR_TEST_REQ 1
5312 #define NVT_DPCD_TEST_RESPONSE_TEST_NAK 1:1
5313 #define NVT_DPCD_TEST_RESPONSE_TEST_NACK_KEEP_TEST_REQ 0
5314 #define NVT_DPCD_TEST_RESPONSE_TEST_NACK_CLEAR_TEST_REQ 1
5315 #define NVT_DPCD_TEST_RESPONSE_TEST_EDID_CHECKSUM_WRITE 2:2
5316 #define NVT_DPCD_TEST_RESPONSE_TEST_EDID_CHECKSUM_WRITE_NO 0
5317 #define NVT_DPCD_TEST_RESPONSE_TEST_EDID_CHECKSUM_WRITE_YES 1
5318 #define NVT_DPCD_TEST_RESPONSE_RSVD 7:3
5319
5320 // 0x261h TEST_EDID_CHECKSUM
5321 #define NVT_DPCD_TEST_EDID_CHECKSUM 0x261
5322
5323 // 0x270 TEST_SINK
5324 #define NVT_DPCD_TEST_SINK 0x270
5325 #define NVT_DPCD_TEST_SINK_TEST_SINK_START 0:0
5326 #define NVT_DPCD_TEST_SINK_TEST_SINK_START_STOP_CALC_CRC 0
5327 #define NVT_DPCD_TEST_SINK_TEST_SINK_START_START_CALC_CRC 1
5328 #define NVT_DPCD_TEST_SINK_RSVD 7:1
5329
5330 #define NVT_DPCD_PAYLOAD_TABLE_UPDATE_STATUS 0x2C0
5331 #define NVT_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_TABLE_UPDATED 0:0
5332 #define NVT_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_TABLE_UPDATED_NO 0
5333 #define NVT_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_TABLE_UPDATED_YES 1
5334 #define NVT_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED 1:1
5335 #define NVT_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_NO 0
5336 #define NVT_DPCD_PAYLOAD_TABLE_UPDATE_STATUS_ACT_HANDLED_YES 1
5337
5338 // 0x300h ~ 0x302h SOURCE_IEEE_OUT
5339 #define NVT_DPCD_SOURCE_IEEE_OUT_7_0 0x300
5340 #define NVT_DPCD_SOURCE_IEEE_OUT_15_8 0x301
5341 #define NVT_DPCD_SOURCE_IEEE_OUT_23_16 0x302
5342
5343 // 0x400h ~ 0x402h SINK_IEEE_OUT
5344 #define NVT_DPCD_SINK_IEEE_OUT_7_0 0x400
5345 #define NVT_DPCD_SINK_IEEE_OUT_15_8 0x401
5346 #define NVT_DPCD_SINK_IEEE_OUT_23_16 0x402
5347
5348 // 0x500h ~ 0x502h BRANCH_IEEE_OUT
5349 #define NVT_DPCD_BRANCH_IEEE_OUT_7_0 0x500
5350 #define NVT_DPCD_BRANCH_IEEE_OUT_15_8 0x501
5351 #define NVT_DPCD_BRANCH_IEEE_OUT_23_16 0x502
5352
5353 // 0x600 SET_POWER
5354 #define NVT_DPCD_SET_POWER 0x600
5355 #define NVT_DPCD_SET_POWER_SET_POWER_STATE 1:0
5356 #define NVT_DPCD_SET_POWER_SET_POWER_STATE_RSVD 0
5357 #define NVT_DPCD_SET_POWER_SET_POWER_STATE_D0 1
5358 #define NVT_DPCD_SET_POWER_SET_POWER_STATE_D3 2
5359 #define NVT_DPCD_SET_POWER_SET_POWER_STATE_RSVD_2 3
5360 #define NVT_DPCD_SET_POWER_RSVD 7:2
5361
5362 //*************************************
5363 // DP 1.2 Main Stream Attribute Fiedls
5364 //*************************************
5365
5366 #define NVT_DP_INFOFRAME_MSA_MISC0_SYNC_CLOCK_MASK 0x01 // MISC0 bit 0 Synchronous Clock
5367 #define NVT_DP_INFOFRAME_MSA_MISC0_SYNC_CLOCK_SHIFT 0x0
5368 #define NVT_DP_INFOFRAME_MSA_MISC0_SYNC_CLOCK_ASYNC 0x0
5369 #define NVT_DP_INFOFRAME_MSA_MISC0_SYNC_CLOCK_INSYNC 0x1
5370
5371 #define NVT_DP_INFOFRAME_MSA_MISC0_BITS_PER_COLOR_MASK 0xe0 // MISC0 bits 7:5 number of bits per color
5372 #define NVT_DP_INFOFRAME_MSA_MISC0_BITS_PER_COLOR_SHIFT 0x5
5373 #define NVT_DP_INFOFRAME_MSA_MISC0_BITS_PER_COLOR_6 0x0
5374 #define NVT_DP_INFOFRAME_MSA_MISC0_BITS_PER_COLOR_8 0x1
5375 #define NVT_DP_INFOFRAME_MSA_MISC0_BITS_PER_COLOR_10 0x2
5376 #define NVT_DP_INFOFRAME_MSA_MISC0_BITS_PER_COLOR_12 0x3
5377 #define NVT_DP_INFOFRAME_MSA_MISC0_BITS_PER_COLOR_16 0x4
5378
5379 #define NVT_DP_INFOFRAME_MSA_MISC0_COLOR_FORMAT_MASK 0x1e // MISC0 bits 4:1 Color Encoding Format and Content Color Gamut
5380 #define NVT_DP_INFOFRAME_MSA_MISC0_COLOR_FORMAT_SHIFT 0x1
5381 #define NVT_DP_INFOFRAME_MSA_MISC0_COLOR_FORMAT_LEGACY 0x0 // RGB unspecified color space (legacy RGB mode)
5382 #define NVT_DP_INFOFRAME_MSA_MISC0_COLOR_FORMAT_CEA_RGB 0x4 // CEA RGB (sRGB primaries)
5383 #define NVT_DP_INFOFRAME_MSA_MISC0_COLOR_FORMAT_WIDE_GAMUT_FIXED_POINT 0x3 // RGB wide gamut fixed point (XR8,XR10, XR12)
5384 #define NVT_DP_INFOFRAME_MSA_MISC0_COLOR_FORMAT_WIDE_GAMUT_FLOAT_POINT 0xb // RGB wide gamut floating point(scRGB)
5385 #define NVT_DP_INFOFRAME_MSA_MISC0_COLOR_FORMAT_YCBCR_422_ITU601 0x5
5386 #define NVT_DP_INFOFRAME_MSA_MISC0_COLOR_FORMAT_YCBCR_422_ITU709 0xd
5387 #define NVT_DP_INFOFRAME_MSA_MISC0_COLOR_FORMAT_YCBCR_444_ITU601 0x6
5388 #define NVT_DP_INFOFRAME_MSA_MISC0_COLOR_FORMAT_YCBCR_444_ITU709 0xe
5389 #define NVT_DP_INFOFRAME_MSA_MISC0_COLOR_FORMAT_XVYCC_422_ITU601 0x1
5390 #define NVT_DP_INFOFRAME_MSA_MISC0_COLOR_FORMAT_XVYCC_422_ITU709 0x9
5391 #define NVT_DP_INFOFRAME_MSA_MISC0_COLOR_FORMAT_XVYCC_444_ITU601 0x2
5392 #define NVT_DP_INFOFRAME_MSA_MISC0_COLOR_FORMAT_XVYCC_444_ITU709 0xa
5393 #define NVT_DP_INFOFRAME_MSA_MISC0_COLOR_FORMAT_ADOBE_RGB 0xc
5394
5395 #define NVT_DP_INFOFRAME_MSA_MISC1_INTERLACED_V_TOTAL_MASK 0x01 // MISC1 bit 0 Interlaced Vertical Total
5396 #define NVT_DP_INFOFRAME_MSA_MISC1_INTERLACED_V_TOTAL_SHIFT 0x0
5397 #define NVT_DP_INFOFRAME_MSA_MISC1_INTERLACED_V_TOTAL_ODD 0x0
5398 #define NVT_DP_INFOFRAME_MSA_MISC1_INTERLACED_V_TOTAL_EVEN 0x1
5399
5400 #define NVT_DP_INFOFRAME_MSA_MISC1_STEREO_MASK 0x06 // MISC1 bits 2:1 stereo video attribute
5401 #define NVT_DP_INFOFRAME_MSA_MISC1_STEREO_SHIFT 0x1
5402 #define NVT_DP_INFOFRAME_MSA_MISC1_STEREO_NONE 0x0
5403 #define NVT_DP_INFOFRAME_MSA_MISC1_STEREO_RIGHT_LEFT 0x1
5404 #define NVT_DP_INFOFRAME_MSA_MISC1_STEREO_LEFT_RIGHT 0x3
5405 #define NVT_DP_INFOFRAME_MSA_MISC1_STEREO_RESERVED 0x2
5406
5407 #define NVT_DP_INFOFRAME_MSA_MISC1_RESERVED_MASK 0x38 // MISC1 bits 5:3 reserved (DP1.3). Note: DP1.2 MISC 6:3 is reserved and undefined.
5408 #define NVT_DP_INFOFRAME_MSA_MISC1_RESERVED_SHIFT 0x3
5409 #define NVT_DP_INFOFRAME_MSA_MISC1_RESERVED_DEFAULT 0x0
5410
5411 #define NVT_DP_INFOFRAME_MSA_MISC1_VSC_SDP_MASK 0x40 // MISC1 bit Using VSC SDP, and sink to ignore MISC1 bit 7 and MISC0 7:1.
5412 #define NVT_DP_INFOFRAME_MSA_MISC1_VSC_SDP_SHIFT 0x6
5413 #define NVT_DP_INFOFRAME_MSA_MISC1_VSC_SDP_DISABLE 0x0
5414 #define NVT_DP_INFOFRAME_MSA_MISC1_VSC_SDP_ENABLE 0x1
5415
5416 #define NVT_DP_INFOFRAME_MSA_MISC1_BITS_PER_COLOR_OR_LUMINANCE_MASK 0x80 // MISC1 bit 7 Y-Only Video
5417 #define NVT_DP_INFOFRAME_MSA_MISC1_BITS_PER_COLOR_OR_LUMINANCE_SHIFT 0x7
5418 #define NVT_DP_INFOFRAME_MSA_MISC1_BITS_PER_COLOR 0x0
5419 #define NVT_DP_INFOFRAME_MSA_MISC1_BITS_PER_LUMINANCE 0x1
5420
5421 // ************************
5422 // ** HDCP DPCD 1.0 Spec **
5423 // ************************
5424
5425 // 0x68029 BSTATUS
5426 #define NVT_DPCD_HDCP_BSTATUS 0x68029
5427 #define NVT_DPCD_HDCP_BSTATUS_LINK_INTEGRITY_FAILURE 0x04
5428 #define NVT_DPCD_HDCP_BSTATUS_REAUTHENTICATION_REQUEST 0x08
5429
5430 #define NVT_DPCD_HDCP_BCAPS_OFFSET 0x00068028
5431 #define NVT_DPCD_HDCP_BCAPS_OFFSET_HDCP_CAPABLE 0:0
5432 #define NVT_DPCD_HDCP_BCAPS_OFFSET_HDCP_CAPABLE_NO 0x00000000
5433 #define NVT_DPCD_HDCP_BCAPS_OFFSET_HDCP_CAPABLE_YES 0x00000001
5434 #define NVT_DPCD_HDCP_BCAPS_OFFSET_HDCP_REPEATER 1:1
5435 #define NVT_DPCD_HDCP_BCAPS_OFFSET_HDCP_REPEATER_NO 0x00000000
5436 #define NVT_DPCD_HDCP_BCAPS_OFFSET_HDCP_REPEATER_YES 0x00000001
5437
5438 #define NVT_DPCD_HDCP_BKSV_OFFSET 0x00068000
5439 #define HDCP_KSV_SIZE 5
5440
5441
5442 // *********************************************
5443 // ** Vendor DPCD for Apple's mDP->VGA dongle **
5444 // *********************************************
5445
5446 // 0x30F DP2VGA_I2C_SPEED_CONTROL
5447 #define NVT_DPCD_DP2VGA_I2C_SPEED_CONTROL 0x30F
5448
5449 // 0x50C DP2VGA_GENERAL_STATUS
5450 #define NVT_DPCD_DP2VGA_GENERAL_STATUS 0x50C
5451
5452 // 0x50D DP2VGA_I2C_SPEED_CAP
5453 #define NVT_DPCD_DP2VGA_I2C_SPEED_CAP 0x50D
5454 #define NVT_DPCD_DP2VGA_I2C_SPEED_CAP_SLOWEST 0xFF
5455 #define NVT_DPCD_DP2VGA_I2C_SPEED_CAP_1KBPS 0x01
5456 #define NVT_DPCD_DP2VGA_I2C_SPEED_CAP_3KBPS 0x02
5457 #define NVT_DPCD_DP2VGA_I2C_SPEED_CAP_10KBPS 0x04
5458 #define NVT_DPCD_DP2VGA_I2C_SPEED_CAP_100KBPS 0x08
5459 #define NVT_DPCD_DP2VGA_I2C_SPEED_CAP_400KBPS 0x10
5460 #define NVT_DPCD_DP2VGA_I2C_SPEED_CAP_1MBPS 0x20
5461
5462
5463 //
5464 // HDMI/DP common definitions
5465
5466 #define NVT_DYNAMIC_RANGE_VESA 0x00
5467 #define NVT_DYNAMIC_RANGE_CEA 0x01
5468 #define NVT_DYNAMIC_RANGE_AUTO 0xFF
5469
5470
5471 typedef struct tagNVT_PARSED_DPCD_INFO_DOWNSTREAM_PORT
5472 {
5473 NvU8 type : 3; // the downstream port type
5474 NvU8 isHpdAware : 1; // if it's HPD aware
5475 NvU8 reserved : 4;
5476 }NVT_PARSED_DPCD_INFO_DOWNSTREAM_PORT;
5477 //
5478 typedef struct tagNVT_DPCD_PARSED_RECEIVER_INFO
5479 {
5480 // receiver info
5481 NvU32 rev; // DPCD version number
5482 NvU32 maxLinkRate; // the max link rate of main link lanes in 10KHz
5483 NvU32 maxLaneCount; // the max number of lanes
5484 NvU32 numOfPorts; // the number of receiver ports
5485 NvU32 p0BufferSizePerLane; // the buffer size per lane (in BYTE)
5486 NvU32 p1BufferSizePerLane; // the buffer size per lane (in BYTE)
5487
5488 // downstream port info
5489 NvU32 downstreamPortCount; // the total number of down stream ports
5490 NvU32 downstreamPort0Type; // type of downstream port 0
5491 NVT_PARSED_DPCD_INFO_DOWNSTREAM_PORT downstreamPort[NVT_DPCD_RECEIVER_MAX_DOWNSTREAM_PORT];
5492
5493 // other misc info
5494 NvU32 cap_support0_005DownSpread : 1;
5495 NvU32 cap_supportEnhancedFrame : 1;
5496 NvU32 cap_noAuxHandshakeLinkTraining : 1;
5497 NvU32 cap_downstreamPortHasFormatConvBlk : 1;
5498 NvU32 cap_mainLinkChSupportANSI8B10B : 1;
5499 NvU32 cap_downstreamPortSupportOUI : 1;
5500 NvU32 cap_p0HasEDID : 1;
5501 NvU32 cap_p0AssociatedToPrecedingPort : 1;
5502 NvU32 cap_p1HasEDID : 1;
5503 NvU32 cap_p1AssociatedToPrecedingPort : 1;
5504
5505 // DP 1.2 fields
5506 NvU32 cap_mstm : 1;
5507 NvU32 cap_reserved : 21;
5508 }NVT_DPCD_PARSED_RECEIVER_INFO;
5509
5510 #define NVT_DPCD_NUM_TRAINING_LANES 4
5511
5512 typedef struct tagNVT_TRAINING_LANE_SETTING
5513 {
5514 NvU8 voltageSwing;
5515 NvU8 maxSwingReached;
5516 NvU8 preEmphasis;
5517 NvU8 maxPreEmphasisReached;
5518 }NVT_TRAINING_LANE_SETTING;
5519
5520 // 00100h LINK CONFIGURATION FIELD
5521 typedef struct tagNVT_DPCD_PARSED_LINK_CONFIG
5522 {
5523 NvU8 linkRate;
5524 NvU8 laneCount;
5525
5526 NVT_TRAINING_LANE_SETTING trainLaneSetting[NVT_DPCD_NUM_TRAINING_LANES];
5527
5528 NvU32 enhancedFrameEnabled : 1;
5529 NvU32 trainingPatternSetting : 2;
5530 NvU32 linkQualityPatternSetting : 2;
5531 NvU32 recoveredClockOutputEnabled : 1;
5532 NvU32 scramblingDisable : 1;
5533 NvU32 symbolErrorCount : 2;
5534 NvU32 spreadAmp : 1;
5535 NvU32 mainLinkCoding8b10b : 1;
5536 NvU32 multiStreamEnabled : 1;
5537 NvU32 reserved : 19;
5538 }NVT_DPCD_PARSED_LINK_CONFIG;
5539
5540 typedef struct tagNVT_DPCD_INFO
5541 {
5542 NVT_DPCD_PARSED_RECEIVER_INFO receiver;
5543 NVT_DPCD_PARSED_LINK_CONFIG linkConfig;
5544 NvU32 sourceOUI;
5545 NvU32 sinkOUI;
5546 NvU32 branchOUI;
5547 }NVT_DPCD_INFO;
5548
5549 typedef struct tagNVT_DPCD_CONFIG
5550 {
5551 NvU32 dpInfoFlags;
5552 #define NV_DISPLAYPORT_INFO_FLAGS_DP_ENABLED 0:0
5553 #define NV_DISPLAYPORT_INFO_FLAGS_DP_ENABLED_FALSE (0x00000000)
5554 #define NV_DISPLAYPORT_INFO_FLAGS_DP_ENABLED_TRUE (0x00000001)
5555 #define NV_DISPLAYPORT_INFO_FLAGS_DONGLE_TYPE 7:4
5556 #define NV_DISPLAYPORT_INFO_FLAGS_DONGLE_TYPE_NONE (0x00000000)
5557 #define NV_DISPLAYPORT_INFO_FLAGS_DONGLE_TYPE_DP2DVI (0x00000001) // B2: dp2dvi-singlelink
5558 #define NV_DISPLAYPORT_INFO_FLAGS_DONGLE_TYPE_DP2HDMI (0x00000002) // dp2hdmi
5559 #define NV_DISPLAYPORT_INFO_FLAGS_DONGLE_TYPE_DP2DVI2 (0x00000003) // B3: dp2dvi-duallink
5560 #define NV_DISPLAYPORT_INFO_FLAGS_DONGLE_TYPE_DP2VGA (0x00000004) // B4: dp2vga
5561 #define NV_DISPLAYPORT_INFO_FLAGS_DONGLE_TYPE_DP2TV (0x00000005) // Composite/SVideo
5562 #define NV_DISPLAYPORT_INFO_FLAGS_DP_MAX_CAP_LANECOUNT 10:8 // Maximum supported laneCount
5563 #define NV_DISPLAYPORT_INFO_FLAGS_DP_MAX_CAP_LANECOUNT_1_LANE (0x00000000)
5564 #define NV_DISPLAYPORT_INFO_FLAGS_DP_MAX_CAP_LANECOUNT_2_LANE (0x00000001)
5565 #define NV_DISPLAYPORT_INFO_FLAGS_DP_MAX_CAP_LANECOUNT_4_LANE (0x00000002)
5566 #define NV_DISPLAYPORT_INFO_FLAGS_DP_MAX_CAP_LINKRATE 13:11 // Maximum supported linkRate
5567 #define NV_DISPLAYPORT_INFO_FLAGS_DP_MAX_CAP_LINKRATE_1_62GBPS (0x00000000)
5568 #define NV_DISPLAYPORT_INFO_FLAGS_DP_MAX_CAP_LINKRATE_2_70GBPS (0x00000001)
5569 #define NV_DISPLAYPORT_INFO_FLAGS_DP_MAX_CAP_LINKRATE_5_40GBPS (0x00000002)
5570 #define NV_DISPLAYPORT_INFO_FLAGS_DP_MAX_CAP_LINKRATE_8_10GBPS (0x00000003)
5571 #define NV_DISPLAYPORT_INFO_FLAGS_DP_MULTISTREAM 16:16 // Bit to check MST/SST
5572 #define NV_DISPLAYPORT_INFO_FLAGS_DP_MULTISTREAM_DISABLED (0x00000000)
5573 #define NV_DISPLAYPORT_INFO_FLAGS_DP_MULTISTREAM_ENABLED (0x00000001)
5574 #define NV_DISPLAYPORT_INFO_FLAGS_DP_ENHANCED_FRAMING 17:17 // Bit to check enhanced framing support
5575 #define NV_DISPLAYPORT_INFO_FLAGS_DP_ENHANCED_FRAMING_DISABLED (0x00000000)
5576 #define NV_DISPLAYPORT_INFO_FLAGS_DP_ENHANCED_FRAMING_ENABLED (0x00000001)
5577 #define NV_DISPLAYPORT_INFO_FLAGS_DP_DOWNSPREAD 18:18 // Bit to check downspread support
5578 #define NV_DISPLAYPORT_INFO_FLAGS_DP_DOWNSPREAD_DISABLED (0x00000000)
5579 #define NV_DISPLAYPORT_INFO_FLAGS_DP_DOWNSPREAD_ENABLED (0x00000001)
5580 #define NV_DISPLAYPORT_INFO_FLAGS_DP_SCRAMBLING 19:19 // Bit to check scrambling
5581 #define NV_DISPLAYPORT_INFO_FLAGS_DP_SCRAMBLING_DISABLED (0x00000000)
5582 #define NV_DISPLAYPORT_INFO_FLAGS_DP_SCRAMBLING_ENABLED (0x00000001)
5583 NvU32 linkRate;
5584 NvU32 laneCount;
5585 NvU32 colorFormat;
5586 NvU32 dynamicRange;
5587 NvU32 colorimetry;
5588 NvU32 bpc;
5589 NvU32 bpp;
5590
5591 // pre-emphasis and drive current level (EFI might need this information)
5592 NvU8 laneData[4];
5593 // DP max pixelClock supported based on DP max laneCount/linkRate
5594 NvU32 dpMaxPixelClk;
5595 NvU8 maxCapLinkRate;
5596 NvU8 maxCapLaneCount;
5597
5598 // B4 (DP2VGA) Vendor Specific I2C Speed Control
5599 NvU8 dp2vga_i2cCap;
5600 NvU8 dp2vga_i2cCtrl;
5601
5602 NvU8 bDpOffline;
5603 }NVT_DPCD_CONFIG;
5604
5605 typedef struct tagNVT_DPCD_DP_TUNNELING_CAPS
5606 {
5607 NvU8 dpTunneling : 1; // DP Tunneling through USB4 Support
5608 NvU8 reserved : 5; // Reserved.
5609 NvU8 dpPanelReplayTunnelingOptSupport : 1; // Panel Replay Tunneling Optimization Support
5610 NvU8 dpInBwAllocationModeSupport : 1; // DP IN Bandwidth Allocation Mode Support
5611 }NVT_DPCD_DP_TUNNELING_CAPS;
5612
5613 typedef struct tagNVT_DPCD_DP_IN_ADAPTER_INFO
5614 {
5615 NvU8 dpInAdapterNumber : 6; // DP IN Adapter Number
5616 NvU8 reserved : 2;
5617 }NVT_DPCD_DP_IN_ADAPTER_INFO;
5618
5619 typedef struct tagNVT_DPCD_USB4_DRIVER_ID
5620 {
5621 NvU8 usb4DriverId : 4; // USB4 Driver ID
5622 NvU8 reserved : 4;
5623 }NVT_DPCD_USB4_DRIVER_ID;
5624
5625 //******************************
5626 // Intel EDID Like Data (ELD)
5627 //******************************
5628 #define NVT_ELD_VER_1 0x1 // ELD version 1, which is an obsolete ELD structure. Treated as reserved
5629 #define NVT_ELD_VER_2 0x2 // ELD version 2, which supports CEA version 861-D or below. Max baseline ELD size of 80 bytes (15 short audio descriptors)
5630 #define NVT_ELD_VER_VIDEO_DRIVER_UNLOAD 0x1F // Indicates an ELD that has been partially populated through implementation specific mean of default programming before an external
5631 // graphics driver is load, Only the fields that is called out as "canned" fields will be populated, and audio driver should
5632 // ignore the non "canned" fields.
5633 #define NVT_ELD_CONN_TYPE_HDMI 0x0 // indicates an HDMI connection type
5634 #define NVT_ELD_CONN_TYPE_DP 0x1 // indicates a DP connection type
5635
5636
5637 //******************************
5638 // Audio
5639 //******************************
5640 #define NVT_AUDIO_768KHZ 768000 // HBR Audio
5641 #define NVT_AUDIO_384KHZ 384000 // HBR Audio
5642 #define NVT_AUDIO_192KHZ 192000
5643 #define NVT_AUDIO_176KHZ 176000
5644 #define NVT_AUDIO_96KHZ 96000
5645 #define NVT_AUDIO_88KHZ 88000
5646 #define NVT_AUDIO_48KHZ 48000
5647 #define NVT_AUDIO_44KHZ 44000
5648 #define NVT_AUDIO_32KHZ 32000
5649
5650 //Default format for HDTV is NVT_DEFAULT_HDTV_FMT i.e 1080i
5651 #define NVT_DEFAULT_HDTV_PREFERRED_TIMING(x, y, z, p) \
5652 if(((x) == 1920) && ((y) == 1080) && ((z) != D3DDDI_VSSLO_PROGRESSIVE )) p = 1;
5653
5654 //Default format for non-DDC displays is 10x7
5655 #define NVT_DEFAULT_NONDCC_PREFERRED_TIMING(x, y, z, p) \
5656 if(((x) == 1024) && ((y) == 768) && ((z) == 60 )) p = 1;
5657
5658
5659 // Length of user-friendly monitor name, derived from the EDID's
5660 // Display Product Name descriptor block, plus the EDID manufacturer PNP
5661 // ID. The Display Product can be distributed across four 13-byte
5662 // descriptor blocks, and the PNP ID currently decodes to at most 40
5663 // characters: 4*13 + 40 = 92
5664 #define NVT_EDID_MONITOR_NAME_STRING_LENGTH 96
5665
5666 // Compute the actual size of an EDID with a pointer to an NVT_EDID_INFO.
NVT_EDID_ACTUAL_SIZE(const NVT_EDID_INFO * pInfo)5667 static NV_INLINE NvU32 NVT_EDID_ACTUAL_SIZE(const NVT_EDID_INFO *pInfo)
5668 {
5669 return (pInfo->total_extensions + 1) * 128;
5670 }
5671
5672 //******************************
5673 //******************************
5674 //** the export functions **
5675 //******************************
5676 //******************************
5677
5678 // the common timing function return values
5679 typedef enum
5680 {
5681 NVT_STATUS_SUCCESS = 0, // Success (no status)
5682 NVT_STATUS_ERR = 0x80000000, // generic get timing error
5683 NVT_STATUS_INVALID_PARAMETER, // passed an invalid parameter
5684 NVT_STATUS_NO_MEMORY, // memory allocation failed
5685 NVT_STATUS_COLOR_FORMAT_NOT_SUPPORTED,
5686 NVT_STATUS_INVALID_HBLANK,
5687 NVT_STATUS_INVALID_BPC,
5688 NVT_STATUS_INVALID_BPP,
5689 NVT_STATUS_MAX_LINE_BUFFER_ERROR,
5690 NVT_STATUS_OVERALL_THROUGHPUT_ERROR,
5691 NVT_STATUS_DSC_SLICE_ERROR,
5692 NVT_STATUS_PPS_SLICE_COUNT_ERROR,
5693 NVT_STATUS_PPS_SLICE_HEIGHT_ERROR,
5694 NVT_STATUS_PPS_SLICE_WIDTH_ERROR,
5695 NVT_STATUS_INVALID_PEAK_THROUGHPUT,
5696 NVT_STATUS_MIN_SLICE_COUNT_ERROR,
5697 } NVT_STATUS;
5698
5699 //*************************************
5700 // The EDID validation Mask
5701 //*************************************
5702 #define NVT_EDID_VALIDATION_MASK 0xFFFFFFFF
5703 #define NVT_IS_EDID_VALIDATION_FLAGS(x, n) ((((x)&NVT_EDID_VALIDATION_MASK)) & NVBIT32(n))
5704 #define NVT_CLEAR_EDID_VALIDATION_FLAGS(x, n) ((x)&=(~NVBIT32(n)))
5705
5706 typedef enum
5707 {
5708 // errors returned as a bitmask by NvTiming_EDIDValidationMask()
5709 NVT_EDID_VALIDATION_ERR_EXT = 0,
5710 NVT_EDID_VALIDATION_ERR_VERSION,
5711 NVT_EDID_VALIDATION_ERR_SIZE,
5712 NVT_EDID_VALIDATION_ERR_CHECKSUM,
5713 NVT_EDID_VALIDATION_ERR_RANGE_LIMIT,
5714 NVT_EDID_VALIDATION_ERR_DTD,
5715 NVT_EDID_VALIDATION_ERR_HEADER,
5716 NVT_EDID_VALIDATION_ERR_EXT_DTD,
5717 NVT_EDID_VALIDATION_ERR_EXTENSION_TAG,
5718 NVT_EDID_VALIDATION_ERR_EXTENSION_COUNT,
5719 NVT_EDID_VALIDATION_ERR_DESCRIPTOR,
5720 NVT_EDID_VALIDATION_ERR_EXT_CTA_BASIC,
5721 NVT_EDID_VALIDATION_ERR_EXT_CTA_DTD,
5722 NVT_EDID_VALIDATION_ERR_EXT_CTA_TAG,
5723 NVT_EDID_VALIDATION_ERR_EXT_CTA_SVD,
5724 NVT_EDID_VALIDATION_ERR_EXT_CTA_INVALID_DATA_BLOCK,
5725 NVT_EDID_VALIDATION_ERR_EXT_CTA_CHECKSUM,
5726 NVT_EDID_VALIDATION_ERR_EXT_DID_VERSION,
5727 NVT_EDID_VALIDATION_ERR_EXT_DID_EXTCOUNT,
5728 NVT_EDID_VALIDATION_ERR_EXT_DID_CHECKSUM,
5729 NVT_EDID_VALIDATION_ERR_EXT_DID_SEC_SIZE,
5730 NVT_EDID_VALIDATION_ERR_EXT_DID13_TAG,
5731 NVT_EDID_VALIDATION_ERR_EXT_DID13_TYPE1,
5732 NVT_EDID_VALIDATION_ERR_EXT_DID2_TAG,
5733 NVT_EDID_VALIDATION_ERR_EXT_DID2_USE_CASE,
5734 NVT_EDID_VALIDATION_ERR_EXT_DID2_MANDATORY_BLOCKS,
5735 NVT_EDID_VALIDATION_ERR_EXT_DID2_TYPE7,
5736 NVT_EDID_VALIDATION_ERR_EXT_DID2_TYPE10,
5737 NVT_EDID_VALIDATION_ERR_EXT_RANGE_LIMIT,
5738 NVT_EDID_VALIDATION_ERR_EXT_DID2_ADAPTIVE_SYNC,
5739 } NVT_EDID_VALIDATION_ERR_STATUS;
5740 #define NVT_EDID_VALIDATION_ERR_MASK(x) NVBIT32(x)
5741
5742 //*************************************
5743 // The DisplayID2 validation Mask
5744 //*************************************
5745 typedef enum
5746 {
5747 // errors returned as a bitmask by NvTiming_DisplayID2ValidationMask()
5748 NVT_DID2_VALIDATION_ERR_VERSION = 0,
5749 NVT_DID2_VALIDATION_ERR_SIZE,
5750 NVT_DID2_VALIDATION_ERR_CHECKSUM,
5751 NVT_DID2_VALIDATION_ERR_NO_DATA_BLOCK,
5752 NVT_EDID_VALIDATION_ERR_TAG,
5753 NVT_DID2_VALIDATION_ERR_RANGE_LIMIT,
5754 NVT_DID2_VALIDATION_ERR_NATIVE_DTD,
5755 NVT_DID2_VALIDATION_ERR_MANDATORY_BLOCKS,
5756 NVT_DID2_VALIDATION_ERR_PRODUCT_IDENTIFY,
5757 NVT_DID2_VALIDATION_ERR_PARAMETER,
5758 NVT_DID2_VALIDATION_ERR_INTERFACE,
5759 NVT_DID2_VALIDATION_ERR_TYPE7,
5760 NVT_DID2_VALIDATION_ERR_TYPE10,
5761 NVT_DID2_VALIDATION_ERR_ADAPTIVE_SYNC,
5762 } NVT_DID2_VALIDATION_ERR_STATUS;
5763 #define NVT_DID2_VALIDATION_ERR_MASK(x) NVBIT32(x)
5764
5765 // timing calculation flags:
5766 #define NVT_FLAG_PROGRESSIVE_TIMING 0x00000000
5767 #define NVT_FLAG_INTERLACED_TIMING NVT_INTERLACED
5768 #define NVT_FLAG_INTERLACED_TIMING2 NVT_INTERLACED_NO_EXTRA_VBLANK_ON_FIELD2 //without extra vblank on field 2
5769 #define NVT_FLAG_DOUBLE_SCAN_TIMING 0x00000010
5770 #define NVT_FLAG_REDUCED_BLANKING_TIMING 0x00000020
5771 #define NVT_FLAG_MAX_EDID_TIMING 0x00000040
5772 #define NVT_FLAG_NV_DOUBLE_SCAN_TIMING 0x00000080
5773 #define NVT_FLAG_NATIVE_TIMING 0x00000100
5774 #define NVT_FLAG_EDID_TIMING 0x00000200
5775 #define NVT_FLAG_CEA_4X3_TIMING 0x00000400
5776 #define NVT_FLAG_CEA_16X9_TIMING 0x00000800
5777 #define NVT_FLAG_OS_ADDED_TIMING 0x00001000
5778 #define NVT_FLAG_SPECTRUM_SPREAD 0x00002000
5779 #define NVT_FLAG_EDID_TIMING_RR_MATCH 0x00004000
5780 #define NVT_FLAG_EDID_861_ST 0x00008000
5781 #define NVT_FLAG_EDID_DTD_EIZO_SPLIT 0x00010000
5782 #define NVT_FLAG_DTD1_TIMING 0x00020000
5783 #define NVT_FLAG_NV_PREFERRED_TIMING 0x00040000
5784 #define NVT_FLAG_DTD1_PREFERRED_TIMING 0x00080000
5785 #define NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING 0x00100000
5786 #define NVT_FLAG_CTA_PREFERRED_TIMING 0x00200000
5787 #define NVT_FLAG_DISPLAYID_T7_DSC_PASSTHRU 0x00400000
5788 #define NVT_FLAG_DISPLAYID_2_0_TIMING 0x00800000 // this one for the CTA861 embedded in DID20
5789 #define NVT_FLAG_DISPLAYID_T7_T8_EXPLICT_YUV420 0x01000000 // DID2 E7 spec. supported yuv420 indicated
5790 #define NVT_FLAG_CTA_NATIVE_TIMING 0x02000000 // NVRDB defined
5791 #define NVT_FLAG_CTA_OVT_TIMING 0x04000000 // CTA861 CTA OVT Timing
5792 #define NVT_FLAG_CTA_OVT_FRR_TIMING 0x08000000 // CTA861 CTA OVT Timing supported ntsc
5793
5794 #define NVT_FLAG_INTERLACED_MASK (NVT_FLAG_INTERLACED_TIMING | NVT_FLAG_INTERLACED_TIMING2)
5795
5796 #ifdef __cplusplus
5797 extern "C" {
5798 #endif
5799
5800 // Generic timing parameter calculation
5801 NvU16 NvTiming_CalcRR(NvU32 pclk, NvU16 interlaced, NvU16 HTotal, NvU16 VTotal);
5802 NvU32 NvTiming_CalcRRx1k(NvU32 pclk, NvU16 interlaced, NvU16 HTotal, NvU16 VTotal);
5803
5804 NvU32 NvTiming_IsRoundedRREqual(NvU16 rr1, NvU32 rr1x1k, NvU16 rr2);
5805 NvU32 NvTiming_IsTimingExactEqual(const NVT_TIMING *pT1, const NVT_TIMING *pT2);
5806 NvU32 NvTiming_IsTimingExactEqualEx(const NVT_TIMING *pT1, const NVT_TIMING *pT2);
5807 NvU32 NvTiming_IsTimingRelaxedEqual(const NVT_TIMING *pT1, const NVT_TIMING *pT2);
5808 NvU16 NvTiming_MaxFrameWidth(NvU16 HVisible, NvU16 rep);
5809
5810 // Establish timing enumeration
5811 NVT_STATUS NvTiming_EnumEST(NvU32 index, NVT_TIMING *pT);
5812 NVT_STATUS NvTiming_EnumESTIII(NvU32 index, NVT_TIMING *pT);
5813
5814 // GTF timing calculation
5815 NVT_STATUS NvTiming_CalcGTF(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT);
5816
5817 // DMT timing calculation
5818 NVT_STATUS NvTiming_EnumDMT(NvU32 dmtId, NVT_TIMING *pT);
5819 NVT_STATUS NvTiming_EnumStdTwoBytesCode(NvU16 std2ByteCodes, NVT_TIMING *pT);
5820 NVT_STATUS NvTiming_CalcDMT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT);
5821 NVT_STATUS NvTiming_CalcDMT_RB(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT);
5822 NVT_STATUS NvTiming_CalcDMT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT);
5823
5824 // CVT timing calculation
5825 NVT_STATUS NvTiming_CalcCVT(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT);
5826 NVT_STATUS NvTiming_CalcCVT_RB(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_TIMING *pT);
5827 NVT_STATUS NvTiming_CalcCVT_RB2(NvU32 width, NvU32 height, NvU32 rr, NvBool is1000div1001, NVT_TIMING *pT);
5828 NVT_STATUS NvTiming_CalcCVT_RB3(NvU32 width, NvU32 height, NvU32 rr, NvU32 deltaHBlank, NvU32 vBlankMicroSec, NvBool isEarlyVSync, NVT_TIMING *pT);
5829 NvBool NvTiming_IsTimingCVTRB(const NVT_TIMING *pTiming);
5830
5831 // OVT timing calculation
5832 NVT_STATUS NvTiming_CalcOVT(NvU32 width, NvU32 height, NvU32 rr, NVT_TIMING *pT);
5833 NvBool NvTiming_IsTimingOVT(const NVT_TIMING *pTiming);
5834
5835 // CEA/EIA/Psf timing
5836 NVT_STATUS NvTiming_CalcCEA861bTiming(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NvU32 pixelRepeatCount, NVT_TIMING *pT);
5837 NVT_STATUS NvTiming_EnumCEA861bTiming(NvU32 ceaFormat, NVT_TIMING *pT);
5838 NVT_STATUS NvTiming_EnumNvPsfTiming(NvU32 nvPsfFormat, NVT_TIMING *pT);
5839 NvU32 NvTiming_GetCEA861TimingIndex(NVT_TIMING *pT);
5840
5841 //expose the HDMI extended video timing defined by the HDMI LLC VSDB
5842 NVT_STATUS NvTiming_EnumHdmiVsdbExtendedTiming(NvU32 hdmi_vic, NVT_TIMING *pT);
5843
5844 // TV(analog) based timing
5845 NVT_STATUS NvTiming_GetTvTiming(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NvU32 tvFormat, NVT_TIMING *pT);
5846
5847 // Get EDID timing
5848 NVT_STATUS NvTiming_GetEdidTimingExWithPclk(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k, NvU32 pclk);
5849 NVT_STATUS NvTiming_GetEdidTimingEx(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT, NvU32 rrx1k);
5850 NVT_STATUS NvTiming_GetEdidTiming(NvU32 width, NvU32 height, NvU32 rr, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_TIMING *pT);
5851
5852 // Get EDID based HDMI Stereo timing
5853 NVT_STATUS NvTiming_GetHDMIStereoExtTimingFromEDID(NvU32 width, NvU32 height, NvU32 rr, NvU8 structure, NvU8 detail, NvU32 flag, NVT_EDID_INFO *pEdidInfo, NVT_EXT_TIMING *pT);
5854 void NvTiming_GetHDMIStereoTimingFrom2DTiming(const NVT_TIMING *pTiming, NvU8 StereoStructureType, NvU8 SideBySideHalfDetail, NVT_EXT_TIMING *pExtTiming);
5855 NVT_STATUS NvTiming_GetHDMIStereoMandatoryFormatDetail(const NvU8 vic, NvU16 *pStereoStructureMask, NvU8 *pSideBySideHalfDetail);
5856
5857 // EDID based AspectRatio Timing
5858 NVT_STATUS NvTiming_GetEDIDBasedASPRTiming(NvU16 width, NvU16 height, NvU16 rr, NVT_EDID_INFO *pEI, NVT_TIMING *ft);
5859
5860 // EDID or DISPLAYID2 version
5861 NvU32 NvTiming_GetVESADisplayDescriptorVersion(NvU8 *rawData, NvU32 *pVer);
5862
5863 // EDID entry parse
5864 NVT_STATUS NV_STDCALL NvTiming_ParseEDIDInfo(NvU8 *pEdid, NvU32 length, NVT_EDID_INFO *pEdidInfo);
5865 NvU32 NvTiming_EDIDValidationMask(NvU8 *pEdid, NvU32 length, NvBool bIsStrongValidation);
5866 NvU32 NvTiming_EDIDStrongValidationMask(NvU8 *pEdid, NvU32 length);
5867 NVT_STATUS NvTiming_EDIDValidation(NvU8 *pEdid, NvU32 length, NvBool bIsStrongValidation);
5868
5869 // DisplayID20 standalone entry parse
5870 NVT_STATUS NV_STDCALL NvTiming_parseDisplayId20Info(const NvU8 *pDisplayId, NvU32 length, NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo);
5871 NvU32 NvTiming_DisplayID2ValidationMask(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, NvBool bIsStrongValidation);
5872 NVT_STATUS NvTiming_DisplayID2ValidationDataBlocks(NVT_DISPLAYID_2_0_INFO *pDisplayIdInfo, NvBool bIsStrongValidation);
5873
5874 NVT_STATUS NvTiming_Get18ByteLongDescriptorIndex(NVT_EDID_INFO *pEdidInfo, NvU8 tag, NvU32 *dtdIndex);
5875 NVT_STATUS NvTiming_GetProductName(const NVT_EDID_INFO *pEdidInfo, NvU8 *pProductName, const NvU32 productNameLength);
5876 NvU32 NvTiming_CalculateEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidsize);
5877 NvU32 NvTiming_CalculateCommonEDIDCRC32(NvU8* pEDIDBuffer, NvU32 edidVersion);
5878 NVT_STATUS NvTiming_CalculateEDIDLimits(NVT_EDID_INFO *pEdidInfo, NVT_EDID_RANGE_LIMIT *pLimit);
5879 void NvTiming_GetMonitorName(NVT_EDID_INFO *pEdidInfo, NvU8 monitor_name[NVT_EDID_MONITOR_NAME_STRING_LENGTH]);
5880
5881 // utility routines
5882 NvU64 axb_div_c_64(NvU64 a, NvU64 b, NvU64 c);
5883 NvU32 axb_div_c(NvU32 a, NvU32 b, NvU32 c);
5884 NvU32 a_div_b(NvU32 a, NvU32 b);
5885 NvU32 calculateCRC32(NvU8* pBuf, NvU32 bufsize);
5886 void patchChecksum(NvU8* pBuf);
5887 NvBool isChecksumValid(NvU8* pBuf);
5888 NvU32 RRx1kToPclk (NVT_TIMING *pT);
5889
5890 NVT_STATUS NvTiming_ComposeCustTimingString(NVT_TIMING *pT);
5891
5892 // Infoframe/SDP composer
5893 NVT_STATUS NvTiming_ConstructVideoInfoframeCtrl(const NVT_TIMING *pTiming, NVT_VIDEO_INFOFRAME_CTRL *pCtrl);
5894 NVT_STATUS NvTiming_ConstructVideoInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VIDEO_INFOFRAME_CTRL *pCtrl, NVT_VIDEO_INFOFRAME *pContext, NVT_VIDEO_INFOFRAME *p);
5895 NVT_STATUS NvTiming_ConstructAudioInfoframe(NVT_AUDIO_INFOFRAME_CTRL *pCtrl, NVT_AUDIO_INFOFRAME *pContext, NVT_AUDIO_INFOFRAME *p);
5896 NVT_STATUS NvTiming_ConstructVendorSpecificInfoframe(NVT_EDID_INFO *pEdidInfo, NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL *pCtrl, NVT_VENDOR_SPECIFIC_INFOFRAME *p);
5897 NVT_STATUS NvTiming_ConstructExtendedMetadataPacketInfoframe(NVT_EXTENDED_METADATA_PACKET_INFOFRAME_CTRL *pCtrl, NVT_EXTENDED_METADATA_PACKET_INFOFRAME *p);
5898 void NvTiming_ConstructAdaptiveSyncSDP(const NVT_ADAPTIVE_SYNC_SDP_CTRL *pCtrl, NVT_ADAPTIVE_SYNC_SDP *p);
5899
5900
5901 // Get specific timing from parsed EDID
5902 NVT_STATUS NvTiming_GetDTD1Timing (NVT_EDID_INFO * pEdidInfo, NVT_TIMING * pT);
5903
5904 #define NVT_IS_DTD(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_EDID_DTD)
5905 #define NVT_IS_EXT_DTD(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_EDID_EXT_DTD)
5906 #define NVT_IS_CTA861(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_EDID_861ST)
5907 #define NVT_IS_CTA861_DID_T7(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_CTA861_DID_T7)
5908 #define NVT_IS_CTA861_DID_T8(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_CTA861_DID_T8)
5909 #define NVT_IS_CTA861_DID_T10(d) (NVT_GET_TIMING_STATUS_TYPE((d)) == NVT_TYPE_CTA861_DID_T10)
5910
5911 #define NVT_IS_DTD1(d) ((NVT_IS_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == 1))
5912 #define NVT_IS_DTDn(d, n) ((NVT_IS_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n))
5913 #define NVT_IS_EXT_DTDn(d, n) ((NVT_IS_EXT_DTD((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n))
5914 #define NVT_IS_CTA861_DID_T7n(d, n) ((NVT_IS_CTA861_DID_T7((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n))
5915 #define NVT_IS_CTA861_DID_T8_1(d) ((NVT_IS_CTA861_DID_T8((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == 1))
5916 #define NVT_IS_CTA861_DID_T10n(d, n) ((NVT_IS_CTA861_DID_T10((d))) && (NVT_GET_TIMING_STATUS_SEQ((d)) == n))
5917
5918 #define NVT_IS_CTA861_OVT_Tn(flag, status, n) ((0 != (NVT_FLAG_CTA_OVT_TIMING & (flag))) && (NVT_GET_TIMING_STATUS_SEQ((status)) == n))
5919
5920 #define NVT_DID20_TIMING_IS_CTA861(flag, status) ((NVT_IS_CTA861((status))) && (0 != (NVT_FLAG_DISPLAYID_2_0_TIMING & (flag))))
5921 #define NVT_PREFERRED_TIMING_IS_DTD1(flag, status) ((NVT_IS_DTD1((status))) && (0 != (NVT_FLAG_DTD1_PREFERRED_TIMING & (flag))))
5922 #define NVT_PREFERRED_TIMING_IS_DISPLAYID(flag) (0 != (NVT_FLAG_DISPLAYID_DTD_PREFERRED_TIMING & flag))
5923 #define NVT_PREFERRED_TIMING_IS_CTA(flag) (0 != (NVT_FLAG_CTA_PREFERRED_TIMING & flag))
5924 #define NVT_NATIVE_TIMING_IS_CTA(flag) (0 != (NVT_FLAG_CTA_NATIVE_TIMING & flag))
5925 #define NVT_TIMING_IS_OVT(flag) (0 != (NVT_FLAG_CTA_OVT_TIMING & flag))
5926 #define NVT_FRR_TIMING_IS_OVT(flag) (0 != (NVT_FLAG_CTA_OVT_FRR_TIMING & flag))
5927
5928 #ifdef __cplusplus
5929 }
5930 #endif
5931
5932 #endif //__NVTIMING_H__
5933