1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_tim.c
4 * @author MCD Application Team
5 * @brief TIM HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Timer (TIM) peripheral:
8 * + TIM Time Base Initialization
9 * + TIM Time Base Start
10 * + TIM Time Base Start Interruption
11 * + TIM Time Base Start DMA
12 * + TIM Output Compare/PWM Initialization
13 * + TIM Output Compare/PWM Channel Configuration
14 * + TIM Output Compare/PWM Start
15 * + TIM Output Compare/PWM Start Interruption
16 * + TIM Output Compare/PWM Start DMA
17 * + TIM Input Capture Initialization
18 * + TIM Input Capture Channel Configuration
19 * + TIM Input Capture Start
20 * + TIM Input Capture Start Interruption
21 * + TIM Input Capture Start DMA
22 * + TIM One Pulse Initialization
23 * + TIM One Pulse Channel Configuration
24 * + TIM One Pulse Start
25 * + TIM Encoder Interface Initialization
26 * + TIM Encoder Interface Start
27 * + TIM Encoder Interface Start Interruption
28 * + TIM Encoder Interface Start DMA
29 * + Commutation Event configuration with Interruption and DMA
30 * + TIM OCRef clear configuration
31 * + TIM External Clock configuration
32 @verbatim
33 ==============================================================================
34 ##### TIMER Generic features #####
35 ==============================================================================
36 [..] The Timer features include:
37 (#) 16-bit up, down, up/down auto-reload counter.
38 (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
39 counter clock frequency either by any factor between 1 and 65536.
40 (#) Up to 4 independent channels for:
41 (++) Input Capture
42 (++) Output Compare
43 (++) PWM generation (Edge and Center-aligned Mode)
44 (++) One-pulse mode output
45 (#) Synchronization circuit to control the timer with external signals and to interconnect
46 several timers together.
47 (#) Supports incremental encoder for positioning purposes
48
49 ##### How to use this driver #####
50 ==============================================================================
51 [..]
52 (#) Initialize the TIM low level resources by implementing the following functions
53 depending on the selected feature:
54 (++) Time Base : HAL_TIM_Base_MspInit()
55 (++) Input Capture : HAL_TIM_IC_MspInit()
56 (++) Output Compare : HAL_TIM_OC_MspInit()
57 (++) PWM generation : HAL_TIM_PWM_MspInit()
58 (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
59 (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
60
61 (#) Initialize the TIM low level resources :
62 (##) Enable the TIM interface clock using __HAL_RCC_TIMx_CLK_ENABLE();
63 (##) TIM pins configuration
64 (+++) Enable the clock for the TIM GPIOs using the following function:
65 __HAL_RCC_GPIOx_CLK_ENABLE();
66 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
67
68 (#) The external Clock can be configured, if needed (the default clock is the
69 internal clock from the APBx), using the following function:
70 HAL_TIM_ConfigClockSource, the clock configuration should be done before
71 any start function.
72
73 (#) Configure the TIM in the desired functioning mode using one of the
74 Initialization function of this driver:
75 (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
76 (++) HAL_TIM_OC_Init, HAL_TIM_OC_ConfigChannel and optionally HAL_TIMEx_OC_ConfigPulseOnCompare:
77 to use the Timer to generate an Output Compare signal.
78 (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
79 PWM signal.
80 (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
81 external signal.
82 (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
83 in One Pulse Mode.
84 (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
85
86 (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
87 (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
88 (++) Input Capture : HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
89 (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
90 (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
91 (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
92 (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
93
94 (#) The DMA Burst is managed with the two following functions:
95 HAL_TIM_DMABurst_WriteStart()
96 HAL_TIM_DMABurst_ReadStart()
97
98 *** Callback registration ***
99 =============================================
100
101 [..]
102 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
103 allows the user to configure dynamically the driver callbacks.
104
105 [..]
106 Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
107 @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
108 the Callback ID and a pointer to the user callback function.
109
110 [..]
111 Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
112 weak function.
113 @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
114 and the Callback ID.
115
116 [..]
117 These functions allow to register/unregister following callbacks:
118 (+) Base_MspInitCallback : TIM Base Msp Init Callback.
119 (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
120 (+) IC_MspInitCallback : TIM IC Msp Init Callback.
121 (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
122 (+) OC_MspInitCallback : TIM OC Msp Init Callback.
123 (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
124 (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
125 (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
126 (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
127 (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
128 (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
129 (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
130 (+) HallSensor_MspInitCallback : TIM Hall Sensor Msp Init Callback.
131 (+) HallSensor_MspDeInitCallback : TIM Hall Sensor Msp DeInit Callback.
132 (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
133 (+) PeriodElapsedHalfCpltCallback : TIM Period Elapsed half complete Callback.
134 (+) TriggerCallback : TIM Trigger Callback.
135 (+) TriggerHalfCpltCallback : TIM Trigger half complete Callback.
136 (+) IC_CaptureCallback : TIM Input Capture Callback.
137 (+) IC_CaptureHalfCpltCallback : TIM Input Capture half complete Callback.
138 (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
139 (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
140 (+) PWM_PulseFinishedHalfCpltCallback : TIM PWM Pulse Finished half complete Callback.
141 (+) ErrorCallback : TIM Error Callback.
142 (+) CommutationCallback : TIM Commutation Callback.
143 (+) CommutationHalfCpltCallback : TIM Commutation half complete Callback.
144 (+) BreakCallback : TIM Break Callback.
145 (+) Break2Callback : TIM Break2 Callback.
146 (+) EncoderIndexCallback : TIM Encoder Index Callback.
147 (+) DirectionChangeCallback : TIM Direction Change Callback
148 (+) IndexErrorCallback : TIM Index Error Callback.
149 (+) TransitionErrorCallback : TIM Transition Error Callback
150
151 [..]
152 By default, after the Init and when the state is HAL_TIM_STATE_RESET
153 all interrupt callbacks are set to the corresponding weak functions:
154 examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
155
156 [..]
157 Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
158 functionalities in the Init / DeInit only when these callbacks are null
159 (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
160 keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
161
162 [..]
163 Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
164 Exception done MspInit / MspDeInit that can be registered / unregistered
165 in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
166 thus registered(user) MspInit / DeInit callbacks can be used during the Init / DeInit.
167 In that case first register the MspInit/MspDeInit user callbacks
168 using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
169
170 [..]
171 When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
172 not defined, the callback registration feature is not available and all callbacks
173 are set to the corresponding weak functions.
174
175 @endverbatim
176 ******************************************************************************
177 * @attention
178 *
179 * <h2><center>© Copyright (c) 2019 STMicroelectronics.
180 * All rights reserved.</center></h2>
181 *
182 * This software component is licensed by ST under BSD 3-Clause license,
183 * the "License"; You may not use this file except in compliance with the
184 * License. You may obtain a copy of the License at:
185 * opensource.org/licenses/BSD-3-Clause
186 *
187 ******************************************************************************
188 */
189
190 /* Includes ------------------------------------------------------------------*/
191 #include "stm32g4xx_hal.h"
192
193 /** @addtogroup STM32G4xx_HAL_Driver
194 * @{
195 */
196
197 /** @defgroup TIM TIM
198 * @brief TIM HAL module driver
199 * @{
200 */
201
202 #ifdef HAL_TIM_MODULE_ENABLED
203
204 /* Private typedef -----------------------------------------------------------*/
205 /* Private define ------------------------------------------------------------*/
206 #define TIMx_AF2_OCRSEL TIM1_AF2_OCRSEL
207
208 /* Private macros ------------------------------------------------------------*/
209 /* Private variables ---------------------------------------------------------*/
210 /* Private function prototypes -----------------------------------------------*/
211 /** @addtogroup TIM_Private_Functions
212 * @{
213 */
214 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
215 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
216 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
217 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
218 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
219 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
220 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
221 uint32_t TIM_ICFilter);
222 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
223 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
224 uint32_t TIM_ICFilter);
225 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
226 uint32_t TIM_ICFilter);
227 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource);
228 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
229 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
230 static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
231 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
232 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
233 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
234 TIM_SlaveConfigTypeDef *sSlaveConfig);
235 /**
236 * @}
237 */
238 /* Exported functions --------------------------------------------------------*/
239
240 /** @defgroup TIM_Exported_Functions TIM Exported Functions
241 * @{
242 */
243
244 /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
245 * @brief Time Base functions
246 *
247 @verbatim
248 ==============================================================================
249 ##### Time Base functions #####
250 ==============================================================================
251 [..]
252 This section provides functions allowing to:
253 (+) Initialize and configure the TIM base.
254 (+) De-initialize the TIM base.
255 (+) Start the Time Base.
256 (+) Stop the Time Base.
257 (+) Start the Time Base and enable interrupt.
258 (+) Stop the Time Base and disable interrupt.
259 (+) Start the Time Base and enable DMA transfer.
260 (+) Stop the Time Base and disable DMA transfer.
261
262 @endverbatim
263 * @{
264 */
265 /**
266 * @brief Initializes the TIM Time base Unit according to the specified
267 * parameters in the TIM_HandleTypeDef and initialize the associated handle.
268 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
269 * requires a timer reset to avoid unexpected direction
270 * due to DIR bit readonly in center aligned mode.
271 * Ex: call @ref HAL_TIM_Base_DeInit() before HAL_TIM_Base_Init()
272 * @param htim TIM Base handle
273 * @retval HAL status
274 */
HAL_TIM_Base_Init(TIM_HandleTypeDef * htim)275 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
276 {
277 /* Check the TIM handle allocation */
278 if (htim == NULL)
279 {
280 return HAL_ERROR;
281 }
282
283 /* Check the parameters */
284 assert_param(IS_TIM_INSTANCE(htim->Instance));
285 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
286 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
287 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
288
289 if (htim->State == HAL_TIM_STATE_RESET)
290 {
291 /* Allocate lock resource and initialize it */
292 htim->Lock = HAL_UNLOCKED;
293
294 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
295 /* Reset interrupt callbacks to legacy weak callbacks */
296 TIM_ResetCallback(htim);
297
298 if (htim->Base_MspInitCallback == NULL)
299 {
300 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
301 }
302 /* Init the low level hardware : GPIO, CLOCK, NVIC */
303 htim->Base_MspInitCallback(htim);
304 #else
305 /* Init the low level hardware : GPIO, CLOCK, NVIC */
306 HAL_TIM_Base_MspInit(htim);
307 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
308 }
309
310 /* Set the TIM state */
311 htim->State = HAL_TIM_STATE_BUSY;
312
313 /* Set the Time Base configuration */
314 TIM_Base_SetConfig(htim->Instance, &htim->Init);
315
316 /* Initialize the DMA burst operation state */
317 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
318
319 /* Initialize the TIM channels state */
320 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
321 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
322
323 /* Initialize the TIM state*/
324 htim->State = HAL_TIM_STATE_READY;
325
326 return HAL_OK;
327 }
328
329 /**
330 * @brief DeInitializes the TIM Base peripheral
331 * @param htim TIM Base handle
332 * @retval HAL status
333 */
HAL_TIM_Base_DeInit(TIM_HandleTypeDef * htim)334 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
335 {
336 /* Check the parameters */
337 assert_param(IS_TIM_INSTANCE(htim->Instance));
338
339 htim->State = HAL_TIM_STATE_BUSY;
340
341 /* Disable the TIM Peripheral Clock */
342 __HAL_TIM_DISABLE(htim);
343
344 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
345 if (htim->Base_MspDeInitCallback == NULL)
346 {
347 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
348 }
349 /* DeInit the low level hardware */
350 htim->Base_MspDeInitCallback(htim);
351 #else
352 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
353 HAL_TIM_Base_MspDeInit(htim);
354 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
355
356 /* Change the DMA burst operation state */
357 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
358
359 /* Change the TIM channels state */
360 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
361 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
362
363 /* Change TIM state */
364 htim->State = HAL_TIM_STATE_RESET;
365
366 /* Release Lock */
367 __HAL_UNLOCK(htim);
368
369 return HAL_OK;
370 }
371
372 /**
373 * @brief Initializes the TIM Base MSP.
374 * @param htim TIM Base handle
375 * @retval None
376 */
HAL_TIM_Base_MspInit(TIM_HandleTypeDef * htim)377 __weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
378 {
379 /* Prevent unused argument(s) compilation warning */
380 UNUSED(htim);
381
382 /* NOTE : This function should not be modified, when the callback is needed,
383 the HAL_TIM_Base_MspInit could be implemented in the user file
384 */
385 }
386
387 /**
388 * @brief DeInitializes TIM Base MSP.
389 * @param htim TIM Base handle
390 * @retval None
391 */
HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef * htim)392 __weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
393 {
394 /* Prevent unused argument(s) compilation warning */
395 UNUSED(htim);
396
397 /* NOTE : This function should not be modified, when the callback is needed,
398 the HAL_TIM_Base_MspDeInit could be implemented in the user file
399 */
400 }
401
402
403 /**
404 * @brief Starts the TIM Base generation.
405 * @param htim TIM Base handle
406 * @retval HAL status
407 */
HAL_TIM_Base_Start(TIM_HandleTypeDef * htim)408 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
409 {
410 uint32_t tmpsmcr;
411
412 /* Check the parameters */
413 assert_param(IS_TIM_INSTANCE(htim->Instance));
414
415 /* Check the TIM state */
416 if (htim->State != HAL_TIM_STATE_READY)
417 {
418 return HAL_ERROR;
419 }
420
421 /* Set the TIM state */
422 htim->State = HAL_TIM_STATE_BUSY;
423
424 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
425 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
426 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
427 {
428 __HAL_TIM_ENABLE(htim);
429 }
430
431 /* Return function status */
432 return HAL_OK;
433 }
434
435 /**
436 * @brief Stops the TIM Base generation.
437 * @param htim TIM Base handle
438 * @retval HAL status
439 */
HAL_TIM_Base_Stop(TIM_HandleTypeDef * htim)440 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
441 {
442 /* Check the parameters */
443 assert_param(IS_TIM_INSTANCE(htim->Instance));
444
445 /* Disable the Peripheral */
446 __HAL_TIM_DISABLE(htim);
447
448 /* Set the TIM state */
449 htim->State = HAL_TIM_STATE_READY;
450
451 /* Return function status */
452 return HAL_OK;
453 }
454
455 /**
456 * @brief Starts the TIM Base generation in interrupt mode.
457 * @param htim TIM Base handle
458 * @retval HAL status
459 */
HAL_TIM_Base_Start_IT(TIM_HandleTypeDef * htim)460 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
461 {
462 uint32_t tmpsmcr;
463
464 /* Check the parameters */
465 assert_param(IS_TIM_INSTANCE(htim->Instance));
466
467 /* Check the TIM state */
468 if (htim->State != HAL_TIM_STATE_READY)
469 {
470 return HAL_ERROR;
471 }
472
473 /* Set the TIM state */
474 htim->State = HAL_TIM_STATE_BUSY;
475
476 /* Enable the TIM Update interrupt */
477 __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
478
479 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
480 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
481 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
482 {
483 __HAL_TIM_ENABLE(htim);
484 }
485
486 /* Return function status */
487 return HAL_OK;
488 }
489
490 /**
491 * @brief Stops the TIM Base generation in interrupt mode.
492 * @param htim TIM Base handle
493 * @retval HAL status
494 */
HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef * htim)495 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
496 {
497 /* Check the parameters */
498 assert_param(IS_TIM_INSTANCE(htim->Instance));
499
500 /* Disable the TIM Update interrupt */
501 __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
502
503 /* Disable the Peripheral */
504 __HAL_TIM_DISABLE(htim);
505
506 /* Set the TIM state */
507 htim->State = HAL_TIM_STATE_READY;
508
509 /* Return function status */
510 return HAL_OK;
511 }
512
513 /**
514 * @brief Starts the TIM Base generation in DMA mode.
515 * @param htim TIM Base handle
516 * @param pData The source Buffer address.
517 * @param Length The length of data to be transferred from memory to peripheral.
518 * @retval HAL status
519 */
HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef * htim,uint32_t * pData,uint16_t Length)520 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
521 {
522 uint32_t tmpsmcr;
523
524 /* Check the parameters */
525 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
526
527 /* Set the TIM state */
528 if (htim->State == HAL_TIM_STATE_BUSY)
529 {
530 return HAL_BUSY;
531 }
532 else if (htim->State == HAL_TIM_STATE_READY)
533 {
534 if ((pData == NULL) && (Length > 0U))
535 {
536 return HAL_ERROR;
537 }
538 else
539 {
540 htim->State = HAL_TIM_STATE_BUSY;
541 }
542 }
543 else
544 {
545 return HAL_ERROR;
546 }
547
548 /* Set the DMA Period elapsed callbacks */
549 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
550 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
551
552 /* Set the DMA error callback */
553 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
554
555 /* Enable the DMA channel */
556 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length) != HAL_OK)
557 {
558 return HAL_ERROR;
559 }
560
561 /* Enable the TIM Update DMA request */
562 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
563
564 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
565 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
566 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
567 {
568 __HAL_TIM_ENABLE(htim);
569 }
570
571 /* Return function status */
572 return HAL_OK;
573 }
574
575 /**
576 * @brief Stops the TIM Base generation in DMA mode.
577 * @param htim TIM Base handle
578 * @retval HAL status
579 */
HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef * htim)580 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
581 {
582 /* Check the parameters */
583 assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
584
585 /* Disable the TIM Update DMA request */
586 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
587
588 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
589
590 /* Disable the Peripheral */
591 __HAL_TIM_DISABLE(htim);
592
593 /* Set the TIM state */
594 htim->State = HAL_TIM_STATE_READY;
595
596 /* Return function status */
597 return HAL_OK;
598 }
599
600 /**
601 * @}
602 */
603
604 /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
605 * @brief TIM Output Compare functions
606 *
607 @verbatim
608 ==============================================================================
609 ##### TIM Output Compare functions #####
610 ==============================================================================
611 [..]
612 This section provides functions allowing to:
613 (+) Initialize and configure the TIM Output Compare.
614 (+) De-initialize the TIM Output Compare.
615 (+) Start the TIM Output Compare.
616 (+) Stop the TIM Output Compare.
617 (+) Start the TIM Output Compare and enable interrupt.
618 (+) Stop the TIM Output Compare and disable interrupt.
619 (+) Start the TIM Output Compare and enable DMA transfer.
620 (+) Stop the TIM Output Compare and disable DMA transfer.
621
622 @endverbatim
623 * @{
624 */
625 /**
626 * @brief Initializes the TIM Output Compare according to the specified
627 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
628 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
629 * requires a timer reset to avoid unexpected direction
630 * due to DIR bit readonly in center aligned mode.
631 * Ex: call @ref HAL_TIM_OC_DeInit() before HAL_TIM_OC_Init()
632 * @param htim TIM Output Compare handle
633 * @retval HAL status
634 */
HAL_TIM_OC_Init(TIM_HandleTypeDef * htim)635 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim)
636 {
637 /* Check the TIM handle allocation */
638 if (htim == NULL)
639 {
640 return HAL_ERROR;
641 }
642
643 /* Check the parameters */
644 assert_param(IS_TIM_INSTANCE(htim->Instance));
645 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
646 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
647 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
648
649 if (htim->State == HAL_TIM_STATE_RESET)
650 {
651 /* Allocate lock resource and initialize it */
652 htim->Lock = HAL_UNLOCKED;
653
654 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
655 /* Reset interrupt callbacks to legacy weak callbacks */
656 TIM_ResetCallback(htim);
657
658 if (htim->OC_MspInitCallback == NULL)
659 {
660 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit;
661 }
662 /* Init the low level hardware : GPIO, CLOCK, NVIC */
663 htim->OC_MspInitCallback(htim);
664 #else
665 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
666 HAL_TIM_OC_MspInit(htim);
667 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
668 }
669
670 /* Set the TIM state */
671 htim->State = HAL_TIM_STATE_BUSY;
672
673 /* Init the base time for the Output Compare */
674 TIM_Base_SetConfig(htim->Instance, &htim->Init);
675
676 /* Initialize the DMA burst operation state */
677 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
678
679 /* Initialize the TIM channels state */
680 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
681 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
682
683 /* Initialize the TIM state*/
684 htim->State = HAL_TIM_STATE_READY;
685
686 return HAL_OK;
687 }
688
689 /**
690 * @brief DeInitializes the TIM peripheral
691 * @param htim TIM Output Compare handle
692 * @retval HAL status
693 */
HAL_TIM_OC_DeInit(TIM_HandleTypeDef * htim)694 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
695 {
696 /* Check the parameters */
697 assert_param(IS_TIM_INSTANCE(htim->Instance));
698
699 htim->State = HAL_TIM_STATE_BUSY;
700
701 /* Disable the TIM Peripheral Clock */
702 __HAL_TIM_DISABLE(htim);
703
704 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
705 if (htim->OC_MspDeInitCallback == NULL)
706 {
707 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
708 }
709 /* DeInit the low level hardware */
710 htim->OC_MspDeInitCallback(htim);
711 #else
712 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
713 HAL_TIM_OC_MspDeInit(htim);
714 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
715
716 /* Change the DMA burst operation state */
717 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
718
719 /* Change the TIM channels state */
720 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
721 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
722
723 /* Change TIM state */
724 htim->State = HAL_TIM_STATE_RESET;
725
726 /* Release Lock */
727 __HAL_UNLOCK(htim);
728
729 return HAL_OK;
730 }
731
732 /**
733 * @brief Initializes the TIM Output Compare MSP.
734 * @param htim TIM Output Compare handle
735 * @retval None
736 */
HAL_TIM_OC_MspInit(TIM_HandleTypeDef * htim)737 __weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
738 {
739 /* Prevent unused argument(s) compilation warning */
740 UNUSED(htim);
741
742 /* NOTE : This function should not be modified, when the callback is needed,
743 the HAL_TIM_OC_MspInit could be implemented in the user file
744 */
745 }
746
747 /**
748 * @brief DeInitializes TIM Output Compare MSP.
749 * @param htim TIM Output Compare handle
750 * @retval None
751 */
HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef * htim)752 __weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
753 {
754 /* Prevent unused argument(s) compilation warning */
755 UNUSED(htim);
756
757 /* NOTE : This function should not be modified, when the callback is needed,
758 the HAL_TIM_OC_MspDeInit could be implemented in the user file
759 */
760 }
761
762 /**
763 * @brief Starts the TIM Output Compare signal generation.
764 * @param htim TIM Output Compare handle
765 * @param Channel TIM Channel to be enabled
766 * This parameter can be one of the following values:
767 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
768 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
769 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
770 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
771 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
772 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
773 * @retval HAL status
774 */
HAL_TIM_OC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)775 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
776 {
777 uint32_t tmpsmcr;
778
779 /* Check the parameters */
780 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
781
782 /* Check the TIM channel state */
783 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
784 {
785 return HAL_ERROR;
786 }
787
788 /* Set the TIM channel state */
789 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
790
791 /* Enable the Output compare channel */
792 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
793
794 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
795 {
796 /* Enable the main output */
797 __HAL_TIM_MOE_ENABLE(htim);
798 }
799
800 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
801 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
802 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
803 {
804 __HAL_TIM_ENABLE(htim);
805 }
806
807 /* Return function status */
808 return HAL_OK;
809 }
810
811 /**
812 * @brief Stops the TIM Output Compare signal generation.
813 * @param htim TIM Output Compare handle
814 * @param Channel TIM Channel to be disabled
815 * This parameter can be one of the following values:
816 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
817 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
818 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
819 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
820 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
821 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
822 * @retval HAL status
823 */
HAL_TIM_OC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)824 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
825 {
826 /* Check the parameters */
827 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
828
829 /* Disable the Output compare channel */
830 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
831
832 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
833 {
834 /* Disable the Main Output */
835 __HAL_TIM_MOE_DISABLE(htim);
836 }
837
838 /* Disable the Peripheral */
839 __HAL_TIM_DISABLE(htim);
840
841 /* Set the TIM channel state */
842 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
843
844 /* Return function status */
845 return HAL_OK;
846 }
847
848 /**
849 * @brief Starts the TIM Output Compare signal generation in interrupt mode.
850 * @param htim TIM Output Compare handle
851 * @param Channel TIM Channel to be enabled
852 * This parameter can be one of the following values:
853 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
854 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
855 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
856 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
857 * @retval HAL status
858 */
HAL_TIM_OC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)859 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
860 {
861 uint32_t tmpsmcr;
862
863 /* Check the parameters */
864 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
865
866 /* Check the TIM channel state */
867 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
868 {
869 return HAL_ERROR;
870 }
871
872 /* Set the TIM channel state */
873 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
874
875 switch (Channel)
876 {
877 case TIM_CHANNEL_1:
878 {
879 /* Enable the TIM Capture/Compare 1 interrupt */
880 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
881 break;
882 }
883
884 case TIM_CHANNEL_2:
885 {
886 /* Enable the TIM Capture/Compare 2 interrupt */
887 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
888 break;
889 }
890
891 case TIM_CHANNEL_3:
892 {
893 /* Enable the TIM Capture/Compare 3 interrupt */
894 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
895 break;
896 }
897
898 case TIM_CHANNEL_4:
899 {
900 /* Enable the TIM Capture/Compare 4 interrupt */
901 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
902 break;
903 }
904
905 default:
906 break;
907 }
908
909 /* Enable the Output compare channel */
910 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
911
912 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
913 {
914 /* Enable the main output */
915 __HAL_TIM_MOE_ENABLE(htim);
916 }
917
918 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
919 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
920 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
921 {
922 __HAL_TIM_ENABLE(htim);
923 }
924
925 /* Return function status */
926 return HAL_OK;
927 }
928
929 /**
930 * @brief Stops the TIM Output Compare signal generation in interrupt mode.
931 * @param htim TIM Output Compare handle
932 * @param Channel TIM Channel to be disabled
933 * This parameter can be one of the following values:
934 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
935 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
936 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
937 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
938 * @retval HAL status
939 */
HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)940 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
941 {
942 /* Check the parameters */
943 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
944
945 switch (Channel)
946 {
947 case TIM_CHANNEL_1:
948 {
949 /* Disable the TIM Capture/Compare 1 interrupt */
950 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
951 break;
952 }
953
954 case TIM_CHANNEL_2:
955 {
956 /* Disable the TIM Capture/Compare 2 interrupt */
957 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
958 break;
959 }
960
961 case TIM_CHANNEL_3:
962 {
963 /* Disable the TIM Capture/Compare 3 interrupt */
964 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
965 break;
966 }
967
968 case TIM_CHANNEL_4:
969 {
970 /* Disable the TIM Capture/Compare 4 interrupt */
971 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
972 break;
973 }
974
975 default:
976 break;
977 }
978
979 /* Disable the Output compare channel */
980 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
981
982 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
983 {
984 /* Disable the Main Output */
985 __HAL_TIM_MOE_DISABLE(htim);
986 }
987
988 /* Disable the Peripheral */
989 __HAL_TIM_DISABLE(htim);
990
991 /* Set the TIM channel state */
992 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
993
994 /* Return function status */
995 return HAL_OK;
996 }
997
998 /**
999 * @brief Starts the TIM Output Compare signal generation in DMA mode.
1000 * @param htim TIM Output Compare handle
1001 * @param Channel TIM Channel to be enabled
1002 * This parameter can be one of the following values:
1003 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1004 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1005 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1006 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1007 * @param pData The source Buffer address.
1008 * @param Length The length of data to be transferred from memory to TIM peripheral
1009 * @retval HAL status
1010 */
HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1011 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1012 {
1013 uint32_t tmpsmcr;
1014
1015 /* Check the parameters */
1016 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1017
1018 /* Set the TIM channel state */
1019 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1020 {
1021 return HAL_BUSY;
1022 }
1023 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1024 {
1025 if ((pData == NULL) && (Length > 0U))
1026 {
1027 return HAL_ERROR;
1028 }
1029 else
1030 {
1031 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1032 }
1033 }
1034 else
1035 {
1036 return HAL_ERROR;
1037 }
1038
1039 switch (Channel)
1040 {
1041 case TIM_CHANNEL_1:
1042 {
1043 /* Set the DMA compare callbacks */
1044 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1045 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1046
1047 /* Set the DMA error callback */
1048 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1049
1050 /* Enable the DMA channel */
1051 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
1052 {
1053 return HAL_ERROR;
1054 }
1055
1056 /* Enable the TIM Capture/Compare 1 DMA request */
1057 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1058 break;
1059 }
1060
1061 case TIM_CHANNEL_2:
1062 {
1063 /* Set the DMA compare callbacks */
1064 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1065 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1066
1067 /* Set the DMA error callback */
1068 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1069
1070 /* Enable the DMA channel */
1071 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
1072 {
1073 return HAL_ERROR;
1074 }
1075
1076 /* Enable the TIM Capture/Compare 2 DMA request */
1077 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1078 break;
1079 }
1080
1081 case TIM_CHANNEL_3:
1082 {
1083 /* Set the DMA compare callbacks */
1084 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1085 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1086
1087 /* Set the DMA error callback */
1088 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1089
1090 /* Enable the DMA channel */
1091 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1092 {
1093 return HAL_ERROR;
1094 }
1095 /* Enable the TIM Capture/Compare 3 DMA request */
1096 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1097 break;
1098 }
1099
1100 case TIM_CHANNEL_4:
1101 {
1102 /* Set the DMA compare callbacks */
1103 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1104 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1105
1106 /* Set the DMA error callback */
1107 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1108
1109 /* Enable the DMA channel */
1110 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1111 {
1112 return HAL_ERROR;
1113 }
1114 /* Enable the TIM Capture/Compare 4 DMA request */
1115 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1116 break;
1117 }
1118
1119 default:
1120 break;
1121 }
1122
1123 /* Enable the Output compare channel */
1124 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1125
1126 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1127 {
1128 /* Enable the main output */
1129 __HAL_TIM_MOE_ENABLE(htim);
1130 }
1131
1132 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1133 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1134 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1135 {
1136 __HAL_TIM_ENABLE(htim);
1137 }
1138
1139 /* Return function status */
1140 return HAL_OK;
1141 }
1142
1143 /**
1144 * @brief Stops the TIM Output Compare signal generation in DMA mode.
1145 * @param htim TIM Output Compare handle
1146 * @param Channel TIM Channel to be disabled
1147 * This parameter can be one of the following values:
1148 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1149 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1150 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1151 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1152 * @retval HAL status
1153 */
HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1154 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1155 {
1156 /* Check the parameters */
1157 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1158
1159 switch (Channel)
1160 {
1161 case TIM_CHANNEL_1:
1162 {
1163 /* Disable the TIM Capture/Compare 1 DMA request */
1164 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1165 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1166 break;
1167 }
1168
1169 case TIM_CHANNEL_2:
1170 {
1171 /* Disable the TIM Capture/Compare 2 DMA request */
1172 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1173 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1174 break;
1175 }
1176
1177 case TIM_CHANNEL_3:
1178 {
1179 /* Disable the TIM Capture/Compare 3 DMA request */
1180 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1181 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1182 break;
1183 }
1184
1185 case TIM_CHANNEL_4:
1186 {
1187 /* Disable the TIM Capture/Compare 4 interrupt */
1188 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1189 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1190 break;
1191 }
1192
1193 default:
1194 break;
1195 }
1196
1197 /* Disable the Output compare channel */
1198 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1199
1200 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1201 {
1202 /* Disable the Main Output */
1203 __HAL_TIM_MOE_DISABLE(htim);
1204 }
1205
1206 /* Disable the Peripheral */
1207 __HAL_TIM_DISABLE(htim);
1208
1209 /* Set the TIM channel state */
1210 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1211
1212 /* Return function status */
1213 return HAL_OK;
1214 }
1215
1216 /**
1217 * @}
1218 */
1219
1220 /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
1221 * @brief TIM PWM functions
1222 *
1223 @verbatim
1224 ==============================================================================
1225 ##### TIM PWM functions #####
1226 ==============================================================================
1227 [..]
1228 This section provides functions allowing to:
1229 (+) Initialize and configure the TIM PWM.
1230 (+) De-initialize the TIM PWM.
1231 (+) Start the TIM PWM.
1232 (+) Stop the TIM PWM.
1233 (+) Start the TIM PWM and enable interrupt.
1234 (+) Stop the TIM PWM and disable interrupt.
1235 (+) Start the TIM PWM and enable DMA transfer.
1236 (+) Stop the TIM PWM and disable DMA transfer.
1237
1238 @endverbatim
1239 * @{
1240 */
1241 /**
1242 * @brief Initializes the TIM PWM Time Base according to the specified
1243 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1244 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1245 * requires a timer reset to avoid unexpected direction
1246 * due to DIR bit readonly in center aligned mode.
1247 * Ex: call @ref HAL_TIM_PWM_DeInit() before HAL_TIM_PWM_Init()
1248 * @param htim TIM PWM handle
1249 * @retval HAL status
1250 */
HAL_TIM_PWM_Init(TIM_HandleTypeDef * htim)1251 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
1252 {
1253 /* Check the TIM handle allocation */
1254 if (htim == NULL)
1255 {
1256 return HAL_ERROR;
1257 }
1258
1259 /* Check the parameters */
1260 assert_param(IS_TIM_INSTANCE(htim->Instance));
1261 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1262 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1263 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1264
1265 if (htim->State == HAL_TIM_STATE_RESET)
1266 {
1267 /* Allocate lock resource and initialize it */
1268 htim->Lock = HAL_UNLOCKED;
1269
1270 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1271 /* Reset interrupt callbacks to legacy weak callbacks */
1272 TIM_ResetCallback(htim);
1273
1274 if (htim->PWM_MspInitCallback == NULL)
1275 {
1276 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
1277 }
1278 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1279 htim->PWM_MspInitCallback(htim);
1280 #else
1281 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1282 HAL_TIM_PWM_MspInit(htim);
1283 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1284 }
1285
1286 /* Set the TIM state */
1287 htim->State = HAL_TIM_STATE_BUSY;
1288
1289 /* Init the base time for the PWM */
1290 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1291
1292 /* Initialize the DMA burst operation state */
1293 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1294
1295 /* Initialize the TIM channels state */
1296 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1297 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1298
1299 /* Initialize the TIM state*/
1300 htim->State = HAL_TIM_STATE_READY;
1301
1302 return HAL_OK;
1303 }
1304
1305 /**
1306 * @brief DeInitializes the TIM peripheral
1307 * @param htim TIM PWM handle
1308 * @retval HAL status
1309 */
HAL_TIM_PWM_DeInit(TIM_HandleTypeDef * htim)1310 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
1311 {
1312 /* Check the parameters */
1313 assert_param(IS_TIM_INSTANCE(htim->Instance));
1314
1315 htim->State = HAL_TIM_STATE_BUSY;
1316
1317 /* Disable the TIM Peripheral Clock */
1318 __HAL_TIM_DISABLE(htim);
1319
1320 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1321 if (htim->PWM_MspDeInitCallback == NULL)
1322 {
1323 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
1324 }
1325 /* DeInit the low level hardware */
1326 htim->PWM_MspDeInitCallback(htim);
1327 #else
1328 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1329 HAL_TIM_PWM_MspDeInit(htim);
1330 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1331
1332 /* Change the DMA burst operation state */
1333 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1334
1335 /* Change the TIM channels state */
1336 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1337 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1338
1339 /* Change TIM state */
1340 htim->State = HAL_TIM_STATE_RESET;
1341
1342 /* Release Lock */
1343 __HAL_UNLOCK(htim);
1344
1345 return HAL_OK;
1346 }
1347
1348 /**
1349 * @brief Initializes the TIM PWM MSP.
1350 * @param htim TIM PWM handle
1351 * @retval None
1352 */
HAL_TIM_PWM_MspInit(TIM_HandleTypeDef * htim)1353 __weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
1354 {
1355 /* Prevent unused argument(s) compilation warning */
1356 UNUSED(htim);
1357
1358 /* NOTE : This function should not be modified, when the callback is needed,
1359 the HAL_TIM_PWM_MspInit could be implemented in the user file
1360 */
1361 }
1362
1363 /**
1364 * @brief DeInitializes TIM PWM MSP.
1365 * @param htim TIM PWM handle
1366 * @retval None
1367 */
HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef * htim)1368 __weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
1369 {
1370 /* Prevent unused argument(s) compilation warning */
1371 UNUSED(htim);
1372
1373 /* NOTE : This function should not be modified, when the callback is needed,
1374 the HAL_TIM_PWM_MspDeInit could be implemented in the user file
1375 */
1376 }
1377
1378 /**
1379 * @brief Starts the PWM signal generation.
1380 * @param htim TIM handle
1381 * @param Channel TIM Channels to be enabled
1382 * This parameter can be one of the following values:
1383 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1384 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1385 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1386 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1387 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1388 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1389 * @retval HAL status
1390 */
HAL_TIM_PWM_Start(TIM_HandleTypeDef * htim,uint32_t Channel)1391 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
1392 {
1393 uint32_t tmpsmcr;
1394
1395 /* Check the parameters */
1396 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1397
1398 /* Check the TIM channel state */
1399 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1400 {
1401 return HAL_ERROR;
1402 }
1403
1404 /* Set the TIM channel state */
1405 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1406
1407 /* Enable the Capture compare channel */
1408 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1409
1410 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1411 {
1412 /* Enable the main output */
1413 __HAL_TIM_MOE_ENABLE(htim);
1414 }
1415
1416 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1417 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1418 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1419 {
1420 __HAL_TIM_ENABLE(htim);
1421 }
1422
1423 /* Return function status */
1424 return HAL_OK;
1425 }
1426
1427 /**
1428 * @brief Stops the PWM signal generation.
1429 * @param htim TIM PWM handle
1430 * @param Channel TIM Channels to be disabled
1431 * This parameter can be one of the following values:
1432 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1433 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1434 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1435 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1436 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
1437 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
1438 * @retval HAL status
1439 */
HAL_TIM_PWM_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)1440 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
1441 {
1442 /* Check the parameters */
1443 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1444
1445 /* Disable the Capture compare channel */
1446 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1447
1448 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1449 {
1450 /* Disable the Main Output */
1451 __HAL_TIM_MOE_DISABLE(htim);
1452 }
1453
1454 /* Disable the Peripheral */
1455 __HAL_TIM_DISABLE(htim);
1456
1457 /* Set the TIM channel state */
1458 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1459
1460 /* Return function status */
1461 return HAL_OK;
1462 }
1463
1464 /**
1465 * @brief Starts the PWM signal generation in interrupt mode.
1466 * @param htim TIM PWM handle
1467 * @param Channel TIM Channel to be enabled
1468 * This parameter can be one of the following values:
1469 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1470 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1471 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1472 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1473 * @retval HAL status
1474 */
HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1475 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1476 {
1477 uint32_t tmpsmcr;
1478 /* Check the parameters */
1479 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1480
1481 /* Check the TIM channel state */
1482 if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
1483 {
1484 return HAL_ERROR;
1485 }
1486
1487 /* Set the TIM channel state */
1488 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1489
1490 switch (Channel)
1491 {
1492 case TIM_CHANNEL_1:
1493 {
1494 /* Enable the TIM Capture/Compare 1 interrupt */
1495 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
1496 break;
1497 }
1498
1499 case TIM_CHANNEL_2:
1500 {
1501 /* Enable the TIM Capture/Compare 2 interrupt */
1502 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
1503 break;
1504 }
1505
1506 case TIM_CHANNEL_3:
1507 {
1508 /* Enable the TIM Capture/Compare 3 interrupt */
1509 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
1510 break;
1511 }
1512
1513 case TIM_CHANNEL_4:
1514 {
1515 /* Enable the TIM Capture/Compare 4 interrupt */
1516 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
1517 break;
1518 }
1519
1520 default:
1521 break;
1522 }
1523
1524 /* Enable the Capture compare channel */
1525 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1526
1527 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1528 {
1529 /* Enable the main output */
1530 __HAL_TIM_MOE_ENABLE(htim);
1531 }
1532
1533 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1534 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1535 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1536 {
1537 __HAL_TIM_ENABLE(htim);
1538 }
1539
1540 /* Return function status */
1541 return HAL_OK;
1542 }
1543
1544 /**
1545 * @brief Stops the PWM signal generation in interrupt mode.
1546 * @param htim TIM PWM handle
1547 * @param Channel TIM Channels to be disabled
1548 * This parameter can be one of the following values:
1549 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1550 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1551 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1552 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1553 * @retval HAL status
1554 */
HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)1555 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
1556 {
1557 /* Check the parameters */
1558 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1559
1560 switch (Channel)
1561 {
1562 case TIM_CHANNEL_1:
1563 {
1564 /* Disable the TIM Capture/Compare 1 interrupt */
1565 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
1566 break;
1567 }
1568
1569 case TIM_CHANNEL_2:
1570 {
1571 /* Disable the TIM Capture/Compare 2 interrupt */
1572 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
1573 break;
1574 }
1575
1576 case TIM_CHANNEL_3:
1577 {
1578 /* Disable the TIM Capture/Compare 3 interrupt */
1579 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
1580 break;
1581 }
1582
1583 case TIM_CHANNEL_4:
1584 {
1585 /* Disable the TIM Capture/Compare 4 interrupt */
1586 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
1587 break;
1588 }
1589
1590 default:
1591 break;
1592 }
1593
1594 /* Disable the Capture compare channel */
1595 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1596
1597 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1598 {
1599 /* Disable the Main Output */
1600 __HAL_TIM_MOE_DISABLE(htim);
1601 }
1602
1603 /* Disable the Peripheral */
1604 __HAL_TIM_DISABLE(htim);
1605
1606 /* Set the TIM channel state */
1607 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1608
1609 /* Return function status */
1610 return HAL_OK;
1611 }
1612
1613 /**
1614 * @brief Starts the TIM PWM signal generation in DMA mode.
1615 * @param htim TIM PWM handle
1616 * @param Channel TIM Channels to be enabled
1617 * This parameter can be one of the following values:
1618 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1619 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1620 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1621 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1622 * @param pData The source Buffer address.
1623 * @param Length The length of data to be transferred from memory to TIM peripheral
1624 * @retval HAL status
1625 */
HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)1626 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
1627 {
1628 uint32_t tmpsmcr;
1629
1630 /* Check the parameters */
1631 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1632
1633 /* Set the TIM channel state */
1634 if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
1635 {
1636 return HAL_BUSY;
1637 }
1638 else if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_READY)
1639 {
1640 if ((pData == NULL) && (Length > 0U))
1641 {
1642 return HAL_ERROR;
1643 }
1644 else
1645 {
1646 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
1647 }
1648 }
1649 else
1650 {
1651 return HAL_ERROR;
1652 }
1653
1654 switch (Channel)
1655 {
1656 case TIM_CHANNEL_1:
1657 {
1658 /* Set the DMA compare callbacks */
1659 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
1660 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1661
1662 /* Set the DMA error callback */
1663 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
1664
1665 /* Enable the DMA channel */
1666 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length) != HAL_OK)
1667 {
1668 return HAL_ERROR;
1669 }
1670
1671 /* Enable the TIM Capture/Compare 1 DMA request */
1672 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
1673 break;
1674 }
1675
1676 case TIM_CHANNEL_2:
1677 {
1678 /* Set the DMA compare callbacks */
1679 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
1680 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1681
1682 /* Set the DMA error callback */
1683 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
1684
1685 /* Enable the DMA channel */
1686 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length) != HAL_OK)
1687 {
1688 return HAL_ERROR;
1689 }
1690 /* Enable the TIM Capture/Compare 2 DMA request */
1691 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
1692 break;
1693 }
1694
1695 case TIM_CHANNEL_3:
1696 {
1697 /* Set the DMA compare callbacks */
1698 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
1699 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1700
1701 /* Set the DMA error callback */
1702 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
1703
1704 /* Enable the DMA channel */
1705 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3, Length) != HAL_OK)
1706 {
1707 return HAL_ERROR;
1708 }
1709 /* Enable the TIM Output Capture/Compare 3 request */
1710 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
1711 break;
1712 }
1713
1714 case TIM_CHANNEL_4:
1715 {
1716 /* Set the DMA compare callbacks */
1717 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
1718 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
1719
1720 /* Set the DMA error callback */
1721 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
1722
1723 /* Enable the DMA channel */
1724 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length) != HAL_OK)
1725 {
1726 return HAL_ERROR;
1727 }
1728 /* Enable the TIM Capture/Compare 4 DMA request */
1729 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
1730 break;
1731 }
1732
1733 default:
1734 break;
1735 }
1736
1737 /* Enable the Capture compare channel */
1738 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
1739
1740 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1741 {
1742 /* Enable the main output */
1743 __HAL_TIM_MOE_ENABLE(htim);
1744 }
1745
1746 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
1747 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
1748 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
1749 {
1750 __HAL_TIM_ENABLE(htim);
1751 }
1752
1753 /* Return function status */
1754 return HAL_OK;
1755 }
1756
1757 /**
1758 * @brief Stops the TIM PWM signal generation in DMA mode.
1759 * @param htim TIM PWM handle
1760 * @param Channel TIM Channels to be disabled
1761 * This parameter can be one of the following values:
1762 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1763 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1764 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1765 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1766 * @retval HAL status
1767 */
HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)1768 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
1769 {
1770 /* Check the parameters */
1771 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
1772
1773 switch (Channel)
1774 {
1775 case TIM_CHANNEL_1:
1776 {
1777 /* Disable the TIM Capture/Compare 1 DMA request */
1778 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
1779 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
1780 break;
1781 }
1782
1783 case TIM_CHANNEL_2:
1784 {
1785 /* Disable the TIM Capture/Compare 2 DMA request */
1786 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
1787 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
1788 break;
1789 }
1790
1791 case TIM_CHANNEL_3:
1792 {
1793 /* Disable the TIM Capture/Compare 3 DMA request */
1794 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
1795 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
1796 break;
1797 }
1798
1799 case TIM_CHANNEL_4:
1800 {
1801 /* Disable the TIM Capture/Compare 4 interrupt */
1802 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
1803 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
1804 break;
1805 }
1806
1807 default:
1808 break;
1809 }
1810
1811 /* Disable the Capture compare channel */
1812 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
1813
1814 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
1815 {
1816 /* Disable the Main Output */
1817 __HAL_TIM_MOE_DISABLE(htim);
1818 }
1819
1820 /* Disable the Peripheral */
1821 __HAL_TIM_DISABLE(htim);
1822
1823 /* Set the TIM channel state */
1824 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
1825
1826 /* Return function status */
1827 return HAL_OK;
1828 }
1829
1830 /**
1831 * @}
1832 */
1833
1834 /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
1835 * @brief TIM Input Capture functions
1836 *
1837 @verbatim
1838 ==============================================================================
1839 ##### TIM Input Capture functions #####
1840 ==============================================================================
1841 [..]
1842 This section provides functions allowing to:
1843 (+) Initialize and configure the TIM Input Capture.
1844 (+) De-initialize the TIM Input Capture.
1845 (+) Start the TIM Input Capture.
1846 (+) Stop the TIM Input Capture.
1847 (+) Start the TIM Input Capture and enable interrupt.
1848 (+) Stop the TIM Input Capture and disable interrupt.
1849 (+) Start the TIM Input Capture and enable DMA transfer.
1850 (+) Stop the TIM Input Capture and disable DMA transfer.
1851
1852 @endverbatim
1853 * @{
1854 */
1855 /**
1856 * @brief Initializes the TIM Input Capture Time base according to the specified
1857 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
1858 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
1859 * requires a timer reset to avoid unexpected direction
1860 * due to DIR bit readonly in center aligned mode.
1861 * Ex: call @ref HAL_TIM_IC_DeInit() before HAL_TIM_IC_Init()
1862 * @param htim TIM Input Capture handle
1863 * @retval HAL status
1864 */
HAL_TIM_IC_Init(TIM_HandleTypeDef * htim)1865 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
1866 {
1867 /* Check the TIM handle allocation */
1868 if (htim == NULL)
1869 {
1870 return HAL_ERROR;
1871 }
1872
1873 /* Check the parameters */
1874 assert_param(IS_TIM_INSTANCE(htim->Instance));
1875 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
1876 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
1877 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
1878
1879 if (htim->State == HAL_TIM_STATE_RESET)
1880 {
1881 /* Allocate lock resource and initialize it */
1882 htim->Lock = HAL_UNLOCKED;
1883
1884 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1885 /* Reset interrupt callbacks to legacy weak callbacks */
1886 TIM_ResetCallback(htim);
1887
1888 if (htim->IC_MspInitCallback == NULL)
1889 {
1890 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
1891 }
1892 /* Init the low level hardware : GPIO, CLOCK, NVIC */
1893 htim->IC_MspInitCallback(htim);
1894 #else
1895 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
1896 HAL_TIM_IC_MspInit(htim);
1897 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1898 }
1899
1900 /* Set the TIM state */
1901 htim->State = HAL_TIM_STATE_BUSY;
1902
1903 /* Init the base time for the input capture */
1904 TIM_Base_SetConfig(htim->Instance, &htim->Init);
1905
1906 /* Initialize the DMA burst operation state */
1907 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
1908
1909 /* Initialize the TIM channels state */
1910 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1911 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_READY);
1912
1913 /* Initialize the TIM state*/
1914 htim->State = HAL_TIM_STATE_READY;
1915
1916 return HAL_OK;
1917 }
1918
1919 /**
1920 * @brief DeInitializes the TIM peripheral
1921 * @param htim TIM Input Capture handle
1922 * @retval HAL status
1923 */
HAL_TIM_IC_DeInit(TIM_HandleTypeDef * htim)1924 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
1925 {
1926 /* Check the parameters */
1927 assert_param(IS_TIM_INSTANCE(htim->Instance));
1928
1929 htim->State = HAL_TIM_STATE_BUSY;
1930
1931 /* Disable the TIM Peripheral Clock */
1932 __HAL_TIM_DISABLE(htim);
1933
1934 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
1935 if (htim->IC_MspDeInitCallback == NULL)
1936 {
1937 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
1938 }
1939 /* DeInit the low level hardware */
1940 htim->IC_MspDeInitCallback(htim);
1941 #else
1942 /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
1943 HAL_TIM_IC_MspDeInit(htim);
1944 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
1945
1946 /* Change the DMA burst operation state */
1947 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
1948
1949 /* Change the TIM channels state */
1950 TIM_CHANNEL_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1951 TIM_CHANNEL_N_STATE_SET_ALL(htim, HAL_TIM_CHANNEL_STATE_RESET);
1952
1953 /* Change TIM state */
1954 htim->State = HAL_TIM_STATE_RESET;
1955
1956 /* Release Lock */
1957 __HAL_UNLOCK(htim);
1958
1959 return HAL_OK;
1960 }
1961
1962 /**
1963 * @brief Initializes the TIM Input Capture MSP.
1964 * @param htim TIM Input Capture handle
1965 * @retval None
1966 */
HAL_TIM_IC_MspInit(TIM_HandleTypeDef * htim)1967 __weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
1968 {
1969 /* Prevent unused argument(s) compilation warning */
1970 UNUSED(htim);
1971
1972 /* NOTE : This function should not be modified, when the callback is needed,
1973 the HAL_TIM_IC_MspInit could be implemented in the user file
1974 */
1975 }
1976
1977 /**
1978 * @brief DeInitializes TIM Input Capture MSP.
1979 * @param htim TIM handle
1980 * @retval None
1981 */
HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef * htim)1982 __weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
1983 {
1984 /* Prevent unused argument(s) compilation warning */
1985 UNUSED(htim);
1986
1987 /* NOTE : This function should not be modified, when the callback is needed,
1988 the HAL_TIM_IC_MspDeInit could be implemented in the user file
1989 */
1990 }
1991
1992 /**
1993 * @brief Starts the TIM Input Capture measurement.
1994 * @param htim TIM Input Capture handle
1995 * @param Channel TIM Channels to be enabled
1996 * This parameter can be one of the following values:
1997 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1998 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1999 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2000 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2001 * @retval HAL status
2002 */
HAL_TIM_IC_Start(TIM_HandleTypeDef * htim,uint32_t Channel)2003 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
2004 {
2005 uint32_t tmpsmcr;
2006 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2007 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2008
2009 /* Check the parameters */
2010 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2011
2012 /* Check the TIM channel state */
2013 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2014 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2015 {
2016 return HAL_ERROR;
2017 }
2018
2019 /* Set the TIM channel state */
2020 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2021 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2022
2023 /* Enable the Input Capture channel */
2024 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2025
2026 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2027 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2028 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2029 {
2030 __HAL_TIM_ENABLE(htim);
2031 }
2032
2033 /* Return function status */
2034 return HAL_OK;
2035 }
2036
2037 /**
2038 * @brief Stops the TIM Input Capture measurement.
2039 * @param htim TIM Input Capture handle
2040 * @param Channel TIM Channels to be disabled
2041 * This parameter can be one of the following values:
2042 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2043 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2044 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2045 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2046 * @retval HAL status
2047 */
HAL_TIM_IC_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)2048 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
2049 {
2050 /* Check the parameters */
2051 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2052
2053 /* Disable the Input Capture channel */
2054 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2055
2056 /* Disable the Peripheral */
2057 __HAL_TIM_DISABLE(htim);
2058
2059 /* Set the TIM channel state */
2060 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2061 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2062
2063 /* Return function status */
2064 return HAL_OK;
2065 }
2066
2067 /**
2068 * @brief Starts the TIM Input Capture measurement in interrupt mode.
2069 * @param htim TIM Input Capture handle
2070 * @param Channel TIM Channels to be enabled
2071 * This parameter can be one of the following values:
2072 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2073 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2074 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2075 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2076 * @retval HAL status
2077 */
HAL_TIM_IC_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2078 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2079 {
2080 uint32_t tmpsmcr;
2081 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2082 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2083
2084 /* Check the parameters */
2085 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2086
2087 /* Check the TIM channel state */
2088 if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
2089 || (complementary_channel_state != HAL_TIM_CHANNEL_STATE_READY))
2090 {
2091 return HAL_ERROR;
2092 }
2093
2094 /* Set the TIM channel state */
2095 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2096 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2097
2098 switch (Channel)
2099 {
2100 case TIM_CHANNEL_1:
2101 {
2102 /* Enable the TIM Capture/Compare 1 interrupt */
2103 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2104 break;
2105 }
2106
2107 case TIM_CHANNEL_2:
2108 {
2109 /* Enable the TIM Capture/Compare 2 interrupt */
2110 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2111 break;
2112 }
2113
2114 case TIM_CHANNEL_3:
2115 {
2116 /* Enable the TIM Capture/Compare 3 interrupt */
2117 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
2118 break;
2119 }
2120
2121 case TIM_CHANNEL_4:
2122 {
2123 /* Enable the TIM Capture/Compare 4 interrupt */
2124 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
2125 break;
2126 }
2127
2128 default:
2129 break;
2130 }
2131 /* Enable the Input Capture channel */
2132 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2133
2134 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2135 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2136 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2137 {
2138 __HAL_TIM_ENABLE(htim);
2139 }
2140
2141 /* Return function status */
2142 return HAL_OK;
2143 }
2144
2145 /**
2146 * @brief Stops the TIM Input Capture measurement in interrupt mode.
2147 * @param htim TIM Input Capture handle
2148 * @param Channel TIM Channels to be disabled
2149 * This parameter can be one of the following values:
2150 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2151 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2152 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2153 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2154 * @retval HAL status
2155 */
HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)2156 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
2157 {
2158 /* Check the parameters */
2159 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2160
2161 switch (Channel)
2162 {
2163 case TIM_CHANNEL_1:
2164 {
2165 /* Disable the TIM Capture/Compare 1 interrupt */
2166 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2167 break;
2168 }
2169
2170 case TIM_CHANNEL_2:
2171 {
2172 /* Disable the TIM Capture/Compare 2 interrupt */
2173 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2174 break;
2175 }
2176
2177 case TIM_CHANNEL_3:
2178 {
2179 /* Disable the TIM Capture/Compare 3 interrupt */
2180 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
2181 break;
2182 }
2183
2184 case TIM_CHANNEL_4:
2185 {
2186 /* Disable the TIM Capture/Compare 4 interrupt */
2187 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
2188 break;
2189 }
2190
2191 default:
2192 break;
2193 }
2194
2195 /* Disable the Input Capture channel */
2196 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2197
2198 /* Disable the Peripheral */
2199 __HAL_TIM_DISABLE(htim);
2200
2201 /* Set the TIM channel state */
2202 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2203 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2204
2205 /* Return function status */
2206 return HAL_OK;
2207 }
2208
2209 /**
2210 * @brief Starts the TIM Input Capture measurement in DMA mode.
2211 * @param htim TIM Input Capture handle
2212 * @param Channel TIM Channels to be enabled
2213 * This parameter can be one of the following values:
2214 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2215 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2216 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2217 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2218 * @param pData The destination Buffer address.
2219 * @param Length The length of data to be transferred from TIM peripheral to memory.
2220 * @retval HAL status
2221 */
HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData,uint16_t Length)2222 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
2223 {
2224 uint32_t tmpsmcr;
2225 HAL_TIM_ChannelStateTypeDef channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
2226 HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
2227
2228 /* Check the parameters */
2229 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2230 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2231
2232 /* Set the TIM channel state */
2233 if ((channel_state == HAL_TIM_CHANNEL_STATE_BUSY)
2234 || (complementary_channel_state == HAL_TIM_CHANNEL_STATE_BUSY))
2235 {
2236 return HAL_BUSY;
2237 }
2238 else if ((channel_state == HAL_TIM_CHANNEL_STATE_READY)
2239 && (complementary_channel_state == HAL_TIM_CHANNEL_STATE_READY))
2240 {
2241 if ((pData == NULL) && (Length > 0U))
2242 {
2243 return HAL_ERROR;
2244 }
2245 else
2246 {
2247 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2248 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_BUSY);
2249 }
2250 }
2251 else
2252 {
2253 return HAL_ERROR;
2254 }
2255
2256 switch (Channel)
2257 {
2258 case TIM_CHANNEL_1:
2259 {
2260 /* Set the DMA capture callbacks */
2261 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
2262 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2263
2264 /* Set the DMA error callback */
2265 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
2266
2267 /* Enable the DMA channel */
2268 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length) != HAL_OK)
2269 {
2270 return HAL_ERROR;
2271 }
2272 /* Enable the TIM Capture/Compare 1 DMA request */
2273 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
2274 break;
2275 }
2276
2277 case TIM_CHANNEL_2:
2278 {
2279 /* Set the DMA capture callbacks */
2280 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
2281 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2282
2283 /* Set the DMA error callback */
2284 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
2285
2286 /* Enable the DMA channel */
2287 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length) != HAL_OK)
2288 {
2289 return HAL_ERROR;
2290 }
2291 /* Enable the TIM Capture/Compare 2 DMA request */
2292 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
2293 break;
2294 }
2295
2296 case TIM_CHANNEL_3:
2297 {
2298 /* Set the DMA capture callbacks */
2299 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
2300 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2301
2302 /* Set the DMA error callback */
2303 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
2304
2305 /* Enable the DMA channel */
2306 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length) != HAL_OK)
2307 {
2308 return HAL_ERROR;
2309 }
2310 /* Enable the TIM Capture/Compare 3 DMA request */
2311 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
2312 break;
2313 }
2314
2315 case TIM_CHANNEL_4:
2316 {
2317 /* Set the DMA capture callbacks */
2318 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
2319 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
2320
2321 /* Set the DMA error callback */
2322 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
2323
2324 /* Enable the DMA channel */
2325 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length) != HAL_OK)
2326 {
2327 return HAL_ERROR;
2328 }
2329 /* Enable the TIM Capture/Compare 4 DMA request */
2330 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
2331 break;
2332 }
2333
2334 default:
2335 break;
2336 }
2337
2338 /* Enable the Input Capture channel */
2339 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
2340
2341 /* Enable the Peripheral, except in trigger mode where enable is automatically done with trigger */
2342 tmpsmcr = htim->Instance->SMCR & TIM_SMCR_SMS;
2343 if (!IS_TIM_SLAVEMODE_TRIGGER_ENABLED(tmpsmcr))
2344 {
2345 __HAL_TIM_ENABLE(htim);
2346 }
2347
2348 /* Return function status */
2349 return HAL_OK;
2350 }
2351
2352 /**
2353 * @brief Stops the TIM Input Capture measurement in DMA mode.
2354 * @param htim TIM Input Capture handle
2355 * @param Channel TIM Channels to be disabled
2356 * This parameter can be one of the following values:
2357 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2358 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2359 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
2360 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
2361 * @retval HAL status
2362 */
HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)2363 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
2364 {
2365 /* Check the parameters */
2366 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
2367 assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
2368
2369 switch (Channel)
2370 {
2371 case TIM_CHANNEL_1:
2372 {
2373 /* Disable the TIM Capture/Compare 1 DMA request */
2374 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
2375 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
2376 break;
2377 }
2378
2379 case TIM_CHANNEL_2:
2380 {
2381 /* Disable the TIM Capture/Compare 2 DMA request */
2382 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
2383 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
2384 break;
2385 }
2386
2387 case TIM_CHANNEL_3:
2388 {
2389 /* Disable the TIM Capture/Compare 3 DMA request */
2390 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
2391 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
2392 break;
2393 }
2394
2395 case TIM_CHANNEL_4:
2396 {
2397 /* Disable the TIM Capture/Compare 4 DMA request */
2398 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
2399 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
2400 break;
2401 }
2402
2403 default:
2404 break;
2405 }
2406
2407 /* Disable the Input Capture channel */
2408 TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
2409
2410 /* Disable the Peripheral */
2411 __HAL_TIM_DISABLE(htim);
2412
2413 /* Set the TIM channel state */
2414 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2415 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
2416
2417 /* Return function status */
2418 return HAL_OK;
2419 }
2420 /**
2421 * @}
2422 */
2423
2424 /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
2425 * @brief TIM One Pulse functions
2426 *
2427 @verbatim
2428 ==============================================================================
2429 ##### TIM One Pulse functions #####
2430 ==============================================================================
2431 [..]
2432 This section provides functions allowing to:
2433 (+) Initialize and configure the TIM One Pulse.
2434 (+) De-initialize the TIM One Pulse.
2435 (+) Start the TIM One Pulse.
2436 (+) Stop the TIM One Pulse.
2437 (+) Start the TIM One Pulse and enable interrupt.
2438 (+) Stop the TIM One Pulse and disable interrupt.
2439 (+) Start the TIM One Pulse and enable DMA transfer.
2440 (+) Stop the TIM One Pulse and disable DMA transfer.
2441
2442 @endverbatim
2443 * @{
2444 */
2445 /**
2446 * @brief Initializes the TIM One Pulse Time Base according to the specified
2447 * parameters in the TIM_HandleTypeDef and initializes the associated handle.
2448 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2449 * requires a timer reset to avoid unexpected direction
2450 * due to DIR bit readonly in center aligned mode.
2451 * Ex: call @ref HAL_TIM_OnePulse_DeInit() before HAL_TIM_OnePulse_Init()
2452 * @note When the timer instance is initialized in One Pulse mode, timer
2453 * channels 1 and channel 2 are reserved and cannot be used for other
2454 * purpose.
2455 * @param htim TIM One Pulse handle
2456 * @param OnePulseMode Select the One pulse mode.
2457 * This parameter can be one of the following values:
2458 * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
2459 * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
2460 * @retval HAL status
2461 */
HAL_TIM_OnePulse_Init(TIM_HandleTypeDef * htim,uint32_t OnePulseMode)2462 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
2463 {
2464 /* Check the TIM handle allocation */
2465 if (htim == NULL)
2466 {
2467 return HAL_ERROR;
2468 }
2469
2470 /* Check the parameters */
2471 assert_param(IS_TIM_INSTANCE(htim->Instance));
2472 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2473 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2474 assert_param(IS_TIM_OPM_MODE(OnePulseMode));
2475 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2476
2477 if (htim->State == HAL_TIM_STATE_RESET)
2478 {
2479 /* Allocate lock resource and initialize it */
2480 htim->Lock = HAL_UNLOCKED;
2481
2482 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2483 /* Reset interrupt callbacks to legacy weak callbacks */
2484 TIM_ResetCallback(htim);
2485
2486 if (htim->OnePulse_MspInitCallback == NULL)
2487 {
2488 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit;
2489 }
2490 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2491 htim->OnePulse_MspInitCallback(htim);
2492 #else
2493 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2494 HAL_TIM_OnePulse_MspInit(htim);
2495 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2496 }
2497
2498 /* Set the TIM state */
2499 htim->State = HAL_TIM_STATE_BUSY;
2500
2501 /* Configure the Time base in the One Pulse Mode */
2502 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2503
2504 /* Reset the OPM Bit */
2505 htim->Instance->CR1 &= ~TIM_CR1_OPM;
2506
2507 /* Configure the OPM Mode */
2508 htim->Instance->CR1 |= OnePulseMode;
2509
2510 /* Initialize the DMA burst operation state */
2511 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2512
2513 /* Initialize the TIM channels state */
2514 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2515 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2516 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2517 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2518
2519 /* Initialize the TIM state*/
2520 htim->State = HAL_TIM_STATE_READY;
2521
2522 return HAL_OK;
2523 }
2524
2525 /**
2526 * @brief DeInitializes the TIM One Pulse
2527 * @param htim TIM One Pulse handle
2528 * @retval HAL status
2529 */
HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef * htim)2530 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
2531 {
2532 /* Check the parameters */
2533 assert_param(IS_TIM_INSTANCE(htim->Instance));
2534
2535 htim->State = HAL_TIM_STATE_BUSY;
2536
2537 /* Disable the TIM Peripheral Clock */
2538 __HAL_TIM_DISABLE(htim);
2539
2540 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2541 if (htim->OnePulse_MspDeInitCallback == NULL)
2542 {
2543 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
2544 }
2545 /* DeInit the low level hardware */
2546 htim->OnePulse_MspDeInitCallback(htim);
2547 #else
2548 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2549 HAL_TIM_OnePulse_MspDeInit(htim);
2550 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2551
2552 /* Change the DMA burst operation state */
2553 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2554
2555 /* Set the TIM channel state */
2556 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2557 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2558 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2559 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2560
2561 /* Change TIM state */
2562 htim->State = HAL_TIM_STATE_RESET;
2563
2564 /* Release Lock */
2565 __HAL_UNLOCK(htim);
2566
2567 return HAL_OK;
2568 }
2569
2570 /**
2571 * @brief Initializes the TIM One Pulse MSP.
2572 * @param htim TIM One Pulse handle
2573 * @retval None
2574 */
HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef * htim)2575 __weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
2576 {
2577 /* Prevent unused argument(s) compilation warning */
2578 UNUSED(htim);
2579
2580 /* NOTE : This function should not be modified, when the callback is needed,
2581 the HAL_TIM_OnePulse_MspInit could be implemented in the user file
2582 */
2583 }
2584
2585 /**
2586 * @brief DeInitializes TIM One Pulse MSP.
2587 * @param htim TIM One Pulse handle
2588 * @retval None
2589 */
HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef * htim)2590 __weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
2591 {
2592 /* Prevent unused argument(s) compilation warning */
2593 UNUSED(htim);
2594
2595 /* NOTE : This function should not be modified, when the callback is needed,
2596 the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
2597 */
2598 }
2599
2600 /**
2601 * @brief Starts the TIM One Pulse signal generation.
2602 * @param htim TIM One Pulse handle
2603 * @param OutputChannel TIM Channels to be enabled
2604 * This parameter can be one of the following values:
2605 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2606 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2607 * @retval HAL status
2608 */
HAL_TIM_OnePulse_Start(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2609 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2610 {
2611 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2612 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2613 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2614 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2615
2616 /* Prevent unused argument(s) compilation warning */
2617 UNUSED(OutputChannel);
2618
2619 /* Check the TIM channels state */
2620 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2621 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2622 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2623 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2624 {
2625 return HAL_ERROR;
2626 }
2627
2628 /* Set the TIM channels state */
2629 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2630 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2631 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2632 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2633
2634 /* Enable the Capture compare and the Input Capture channels
2635 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2636 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2637 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2638 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2639
2640 No need to enable the counter, it's enabled automatically by hardware
2641 (the counter starts in response to a stimulus and generate a pulse */
2642
2643 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2644 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2645
2646 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2647 {
2648 /* Enable the main output */
2649 __HAL_TIM_MOE_ENABLE(htim);
2650 }
2651
2652 /* Return function status */
2653 return HAL_OK;
2654 }
2655
2656 /**
2657 * @brief Stops the TIM One Pulse signal generation.
2658 * @param htim TIM One Pulse handle
2659 * @param OutputChannel TIM Channels to be disable
2660 * This parameter can be one of the following values:
2661 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2662 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2663 * @retval HAL status
2664 */
HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2665 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2666 {
2667 /* Prevent unused argument(s) compilation warning */
2668 UNUSED(OutputChannel);
2669
2670 /* Disable the Capture compare and the Input Capture channels
2671 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2672 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2673 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2674 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2675
2676 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2677 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2678
2679 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2680 {
2681 /* Disable the Main Output */
2682 __HAL_TIM_MOE_DISABLE(htim);
2683 }
2684
2685 /* Disable the Peripheral */
2686 __HAL_TIM_DISABLE(htim);
2687
2688 /* Set the TIM channels state */
2689 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2690 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2691 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2692 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2693
2694 /* Return function status */
2695 return HAL_OK;
2696 }
2697
2698 /**
2699 * @brief Starts the TIM One Pulse signal generation in interrupt mode.
2700 * @param htim TIM One Pulse handle
2701 * @param OutputChannel TIM Channels to be enabled
2702 * This parameter can be one of the following values:
2703 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2704 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2705 * @retval HAL status
2706 */
HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2707 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2708 {
2709 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
2710 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
2711 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
2712 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
2713
2714 /* Prevent unused argument(s) compilation warning */
2715 UNUSED(OutputChannel);
2716
2717 /* Check the TIM channels state */
2718 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2719 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
2720 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
2721 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
2722 {
2723 return HAL_ERROR;
2724 }
2725
2726 /* Set the TIM channels state */
2727 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2728 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2729 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
2730 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
2731
2732 /* Enable the Capture compare and the Input Capture channels
2733 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2734 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2735 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2736 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
2737
2738 No need to enable the counter, it's enabled automatically by hardware
2739 (the counter starts in response to a stimulus and generate a pulse */
2740
2741 /* Enable the TIM Capture/Compare 1 interrupt */
2742 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
2743
2744 /* Enable the TIM Capture/Compare 2 interrupt */
2745 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
2746
2747 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
2748 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
2749
2750 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2751 {
2752 /* Enable the main output */
2753 __HAL_TIM_MOE_ENABLE(htim);
2754 }
2755
2756 /* Return function status */
2757 return HAL_OK;
2758 }
2759
2760 /**
2761 * @brief Stops the TIM One Pulse signal generation in interrupt mode.
2762 * @param htim TIM One Pulse handle
2763 * @param OutputChannel TIM Channels to be enabled
2764 * This parameter can be one of the following values:
2765 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
2766 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
2767 * @retval HAL status
2768 */
HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef * htim,uint32_t OutputChannel)2769 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
2770 {
2771 /* Prevent unused argument(s) compilation warning */
2772 UNUSED(OutputChannel);
2773
2774 /* Disable the TIM Capture/Compare 1 interrupt */
2775 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
2776
2777 /* Disable the TIM Capture/Compare 2 interrupt */
2778 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
2779
2780 /* Disable the Capture compare and the Input Capture channels
2781 (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
2782 if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
2783 if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
2784 in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
2785 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
2786 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
2787
2788 if (IS_TIM_BREAK_INSTANCE(htim->Instance) != RESET)
2789 {
2790 /* Disable the Main Output */
2791 __HAL_TIM_MOE_DISABLE(htim);
2792 }
2793
2794 /* Disable the Peripheral */
2795 __HAL_TIM_DISABLE(htim);
2796
2797 /* Set the TIM channels state */
2798 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2799 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2800 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2801 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2802
2803 /* Return function status */
2804 return HAL_OK;
2805 }
2806
2807 /**
2808 * @}
2809 */
2810
2811 /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
2812 * @brief TIM Encoder functions
2813 *
2814 @verbatim
2815 ==============================================================================
2816 ##### TIM Encoder functions #####
2817 ==============================================================================
2818 [..]
2819 This section provides functions allowing to:
2820 (+) Initialize and configure the TIM Encoder.
2821 (+) De-initialize the TIM Encoder.
2822 (+) Start the TIM Encoder.
2823 (+) Stop the TIM Encoder.
2824 (+) Start the TIM Encoder and enable interrupt.
2825 (+) Stop the TIM Encoder and disable interrupt.
2826 (+) Start the TIM Encoder and enable DMA transfer.
2827 (+) Stop the TIM Encoder and disable DMA transfer.
2828
2829 @endverbatim
2830 * @{
2831 */
2832 /**
2833 * @brief Initializes the TIM Encoder Interface and initialize the associated handle.
2834 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse)
2835 * requires a timer reset to avoid unexpected direction
2836 * due to DIR bit readonly in center aligned mode.
2837 * Ex: call @ref HAL_TIM_Encoder_DeInit() before HAL_TIM_Encoder_Init()
2838 * @note Encoder mode and External clock mode 2 are not compatible and must not be selected together
2839 * Ex: A call for @ref HAL_TIM_Encoder_Init will erase the settings of @ref HAL_TIM_ConfigClockSource
2840 * using TIM_CLOCKSOURCE_ETRMODE2 and vice versa
2841 * @note When the timer instance is initialized in Encoder mode, timer
2842 * channels 1 and channel 2 are reserved and cannot be used for other
2843 * purpose.
2844 * @param htim TIM Encoder Interface handle
2845 * @param sConfig TIM Encoder Interface configuration structure
2846 * @retval HAL status
2847 */
HAL_TIM_Encoder_Init(TIM_HandleTypeDef * htim,TIM_Encoder_InitTypeDef * sConfig)2848 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
2849 {
2850 uint32_t tmpsmcr;
2851 uint32_t tmpccmr1;
2852 uint32_t tmpccer;
2853
2854 /* Check the TIM handle allocation */
2855 if (htim == NULL)
2856 {
2857 return HAL_ERROR;
2858 }
2859
2860 /* Check the parameters */
2861 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
2862 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
2863 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
2864 assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
2865 assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
2866 assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
2867 assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
2868 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
2869 assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
2870 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
2871 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
2872 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
2873 assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
2874
2875 if (htim->State == HAL_TIM_STATE_RESET)
2876 {
2877 /* Allocate lock resource and initialize it */
2878 htim->Lock = HAL_UNLOCKED;
2879
2880 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2881 /* Reset interrupt callbacks to legacy weak callbacks */
2882 TIM_ResetCallback(htim);
2883
2884 if (htim->Encoder_MspInitCallback == NULL)
2885 {
2886 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
2887 }
2888 /* Init the low level hardware : GPIO, CLOCK, NVIC */
2889 htim->Encoder_MspInitCallback(htim);
2890 #else
2891 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
2892 HAL_TIM_Encoder_MspInit(htim);
2893 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2894 }
2895
2896 /* Set the TIM state */
2897 htim->State = HAL_TIM_STATE_BUSY;
2898
2899 /* Reset the SMS and ECE bits */
2900 htim->Instance->SMCR &= ~(TIM_SMCR_SMS | TIM_SMCR_ECE);
2901
2902 /* Configure the Time base in the Encoder Mode */
2903 TIM_Base_SetConfig(htim->Instance, &htim->Init);
2904
2905 /* Get the TIMx SMCR register value */
2906 tmpsmcr = htim->Instance->SMCR;
2907
2908 /* Get the TIMx CCMR1 register value */
2909 tmpccmr1 = htim->Instance->CCMR1;
2910
2911 /* Get the TIMx CCER register value */
2912 tmpccer = htim->Instance->CCER;
2913
2914 /* Set the encoder Mode */
2915 tmpsmcr |= sConfig->EncoderMode;
2916
2917 /* Select the Capture Compare 1 and the Capture Compare 2 as input */
2918 tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
2919 tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8U));
2920
2921 /* Set the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
2922 tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
2923 tmpccmr1 &= ~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F);
2924 tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8U);
2925 tmpccmr1 |= (sConfig->IC1Filter << 4U) | (sConfig->IC2Filter << 12U);
2926
2927 /* Set the TI1 and the TI2 Polarities */
2928 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
2929 tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
2930 tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4U);
2931
2932 /* Write to TIMx SMCR */
2933 htim->Instance->SMCR = tmpsmcr;
2934
2935 /* Write to TIMx CCMR1 */
2936 htim->Instance->CCMR1 = tmpccmr1;
2937
2938 /* Write to TIMx CCER */
2939 htim->Instance->CCER = tmpccer;
2940
2941 /* Initialize the DMA burst operation state */
2942 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
2943
2944 /* Set the TIM channels state */
2945 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2946 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2947 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
2948 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
2949
2950 /* Initialize the TIM state*/
2951 htim->State = HAL_TIM_STATE_READY;
2952
2953 return HAL_OK;
2954 }
2955
2956
2957 /**
2958 * @brief DeInitializes the TIM Encoder interface
2959 * @param htim TIM Encoder Interface handle
2960 * @retval HAL status
2961 */
HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef * htim)2962 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
2963 {
2964 /* Check the parameters */
2965 assert_param(IS_TIM_INSTANCE(htim->Instance));
2966
2967 htim->State = HAL_TIM_STATE_BUSY;
2968
2969 /* Disable the TIM Peripheral Clock */
2970 __HAL_TIM_DISABLE(htim);
2971
2972 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
2973 if (htim->Encoder_MspDeInitCallback == NULL)
2974 {
2975 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
2976 }
2977 /* DeInit the low level hardware */
2978 htim->Encoder_MspDeInitCallback(htim);
2979 #else
2980 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
2981 HAL_TIM_Encoder_MspDeInit(htim);
2982 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
2983
2984 /* Change the DMA burst operation state */
2985 htim->DMABurstState = HAL_DMA_BURST_STATE_RESET;
2986
2987 /* Set the TIM channels state */
2988 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2989 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2990 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_RESET);
2991 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_RESET);
2992
2993 /* Change TIM state */
2994 htim->State = HAL_TIM_STATE_RESET;
2995
2996 /* Release Lock */
2997 __HAL_UNLOCK(htim);
2998
2999 return HAL_OK;
3000 }
3001
3002 /**
3003 * @brief Initializes the TIM Encoder Interface MSP.
3004 * @param htim TIM Encoder Interface handle
3005 * @retval None
3006 */
HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef * htim)3007 __weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
3008 {
3009 /* Prevent unused argument(s) compilation warning */
3010 UNUSED(htim);
3011
3012 /* NOTE : This function should not be modified, when the callback is needed,
3013 the HAL_TIM_Encoder_MspInit could be implemented in the user file
3014 */
3015 }
3016
3017 /**
3018 * @brief DeInitializes TIM Encoder Interface MSP.
3019 * @param htim TIM Encoder Interface handle
3020 * @retval None
3021 */
HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef * htim)3022 __weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
3023 {
3024 /* Prevent unused argument(s) compilation warning */
3025 UNUSED(htim);
3026
3027 /* NOTE : This function should not be modified, when the callback is needed,
3028 the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
3029 */
3030 }
3031
3032 /**
3033 * @brief Starts the TIM Encoder Interface.
3034 * @param htim TIM Encoder Interface handle
3035 * @param Channel TIM Channels to be enabled
3036 * This parameter can be one of the following values:
3037 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3038 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3039 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3040 * @retval HAL status
3041 */
HAL_TIM_Encoder_Start(TIM_HandleTypeDef * htim,uint32_t Channel)3042 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
3043 {
3044 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3045 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3046 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3047 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3048
3049 /* Check the parameters */
3050 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3051
3052 /* Set the TIM channel(s) state */
3053 if (Channel == TIM_CHANNEL_1)
3054 {
3055 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3056 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3057 {
3058 return HAL_ERROR;
3059 }
3060 else
3061 {
3062 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3063 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3064 }
3065 }
3066 else if (Channel == TIM_CHANNEL_2)
3067 {
3068 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3069 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3070 {
3071 return HAL_ERROR;
3072 }
3073 else
3074 {
3075 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3076 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3077 }
3078 }
3079 else
3080 {
3081 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3082 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3083 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3084 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3085 {
3086 return HAL_ERROR;
3087 }
3088 else
3089 {
3090 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3091 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3092 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3093 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3094 }
3095 }
3096
3097 /* Enable the encoder interface channels */
3098 switch (Channel)
3099 {
3100 case TIM_CHANNEL_1:
3101 {
3102 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3103 break;
3104 }
3105
3106 case TIM_CHANNEL_2:
3107 {
3108 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3109 break;
3110 }
3111
3112 default :
3113 {
3114 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3115 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3116 break;
3117 }
3118 }
3119 /* Enable the Peripheral */
3120 __HAL_TIM_ENABLE(htim);
3121
3122 /* Return function status */
3123 return HAL_OK;
3124 }
3125
3126 /**
3127 * @brief Stops the TIM Encoder Interface.
3128 * @param htim TIM Encoder Interface handle
3129 * @param Channel TIM Channels to be disabled
3130 * This parameter can be one of the following values:
3131 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3132 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3133 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3134 * @retval HAL status
3135 */
HAL_TIM_Encoder_Stop(TIM_HandleTypeDef * htim,uint32_t Channel)3136 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
3137 {
3138 /* Check the parameters */
3139 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3140
3141 /* Disable the Input Capture channels 1 and 2
3142 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3143 switch (Channel)
3144 {
3145 case TIM_CHANNEL_1:
3146 {
3147 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3148 break;
3149 }
3150
3151 case TIM_CHANNEL_2:
3152 {
3153 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3154 break;
3155 }
3156
3157 default :
3158 {
3159 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3160 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3161 break;
3162 }
3163 }
3164
3165 /* Disable the Peripheral */
3166 __HAL_TIM_DISABLE(htim);
3167
3168 /* Set the TIM channel(s) state */
3169 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3170 {
3171 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3172 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3173 }
3174 else
3175 {
3176 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3177 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3178 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3179 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3180 }
3181
3182 /* Return function status */
3183 return HAL_OK;
3184 }
3185
3186 /**
3187 * @brief Starts the TIM Encoder Interface in interrupt mode.
3188 * @param htim TIM Encoder Interface handle
3189 * @param Channel TIM Channels to be enabled
3190 * This parameter can be one of the following values:
3191 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3192 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3193 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3194 * @retval HAL status
3195 */
HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3196 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3197 {
3198 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3199 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3200 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3201 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3202
3203 /* Check the parameters */
3204 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3205
3206 /* Set the TIM channel(s) state */
3207 if (Channel == TIM_CHANNEL_1)
3208 {
3209 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3210 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY))
3211 {
3212 return HAL_ERROR;
3213 }
3214 else
3215 {
3216 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3217 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3218 }
3219 }
3220 else if (Channel == TIM_CHANNEL_2)
3221 {
3222 if ((channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3223 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3224 {
3225 return HAL_ERROR;
3226 }
3227 else
3228 {
3229 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3230 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3231 }
3232 }
3233 else
3234 {
3235 if ((channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3236 || (channel_2_state != HAL_TIM_CHANNEL_STATE_READY)
3237 || (complementary_channel_1_state != HAL_TIM_CHANNEL_STATE_READY)
3238 || (complementary_channel_2_state != HAL_TIM_CHANNEL_STATE_READY))
3239 {
3240 return HAL_ERROR;
3241 }
3242 else
3243 {
3244 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3245 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3246 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3247 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3248 }
3249 }
3250
3251 /* Enable the encoder interface channels */
3252 /* Enable the capture compare Interrupts 1 and/or 2 */
3253 switch (Channel)
3254 {
3255 case TIM_CHANNEL_1:
3256 {
3257 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3258 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3259 break;
3260 }
3261
3262 case TIM_CHANNEL_2:
3263 {
3264 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3265 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3266 break;
3267 }
3268
3269 default :
3270 {
3271 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3272 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3273 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
3274 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
3275 break;
3276 }
3277 }
3278
3279 /* Enable the Peripheral */
3280 __HAL_TIM_ENABLE(htim);
3281
3282 /* Return function status */
3283 return HAL_OK;
3284 }
3285
3286 /**
3287 * @brief Stops the TIM Encoder Interface in interrupt mode.
3288 * @param htim TIM Encoder Interface handle
3289 * @param Channel TIM Channels to be disabled
3290 * This parameter can be one of the following values:
3291 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3292 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3293 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3294 * @retval HAL status
3295 */
HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef * htim,uint32_t Channel)3296 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
3297 {
3298 /* Check the parameters */
3299 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3300
3301 /* Disable the Input Capture channels 1 and 2
3302 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3303 if (Channel == TIM_CHANNEL_1)
3304 {
3305 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3306
3307 /* Disable the capture compare Interrupts 1 */
3308 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3309 }
3310 else if (Channel == TIM_CHANNEL_2)
3311 {
3312 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3313
3314 /* Disable the capture compare Interrupts 2 */
3315 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3316 }
3317 else
3318 {
3319 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3320 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3321
3322 /* Disable the capture compare Interrupts 1 and 2 */
3323 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
3324 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
3325 }
3326
3327 /* Disable the Peripheral */
3328 __HAL_TIM_DISABLE(htim);
3329
3330 /* Set the TIM channel(s) state */
3331 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3332 {
3333 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3334 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3335 }
3336 else
3337 {
3338 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3339 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3340 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3341 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3342 }
3343
3344 /* Return function status */
3345 return HAL_OK;
3346 }
3347
3348 /**
3349 * @brief Starts the TIM Encoder Interface in DMA mode.
3350 * @param htim TIM Encoder Interface handle
3351 * @param Channel TIM Channels to be enabled
3352 * This parameter can be one of the following values:
3353 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3354 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3355 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3356 * @param pData1 The destination Buffer address for IC1.
3357 * @param pData2 The destination Buffer address for IC2.
3358 * @param Length The length of data to be transferred from TIM peripheral to memory.
3359 * @retval HAL status
3360 */
HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef * htim,uint32_t Channel,uint32_t * pData1,uint32_t * pData2,uint16_t Length)3361 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
3362 uint32_t *pData2, uint16_t Length)
3363 {
3364 HAL_TIM_ChannelStateTypeDef channel_1_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_1);
3365 HAL_TIM_ChannelStateTypeDef channel_2_state = TIM_CHANNEL_STATE_GET(htim, TIM_CHANNEL_2);
3366 HAL_TIM_ChannelStateTypeDef complementary_channel_1_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_1);
3367 HAL_TIM_ChannelStateTypeDef complementary_channel_2_state = TIM_CHANNEL_N_STATE_GET(htim, TIM_CHANNEL_2);
3368
3369 /* Check the parameters */
3370 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3371
3372 /* Set the TIM channel(s) state */
3373 if (Channel == TIM_CHANNEL_1)
3374 {
3375 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3376 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY))
3377 {
3378 return HAL_BUSY;
3379 }
3380 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3381 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY))
3382 {
3383 if ((pData1 == NULL) && (Length > 0U))
3384 {
3385 return HAL_ERROR;
3386 }
3387 else
3388 {
3389 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3390 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3391 }
3392 }
3393 else
3394 {
3395 return HAL_ERROR;
3396 }
3397 }
3398 else if (Channel == TIM_CHANNEL_2)
3399 {
3400 if ((channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3401 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3402 {
3403 return HAL_BUSY;
3404 }
3405 else if ((channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3406 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3407 {
3408 if ((pData2 == NULL) && (Length > 0U))
3409 {
3410 return HAL_ERROR;
3411 }
3412 else
3413 {
3414 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3415 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3416 }
3417 }
3418 else
3419 {
3420 return HAL_ERROR;
3421 }
3422 }
3423 else
3424 {
3425 if ((channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3426 || (channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY)
3427 || (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_BUSY)
3428 || (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_BUSY))
3429 {
3430 return HAL_BUSY;
3431 }
3432 else if ((channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3433 && (channel_2_state == HAL_TIM_CHANNEL_STATE_READY)
3434 && (complementary_channel_1_state == HAL_TIM_CHANNEL_STATE_READY)
3435 && (complementary_channel_2_state == HAL_TIM_CHANNEL_STATE_READY))
3436 {
3437 if ((((pData1 == NULL) || (pData2 == NULL))) && (Length > 0U))
3438 {
3439 return HAL_ERROR;
3440 }
3441 else
3442 {
3443 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3444 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3445 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_BUSY);
3446 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_BUSY);
3447 }
3448 }
3449 else
3450 {
3451 return HAL_ERROR;
3452 }
3453 }
3454
3455 switch (Channel)
3456 {
3457 case TIM_CHANNEL_1:
3458 {
3459 /* Set the DMA capture callbacks */
3460 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3461 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3462
3463 /* Set the DMA error callback */
3464 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3465
3466 /* Enable the DMA channel */
3467 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
3468 {
3469 return HAL_ERROR;
3470 }
3471 /* Enable the TIM Input Capture DMA request */
3472 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3473
3474 /* Enable the Peripheral */
3475 __HAL_TIM_ENABLE(htim);
3476
3477 /* Enable the Capture compare channel */
3478 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3479 break;
3480 }
3481
3482 case TIM_CHANNEL_2:
3483 {
3484 /* Set the DMA capture callbacks */
3485 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3486 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3487
3488 /* Set the DMA error callback */
3489 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
3490 /* Enable the DMA channel */
3491 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
3492 {
3493 return HAL_ERROR;
3494 }
3495 /* Enable the TIM Input Capture DMA request */
3496 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3497
3498 /* Enable the Peripheral */
3499 __HAL_TIM_ENABLE(htim);
3500
3501 /* Enable the Capture compare channel */
3502 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3503 break;
3504 }
3505
3506 case TIM_CHANNEL_ALL:
3507 {
3508 /* Set the DMA capture callbacks */
3509 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
3510 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3511
3512 /* Set the DMA error callback */
3513 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
3514
3515 /* Enable the DMA channel */
3516 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length) != HAL_OK)
3517 {
3518 return HAL_ERROR;
3519 }
3520
3521 /* Set the DMA capture callbacks */
3522 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
3523 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
3524
3525 /* Set the DMA error callback */
3526 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
3527
3528 /* Enable the DMA channel */
3529 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length) != HAL_OK)
3530 {
3531 return HAL_ERROR;
3532 }
3533 /* Enable the Peripheral */
3534 __HAL_TIM_ENABLE(htim);
3535
3536 /* Enable the Capture compare channel */
3537 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
3538 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
3539
3540 /* Enable the TIM Input Capture DMA request */
3541 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
3542 /* Enable the TIM Input Capture DMA request */
3543 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
3544 break;
3545 }
3546
3547 default:
3548 break;
3549 }
3550
3551 /* Return function status */
3552 return HAL_OK;
3553 }
3554
3555 /**
3556 * @brief Stops the TIM Encoder Interface in DMA mode.
3557 * @param htim TIM Encoder Interface handle
3558 * @param Channel TIM Channels to be enabled
3559 * This parameter can be one of the following values:
3560 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3561 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3562 * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
3563 * @retval HAL status
3564 */
HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef * htim,uint32_t Channel)3565 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
3566 {
3567 /* Check the parameters */
3568 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(htim->Instance));
3569
3570 /* Disable the Input Capture channels 1 and 2
3571 (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
3572 if (Channel == TIM_CHANNEL_1)
3573 {
3574 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3575
3576 /* Disable the capture compare DMA Request 1 */
3577 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3578 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3579 }
3580 else if (Channel == TIM_CHANNEL_2)
3581 {
3582 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3583
3584 /* Disable the capture compare DMA Request 2 */
3585 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3586 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3587 }
3588 else
3589 {
3590 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
3591 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
3592
3593 /* Disable the capture compare DMA Request 1 and 2 */
3594 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
3595 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
3596 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
3597 (void)HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
3598 }
3599
3600 /* Disable the Peripheral */
3601 __HAL_TIM_DISABLE(htim);
3602
3603 /* Set the TIM channel(s) state */
3604 if ((Channel == TIM_CHANNEL_1) || (Channel == TIM_CHANNEL_2))
3605 {
3606 TIM_CHANNEL_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3607 TIM_CHANNEL_N_STATE_SET(htim, Channel, HAL_TIM_CHANNEL_STATE_READY);
3608 }
3609 else
3610 {
3611 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3612 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3613 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
3614 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
3615 }
3616
3617 /* Return function status */
3618 return HAL_OK;
3619 }
3620
3621 /**
3622 * @}
3623 */
3624 /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
3625 * @brief TIM IRQ handler management
3626 *
3627 @verbatim
3628 ==============================================================================
3629 ##### IRQ handler management #####
3630 ==============================================================================
3631 [..]
3632 This section provides Timer IRQ handler function.
3633
3634 @endverbatim
3635 * @{
3636 */
3637 /**
3638 * @brief This function handles TIM interrupts requests.
3639 * @param htim TIM handle
3640 * @retval None
3641 */
HAL_TIM_IRQHandler(TIM_HandleTypeDef * htim)3642 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
3643 {
3644 /* Capture compare 1 event */
3645 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
3646 {
3647 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
3648 {
3649 {
3650 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
3651 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
3652
3653 /* Input capture event */
3654 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00U)
3655 {
3656 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3657 htim->IC_CaptureCallback(htim);
3658 #else
3659 HAL_TIM_IC_CaptureCallback(htim);
3660 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3661 }
3662 /* Output compare event */
3663 else
3664 {
3665 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3666 htim->OC_DelayElapsedCallback(htim);
3667 htim->PWM_PulseFinishedCallback(htim);
3668 #else
3669 HAL_TIM_OC_DelayElapsedCallback(htim);
3670 HAL_TIM_PWM_PulseFinishedCallback(htim);
3671 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3672 }
3673 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3674 }
3675 }
3676 }
3677 /* Capture compare 2 event */
3678 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
3679 {
3680 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
3681 {
3682 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
3683 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
3684 /* Input capture event */
3685 if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
3686 {
3687 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3688 htim->IC_CaptureCallback(htim);
3689 #else
3690 HAL_TIM_IC_CaptureCallback(htim);
3691 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3692 }
3693 /* Output compare event */
3694 else
3695 {
3696 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3697 htim->OC_DelayElapsedCallback(htim);
3698 htim->PWM_PulseFinishedCallback(htim);
3699 #else
3700 HAL_TIM_OC_DelayElapsedCallback(htim);
3701 HAL_TIM_PWM_PulseFinishedCallback(htim);
3702 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3703 }
3704 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3705 }
3706 }
3707 /* Capture compare 3 event */
3708 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
3709 {
3710 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
3711 {
3712 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
3713 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
3714 /* Input capture event */
3715 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
3716 {
3717 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3718 htim->IC_CaptureCallback(htim);
3719 #else
3720 HAL_TIM_IC_CaptureCallback(htim);
3721 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3722 }
3723 /* Output compare event */
3724 else
3725 {
3726 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3727 htim->OC_DelayElapsedCallback(htim);
3728 htim->PWM_PulseFinishedCallback(htim);
3729 #else
3730 HAL_TIM_OC_DelayElapsedCallback(htim);
3731 HAL_TIM_PWM_PulseFinishedCallback(htim);
3732 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3733 }
3734 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3735 }
3736 }
3737 /* Capture compare 4 event */
3738 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
3739 {
3740 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
3741 {
3742 __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
3743 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
3744 /* Input capture event */
3745 if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
3746 {
3747 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3748 htim->IC_CaptureCallback(htim);
3749 #else
3750 HAL_TIM_IC_CaptureCallback(htim);
3751 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3752 }
3753 /* Output compare event */
3754 else
3755 {
3756 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3757 htim->OC_DelayElapsedCallback(htim);
3758 htim->PWM_PulseFinishedCallback(htim);
3759 #else
3760 HAL_TIM_OC_DelayElapsedCallback(htim);
3761 HAL_TIM_PWM_PulseFinishedCallback(htim);
3762 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3763 }
3764 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
3765 }
3766 }
3767 /* TIM Update event */
3768 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
3769 {
3770 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
3771 {
3772 __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
3773 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3774 htim->PeriodElapsedCallback(htim);
3775 #else
3776 HAL_TIM_PeriodElapsedCallback(htim);
3777 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3778 }
3779 }
3780 /* TIM Break input event */
3781 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
3782 {
3783 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3784 {
3785 __HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
3786 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3787 htim->BreakCallback(htim);
3788 #else
3789 HAL_TIMEx_BreakCallback(htim);
3790 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3791 }
3792 }
3793 /* TIM Break2 input event */
3794 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
3795 {
3796 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
3797 {
3798 __HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
3799 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3800 htim->Break2Callback(htim);
3801 #else
3802 HAL_TIMEx_Break2Callback(htim);
3803 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3804 }
3805 }
3806 /* TIM Trigger detection event */
3807 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
3808 {
3809 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
3810 {
3811 __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
3812 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3813 htim->TriggerCallback(htim);
3814 #else
3815 HAL_TIM_TriggerCallback(htim);
3816 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3817 }
3818 }
3819 /* TIM commutation event */
3820 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
3821 {
3822 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
3823 {
3824 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
3825 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3826 htim->CommutationCallback(htim);
3827 #else
3828 HAL_TIMEx_CommutCallback(htim);
3829 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3830 }
3831 }
3832 /* TIM Encoder index event */
3833 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IDX) != RESET)
3834 {
3835 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IDX) != RESET)
3836 {
3837 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IDX);
3838 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3839 htim->EncoderIndexCallback(htim);
3840 #else
3841 HAL_TIMEx_EncoderIndexCallback(htim);
3842 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3843 }
3844 }
3845 /* TIM Direction change event */
3846 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_DIR) != RESET)
3847 {
3848 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_DIR) != RESET)
3849 {
3850 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_DIR);
3851 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3852 htim->DirectionChangeCallback(htim);
3853 #else
3854 HAL_TIMEx_DirectionChangeCallback(htim);
3855 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3856 }
3857 }
3858 /* TIM Index error event */
3859 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_IERR) != RESET)
3860 {
3861 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_IERR) != RESET)
3862 {
3863 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_IERR);
3864 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3865 htim->IndexErrorCallback(htim);
3866 #else
3867 HAL_TIMEx_IndexErrorCallback(htim);
3868 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3869 }
3870 }
3871 /* TIM Transition error event */
3872 if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TERR) != RESET)
3873 {
3874 if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TERR) != RESET)
3875 {
3876 __HAL_TIM_CLEAR_IT(htim, TIM_FLAG_TERR);
3877 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
3878 htim->TransitionErrorCallback(htim);
3879 #else
3880 HAL_TIMEx_TransitionErrorCallback(htim);
3881 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
3882 }
3883 }
3884 }
3885
3886 /**
3887 * @}
3888 */
3889
3890 /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
3891 * @brief TIM Peripheral Control functions
3892 *
3893 @verbatim
3894 ==============================================================================
3895 ##### Peripheral Control functions #####
3896 ==============================================================================
3897 [..]
3898 This section provides functions allowing to:
3899 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
3900 (+) Configure External Clock source.
3901 (+) Configure Complementary channels, break features and dead time.
3902 (+) Configure Master and the Slave synchronization.
3903 (+) Configure the DMA Burst Mode.
3904
3905 @endverbatim
3906 * @{
3907 */
3908
3909 /**
3910 * @brief Initializes the TIM Output Compare Channels according to the specified
3911 * parameters in the TIM_OC_InitTypeDef.
3912 * @param htim TIM Output Compare handle
3913 * @param sConfig TIM Output Compare configuration structure
3914 * @param Channel TIM Channels to configure
3915 * This parameter can be one of the following values:
3916 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
3917 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
3918 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
3919 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
3920 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
3921 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
3922 * @retval HAL status
3923 */
HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)3924 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim,
3925 TIM_OC_InitTypeDef *sConfig,
3926 uint32_t Channel)
3927 {
3928 /* Check the parameters */
3929 assert_param(IS_TIM_CHANNELS(Channel));
3930 assert_param(IS_TIM_OC_CHANNEL_MODE(sConfig->OCMode, Channel));
3931 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
3932
3933 /* Process Locked */
3934 __HAL_LOCK(htim);
3935
3936 switch (Channel)
3937 {
3938 case TIM_CHANNEL_1:
3939 {
3940 /* Check the parameters */
3941 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
3942
3943 /* Configure the TIM Channel 1 in Output Compare */
3944 TIM_OC1_SetConfig(htim->Instance, sConfig);
3945 break;
3946 }
3947
3948 case TIM_CHANNEL_2:
3949 {
3950 /* Check the parameters */
3951 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
3952
3953 /* Configure the TIM Channel 2 in Output Compare */
3954 TIM_OC2_SetConfig(htim->Instance, sConfig);
3955 break;
3956 }
3957
3958 case TIM_CHANNEL_3:
3959 {
3960 /* Check the parameters */
3961 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
3962
3963 /* Configure the TIM Channel 3 in Output Compare */
3964 TIM_OC3_SetConfig(htim->Instance, sConfig);
3965 break;
3966 }
3967
3968 case TIM_CHANNEL_4:
3969 {
3970 /* Check the parameters */
3971 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
3972
3973 /* Configure the TIM Channel 4 in Output Compare */
3974 TIM_OC4_SetConfig(htim->Instance, sConfig);
3975 break;
3976 }
3977
3978 case TIM_CHANNEL_5:
3979 {
3980 /* Check the parameters */
3981 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
3982
3983 /* Configure the TIM Channel 5 in Output Compare */
3984 TIM_OC5_SetConfig(htim->Instance, sConfig);
3985 break;
3986 }
3987
3988 case TIM_CHANNEL_6:
3989 {
3990 /* Check the parameters */
3991 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
3992
3993 /* Configure the TIM Channel 6 in Output Compare */
3994 TIM_OC6_SetConfig(htim->Instance, sConfig);
3995 break;
3996 }
3997
3998 default:
3999 break;
4000 }
4001
4002 __HAL_UNLOCK(htim);
4003
4004 return HAL_OK;
4005 }
4006
4007 /**
4008 * @brief Initializes the TIM Input Capture Channels according to the specified
4009 * parameters in the TIM_IC_InitTypeDef.
4010 * @param htim TIM IC handle
4011 * @param sConfig TIM Input Capture configuration structure
4012 * @param Channel TIM Channel to configure
4013 * This parameter can be one of the following values:
4014 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4015 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4016 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4017 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4018 * @retval HAL status
4019 */
HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef * htim,TIM_IC_InitTypeDef * sConfig,uint32_t Channel)4020 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel)
4021 {
4022 /* Check the parameters */
4023 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4024 assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
4025 assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
4026 assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
4027 assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
4028
4029 /* Process Locked */
4030 __HAL_LOCK(htim);
4031
4032 if (Channel == TIM_CHANNEL_1)
4033 {
4034 /* TI1 Configuration */
4035 TIM_TI1_SetConfig(htim->Instance,
4036 sConfig->ICPolarity,
4037 sConfig->ICSelection,
4038 sConfig->ICFilter);
4039
4040 /* Reset the IC1PSC Bits */
4041 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4042
4043 /* Set the IC1PSC value */
4044 htim->Instance->CCMR1 |= sConfig->ICPrescaler;
4045 }
4046 else if (Channel == TIM_CHANNEL_2)
4047 {
4048 /* TI2 Configuration */
4049 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4050
4051 TIM_TI2_SetConfig(htim->Instance,
4052 sConfig->ICPolarity,
4053 sConfig->ICSelection,
4054 sConfig->ICFilter);
4055
4056 /* Reset the IC2PSC Bits */
4057 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4058
4059 /* Set the IC2PSC value */
4060 htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8U);
4061 }
4062 else if (Channel == TIM_CHANNEL_3)
4063 {
4064 /* TI3 Configuration */
4065 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4066
4067 TIM_TI3_SetConfig(htim->Instance,
4068 sConfig->ICPolarity,
4069 sConfig->ICSelection,
4070 sConfig->ICFilter);
4071
4072 /* Reset the IC3PSC Bits */
4073 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
4074
4075 /* Set the IC3PSC value */
4076 htim->Instance->CCMR2 |= sConfig->ICPrescaler;
4077 }
4078 else
4079 {
4080 /* TI4 Configuration */
4081 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4082
4083 TIM_TI4_SetConfig(htim->Instance,
4084 sConfig->ICPolarity,
4085 sConfig->ICSelection,
4086 sConfig->ICFilter);
4087
4088 /* Reset the IC4PSC Bits */
4089 htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
4090
4091 /* Set the IC4PSC value */
4092 htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8U);
4093 }
4094
4095 __HAL_UNLOCK(htim);
4096
4097 return HAL_OK;
4098 }
4099
4100 /**
4101 * @brief Initializes the TIM PWM channels according to the specified
4102 * parameters in the TIM_OC_InitTypeDef.
4103 * @param htim TIM PWM handle
4104 * @param sConfig TIM PWM configuration structure
4105 * @param Channel TIM Channels to be configured
4106 * This parameter can be one of the following values:
4107 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4108 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4109 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
4110 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
4111 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
4112 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
4113 * @retval HAL status
4114 */
HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OC_InitTypeDef * sConfig,uint32_t Channel)4115 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
4116 TIM_OC_InitTypeDef *sConfig,
4117 uint32_t Channel)
4118 {
4119 /* Check the parameters */
4120 assert_param(IS_TIM_CHANNELS(Channel));
4121 assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
4122 assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
4123 assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
4124
4125 /* Process Locked */
4126 __HAL_LOCK(htim);
4127
4128 switch (Channel)
4129 {
4130 case TIM_CHANNEL_1:
4131 {
4132 /* Check the parameters */
4133 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4134
4135 /* Configure the Channel 1 in PWM mode */
4136 TIM_OC1_SetConfig(htim->Instance, sConfig);
4137
4138 /* Set the Preload enable bit for channel1 */
4139 htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
4140
4141 /* Configure the Output Fast mode */
4142 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
4143 htim->Instance->CCMR1 |= sConfig->OCFastMode;
4144 break;
4145 }
4146
4147 case TIM_CHANNEL_2:
4148 {
4149 /* Check the parameters */
4150 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4151
4152 /* Configure the Channel 2 in PWM mode */
4153 TIM_OC2_SetConfig(htim->Instance, sConfig);
4154
4155 /* Set the Preload enable bit for channel2 */
4156 htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
4157
4158 /* Configure the Output Fast mode */
4159 htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
4160 htim->Instance->CCMR1 |= sConfig->OCFastMode << 8U;
4161 break;
4162 }
4163
4164 case TIM_CHANNEL_3:
4165 {
4166 /* Check the parameters */
4167 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
4168
4169 /* Configure the Channel 3 in PWM mode */
4170 TIM_OC3_SetConfig(htim->Instance, sConfig);
4171
4172 /* Set the Preload enable bit for channel3 */
4173 htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
4174
4175 /* Configure the Output Fast mode */
4176 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
4177 htim->Instance->CCMR2 |= sConfig->OCFastMode;
4178 break;
4179 }
4180
4181 case TIM_CHANNEL_4:
4182 {
4183 /* Check the parameters */
4184 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
4185
4186 /* Configure the Channel 4 in PWM mode */
4187 TIM_OC4_SetConfig(htim->Instance, sConfig);
4188
4189 /* Set the Preload enable bit for channel4 */
4190 htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
4191
4192 /* Configure the Output Fast mode */
4193 htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
4194 htim->Instance->CCMR2 |= sConfig->OCFastMode << 8U;
4195 break;
4196 }
4197
4198 case TIM_CHANNEL_5:
4199 {
4200 /* Check the parameters */
4201 assert_param(IS_TIM_CC5_INSTANCE(htim->Instance));
4202
4203 /* Configure the Channel 5 in PWM mode */
4204 TIM_OC5_SetConfig(htim->Instance, sConfig);
4205
4206 /* Set the Preload enable bit for channel5*/
4207 htim->Instance->CCMR3 |= TIM_CCMR3_OC5PE;
4208
4209 /* Configure the Output Fast mode */
4210 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE;
4211 htim->Instance->CCMR3 |= sConfig->OCFastMode;
4212 break;
4213 }
4214
4215 case TIM_CHANNEL_6:
4216 {
4217 /* Check the parameters */
4218 assert_param(IS_TIM_CC6_INSTANCE(htim->Instance));
4219
4220 /* Configure the Channel 6 in PWM mode */
4221 TIM_OC6_SetConfig(htim->Instance, sConfig);
4222
4223 /* Set the Preload enable bit for channel6 */
4224 htim->Instance->CCMR3 |= TIM_CCMR3_OC6PE;
4225
4226 /* Configure the Output Fast mode */
4227 htim->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE;
4228 htim->Instance->CCMR3 |= sConfig->OCFastMode << 8U;
4229 break;
4230 }
4231
4232 default:
4233 break;
4234 }
4235
4236 __HAL_UNLOCK(htim);
4237
4238 return HAL_OK;
4239 }
4240
4241 /**
4242 * @brief Initializes the TIM One Pulse Channels according to the specified
4243 * parameters in the TIM_OnePulse_InitTypeDef.
4244 * @param htim TIM One Pulse handle
4245 * @param sConfig TIM One Pulse configuration structure
4246 * @param OutputChannel TIM output channel to configure
4247 * This parameter can be one of the following values:
4248 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4249 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4250 * @param InputChannel TIM input Channel to configure
4251 * This parameter can be one of the following values:
4252 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
4253 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
4254 * @note To output a waveform with a minimum delay user can enable the fast
4255 * mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
4256 * output is forced in response to the edge detection on TIx input,
4257 * without taking in account the comparison.
4258 * @retval HAL status
4259 */
HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef * htim,TIM_OnePulse_InitTypeDef * sConfig,uint32_t OutputChannel,uint32_t InputChannel)4260 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
4261 uint32_t OutputChannel, uint32_t InputChannel)
4262 {
4263 TIM_OC_InitTypeDef temp1;
4264
4265 /* Check the parameters */
4266 assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
4267 assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
4268
4269 if (OutputChannel != InputChannel)
4270 {
4271 /* Process Locked */
4272 __HAL_LOCK(htim);
4273
4274 htim->State = HAL_TIM_STATE_BUSY;
4275
4276 /* Extract the Output compare configuration from sConfig structure */
4277 temp1.OCMode = sConfig->OCMode;
4278 temp1.Pulse = sConfig->Pulse;
4279 temp1.OCPolarity = sConfig->OCPolarity;
4280 temp1.OCNPolarity = sConfig->OCNPolarity;
4281 temp1.OCIdleState = sConfig->OCIdleState;
4282 temp1.OCNIdleState = sConfig->OCNIdleState;
4283
4284 switch (OutputChannel)
4285 {
4286 case TIM_CHANNEL_1:
4287 {
4288 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4289
4290 TIM_OC1_SetConfig(htim->Instance, &temp1);
4291 break;
4292 }
4293 case TIM_CHANNEL_2:
4294 {
4295 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4296
4297 TIM_OC2_SetConfig(htim->Instance, &temp1);
4298 break;
4299 }
4300 default:
4301 break;
4302 }
4303
4304 switch (InputChannel)
4305 {
4306 case TIM_CHANNEL_1:
4307 {
4308 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
4309
4310 TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
4311 sConfig->ICSelection, sConfig->ICFilter);
4312
4313 /* Reset the IC1PSC Bits */
4314 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
4315
4316 /* Select the Trigger source */
4317 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4318 htim->Instance->SMCR |= TIM_TS_TI1FP1;
4319
4320 /* Select the Slave Mode */
4321 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4322 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4323 break;
4324 }
4325 case TIM_CHANNEL_2:
4326 {
4327 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
4328
4329 TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
4330 sConfig->ICSelection, sConfig->ICFilter);
4331
4332 /* Reset the IC2PSC Bits */
4333 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
4334
4335 /* Select the Trigger source */
4336 htim->Instance->SMCR &= ~TIM_SMCR_TS;
4337 htim->Instance->SMCR |= TIM_TS_TI2FP2;
4338
4339 /* Select the Slave Mode */
4340 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
4341 htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
4342 break;
4343 }
4344
4345 default:
4346 break;
4347 }
4348
4349 htim->State = HAL_TIM_STATE_READY;
4350
4351 __HAL_UNLOCK(htim);
4352
4353 return HAL_OK;
4354 }
4355 else
4356 {
4357 return HAL_ERROR;
4358 }
4359 }
4360
4361 /**
4362 * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
4363 * @param htim TIM handle
4364 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4365 * This parameter can be one of the following values:
4366 * @arg TIM_DMABASE_CR1
4367 * @arg TIM_DMABASE_CR2
4368 * @arg TIM_DMABASE_SMCR
4369 * @arg TIM_DMABASE_DIER
4370 * @arg TIM_DMABASE_SR
4371 * @arg TIM_DMABASE_EGR
4372 * @arg TIM_DMABASE_CCMR1
4373 * @arg TIM_DMABASE_CCMR2
4374 * @arg TIM_DMABASE_CCER
4375 * @arg TIM_DMABASE_CNT
4376 * @arg TIM_DMABASE_PSC
4377 * @arg TIM_DMABASE_ARR
4378 * @arg TIM_DMABASE_RCR
4379 * @arg TIM_DMABASE_CCR1
4380 * @arg TIM_DMABASE_CCR2
4381 * @arg TIM_DMABASE_CCR3
4382 * @arg TIM_DMABASE_CCR4
4383 * @arg TIM_DMABASE_BDTR
4384 * @arg TIM_DMABASE_CCMR3
4385 * @arg TIM_DMABASE_CCR5
4386 * @arg TIM_DMABASE_CCR6
4387 * @arg TIM_DMABASE_DTR2
4388 * @arg TIM_DMABASE_ECR
4389 * @arg TIM_DMABASE_TISEL
4390 * @arg TIM_DMABASE_AF1
4391 * @arg TIM_DMABASE_AF2
4392 * @arg TIM_DMABASE_OR
4393 * @param BurstRequestSrc TIM DMA Request sources
4394 * This parameter can be one of the following values:
4395 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4396 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4397 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4398 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4399 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4400 * @arg TIM_DMA_COM: TIM Commutation DMA source
4401 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4402 * @param BurstBuffer The Buffer address.
4403 * @param BurstLength DMA Burst length. This parameter can be one value
4404 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
4405 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4406 * @retval HAL status
4407 */
HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4408 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4409 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4410 {
4411 return HAL_TIM_DMABurst_MultiWriteStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4412 ((BurstLength) >> 8U) + 1U);
4413 }
4414
4415 /**
4416 * @brief Configure the DMA Burst to transfer multiple Data from the memory to the TIM peripheral
4417 * @param htim TIM handle
4418 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data write
4419 * This parameter can be one of the following values:
4420 * @arg TIM_DMABASE_CR1
4421 * @arg TIM_DMABASE_CR2
4422 * @arg TIM_DMABASE_SMCR
4423 * @arg TIM_DMABASE_DIER
4424 * @arg TIM_DMABASE_SR
4425 * @arg TIM_DMABASE_EGR
4426 * @arg TIM_DMABASE_CCMR1
4427 * @arg TIM_DMABASE_CCMR2
4428 * @arg TIM_DMABASE_CCER
4429 * @arg TIM_DMABASE_CNT
4430 * @arg TIM_DMABASE_PSC
4431 * @arg TIM_DMABASE_ARR
4432 * @arg TIM_DMABASE_RCR
4433 * @arg TIM_DMABASE_CCR1
4434 * @arg TIM_DMABASE_CCR2
4435 * @arg TIM_DMABASE_CCR3
4436 * @arg TIM_DMABASE_CCR4
4437 * @arg TIM_DMABASE_BDTR
4438 * @arg TIM_DMABASE_CCMR3
4439 * @arg TIM_DMABASE_CCR5
4440 * @arg TIM_DMABASE_CCR6
4441 * @arg TIM_DMABASE_DTR2
4442 * @arg TIM_DMABASE_ECR
4443 * @arg TIM_DMABASE_TISEL
4444 * @arg TIM_DMABASE_AF1
4445 * @arg TIM_DMABASE_AF2
4446 * @arg TIM_DMABASE_OR
4447 * @param BurstRequestSrc TIM DMA Request sources
4448 * This parameter can be one of the following values:
4449 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4450 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4451 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4452 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4453 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4454 * @arg TIM_DMA_COM: TIM Commutation DMA source
4455 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4456 * @param BurstBuffer The Buffer address.
4457 * @param BurstLength DMA Burst length. This parameter can be one value
4458 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
4459 * @param DataLength Data length. This parameter can be one value
4460 * between 1 and 0xFFFF.
4461 * @retval HAL status
4462 */
HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4463 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4464 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4465 uint32_t BurstLength, uint32_t DataLength)
4466 {
4467 /* Check the parameters */
4468 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4469 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4470 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4471 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4472 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4473
4474 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4475 {
4476 return HAL_BUSY;
4477 }
4478 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4479 {
4480 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4481 {
4482 return HAL_ERROR;
4483 }
4484 else
4485 {
4486 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4487 }
4488 }
4489 else
4490 {
4491 /* nothing to do */
4492 }
4493 switch (BurstRequestSrc)
4494 {
4495 case TIM_DMA_UPDATE:
4496 {
4497 /* Set the DMA Period elapsed callbacks */
4498 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4499 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4500
4501 /* Set the DMA error callback */
4502 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4503
4504 /* Enable the DMA channel */
4505 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer,
4506 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4507 {
4508 return HAL_ERROR;
4509 }
4510 break;
4511 }
4512 case TIM_DMA_CC1:
4513 {
4514 /* Set the DMA compare callbacks */
4515 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
4516 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4517
4518 /* Set the DMA error callback */
4519 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4520
4521 /* Enable the DMA channel */
4522 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
4523 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4524 {
4525 return HAL_ERROR;
4526 }
4527 break;
4528 }
4529 case TIM_DMA_CC2:
4530 {
4531 /* Set the DMA compare callbacks */
4532 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
4533 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4534
4535 /* Set the DMA error callback */
4536 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4537
4538 /* Enable the DMA channel */
4539 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
4540 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4541 {
4542 return HAL_ERROR;
4543 }
4544 break;
4545 }
4546 case TIM_DMA_CC3:
4547 {
4548 /* Set the DMA compare callbacks */
4549 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
4550 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4551
4552 /* Set the DMA error callback */
4553 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4554
4555 /* Enable the DMA channel */
4556 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
4557 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4558 {
4559 return HAL_ERROR;
4560 }
4561 break;
4562 }
4563 case TIM_DMA_CC4:
4564 {
4565 /* Set the DMA compare callbacks */
4566 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
4567 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMADelayPulseHalfCplt;
4568
4569 /* Set the DMA error callback */
4570 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4571
4572 /* Enable the DMA channel */
4573 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
4574 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4575 {
4576 return HAL_ERROR;
4577 }
4578 break;
4579 }
4580 case TIM_DMA_COM:
4581 {
4582 /* Set the DMA commutation callbacks */
4583 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4584 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4585
4586 /* Set the DMA error callback */
4587 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4588
4589 /* Enable the DMA channel */
4590 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
4591 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4592 {
4593 return HAL_ERROR;
4594 }
4595 break;
4596 }
4597 case TIM_DMA_TRIGGER:
4598 {
4599 /* Set the DMA trigger callbacks */
4600 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4601 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4602
4603 /* Set the DMA error callback */
4604 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4605
4606 /* Enable the DMA channel */
4607 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
4608 (uint32_t)&htim->Instance->DMAR, DataLength) != HAL_OK)
4609 {
4610 return HAL_ERROR;
4611 }
4612 break;
4613 }
4614 default:
4615 break;
4616 }
4617
4618 /* Configure the DMA Burst Mode */
4619 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4620 /* Enable the TIM DMA Request */
4621 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4622
4623 /* Return function status */
4624 return HAL_OK;
4625 }
4626
4627 /**
4628 * @brief Stops the TIM DMA Burst mode
4629 * @param htim TIM handle
4630 * @param BurstRequestSrc TIM DMA Request sources to disable
4631 * @retval HAL status
4632 */
HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4633 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4634 {
4635 HAL_StatusTypeDef status = HAL_OK;
4636 /* Check the parameters */
4637 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4638
4639 /* Abort the DMA transfer (at least disable the DMA channel) */
4640 switch (BurstRequestSrc)
4641 {
4642 case TIM_DMA_UPDATE:
4643 {
4644 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4645 break;
4646 }
4647 case TIM_DMA_CC1:
4648 {
4649 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4650 break;
4651 }
4652 case TIM_DMA_CC2:
4653 {
4654 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4655 break;
4656 }
4657 case TIM_DMA_CC3:
4658 {
4659 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4660 break;
4661 }
4662 case TIM_DMA_CC4:
4663 {
4664 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4665 break;
4666 }
4667 case TIM_DMA_COM:
4668 {
4669 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
4670 break;
4671 }
4672 case TIM_DMA_TRIGGER:
4673 {
4674 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
4675 break;
4676 }
4677 default:
4678 break;
4679 }
4680
4681 if (HAL_OK == status)
4682 {
4683 /* Disable the TIM Update DMA request */
4684 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
4685 }
4686
4687 /* Change the DMA burst operation state */
4688 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
4689
4690 /* Return function status */
4691 return status;
4692 }
4693
4694 /**
4695 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4696 * @param htim TIM handle
4697 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4698 * This parameter can be one of the following values:
4699 * @arg TIM_DMABASE_CR1
4700 * @arg TIM_DMABASE_CR2
4701 * @arg TIM_DMABASE_SMCR
4702 * @arg TIM_DMABASE_DIER
4703 * @arg TIM_DMABASE_SR
4704 * @arg TIM_DMABASE_EGR
4705 * @arg TIM_DMABASE_CCMR1
4706 * @arg TIM_DMABASE_CCMR2
4707 * @arg TIM_DMABASE_CCER
4708 * @arg TIM_DMABASE_CNT
4709 * @arg TIM_DMABASE_PSC
4710 * @arg TIM_DMABASE_ARR
4711 * @arg TIM_DMABASE_RCR
4712 * @arg TIM_DMABASE_CCR1
4713 * @arg TIM_DMABASE_CCR2
4714 * @arg TIM_DMABASE_CCR3
4715 * @arg TIM_DMABASE_CCR4
4716 * @arg TIM_DMABASE_BDTR
4717 * @arg TIM_DMABASE_CCMR3
4718 * @arg TIM_DMABASE_CCR5
4719 * @arg TIM_DMABASE_CCR6
4720 * @arg TIM_DMABASE_DTR2
4721 * @arg TIM_DMABASE_ECR
4722 * @arg TIM_DMABASE_TISEL
4723 * @arg TIM_DMABASE_AF1
4724 * @arg TIM_DMABASE_AF2
4725 * @arg TIM_DMABASE_OR
4726 * @param BurstRequestSrc TIM DMA Request sources
4727 * This parameter can be one of the following values:
4728 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4729 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4730 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4731 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4732 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4733 * @arg TIM_DMA_COM: TIM Commutation DMA source
4734 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4735 * @param BurstBuffer The Buffer address.
4736 * @param BurstLength DMA Burst length. This parameter can be one value
4737 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
4738 * @note This function should be used only when BurstLength is equal to DMA data transfer length.
4739 * @retval HAL status
4740 */
HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength)4741 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4742 uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
4743 {
4744 return HAL_TIM_DMABurst_MultiReadStart(htim, BurstBaseAddress, BurstRequestSrc, BurstBuffer, BurstLength,
4745 ((BurstLength) >> 8U) + 1U);
4746 }
4747
4748 /**
4749 * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
4750 * @param htim TIM handle
4751 * @param BurstBaseAddress TIM Base address from where the DMA will start the Data read
4752 * This parameter can be one of the following values:
4753 * @arg TIM_DMABASE_CR1
4754 * @arg TIM_DMABASE_CR2
4755 * @arg TIM_DMABASE_SMCR
4756 * @arg TIM_DMABASE_DIER
4757 * @arg TIM_DMABASE_SR
4758 * @arg TIM_DMABASE_EGR
4759 * @arg TIM_DMABASE_CCMR1
4760 * @arg TIM_DMABASE_CCMR2
4761 * @arg TIM_DMABASE_CCER
4762 * @arg TIM_DMABASE_CNT
4763 * @arg TIM_DMABASE_PSC
4764 * @arg TIM_DMABASE_ARR
4765 * @arg TIM_DMABASE_RCR
4766 * @arg TIM_DMABASE_CCR1
4767 * @arg TIM_DMABASE_CCR2
4768 * @arg TIM_DMABASE_CCR3
4769 * @arg TIM_DMABASE_CCR4
4770 * @arg TIM_DMABASE_BDTR
4771 * @arg TIM_DMABASE_CCMR3
4772 * @arg TIM_DMABASE_CCR5
4773 * @arg TIM_DMABASE_CCR6
4774 * @arg TIM_DMABASE_DTR2
4775 * @arg TIM_DMABASE_ECR
4776 * @arg TIM_DMABASE_TISEL
4777 * @arg TIM_DMABASE_AF1
4778 * @arg TIM_DMABASE_AF2
4779 * @arg TIM_DMABASE_OR
4780 * @param BurstRequestSrc TIM DMA Request sources
4781 * This parameter can be one of the following values:
4782 * @arg TIM_DMA_UPDATE: TIM update Interrupt source
4783 * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
4784 * @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
4785 * @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
4786 * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
4787 * @arg TIM_DMA_COM: TIM Commutation DMA source
4788 * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
4789 * @param BurstBuffer The Buffer address.
4790 * @param BurstLength DMA Burst length. This parameter can be one value
4791 * between: TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_26TRANSFER.
4792 * @param DataLength Data length. This parameter can be one value
4793 * between 1 and 0xFFFF.
4794 * @retval HAL status
4795 */
HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef * htim,uint32_t BurstBaseAddress,uint32_t BurstRequestSrc,uint32_t * BurstBuffer,uint32_t BurstLength,uint32_t DataLength)4796 HAL_StatusTypeDef HAL_TIM_DMABurst_MultiReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
4797 uint32_t BurstRequestSrc, uint32_t *BurstBuffer,
4798 uint32_t BurstLength, uint32_t DataLength)
4799 {
4800 /* Check the parameters */
4801 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
4802 assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
4803 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4804 assert_param(IS_TIM_DMA_LENGTH(BurstLength));
4805 assert_param(IS_TIM_DMA_DATA_LENGTH(DataLength));
4806
4807 if (htim->DMABurstState == HAL_DMA_BURST_STATE_BUSY)
4808 {
4809 return HAL_BUSY;
4810 }
4811 else if (htim->DMABurstState == HAL_DMA_BURST_STATE_READY)
4812 {
4813 if ((BurstBuffer == NULL) && (BurstLength > 0U))
4814 {
4815 return HAL_ERROR;
4816 }
4817 else
4818 {
4819 htim->DMABurstState = HAL_DMA_BURST_STATE_BUSY;
4820 }
4821 }
4822 else
4823 {
4824 /* nothing to do */
4825 }
4826 switch (BurstRequestSrc)
4827 {
4828 case TIM_DMA_UPDATE:
4829 {
4830 /* Set the DMA Period elapsed callbacks */
4831 htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
4832 htim->hdma[TIM_DMA_ID_UPDATE]->XferHalfCpltCallback = TIM_DMAPeriodElapsedHalfCplt;
4833
4834 /* Set the DMA error callback */
4835 htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
4836
4837 /* Enable the DMA channel */
4838 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4839 DataLength) != HAL_OK)
4840 {
4841 return HAL_ERROR;
4842 }
4843 break;
4844 }
4845 case TIM_DMA_CC1:
4846 {
4847 /* Set the DMA capture callbacks */
4848 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
4849 htim->hdma[TIM_DMA_ID_CC1]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4850
4851 /* Set the DMA error callback */
4852 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
4853
4854 /* Enable the DMA channel */
4855 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4856 DataLength) != HAL_OK)
4857 {
4858 return HAL_ERROR;
4859 }
4860 break;
4861 }
4862 case TIM_DMA_CC2:
4863 {
4864 /* Set the DMA capture callbacks */
4865 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
4866 htim->hdma[TIM_DMA_ID_CC2]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4867
4868 /* Set the DMA error callback */
4869 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
4870
4871 /* Enable the DMA channel */
4872 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4873 DataLength) != HAL_OK)
4874 {
4875 return HAL_ERROR;
4876 }
4877 break;
4878 }
4879 case TIM_DMA_CC3:
4880 {
4881 /* Set the DMA capture callbacks */
4882 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
4883 htim->hdma[TIM_DMA_ID_CC3]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4884
4885 /* Set the DMA error callback */
4886 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
4887
4888 /* Enable the DMA channel */
4889 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4890 DataLength) != HAL_OK)
4891 {
4892 return HAL_ERROR;
4893 }
4894 break;
4895 }
4896 case TIM_DMA_CC4:
4897 {
4898 /* Set the DMA capture callbacks */
4899 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
4900 htim->hdma[TIM_DMA_ID_CC4]->XferHalfCpltCallback = TIM_DMACaptureHalfCplt;
4901
4902 /* Set the DMA error callback */
4903 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
4904
4905 /* Enable the DMA channel */
4906 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4907 DataLength) != HAL_OK)
4908 {
4909 return HAL_ERROR;
4910 }
4911 break;
4912 }
4913 case TIM_DMA_COM:
4914 {
4915 /* Set the DMA commutation callbacks */
4916 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
4917 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferHalfCpltCallback = TIMEx_DMACommutationHalfCplt;
4918
4919 /* Set the DMA error callback */
4920 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
4921
4922 /* Enable the DMA channel */
4923 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4924 DataLength) != HAL_OK)
4925 {
4926 return HAL_ERROR;
4927 }
4928 break;
4929 }
4930 case TIM_DMA_TRIGGER:
4931 {
4932 /* Set the DMA trigger callbacks */
4933 htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
4934 htim->hdma[TIM_DMA_ID_TRIGGER]->XferHalfCpltCallback = TIM_DMATriggerHalfCplt;
4935
4936 /* Set the DMA error callback */
4937 htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
4938
4939 /* Enable the DMA channel */
4940 if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer,
4941 DataLength) != HAL_OK)
4942 {
4943 return HAL_ERROR;
4944 }
4945 break;
4946 }
4947 default:
4948 break;
4949 }
4950
4951 /* Configure the DMA Burst Mode */
4952 htim->Instance->DCR = (BurstBaseAddress | BurstLength);
4953
4954 /* Enable the TIM DMA Request */
4955 __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
4956
4957 /* Return function status */
4958 return HAL_OK;
4959 }
4960
4961 /**
4962 * @brief Stop the DMA burst reading
4963 * @param htim TIM handle
4964 * @param BurstRequestSrc TIM DMA Request sources to disable.
4965 * @retval HAL status
4966 */
HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef * htim,uint32_t BurstRequestSrc)4967 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
4968 {
4969 HAL_StatusTypeDef status = HAL_OK;
4970 /* Check the parameters */
4971 assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
4972
4973 /* Abort the DMA transfer (at least disable the DMA channel) */
4974 switch (BurstRequestSrc)
4975 {
4976 case TIM_DMA_UPDATE:
4977 {
4978 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_UPDATE]);
4979 break;
4980 }
4981 case TIM_DMA_CC1:
4982 {
4983 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC1]);
4984 break;
4985 }
4986 case TIM_DMA_CC2:
4987 {
4988 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC2]);
4989 break;
4990 }
4991 case TIM_DMA_CC3:
4992 {
4993 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC3]);
4994 break;
4995 }
4996 case TIM_DMA_CC4:
4997 {
4998 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_CC4]);
4999 break;
5000 }
5001 case TIM_DMA_COM:
5002 {
5003 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_COMMUTATION]);
5004 break;
5005 }
5006 case TIM_DMA_TRIGGER:
5007 {
5008 status = HAL_DMA_Abort_IT(htim->hdma[TIM_DMA_ID_TRIGGER]);
5009 break;
5010 }
5011 default:
5012 break;
5013 }
5014
5015 if (HAL_OK == status)
5016 {
5017 /* Disable the TIM Update DMA request */
5018 __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
5019 }
5020
5021 /* Change the DMA burst operation state */
5022 htim->DMABurstState = HAL_DMA_BURST_STATE_READY;
5023
5024 /* Return function status */
5025 return status;
5026 }
5027
5028 /**
5029 * @brief Generate a software event
5030 * @param htim TIM handle
5031 * @param EventSource specifies the event source.
5032 * This parameter can be one of the following values:
5033 * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
5034 * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
5035 * @arg TIM_EVENTSOURCE_CC2: Timer Capture Compare 2 Event source
5036 * @arg TIM_EVENTSOURCE_CC3: Timer Capture Compare 3 Event source
5037 * @arg TIM_EVENTSOURCE_CC4: Timer Capture Compare 4 Event source
5038 * @arg TIM_EVENTSOURCE_COM: Timer COM event source
5039 * @arg TIM_EVENTSOURCE_TRIGGER: Timer Trigger Event source
5040 * @arg TIM_EVENTSOURCE_BREAK: Timer Break event source
5041 * @arg TIM_EVENTSOURCE_BREAK2: Timer Break2 event source
5042 * @note Basic timers can only generate an update event.
5043 * @note TIM_EVENTSOURCE_COM is relevant only with advanced timer instances.
5044 * @note TIM_EVENTSOURCE_BREAK and TIM_EVENTSOURCE_BREAK2 are relevant
5045 * only for timer instances supporting break input(s).
5046 * @retval HAL status
5047 */
5048
HAL_TIM_GenerateEvent(TIM_HandleTypeDef * htim,uint32_t EventSource)5049 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
5050 {
5051 /* Check the parameters */
5052 assert_param(IS_TIM_INSTANCE(htim->Instance));
5053 assert_param(IS_TIM_EVENT_SOURCE(EventSource));
5054
5055 /* Process Locked */
5056 __HAL_LOCK(htim);
5057
5058 /* Change the TIM state */
5059 htim->State = HAL_TIM_STATE_BUSY;
5060
5061 /* Set the event sources */
5062 htim->Instance->EGR = EventSource;
5063
5064 /* Change the TIM state */
5065 htim->State = HAL_TIM_STATE_READY;
5066
5067 __HAL_UNLOCK(htim);
5068
5069 /* Return function status */
5070 return HAL_OK;
5071 }
5072
5073 /**
5074 * @brief Configures the OCRef clear feature
5075 * @param htim TIM handle
5076 * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
5077 * contains the OCREF clear feature and parameters for the TIM peripheral.
5078 * @param Channel specifies the TIM Channel
5079 * This parameter can be one of the following values:
5080 * @arg TIM_CHANNEL_1: TIM Channel 1
5081 * @arg TIM_CHANNEL_2: TIM Channel 2
5082 * @arg TIM_CHANNEL_3: TIM Channel 3
5083 * @arg TIM_CHANNEL_4: TIM Channel 4
5084 * @arg TIM_CHANNEL_5: TIM Channel 5
5085 * @arg TIM_CHANNEL_6: TIM Channel 6
5086 * @retval HAL status
5087 */
HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef * htim,TIM_ClearInputConfigTypeDef * sClearInputConfig,uint32_t Channel)5088 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
5089 TIM_ClearInputConfigTypeDef *sClearInputConfig,
5090 uint32_t Channel)
5091 {
5092 /* Check the parameters */
5093 assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
5094 assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
5095
5096 /* Process Locked */
5097 __HAL_LOCK(htim);
5098
5099 htim->State = HAL_TIM_STATE_BUSY;
5100
5101 switch (sClearInputConfig->ClearInputSource)
5102 {
5103 case TIM_CLEARINPUTSOURCE_NONE:
5104 {
5105 /* Clear the OCREF clear selection bit and the the ETR Bits */
5106 if (IS_TIM_OCCS_INSTANCE(htim->Instance))
5107 {
5108 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_OCCS | TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5109
5110 /* Clear TIMx_AF2_OCRSEL (reset value) */
5111 CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
5112 }
5113 else
5114 {
5115 CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
5116 }
5117 break;
5118 }
5119
5120 case TIM_CLEARINPUTSOURCE_COMP1:
5121 case TIM_CLEARINPUTSOURCE_COMP2:
5122 case TIM_CLEARINPUTSOURCE_COMP3:
5123 case TIM_CLEARINPUTSOURCE_COMP4:
5124 #if defined (COMP5)
5125 case TIM_CLEARINPUTSOURCE_COMP5:
5126 #endif /* COMP5 */
5127 #if defined (COMP6)
5128 case TIM_CLEARINPUTSOURCE_COMP6:
5129 #endif /* COMP6 */
5130 #if defined (COMP7)
5131 case TIM_CLEARINPUTSOURCE_COMP7:
5132 #endif /* COMP7 */
5133 {
5134 if (IS_TIM_OCCS_INSTANCE(htim->Instance))
5135 {
5136 /* Clear the OCREF clear selection bit */
5137 CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5138
5139 /* Clear TIM1_AF2_OCRSEL (reset value) */
5140 MODIFY_REG(htim->Instance->AF2, TIMx_AF2_OCRSEL, sClearInputConfig->ClearInputSource);
5141 }
5142 break;
5143 }
5144
5145 case TIM_CLEARINPUTSOURCE_ETR:
5146 {
5147 /* Check the parameters */
5148 assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
5149 assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
5150 assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
5151
5152 /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
5153 if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
5154 {
5155 htim->State = HAL_TIM_STATE_READY;
5156 __HAL_UNLOCK(htim);
5157 return HAL_ERROR;
5158 }
5159
5160 TIM_ETR_SetConfig(htim->Instance,
5161 sClearInputConfig->ClearInputPrescaler,
5162 sClearInputConfig->ClearInputPolarity,
5163 sClearInputConfig->ClearInputFilter);
5164
5165 if (IS_TIM_OCCS_INSTANCE(htim->Instance))
5166 {
5167 /* Set the OCREF clear selection bit */
5168 SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
5169
5170 /* Clear TIMx_AF2_OCRSEL (reset value) */
5171 CLEAR_BIT(htim->Instance->AF2, TIMx_AF2_OCRSEL);
5172 }
5173 break;
5174 }
5175
5176 default:
5177 break;
5178 }
5179
5180 switch (Channel)
5181 {
5182 case TIM_CHANNEL_1:
5183 {
5184 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5185 {
5186 /* Enable the OCREF clear feature for Channel 1 */
5187 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5188 }
5189 else
5190 {
5191 /* Disable the OCREF clear feature for Channel 1 */
5192 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC1CE);
5193 }
5194 break;
5195 }
5196 case TIM_CHANNEL_2:
5197 {
5198 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5199 {
5200 /* Enable the OCREF clear feature for Channel 2 */
5201 SET_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5202 }
5203 else
5204 {
5205 /* Disable the OCREF clear feature for Channel 2 */
5206 CLEAR_BIT(htim->Instance->CCMR1, TIM_CCMR1_OC2CE);
5207 }
5208 break;
5209 }
5210 case TIM_CHANNEL_3:
5211 {
5212 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5213 {
5214 /* Enable the OCREF clear feature for Channel 3 */
5215 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5216 }
5217 else
5218 {
5219 /* Disable the OCREF clear feature for Channel 3 */
5220 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC3CE);
5221 }
5222 break;
5223 }
5224 case TIM_CHANNEL_4:
5225 {
5226 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5227 {
5228 /* Enable the OCREF clear feature for Channel 4 */
5229 SET_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5230 }
5231 else
5232 {
5233 /* Disable the OCREF clear feature for Channel 4 */
5234 CLEAR_BIT(htim->Instance->CCMR2, TIM_CCMR2_OC4CE);
5235 }
5236 break;
5237 }
5238 case TIM_CHANNEL_5:
5239 {
5240 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5241 {
5242 /* Enable the OCREF clear feature for Channel 5 */
5243 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5244 }
5245 else
5246 {
5247 /* Disable the OCREF clear feature for Channel 5 */
5248 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC5CE);
5249 }
5250 break;
5251 }
5252 case TIM_CHANNEL_6:
5253 {
5254 if (sClearInputConfig->ClearInputState != (uint32_t)DISABLE)
5255 {
5256 /* Enable the OCREF clear feature for Channel 6 */
5257 SET_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5258 }
5259 else
5260 {
5261 /* Disable the OCREF clear feature for Channel 6 */
5262 CLEAR_BIT(htim->Instance->CCMR3, TIM_CCMR3_OC6CE);
5263 }
5264 break;
5265 }
5266 default:
5267 break;
5268 }
5269
5270 htim->State = HAL_TIM_STATE_READY;
5271
5272 __HAL_UNLOCK(htim);
5273
5274 return HAL_OK;
5275 }
5276
5277 /**
5278 * @brief Configures the clock source to be used
5279 * @param htim TIM handle
5280 * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
5281 * contains the clock source information for the TIM peripheral.
5282 * @retval HAL status
5283 */
HAL_TIM_ConfigClockSource(TIM_HandleTypeDef * htim,TIM_ClockConfigTypeDef * sClockSourceConfig)5284 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig)
5285 {
5286 uint32_t tmpsmcr;
5287
5288 /* Process Locked */
5289 __HAL_LOCK(htim);
5290
5291 htim->State = HAL_TIM_STATE_BUSY;
5292
5293 /* Check the parameters */
5294 assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
5295
5296 /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
5297 tmpsmcr = htim->Instance->SMCR;
5298 tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
5299 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
5300 htim->Instance->SMCR = tmpsmcr;
5301
5302 switch (sClockSourceConfig->ClockSource)
5303 {
5304 case TIM_CLOCKSOURCE_INTERNAL:
5305 {
5306 assert_param(IS_TIM_INSTANCE(htim->Instance));
5307 break;
5308 }
5309
5310 case TIM_CLOCKSOURCE_ETRMODE1:
5311 {
5312 /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
5313 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
5314
5315 /* Check ETR input conditioning related parameters */
5316 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5317 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5318 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5319
5320 /* Configure the ETR Clock source */
5321 TIM_ETR_SetConfig(htim->Instance,
5322 sClockSourceConfig->ClockPrescaler,
5323 sClockSourceConfig->ClockPolarity,
5324 sClockSourceConfig->ClockFilter);
5325
5326 /* Select the External clock mode1 and the ETRF trigger */
5327 tmpsmcr = htim->Instance->SMCR;
5328 tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
5329 /* Write to TIMx SMCR */
5330 htim->Instance->SMCR = tmpsmcr;
5331 break;
5332 }
5333
5334 case TIM_CLOCKSOURCE_ETRMODE2:
5335 {
5336 /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
5337 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
5338
5339 /* Check ETR input conditioning related parameters */
5340 assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
5341 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5342 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5343
5344 /* Configure the ETR Clock source */
5345 TIM_ETR_SetConfig(htim->Instance,
5346 sClockSourceConfig->ClockPrescaler,
5347 sClockSourceConfig->ClockPolarity,
5348 sClockSourceConfig->ClockFilter);
5349 /* Enable the External clock mode2 */
5350 htim->Instance->SMCR |= TIM_SMCR_ECE;
5351 break;
5352 }
5353
5354 case TIM_CLOCKSOURCE_TI1:
5355 {
5356 /* Check whether or not the timer instance supports external clock mode 1 */
5357 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5358
5359 /* Check TI1 input conditioning related parameters */
5360 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5361 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5362
5363 TIM_TI1_ConfigInputStage(htim->Instance,
5364 sClockSourceConfig->ClockPolarity,
5365 sClockSourceConfig->ClockFilter);
5366 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
5367 break;
5368 }
5369
5370 case TIM_CLOCKSOURCE_TI2:
5371 {
5372 /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
5373 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5374
5375 /* Check TI2 input conditioning related parameters */
5376 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5377 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5378
5379 TIM_TI2_ConfigInputStage(htim->Instance,
5380 sClockSourceConfig->ClockPolarity,
5381 sClockSourceConfig->ClockFilter);
5382 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
5383 break;
5384 }
5385
5386 case TIM_CLOCKSOURCE_TI1ED:
5387 {
5388 /* Check whether or not the timer instance supports external clock mode 1 */
5389 assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
5390
5391 /* Check TI1 input conditioning related parameters */
5392 assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
5393 assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
5394
5395 TIM_TI1_ConfigInputStage(htim->Instance,
5396 sClockSourceConfig->ClockPolarity,
5397 sClockSourceConfig->ClockFilter);
5398 TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
5399 break;
5400 }
5401
5402 case TIM_CLOCKSOURCE_ITR0:
5403 case TIM_CLOCKSOURCE_ITR1:
5404 case TIM_CLOCKSOURCE_ITR2:
5405 case TIM_CLOCKSOURCE_ITR3:
5406 #if defined (TIM5)
5407 case TIM_CLOCKSOURCE_ITR4:
5408 #endif /* TIM5 */
5409 case TIM_CLOCKSOURCE_ITR5:
5410 case TIM_CLOCKSOURCE_ITR6:
5411 case TIM_CLOCKSOURCE_ITR7:
5412 case TIM_CLOCKSOURCE_ITR8:
5413 #if defined (TIM20)
5414 case TIM_CLOCKSOURCE_ITR9:
5415 #endif /* TIM20 */
5416 case TIM_CLOCKSOURCE_ITR10:
5417 case TIM_CLOCKSOURCE_ITR11:
5418 {
5419 /* Check whether or not the timer instance supports internal trigger input */
5420 assert_param(IS_TIM_CLOCKSOURCE_INSTANCE((htim->Instance), sClockSourceConfig->ClockSource));
5421
5422 TIM_ITRx_SetConfig(htim->Instance, sClockSourceConfig->ClockSource);
5423 break;
5424 }
5425
5426 default:
5427 break;
5428 }
5429 htim->State = HAL_TIM_STATE_READY;
5430
5431 __HAL_UNLOCK(htim);
5432
5433 return HAL_OK;
5434 }
5435
5436 /**
5437 * @brief Selects the signal connected to the TI1 input: direct from CH1_input
5438 * or a XOR combination between CH1_input, CH2_input & CH3_input
5439 * @param htim TIM handle.
5440 * @param TI1_Selection Indicate whether or not channel 1 is connected to the
5441 * output of a XOR gate.
5442 * This parameter can be one of the following values:
5443 * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
5444 * @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
5445 * pins are connected to the TI1 input (XOR combination)
5446 * @retval HAL status
5447 */
HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef * htim,uint32_t TI1_Selection)5448 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
5449 {
5450 uint32_t tmpcr2;
5451
5452 /* Check the parameters */
5453 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
5454 assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
5455
5456 /* Get the TIMx CR2 register value */
5457 tmpcr2 = htim->Instance->CR2;
5458
5459 /* Reset the TI1 selection */
5460 tmpcr2 &= ~TIM_CR2_TI1S;
5461
5462 /* Set the TI1 selection */
5463 tmpcr2 |= TI1_Selection;
5464
5465 /* Write to TIMxCR2 */
5466 htim->Instance->CR2 = tmpcr2;
5467
5468 return HAL_OK;
5469 }
5470
5471 /**
5472 * @brief Configures the TIM in Slave mode
5473 * @param htim TIM handle.
5474 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5475 * contains the selected trigger (internal trigger input, filtered
5476 * timer input or external trigger input) and the Slave mode
5477 * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
5478 * @retval HAL status
5479 */
HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)5480 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig)
5481 {
5482 /* Check the parameters */
5483 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5484 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5485 assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
5486
5487 __HAL_LOCK(htim);
5488
5489 htim->State = HAL_TIM_STATE_BUSY;
5490
5491 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5492 {
5493 htim->State = HAL_TIM_STATE_READY;
5494 __HAL_UNLOCK(htim);
5495 return HAL_ERROR;
5496 }
5497
5498 /* Disable Trigger Interrupt */
5499 __HAL_TIM_DISABLE_IT(htim, TIM_IT_TRIGGER);
5500
5501 /* Disable Trigger DMA request */
5502 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5503
5504 htim->State = HAL_TIM_STATE_READY;
5505
5506 __HAL_UNLOCK(htim);
5507
5508 return HAL_OK;
5509 }
5510
5511 /**
5512 * @brief Configures the TIM in Slave mode in interrupt mode
5513 * @param htim TIM handle.
5514 * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
5515 * contains the selected trigger (internal trigger input, filtered
5516 * timer input or external trigger input) and the Slave mode
5517 * (Disable, Reset, Gated, Trigger, External clock mode 1, Reset + Trigger, Gated + Reset).
5518 * @retval HAL status
5519 */
HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)5520 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
5521 TIM_SlaveConfigTypeDef *sSlaveConfig)
5522 {
5523 /* Check the parameters */
5524 assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
5525 assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
5526 assert_param(IS_TIM_TRIGGER_INSTANCE(htim->Instance, sSlaveConfig->InputTrigger));
5527
5528 __HAL_LOCK(htim);
5529
5530 htim->State = HAL_TIM_STATE_BUSY;
5531
5532 if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
5533 {
5534 htim->State = HAL_TIM_STATE_READY;
5535 __HAL_UNLOCK(htim);
5536 return HAL_ERROR;
5537 }
5538
5539 /* Enable Trigger Interrupt */
5540 __HAL_TIM_ENABLE_IT(htim, TIM_IT_TRIGGER);
5541
5542 /* Disable Trigger DMA request */
5543 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_TRIGGER);
5544
5545 htim->State = HAL_TIM_STATE_READY;
5546
5547 __HAL_UNLOCK(htim);
5548
5549 return HAL_OK;
5550 }
5551
5552 /**
5553 * @brief Read the captured value from Capture Compare unit
5554 * @param htim TIM handle.
5555 * @param Channel TIM Channels to be enabled
5556 * This parameter can be one of the following values:
5557 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
5558 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
5559 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
5560 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
5561 * @retval Captured value
5562 */
HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef * htim,uint32_t Channel)5563 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
5564 {
5565 uint32_t tmpreg = 0U;
5566
5567 switch (Channel)
5568 {
5569 case TIM_CHANNEL_1:
5570 {
5571 /* Check the parameters */
5572 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
5573
5574 /* Return the capture 1 value */
5575 tmpreg = htim->Instance->CCR1;
5576
5577 break;
5578 }
5579 case TIM_CHANNEL_2:
5580 {
5581 /* Check the parameters */
5582 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
5583
5584 /* Return the capture 2 value */
5585 tmpreg = htim->Instance->CCR2;
5586
5587 break;
5588 }
5589
5590 case TIM_CHANNEL_3:
5591 {
5592 /* Check the parameters */
5593 assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
5594
5595 /* Return the capture 3 value */
5596 tmpreg = htim->Instance->CCR3;
5597
5598 break;
5599 }
5600
5601 case TIM_CHANNEL_4:
5602 {
5603 /* Check the parameters */
5604 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
5605
5606 /* Return the capture 4 value */
5607 tmpreg = htim->Instance->CCR4;
5608
5609 break;
5610 }
5611
5612 default:
5613 break;
5614 }
5615
5616 return tmpreg;
5617 }
5618
5619 /**
5620 * @}
5621 */
5622
5623 /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
5624 * @brief TIM Callbacks functions
5625 *
5626 @verbatim
5627 ==============================================================================
5628 ##### TIM Callbacks functions #####
5629 ==============================================================================
5630 [..]
5631 This section provides TIM callback functions:
5632 (+) TIM Period elapsed callback
5633 (+) TIM Output Compare callback
5634 (+) TIM Input capture callback
5635 (+) TIM Trigger callback
5636 (+) TIM Error callback
5637 (+) TIM Index callback
5638 (+) TIM Direction change callback
5639 (+) TIM Index error callback
5640 (+) TIM Transition error callback
5641
5642 @endverbatim
5643 * @{
5644 */
5645
5646 /**
5647 * @brief Period elapsed callback in non-blocking mode
5648 * @param htim TIM handle
5649 * @retval None
5650 */
HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef * htim)5651 __weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
5652 {
5653 /* Prevent unused argument(s) compilation warning */
5654 UNUSED(htim);
5655
5656 /* NOTE : This function should not be modified, when the callback is needed,
5657 the HAL_TIM_PeriodElapsedCallback could be implemented in the user file
5658 */
5659 }
5660
5661 /**
5662 * @brief Period elapsed half complete callback in non-blocking mode
5663 * @param htim TIM handle
5664 * @retval None
5665 */
HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef * htim)5666 __weak void HAL_TIM_PeriodElapsedHalfCpltCallback(TIM_HandleTypeDef *htim)
5667 {
5668 /* Prevent unused argument(s) compilation warning */
5669 UNUSED(htim);
5670
5671 /* NOTE : This function should not be modified, when the callback is needed,
5672 the HAL_TIM_PeriodElapsedHalfCpltCallback could be implemented in the user file
5673 */
5674 }
5675
5676 /**
5677 * @brief Output Compare callback in non-blocking mode
5678 * @param htim TIM OC handle
5679 * @retval None
5680 */
HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef * htim)5681 __weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
5682 {
5683 /* Prevent unused argument(s) compilation warning */
5684 UNUSED(htim);
5685
5686 /* NOTE : This function should not be modified, when the callback is needed,
5687 the HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
5688 */
5689 }
5690
5691 /**
5692 * @brief Input Capture callback in non-blocking mode
5693 * @param htim TIM IC handle
5694 * @retval None
5695 */
HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef * htim)5696 __weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
5697 {
5698 /* Prevent unused argument(s) compilation warning */
5699 UNUSED(htim);
5700
5701 /* NOTE : This function should not be modified, when the callback is needed,
5702 the HAL_TIM_IC_CaptureCallback could be implemented in the user file
5703 */
5704 }
5705
5706 /**
5707 * @brief Input Capture half complete callback in non-blocking mode
5708 * @param htim TIM IC handle
5709 * @retval None
5710 */
HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef * htim)5711 __weak void HAL_TIM_IC_CaptureHalfCpltCallback(TIM_HandleTypeDef *htim)
5712 {
5713 /* Prevent unused argument(s) compilation warning */
5714 UNUSED(htim);
5715
5716 /* NOTE : This function should not be modified, when the callback is needed,
5717 the HAL_TIM_IC_CaptureHalfCpltCallback could be implemented in the user file
5718 */
5719 }
5720
5721 /**
5722 * @brief PWM Pulse finished callback in non-blocking mode
5723 * @param htim TIM handle
5724 * @retval None
5725 */
HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef * htim)5726 __weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
5727 {
5728 /* Prevent unused argument(s) compilation warning */
5729 UNUSED(htim);
5730
5731 /* NOTE : This function should not be modified, when the callback is needed,
5732 the HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
5733 */
5734 }
5735
5736 /**
5737 * @brief PWM Pulse finished half complete callback in non-blocking mode
5738 * @param htim TIM handle
5739 * @retval None
5740 */
HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef * htim)5741 __weak void HAL_TIM_PWM_PulseFinishedHalfCpltCallback(TIM_HandleTypeDef *htim)
5742 {
5743 /* Prevent unused argument(s) compilation warning */
5744 UNUSED(htim);
5745
5746 /* NOTE : This function should not be modified, when the callback is needed,
5747 the HAL_TIM_PWM_PulseFinishedHalfCpltCallback could be implemented in the user file
5748 */
5749 }
5750
5751 /**
5752 * @brief Hall Trigger detection callback in non-blocking mode
5753 * @param htim TIM handle
5754 * @retval None
5755 */
HAL_TIM_TriggerCallback(TIM_HandleTypeDef * htim)5756 __weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
5757 {
5758 /* Prevent unused argument(s) compilation warning */
5759 UNUSED(htim);
5760
5761 /* NOTE : This function should not be modified, when the callback is needed,
5762 the HAL_TIM_TriggerCallback could be implemented in the user file
5763 */
5764 }
5765
5766 /**
5767 * @brief Hall Trigger detection half complete callback in non-blocking mode
5768 * @param htim TIM handle
5769 * @retval None
5770 */
HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef * htim)5771 __weak void HAL_TIM_TriggerHalfCpltCallback(TIM_HandleTypeDef *htim)
5772 {
5773 /* Prevent unused argument(s) compilation warning */
5774 UNUSED(htim);
5775
5776 /* NOTE : This function should not be modified, when the callback is needed,
5777 the HAL_TIM_TriggerHalfCpltCallback could be implemented in the user file
5778 */
5779 }
5780
5781 /**
5782 * @brief Timer error callback in non-blocking mode
5783 * @param htim TIM handle
5784 * @retval None
5785 */
HAL_TIM_ErrorCallback(TIM_HandleTypeDef * htim)5786 __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
5787 {
5788 /* Prevent unused argument(s) compilation warning */
5789 UNUSED(htim);
5790
5791 /* NOTE : This function should not be modified, when the callback is needed,
5792 the HAL_TIM_ErrorCallback could be implemented in the user file
5793 */
5794 }
5795
5796 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
5797 /**
5798 * @brief Register a User TIM callback to be used instead of the weak predefined callback
5799 * @param htim tim handle
5800 * @param CallbackID ID of the callback to be registered
5801 * This parameter can be one of the following values:
5802 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
5803 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
5804 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
5805 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
5806 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
5807 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
5808 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
5809 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
5810 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
5811 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
5812 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
5813 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
5814 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
5815 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
5816 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
5817 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
5818 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
5819 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
5820 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
5821 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
5822 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
5823 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
5824 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
5825 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
5826 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
5827 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
5828 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
5829 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
5830 * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
5831 * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
5832 * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
5833 * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transition Error Callback ID
5834 * @param pCallback pointer to the callback function
5835 * @retval status
5836 */
HAL_TIM_RegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID,pTIM_CallbackTypeDef pCallback)5837 HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
5838 pTIM_CallbackTypeDef pCallback)
5839 {
5840 HAL_StatusTypeDef status = HAL_OK;
5841
5842 if (pCallback == NULL)
5843 {
5844 return HAL_ERROR;
5845 }
5846 /* Process locked */
5847 __HAL_LOCK(htim);
5848
5849 if (htim->State == HAL_TIM_STATE_READY)
5850 {
5851 switch (CallbackID)
5852 {
5853 case HAL_TIM_BASE_MSPINIT_CB_ID :
5854 htim->Base_MspInitCallback = pCallback;
5855 break;
5856
5857 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5858 htim->Base_MspDeInitCallback = pCallback;
5859 break;
5860
5861 case HAL_TIM_IC_MSPINIT_CB_ID :
5862 htim->IC_MspInitCallback = pCallback;
5863 break;
5864
5865 case HAL_TIM_IC_MSPDEINIT_CB_ID :
5866 htim->IC_MspDeInitCallback = pCallback;
5867 break;
5868
5869 case HAL_TIM_OC_MSPINIT_CB_ID :
5870 htim->OC_MspInitCallback = pCallback;
5871 break;
5872
5873 case HAL_TIM_OC_MSPDEINIT_CB_ID :
5874 htim->OC_MspDeInitCallback = pCallback;
5875 break;
5876
5877 case HAL_TIM_PWM_MSPINIT_CB_ID :
5878 htim->PWM_MspInitCallback = pCallback;
5879 break;
5880
5881 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
5882 htim->PWM_MspDeInitCallback = pCallback;
5883 break;
5884
5885 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
5886 htim->OnePulse_MspInitCallback = pCallback;
5887 break;
5888
5889 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
5890 htim->OnePulse_MspDeInitCallback = pCallback;
5891 break;
5892
5893 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
5894 htim->Encoder_MspInitCallback = pCallback;
5895 break;
5896
5897 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
5898 htim->Encoder_MspDeInitCallback = pCallback;
5899 break;
5900
5901 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
5902 htim->HallSensor_MspInitCallback = pCallback;
5903 break;
5904
5905 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
5906 htim->HallSensor_MspDeInitCallback = pCallback;
5907 break;
5908
5909 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
5910 htim->PeriodElapsedCallback = pCallback;
5911 break;
5912
5913 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
5914 htim->PeriodElapsedHalfCpltCallback = pCallback;
5915 break;
5916
5917 case HAL_TIM_TRIGGER_CB_ID :
5918 htim->TriggerCallback = pCallback;
5919 break;
5920
5921 case HAL_TIM_TRIGGER_HALF_CB_ID :
5922 htim->TriggerHalfCpltCallback = pCallback;
5923 break;
5924
5925 case HAL_TIM_IC_CAPTURE_CB_ID :
5926 htim->IC_CaptureCallback = pCallback;
5927 break;
5928
5929 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
5930 htim->IC_CaptureHalfCpltCallback = pCallback;
5931 break;
5932
5933 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
5934 htim->OC_DelayElapsedCallback = pCallback;
5935 break;
5936
5937 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
5938 htim->PWM_PulseFinishedCallback = pCallback;
5939 break;
5940
5941 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
5942 htim->PWM_PulseFinishedHalfCpltCallback = pCallback;
5943 break;
5944
5945 case HAL_TIM_ERROR_CB_ID :
5946 htim->ErrorCallback = pCallback;
5947 break;
5948
5949 case HAL_TIM_COMMUTATION_CB_ID :
5950 htim->CommutationCallback = pCallback;
5951 break;
5952
5953 case HAL_TIM_COMMUTATION_HALF_CB_ID :
5954 htim->CommutationHalfCpltCallback = pCallback;
5955 break;
5956
5957 case HAL_TIM_BREAK_CB_ID :
5958 htim->BreakCallback = pCallback;
5959 break;
5960
5961 case HAL_TIM_BREAK2_CB_ID :
5962 htim->Break2Callback = pCallback;
5963 break;
5964
5965 case HAL_TIM_ENCODER_INDEX_CB_ID :
5966 htim->EncoderIndexCallback = pCallback;
5967 break;
5968
5969 case HAL_TIM_DIRECTION_CHANGE_CB_ID :
5970 htim->DirectionChangeCallback = pCallback;
5971 break;
5972
5973 case HAL_TIM_INDEX_ERROR_CB_ID :
5974 htim->IndexErrorCallback = pCallback;
5975 break;
5976
5977 case HAL_TIM_TRANSITION_ERROR_CB_ID :
5978 htim->TransitionErrorCallback = pCallback;
5979 break;
5980
5981 default :
5982 /* Return error status */
5983 status = HAL_ERROR;
5984 break;
5985 }
5986 }
5987 else if (htim->State == HAL_TIM_STATE_RESET)
5988 {
5989 switch (CallbackID)
5990 {
5991 case HAL_TIM_BASE_MSPINIT_CB_ID :
5992 htim->Base_MspInitCallback = pCallback;
5993 break;
5994
5995 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
5996 htim->Base_MspDeInitCallback = pCallback;
5997 break;
5998
5999 case HAL_TIM_IC_MSPINIT_CB_ID :
6000 htim->IC_MspInitCallback = pCallback;
6001 break;
6002
6003 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6004 htim->IC_MspDeInitCallback = pCallback;
6005 break;
6006
6007 case HAL_TIM_OC_MSPINIT_CB_ID :
6008 htim->OC_MspInitCallback = pCallback;
6009 break;
6010
6011 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6012 htim->OC_MspDeInitCallback = pCallback;
6013 break;
6014
6015 case HAL_TIM_PWM_MSPINIT_CB_ID :
6016 htim->PWM_MspInitCallback = pCallback;
6017 break;
6018
6019 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6020 htim->PWM_MspDeInitCallback = pCallback;
6021 break;
6022
6023 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6024 htim->OnePulse_MspInitCallback = pCallback;
6025 break;
6026
6027 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6028 htim->OnePulse_MspDeInitCallback = pCallback;
6029 break;
6030
6031 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6032 htim->Encoder_MspInitCallback = pCallback;
6033 break;
6034
6035 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6036 htim->Encoder_MspDeInitCallback = pCallback;
6037 break;
6038
6039 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6040 htim->HallSensor_MspInitCallback = pCallback;
6041 break;
6042
6043 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6044 htim->HallSensor_MspDeInitCallback = pCallback;
6045 break;
6046
6047 default :
6048 /* Return error status */
6049 status = HAL_ERROR;
6050 break;
6051 }
6052 }
6053 else
6054 {
6055 /* Return error status */
6056 status = HAL_ERROR;
6057 }
6058
6059 /* Release Lock */
6060 __HAL_UNLOCK(htim);
6061
6062 return status;
6063 }
6064
6065 /**
6066 * @brief Unregister a TIM callback
6067 * TIM callback is redirected to the weak predefined callback
6068 * @param htim tim handle
6069 * @param CallbackID ID of the callback to be unregistered
6070 * This parameter can be one of the following values:
6071 * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
6072 * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
6073 * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
6074 * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
6075 * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
6076 * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
6077 * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
6078 * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
6079 * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
6080 * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
6081 * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
6082 * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
6083 * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
6084 * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
6085 * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
6086 * @arg @ref HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID Period Elapsed half complete Callback ID
6087 * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
6088 * @arg @ref HAL_TIM_TRIGGER_HALF_CB_ID Trigger half complete Callback ID
6089 * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
6090 * @arg @ref HAL_TIM_IC_CAPTURE_HALF_CB_ID Input Capture half complete Callback ID
6091 * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
6092 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
6093 * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID PWM Pulse Finished half complete Callback ID
6094 * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
6095 * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
6096 * @arg @ref HAL_TIM_COMMUTATION_HALF_CB_ID Commutation half complete Callback ID
6097 * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
6098 * @arg @ref HAL_TIM_BREAK2_CB_ID Break2 Callback ID
6099 * @arg @ref HAL_TIM_ENCODER_INDEX_CB_ID Encoder Index Callback ID
6100 * @arg @ref HAL_TIM_DIRECTION_CHANGE_CB_ID Direction Change Callback ID
6101 * @arg @ref HAL_TIM_INDEX_ERROR_CB_ID Index Error Callback ID
6102 * @arg @ref HAL_TIM_TRANSITION_ERROR_CB_ID Transistion Error Callback ID
6103 * @retval status
6104 */
HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef * htim,HAL_TIM_CallbackIDTypeDef CallbackID)6105 HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
6106 {
6107 HAL_StatusTypeDef status = HAL_OK;
6108
6109 /* Process locked */
6110 __HAL_LOCK(htim);
6111
6112 if (htim->State == HAL_TIM_STATE_READY)
6113 {
6114 switch (CallbackID)
6115 {
6116 case HAL_TIM_BASE_MSPINIT_CB_ID :
6117 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
6118 break;
6119
6120 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6121 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
6122 break;
6123
6124 case HAL_TIM_IC_MSPINIT_CB_ID :
6125 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
6126 break;
6127
6128 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6129 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
6130 break;
6131
6132 case HAL_TIM_OC_MSPINIT_CB_ID :
6133 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
6134 break;
6135
6136 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6137 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
6138 break;
6139
6140 case HAL_TIM_PWM_MSPINIT_CB_ID :
6141 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
6142 break;
6143
6144 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6145 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
6146 break;
6147
6148 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6149 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
6150 break;
6151
6152 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6153 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
6154 break;
6155
6156 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6157 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
6158 break;
6159
6160 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6161 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
6162 break;
6163
6164 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6165 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
6166 break;
6167
6168 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6169 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
6170 break;
6171
6172 case HAL_TIM_PERIOD_ELAPSED_CB_ID :
6173 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
6174 break;
6175
6176 case HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID :
6177 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak Period Elapsed half complete Callback */
6178 break;
6179
6180 case HAL_TIM_TRIGGER_CB_ID :
6181 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
6182 break;
6183
6184 case HAL_TIM_TRIGGER_HALF_CB_ID :
6185 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak Trigger half complete Callback */
6186 break;
6187
6188 case HAL_TIM_IC_CAPTURE_CB_ID :
6189 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
6190 break;
6191
6192 case HAL_TIM_IC_CAPTURE_HALF_CB_ID :
6193 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC Capture half complete Callback */
6194 break;
6195
6196 case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
6197 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
6198 break;
6199
6200 case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
6201 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
6202 break;
6203
6204 case HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID :
6205 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM Pulse Finished half complete Callback */
6206 break;
6207
6208 case HAL_TIM_ERROR_CB_ID :
6209 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
6210 break;
6211
6212 case HAL_TIM_COMMUTATION_CB_ID :
6213 htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak Commutation Callback */
6214 break;
6215
6216 case HAL_TIM_COMMUTATION_HALF_CB_ID :
6217 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak Commutation half complete Callback */
6218 break;
6219
6220 case HAL_TIM_BREAK_CB_ID :
6221 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
6222 break;
6223
6224 case HAL_TIM_BREAK2_CB_ID :
6225 htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2 Callback */
6226 break;
6227
6228 case HAL_TIM_ENCODER_INDEX_CB_ID :
6229 htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; /* Legacy weak Encoder Index Callback */
6230 break;
6231
6232 case HAL_TIM_DIRECTION_CHANGE_CB_ID :
6233 htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; /* Legacy weak Direction Change Callback */
6234 break;
6235
6236 case HAL_TIM_INDEX_ERROR_CB_ID :
6237 htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; /* Legacy weak Index Error Callback */
6238 break;
6239
6240 case HAL_TIM_TRANSITION_ERROR_CB_ID :
6241 htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; /* Legacy weak Transition Error Callback */
6242 break;
6243
6244 default :
6245 /* Return error status */
6246 status = HAL_ERROR;
6247 break;
6248 }
6249 }
6250 else if (htim->State == HAL_TIM_STATE_RESET)
6251 {
6252 switch (CallbackID)
6253 {
6254 case HAL_TIM_BASE_MSPINIT_CB_ID :
6255 htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
6256 break;
6257
6258 case HAL_TIM_BASE_MSPDEINIT_CB_ID :
6259 htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
6260 break;
6261
6262 case HAL_TIM_IC_MSPINIT_CB_ID :
6263 htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
6264 break;
6265
6266 case HAL_TIM_IC_MSPDEINIT_CB_ID :
6267 htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
6268 break;
6269
6270 case HAL_TIM_OC_MSPINIT_CB_ID :
6271 htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
6272 break;
6273
6274 case HAL_TIM_OC_MSPDEINIT_CB_ID :
6275 htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
6276 break;
6277
6278 case HAL_TIM_PWM_MSPINIT_CB_ID :
6279 htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
6280 break;
6281
6282 case HAL_TIM_PWM_MSPDEINIT_CB_ID :
6283 htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
6284 break;
6285
6286 case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
6287 htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
6288 break;
6289
6290 case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
6291 htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
6292 break;
6293
6294 case HAL_TIM_ENCODER_MSPINIT_CB_ID :
6295 htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
6296 break;
6297
6298 case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
6299 htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
6300 break;
6301
6302 case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
6303 htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
6304 break;
6305
6306 case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
6307 htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
6308 break;
6309
6310 default :
6311 /* Return error status */
6312 status = HAL_ERROR;
6313 break;
6314 }
6315 }
6316 else
6317 {
6318 /* Return error status */
6319 status = HAL_ERROR;
6320 }
6321
6322 /* Release Lock */
6323 __HAL_UNLOCK(htim);
6324
6325 return status;
6326 }
6327 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6328
6329 /**
6330 * @}
6331 */
6332
6333 /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
6334 * @brief TIM Peripheral State functions
6335 *
6336 @verbatim
6337 ==============================================================================
6338 ##### Peripheral State functions #####
6339 ==============================================================================
6340 [..]
6341 This subsection permits to get in run-time the status of the peripheral
6342 and the data flow.
6343
6344 @endverbatim
6345 * @{
6346 */
6347
6348 /**
6349 * @brief Return the TIM Base handle state.
6350 * @param htim TIM Base handle
6351 * @retval HAL state
6352 */
HAL_TIM_Base_GetState(TIM_HandleTypeDef * htim)6353 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
6354 {
6355 return htim->State;
6356 }
6357
6358 /**
6359 * @brief Return the TIM OC handle state.
6360 * @param htim TIM Output Compare handle
6361 * @retval HAL state
6362 */
HAL_TIM_OC_GetState(TIM_HandleTypeDef * htim)6363 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
6364 {
6365 return htim->State;
6366 }
6367
6368 /**
6369 * @brief Return the TIM PWM handle state.
6370 * @param htim TIM handle
6371 * @retval HAL state
6372 */
HAL_TIM_PWM_GetState(TIM_HandleTypeDef * htim)6373 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
6374 {
6375 return htim->State;
6376 }
6377
6378 /**
6379 * @brief Return the TIM Input Capture handle state.
6380 * @param htim TIM IC handle
6381 * @retval HAL state
6382 */
HAL_TIM_IC_GetState(TIM_HandleTypeDef * htim)6383 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
6384 {
6385 return htim->State;
6386 }
6387
6388 /**
6389 * @brief Return the TIM One Pulse Mode handle state.
6390 * @param htim TIM OPM handle
6391 * @retval HAL state
6392 */
HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef * htim)6393 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
6394 {
6395 return htim->State;
6396 }
6397
6398 /**
6399 * @brief Return the TIM Encoder Mode handle state.
6400 * @param htim TIM Encoder Interface handle
6401 * @retval HAL state
6402 */
HAL_TIM_Encoder_GetState(TIM_HandleTypeDef * htim)6403 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
6404 {
6405 return htim->State;
6406 }
6407
6408 /**
6409 * @brief Return the TIM Encoder Mode handle state.
6410 * @param htim TIM handle
6411 * @retval Active channel
6412 */
HAL_TIM_GetActiveChannel(TIM_HandleTypeDef * htim)6413 HAL_TIM_ActiveChannel HAL_TIM_GetActiveChannel(TIM_HandleTypeDef *htim)
6414 {
6415 return htim->Channel;
6416 }
6417
6418 /**
6419 * @brief Return actual state of the TIM channel.
6420 * @param htim TIM handle
6421 * @param Channel TIM Channel
6422 * This parameter can be one of the following values:
6423 * @arg TIM_CHANNEL_1: TIM Channel 1
6424 * @arg TIM_CHANNEL_2: TIM Channel 2
6425 * @arg TIM_CHANNEL_3: TIM Channel 3
6426 * @arg TIM_CHANNEL_4: TIM Channel 4
6427 * @arg TIM_CHANNEL_5: TIM Channel 5
6428 * @arg TIM_CHANNEL_6: TIM Channel 6
6429 * @retval TIM Channel state
6430 */
HAL_TIM_GetChannelState(TIM_HandleTypeDef * htim,uint32_t Channel)6431 HAL_TIM_ChannelStateTypeDef HAL_TIM_GetChannelState(TIM_HandleTypeDef *htim, uint32_t Channel)
6432 {
6433 HAL_TIM_ChannelStateTypeDef channel_state;
6434
6435 /* Check the parameters */
6436 assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
6437
6438 channel_state = TIM_CHANNEL_STATE_GET(htim, Channel);
6439
6440 return channel_state;
6441 }
6442
6443 /**
6444 * @brief Return actual state of a DMA burst operation.
6445 * @param htim TIM handle
6446 * @retval DMA burst state
6447 */
HAL_TIM_DMABurstState(TIM_HandleTypeDef * htim)6448 HAL_TIM_DMABurstStateTypeDef HAL_TIM_DMABurstState(TIM_HandleTypeDef *htim)
6449 {
6450 /* Check the parameters */
6451 assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
6452
6453 return htim->DMABurstState;
6454 }
6455
6456 /**
6457 * @}
6458 */
6459
6460 /**
6461 * @}
6462 */
6463
6464 /** @defgroup TIM_Private_Functions TIM Private Functions
6465 * @{
6466 */
6467
6468 /**
6469 * @brief TIM DMA error callback
6470 * @param hdma pointer to DMA handle.
6471 * @retval None
6472 */
TIM_DMAError(DMA_HandleTypeDef * hdma)6473 void TIM_DMAError(DMA_HandleTypeDef *hdma)
6474 {
6475 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6476
6477 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6478 {
6479 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6480 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6481 }
6482 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6483 {
6484 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6485 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6486 }
6487 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6488 {
6489 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6490 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6491 }
6492 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6493 {
6494 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6495 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6496 }
6497 else
6498 {
6499 htim->State = HAL_TIM_STATE_READY;
6500 }
6501
6502 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6503 htim->ErrorCallback(htim);
6504 #else
6505 HAL_TIM_ErrorCallback(htim);
6506 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6507
6508 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6509 }
6510
6511 /**
6512 * @brief TIM DMA Delay Pulse complete callback.
6513 * @param hdma pointer to DMA handle.
6514 * @retval None
6515 */
TIM_DMADelayPulseCplt(DMA_HandleTypeDef * hdma)6516 void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
6517 {
6518 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6519
6520 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6521 {
6522 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6523
6524 if (hdma->Init.Mode == DMA_NORMAL)
6525 {
6526 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6527 }
6528 }
6529 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6530 {
6531 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6532
6533 if (hdma->Init.Mode == DMA_NORMAL)
6534 {
6535 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6536 }
6537 }
6538 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6539 {
6540 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6541
6542 if (hdma->Init.Mode == DMA_NORMAL)
6543 {
6544 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6545 }
6546 }
6547 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6548 {
6549 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6550
6551 if (hdma->Init.Mode == DMA_NORMAL)
6552 {
6553 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6554 }
6555 }
6556 else
6557 {
6558 /* nothing to do */
6559 }
6560
6561 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6562 htim->PWM_PulseFinishedCallback(htim);
6563 #else
6564 HAL_TIM_PWM_PulseFinishedCallback(htim);
6565 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6566
6567 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6568 }
6569
6570 /**
6571 * @brief TIM DMA Delay Pulse half complete callback.
6572 * @param hdma pointer to DMA handle.
6573 * @retval None
6574 */
TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef * hdma)6575 void TIM_DMADelayPulseHalfCplt(DMA_HandleTypeDef *hdma)
6576 {
6577 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6578
6579 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6580 {
6581 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6582 }
6583 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6584 {
6585 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6586 }
6587 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6588 {
6589 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6590 }
6591 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6592 {
6593 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6594 }
6595 else
6596 {
6597 /* nothing to do */
6598 }
6599
6600 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6601 htim->PWM_PulseFinishedHalfCpltCallback(htim);
6602 #else
6603 HAL_TIM_PWM_PulseFinishedHalfCpltCallback(htim);
6604 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6605
6606 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6607 }
6608
6609 /**
6610 * @brief TIM DMA Capture complete callback.
6611 * @param hdma pointer to DMA handle.
6612 * @retval None
6613 */
TIM_DMACaptureCplt(DMA_HandleTypeDef * hdma)6614 void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
6615 {
6616 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6617
6618 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6619 {
6620 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6621
6622 if (hdma->Init.Mode == DMA_NORMAL)
6623 {
6624 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6625 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_1, HAL_TIM_CHANNEL_STATE_READY);
6626 }
6627 }
6628 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6629 {
6630 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6631
6632 if (hdma->Init.Mode == DMA_NORMAL)
6633 {
6634 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6635 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_2, HAL_TIM_CHANNEL_STATE_READY);
6636 }
6637 }
6638 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6639 {
6640 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6641
6642 if (hdma->Init.Mode == DMA_NORMAL)
6643 {
6644 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6645 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
6646 }
6647 }
6648 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6649 {
6650 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6651
6652 if (hdma->Init.Mode == DMA_NORMAL)
6653 {
6654 TIM_CHANNEL_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6655 TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
6656 }
6657 }
6658 else
6659 {
6660 /* nothing to do */
6661 }
6662
6663 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6664 htim->IC_CaptureCallback(htim);
6665 #else
6666 HAL_TIM_IC_CaptureCallback(htim);
6667 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6668
6669 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6670 }
6671
6672 /**
6673 * @brief TIM DMA Capture half complete callback.
6674 * @param hdma pointer to DMA handle.
6675 * @retval None
6676 */
TIM_DMACaptureHalfCplt(DMA_HandleTypeDef * hdma)6677 void TIM_DMACaptureHalfCplt(DMA_HandleTypeDef *hdma)
6678 {
6679 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6680
6681 if (hdma == htim->hdma[TIM_DMA_ID_CC1])
6682 {
6683 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
6684 }
6685 else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
6686 {
6687 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
6688 }
6689 else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
6690 {
6691 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
6692 }
6693 else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
6694 {
6695 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
6696 }
6697 else
6698 {
6699 /* nothing to do */
6700 }
6701
6702 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6703 htim->IC_CaptureHalfCpltCallback(htim);
6704 #else
6705 HAL_TIM_IC_CaptureHalfCpltCallback(htim);
6706 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6707
6708 htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
6709 }
6710
6711 /**
6712 * @brief TIM DMA Period Elapse complete callback.
6713 * @param hdma pointer to DMA handle.
6714 * @retval None
6715 */
TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef * hdma)6716 static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
6717 {
6718 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6719
6720 if (htim->hdma[TIM_DMA_ID_UPDATE]->Init.Mode == DMA_NORMAL)
6721 {
6722 htim->State = HAL_TIM_STATE_READY;
6723 }
6724
6725 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6726 htim->PeriodElapsedCallback(htim);
6727 #else
6728 HAL_TIM_PeriodElapsedCallback(htim);
6729 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6730 }
6731
6732 /**
6733 * @brief TIM DMA Period Elapse half complete callback.
6734 * @param hdma pointer to DMA handle.
6735 * @retval None
6736 */
TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef * hdma)6737 static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma)
6738 {
6739 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6740
6741 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6742 htim->PeriodElapsedHalfCpltCallback(htim);
6743 #else
6744 HAL_TIM_PeriodElapsedHalfCpltCallback(htim);
6745 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6746 }
6747
6748 /**
6749 * @brief TIM DMA Trigger callback.
6750 * @param hdma pointer to DMA handle.
6751 * @retval None
6752 */
TIM_DMATriggerCplt(DMA_HandleTypeDef * hdma)6753 static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
6754 {
6755 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6756
6757 if (htim->hdma[TIM_DMA_ID_TRIGGER]->Init.Mode == DMA_NORMAL)
6758 {
6759 htim->State = HAL_TIM_STATE_READY;
6760 }
6761
6762 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6763 htim->TriggerCallback(htim);
6764 #else
6765 HAL_TIM_TriggerCallback(htim);
6766 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6767 }
6768
6769 /**
6770 * @brief TIM DMA Trigger half complete callback.
6771 * @param hdma pointer to DMA handle.
6772 * @retval None
6773 */
TIM_DMATriggerHalfCplt(DMA_HandleTypeDef * hdma)6774 static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma)
6775 {
6776 TIM_HandleTypeDef *htim = (TIM_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
6777
6778 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
6779 htim->TriggerHalfCpltCallback(htim);
6780 #else
6781 HAL_TIM_TriggerHalfCpltCallback(htim);
6782 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
6783 }
6784
6785 /**
6786 * @brief Time Base configuration
6787 * @param TIMx TIM peripheral
6788 * @param Structure TIM Base configuration structure
6789 * @retval None
6790 */
TIM_Base_SetConfig(TIM_TypeDef * TIMx,TIM_Base_InitTypeDef * Structure)6791 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
6792 {
6793 uint32_t tmpcr1;
6794 tmpcr1 = TIMx->CR1;
6795
6796 /* Set TIM Time Base Unit parameters ---------------------------------------*/
6797 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
6798 {
6799 /* Select the Counter Mode */
6800 tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
6801 tmpcr1 |= Structure->CounterMode;
6802 }
6803
6804 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
6805 {
6806 /* Set the clock division */
6807 tmpcr1 &= ~TIM_CR1_CKD;
6808 tmpcr1 |= (uint32_t)Structure->ClockDivision;
6809 }
6810
6811 /* Set the auto-reload preload */
6812 MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload);
6813
6814 TIMx->CR1 = tmpcr1;
6815
6816 /* Set the Autoreload value */
6817 TIMx->ARR = (uint32_t)Structure->Period ;
6818
6819 /* Set the Prescaler value */
6820 TIMx->PSC = Structure->Prescaler;
6821
6822 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
6823 {
6824 /* Set the Repetition Counter value */
6825 TIMx->RCR = Structure->RepetitionCounter;
6826 }
6827
6828 /* Generate an update event to reload the Prescaler
6829 and the repetition counter (only for advanced timer) value immediately */
6830 TIMx->EGR = TIM_EGR_UG;
6831 }
6832
6833 /**
6834 * @brief Timer Output Compare 1 configuration
6835 * @param TIMx to select the TIM peripheral
6836 * @param OC_Config The ouput configuration structure
6837 * @retval None
6838 */
TIM_OC1_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6839 static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6840 {
6841 uint32_t tmpccmrx;
6842 uint32_t tmpccer;
6843 uint32_t tmpcr2;
6844
6845 /* Disable the Channel 1: Reset the CC1E Bit */
6846 TIMx->CCER &= ~TIM_CCER_CC1E;
6847
6848 /* Get the TIMx CCER register value */
6849 tmpccer = TIMx->CCER;
6850 /* Get the TIMx CR2 register value */
6851 tmpcr2 = TIMx->CR2;
6852
6853 /* Get the TIMx CCMR1 register value */
6854 tmpccmrx = TIMx->CCMR1;
6855
6856 /* Reset the Output Compare Mode Bits */
6857 tmpccmrx &= ~TIM_CCMR1_OC1M;
6858 tmpccmrx &= ~TIM_CCMR1_CC1S;
6859 /* Select the Output Compare Mode */
6860 tmpccmrx |= OC_Config->OCMode;
6861
6862 /* Reset the Output Polarity level */
6863 tmpccer &= ~TIM_CCER_CC1P;
6864 /* Set the Output Compare Polarity */
6865 tmpccer |= OC_Config->OCPolarity;
6866
6867 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1))
6868 {
6869 /* Check parameters */
6870 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6871
6872 /* Reset the Output N Polarity level */
6873 tmpccer &= ~TIM_CCER_CC1NP;
6874 /* Set the Output N Polarity */
6875 tmpccer |= OC_Config->OCNPolarity;
6876 /* Reset the Output N State */
6877 tmpccer &= ~TIM_CCER_CC1NE;
6878 }
6879
6880 if (IS_TIM_BREAK_INSTANCE(TIMx))
6881 {
6882 /* Check parameters */
6883 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6884 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6885
6886 /* Reset the Output Compare and Output Compare N IDLE State */
6887 tmpcr2 &= ~TIM_CR2_OIS1;
6888 tmpcr2 &= ~TIM_CR2_OIS1N;
6889 /* Set the Output Idle state */
6890 tmpcr2 |= OC_Config->OCIdleState;
6891 /* Set the Output N Idle state */
6892 tmpcr2 |= OC_Config->OCNIdleState;
6893 }
6894
6895 /* Write to TIMx CR2 */
6896 TIMx->CR2 = tmpcr2;
6897
6898 /* Write to TIMx CCMR1 */
6899 TIMx->CCMR1 = tmpccmrx;
6900
6901 /* Set the Capture Compare Register value */
6902 TIMx->CCR1 = OC_Config->Pulse;
6903
6904 /* Write to TIMx CCER */
6905 TIMx->CCER = tmpccer;
6906 }
6907
6908 /**
6909 * @brief Timer Output Compare 2 configuration
6910 * @param TIMx to select the TIM peripheral
6911 * @param OC_Config The ouput configuration structure
6912 * @retval None
6913 */
TIM_OC2_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6914 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6915 {
6916 uint32_t tmpccmrx;
6917 uint32_t tmpccer;
6918 uint32_t tmpcr2;
6919
6920 /* Disable the Channel 2: Reset the CC2E Bit */
6921 TIMx->CCER &= ~TIM_CCER_CC2E;
6922
6923 /* Get the TIMx CCER register value */
6924 tmpccer = TIMx->CCER;
6925 /* Get the TIMx CR2 register value */
6926 tmpcr2 = TIMx->CR2;
6927
6928 /* Get the TIMx CCMR1 register value */
6929 tmpccmrx = TIMx->CCMR1;
6930
6931 /* Reset the Output Compare mode and Capture/Compare selection Bits */
6932 tmpccmrx &= ~TIM_CCMR1_OC2M;
6933 tmpccmrx &= ~TIM_CCMR1_CC2S;
6934
6935 /* Select the Output Compare Mode */
6936 tmpccmrx |= (OC_Config->OCMode << 8U);
6937
6938 /* Reset the Output Polarity level */
6939 tmpccer &= ~TIM_CCER_CC2P;
6940 /* Set the Output Compare Polarity */
6941 tmpccer |= (OC_Config->OCPolarity << 4U);
6942
6943 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2))
6944 {
6945 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
6946
6947 /* Reset the Output N Polarity level */
6948 tmpccer &= ~TIM_CCER_CC2NP;
6949 /* Set the Output N Polarity */
6950 tmpccer |= (OC_Config->OCNPolarity << 4U);
6951 /* Reset the Output N State */
6952 tmpccer &= ~TIM_CCER_CC2NE;
6953
6954 }
6955
6956 if (IS_TIM_BREAK_INSTANCE(TIMx))
6957 {
6958 /* Check parameters */
6959 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
6960 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
6961
6962 /* Reset the Output Compare and Output Compare N IDLE State */
6963 tmpcr2 &= ~TIM_CR2_OIS2;
6964 tmpcr2 &= ~TIM_CR2_OIS2N;
6965 /* Set the Output Idle state */
6966 tmpcr2 |= (OC_Config->OCIdleState << 2U);
6967 /* Set the Output N Idle state */
6968 tmpcr2 |= (OC_Config->OCNIdleState << 2U);
6969 }
6970
6971 /* Write to TIMx CR2 */
6972 TIMx->CR2 = tmpcr2;
6973
6974 /* Write to TIMx CCMR1 */
6975 TIMx->CCMR1 = tmpccmrx;
6976
6977 /* Set the Capture Compare Register value */
6978 TIMx->CCR2 = OC_Config->Pulse;
6979
6980 /* Write to TIMx CCER */
6981 TIMx->CCER = tmpccer;
6982 }
6983
6984 /**
6985 * @brief Timer Output Compare 3 configuration
6986 * @param TIMx to select the TIM peripheral
6987 * @param OC_Config The ouput configuration structure
6988 * @retval None
6989 */
TIM_OC3_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)6990 static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
6991 {
6992 uint32_t tmpccmrx;
6993 uint32_t tmpccer;
6994 uint32_t tmpcr2;
6995
6996 /* Disable the Channel 3: Reset the CC2E Bit */
6997 TIMx->CCER &= ~TIM_CCER_CC3E;
6998
6999 /* Get the TIMx CCER register value */
7000 tmpccer = TIMx->CCER;
7001 /* Get the TIMx CR2 register value */
7002 tmpcr2 = TIMx->CR2;
7003
7004 /* Get the TIMx CCMR2 register value */
7005 tmpccmrx = TIMx->CCMR2;
7006
7007 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7008 tmpccmrx &= ~TIM_CCMR2_OC3M;
7009 tmpccmrx &= ~TIM_CCMR2_CC3S;
7010 /* Select the Output Compare Mode */
7011 tmpccmrx |= OC_Config->OCMode;
7012
7013 /* Reset the Output Polarity level */
7014 tmpccer &= ~TIM_CCER_CC3P;
7015 /* Set the Output Compare Polarity */
7016 tmpccer |= (OC_Config->OCPolarity << 8U);
7017
7018 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3))
7019 {
7020 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7021
7022 /* Reset the Output N Polarity level */
7023 tmpccer &= ~TIM_CCER_CC3NP;
7024 /* Set the Output N Polarity */
7025 tmpccer |= (OC_Config->OCNPolarity << 8U);
7026 /* Reset the Output N State */
7027 tmpccer &= ~TIM_CCER_CC3NE;
7028 }
7029
7030 if (IS_TIM_BREAK_INSTANCE(TIMx))
7031 {
7032 /* Check parameters */
7033 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7034 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7035
7036 /* Reset the Output Compare and Output Compare N IDLE State */
7037 tmpcr2 &= ~TIM_CR2_OIS3;
7038 tmpcr2 &= ~TIM_CR2_OIS3N;
7039 /* Set the Output Idle state */
7040 tmpcr2 |= (OC_Config->OCIdleState << 4U);
7041 /* Set the Output N Idle state */
7042 tmpcr2 |= (OC_Config->OCNIdleState << 4U);
7043 }
7044
7045 /* Write to TIMx CR2 */
7046 TIMx->CR2 = tmpcr2;
7047
7048 /* Write to TIMx CCMR2 */
7049 TIMx->CCMR2 = tmpccmrx;
7050
7051 /* Set the Capture Compare Register value */
7052 TIMx->CCR3 = OC_Config->Pulse;
7053
7054 /* Write to TIMx CCER */
7055 TIMx->CCER = tmpccer;
7056 }
7057
7058 /**
7059 * @brief Timer Output Compare 4 configuration
7060 * @param TIMx to select the TIM peripheral
7061 * @param OC_Config The ouput configuration structure
7062 * @retval None
7063 */
TIM_OC4_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)7064 static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
7065 {
7066 uint32_t tmpccmrx;
7067 uint32_t tmpccer;
7068 uint32_t tmpcr2;
7069
7070 /* Disable the Channel 4: Reset the CC4E Bit */
7071 TIMx->CCER &= ~TIM_CCER_CC4E;
7072
7073 /* Get the TIMx CCER register value */
7074 tmpccer = TIMx->CCER;
7075 /* Get the TIMx CR2 register value */
7076 tmpcr2 = TIMx->CR2;
7077
7078 /* Get the TIMx CCMR2 register value */
7079 tmpccmrx = TIMx->CCMR2;
7080
7081 /* Reset the Output Compare mode and Capture/Compare selection Bits */
7082 tmpccmrx &= ~TIM_CCMR2_OC4M;
7083 tmpccmrx &= ~TIM_CCMR2_CC4S;
7084
7085 /* Select the Output Compare Mode */
7086 tmpccmrx |= (OC_Config->OCMode << 8U);
7087
7088 /* Reset the Output Polarity level */
7089 tmpccer &= ~TIM_CCER_CC4P;
7090 /* Set the Output Compare Polarity */
7091 tmpccer |= (OC_Config->OCPolarity << 12U);
7092
7093 if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_4))
7094 {
7095 assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity));
7096
7097 /* Reset the Output N Polarity level */
7098 tmpccer &= ~TIM_CCER_CC4NP;
7099 /* Set the Output N Polarity */
7100 tmpccer |= (OC_Config->OCNPolarity << 12U);
7101 /* Reset the Output N State */
7102 tmpccer &= ~TIM_CCER_CC4NE;
7103 }
7104
7105 if (IS_TIM_BREAK_INSTANCE(TIMx))
7106 {
7107 /* Check parameters */
7108 assert_param(IS_TIM_OCNIDLE_STATE(OC_Config->OCNIdleState));
7109 assert_param(IS_TIM_OCIDLE_STATE(OC_Config->OCIdleState));
7110
7111 /* Reset the Output Compare IDLE State */
7112 tmpcr2 &= ~TIM_CR2_OIS4;
7113 /* Reset the Output Compare N IDLE State */
7114 tmpcr2 &= ~TIM_CR2_OIS4N;
7115
7116 /* Set the Output Idle state */
7117 tmpcr2 |= (OC_Config->OCIdleState << 6U);
7118 /* Set the Output N Idle state */
7119 tmpcr2 |= (OC_Config->OCNIdleState << 6U);
7120 }
7121
7122 /* Write to TIMx CR2 */
7123 TIMx->CR2 = tmpcr2;
7124
7125 /* Write to TIMx CCMR2 */
7126 TIMx->CCMR2 = tmpccmrx;
7127
7128 /* Set the Capture Compare Register value */
7129 TIMx->CCR4 = OC_Config->Pulse;
7130
7131 /* Write to TIMx CCER */
7132 TIMx->CCER = tmpccer;
7133 }
7134
7135 /**
7136 * @brief Timer Output Compare 5 configuration
7137 * @param TIMx to select the TIM peripheral
7138 * @param OC_Config The ouput configuration structure
7139 * @retval None
7140 */
TIM_OC5_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)7141 static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
7142 TIM_OC_InitTypeDef *OC_Config)
7143 {
7144 uint32_t tmpccmrx;
7145 uint32_t tmpccer;
7146 uint32_t tmpcr2;
7147
7148 /* Disable the output: Reset the CCxE Bit */
7149 TIMx->CCER &= ~TIM_CCER_CC5E;
7150
7151 /* Get the TIMx CCER register value */
7152 tmpccer = TIMx->CCER;
7153 /* Get the TIMx CR2 register value */
7154 tmpcr2 = TIMx->CR2;
7155 /* Get the TIMx CCMR1 register value */
7156 tmpccmrx = TIMx->CCMR3;
7157
7158 /* Reset the Output Compare Mode Bits */
7159 tmpccmrx &= ~(TIM_CCMR3_OC5M);
7160 /* Select the Output Compare Mode */
7161 tmpccmrx |= OC_Config->OCMode;
7162
7163 /* Reset the Output Polarity level */
7164 tmpccer &= ~TIM_CCER_CC5P;
7165 /* Set the Output Compare Polarity */
7166 tmpccer |= (OC_Config->OCPolarity << 16U);
7167
7168 if (IS_TIM_BREAK_INSTANCE(TIMx))
7169 {
7170 /* Reset the Output Compare IDLE State */
7171 tmpcr2 &= ~TIM_CR2_OIS5;
7172 /* Set the Output Idle state */
7173 tmpcr2 |= (OC_Config->OCIdleState << 8U);
7174 }
7175 /* Write to TIMx CR2 */
7176 TIMx->CR2 = tmpcr2;
7177
7178 /* Write to TIMx CCMR3 */
7179 TIMx->CCMR3 = tmpccmrx;
7180
7181 /* Set the Capture Compare Register value */
7182 TIMx->CCR5 = OC_Config->Pulse;
7183
7184 /* Write to TIMx CCER */
7185 TIMx->CCER = tmpccer;
7186 }
7187
7188 /**
7189 * @brief Timer Output Compare 6 configuration
7190 * @param TIMx to select the TIM peripheral
7191 * @param OC_Config The ouput configuration structure
7192 * @retval None
7193 */
TIM_OC6_SetConfig(TIM_TypeDef * TIMx,TIM_OC_InitTypeDef * OC_Config)7194 static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
7195 TIM_OC_InitTypeDef *OC_Config)
7196 {
7197 uint32_t tmpccmrx;
7198 uint32_t tmpccer;
7199 uint32_t tmpcr2;
7200
7201 /* Disable the output: Reset the CCxE Bit */
7202 TIMx->CCER &= ~TIM_CCER_CC6E;
7203
7204 /* Get the TIMx CCER register value */
7205 tmpccer = TIMx->CCER;
7206 /* Get the TIMx CR2 register value */
7207 tmpcr2 = TIMx->CR2;
7208 /* Get the TIMx CCMR1 register value */
7209 tmpccmrx = TIMx->CCMR3;
7210
7211 /* Reset the Output Compare Mode Bits */
7212 tmpccmrx &= ~(TIM_CCMR3_OC6M);
7213 /* Select the Output Compare Mode */
7214 tmpccmrx |= (OC_Config->OCMode << 8U);
7215
7216 /* Reset the Output Polarity level */
7217 tmpccer &= (uint32_t)~TIM_CCER_CC6P;
7218 /* Set the Output Compare Polarity */
7219 tmpccer |= (OC_Config->OCPolarity << 20U);
7220
7221 if (IS_TIM_BREAK_INSTANCE(TIMx))
7222 {
7223 /* Reset the Output Compare IDLE State */
7224 tmpcr2 &= ~TIM_CR2_OIS6;
7225 /* Set the Output Idle state */
7226 tmpcr2 |= (OC_Config->OCIdleState << 10U);
7227 }
7228
7229 /* Write to TIMx CR2 */
7230 TIMx->CR2 = tmpcr2;
7231
7232 /* Write to TIMx CCMR3 */
7233 TIMx->CCMR3 = tmpccmrx;
7234
7235 /* Set the Capture Compare Register value */
7236 TIMx->CCR6 = OC_Config->Pulse;
7237
7238 /* Write to TIMx CCER */
7239 TIMx->CCER = tmpccer;
7240 }
7241
7242 /**
7243 * @brief Slave Timer configuration function
7244 * @param htim TIM handle
7245 * @param sSlaveConfig Slave timer configuration
7246 * @retval None
7247 */
TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef * htim,TIM_SlaveConfigTypeDef * sSlaveConfig)7248 static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
7249 TIM_SlaveConfigTypeDef *sSlaveConfig)
7250 {
7251 uint32_t tmpsmcr;
7252 uint32_t tmpccmr1;
7253 uint32_t tmpccer;
7254
7255 /* Get the TIMx SMCR register value */
7256 tmpsmcr = htim->Instance->SMCR;
7257
7258 /* Reset the Trigger Selection Bits */
7259 tmpsmcr &= ~TIM_SMCR_TS;
7260 /* Set the Input Trigger source */
7261 tmpsmcr |= sSlaveConfig->InputTrigger;
7262
7263 /* Reset the slave mode Bits */
7264 tmpsmcr &= ~TIM_SMCR_SMS;
7265 /* Set the slave mode */
7266 tmpsmcr |= sSlaveConfig->SlaveMode;
7267
7268 /* Write to TIMx SMCR */
7269 htim->Instance->SMCR = tmpsmcr;
7270
7271 /* Configure the trigger prescaler, filter, and polarity */
7272 switch (sSlaveConfig->InputTrigger)
7273 {
7274 case TIM_TS_ETRF:
7275 {
7276 /* Check the parameters */
7277 assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
7278 assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
7279 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7280 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7281 /* Configure the ETR Trigger source */
7282 TIM_ETR_SetConfig(htim->Instance,
7283 sSlaveConfig->TriggerPrescaler,
7284 sSlaveConfig->TriggerPolarity,
7285 sSlaveConfig->TriggerFilter);
7286 break;
7287 }
7288
7289 case TIM_TS_TI1F_ED:
7290 {
7291 /* Check the parameters */
7292 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7293 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7294
7295 if ((sSlaveConfig->SlaveMode == TIM_SLAVEMODE_GATED) || (sSlaveConfig->SlaveMode == TIM_SLAVEMODE_COMBINED_GATEDRESET))
7296 {
7297 return HAL_ERROR;
7298 }
7299
7300 /* Disable the Channel 1: Reset the CC1E Bit */
7301 tmpccer = htim->Instance->CCER;
7302 htim->Instance->CCER &= ~TIM_CCER_CC1E;
7303 tmpccmr1 = htim->Instance->CCMR1;
7304
7305 /* Set the filter */
7306 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7307 tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4U);
7308
7309 /* Write to TIMx CCMR1 and CCER registers */
7310 htim->Instance->CCMR1 = tmpccmr1;
7311 htim->Instance->CCER = tmpccer;
7312 break;
7313 }
7314
7315 case TIM_TS_TI1FP1:
7316 {
7317 /* Check the parameters */
7318 assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
7319 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7320 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7321
7322 /* Configure TI1 Filter and Polarity */
7323 TIM_TI1_ConfigInputStage(htim->Instance,
7324 sSlaveConfig->TriggerPolarity,
7325 sSlaveConfig->TriggerFilter);
7326 break;
7327 }
7328
7329 case TIM_TS_TI2FP2:
7330 {
7331 /* Check the parameters */
7332 assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
7333 assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
7334 assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
7335
7336 /* Configure TI2 Filter and Polarity */
7337 TIM_TI2_ConfigInputStage(htim->Instance,
7338 sSlaveConfig->TriggerPolarity,
7339 sSlaveConfig->TriggerFilter);
7340 break;
7341 }
7342
7343 case TIM_TS_ITR0:
7344 case TIM_TS_ITR1:
7345 case TIM_TS_ITR2:
7346 case TIM_TS_ITR3:
7347 #if defined (TIM5)
7348 case TIM_TS_ITR4:
7349 #endif /* TIM5 */
7350 case TIM_TS_ITR5:
7351 case TIM_TS_ITR6:
7352 case TIM_TS_ITR7:
7353 case TIM_TS_ITR8:
7354 #if defined (TIM20)
7355 case TIM_TS_ITR9:
7356 #endif /* TIM20 */
7357 case TIM_TS_ITR10:
7358 case TIM_TS_ITR11:
7359 {
7360 /* Check the parameter */
7361 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_INSTANCE((htim->Instance), sSlaveConfig->InputTrigger));
7362 break;
7363 }
7364
7365 default:
7366 break;
7367 }
7368 return HAL_OK;
7369 }
7370
7371 /**
7372 * @brief Configure the TI1 as Input.
7373 * @param TIMx to select the TIM peripheral.
7374 * @param TIM_ICPolarity The Input Polarity.
7375 * This parameter can be one of the following values:
7376 * @arg TIM_ICPOLARITY_RISING
7377 * @arg TIM_ICPOLARITY_FALLING
7378 * @arg TIM_ICPOLARITY_BOTHEDGE
7379 * @param TIM_ICSelection specifies the input to be used.
7380 * This parameter can be one of the following values:
7381 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 1 is selected to be connected to IC1.
7382 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 1 is selected to be connected to IC2.
7383 * @arg TIM_ICSELECTION_TRC: TIM Input 1 is selected to be connected to TRC.
7384 * @param TIM_ICFilter Specifies the Input Capture Filter.
7385 * This parameter must be a value between 0x00 and 0x0F.
7386 * @retval None
7387 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
7388 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be
7389 * protected against un-initialized filter and polarity values.
7390 */
TIM_TI1_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7391 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7392 uint32_t TIM_ICFilter)
7393 {
7394 uint32_t tmpccmr1;
7395 uint32_t tmpccer;
7396
7397 /* Disable the Channel 1: Reset the CC1E Bit */
7398 TIMx->CCER &= ~TIM_CCER_CC1E;
7399 tmpccmr1 = TIMx->CCMR1;
7400 tmpccer = TIMx->CCER;
7401
7402 /* Select the Input */
7403 if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
7404 {
7405 tmpccmr1 &= ~TIM_CCMR1_CC1S;
7406 tmpccmr1 |= TIM_ICSelection;
7407 }
7408 else
7409 {
7410 tmpccmr1 |= TIM_CCMR1_CC1S_0;
7411 }
7412
7413 /* Set the filter */
7414 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7415 tmpccmr1 |= ((TIM_ICFilter << 4U) & TIM_CCMR1_IC1F);
7416
7417 /* Select the Polarity and set the CC1E Bit */
7418 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7419 tmpccer |= (TIM_ICPolarity & (TIM_CCER_CC1P | TIM_CCER_CC1NP));
7420
7421 /* Write to TIMx CCMR1 and CCER registers */
7422 TIMx->CCMR1 = tmpccmr1;
7423 TIMx->CCER = tmpccer;
7424 }
7425
7426 /**
7427 * @brief Configure the Polarity and Filter for TI1.
7428 * @param TIMx to select the TIM peripheral.
7429 * @param TIM_ICPolarity The Input Polarity.
7430 * This parameter can be one of the following values:
7431 * @arg TIM_ICPOLARITY_RISING
7432 * @arg TIM_ICPOLARITY_FALLING
7433 * @arg TIM_ICPOLARITY_BOTHEDGE
7434 * @param TIM_ICFilter Specifies the Input Capture Filter.
7435 * This parameter must be a value between 0x00 and 0x0F.
7436 * @retval None
7437 */
TIM_TI1_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7438 static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7439 {
7440 uint32_t tmpccmr1;
7441 uint32_t tmpccer;
7442
7443 /* Disable the Channel 1: Reset the CC1E Bit */
7444 tmpccer = TIMx->CCER;
7445 TIMx->CCER &= ~TIM_CCER_CC1E;
7446 tmpccmr1 = TIMx->CCMR1;
7447
7448 /* Set the filter */
7449 tmpccmr1 &= ~TIM_CCMR1_IC1F;
7450 tmpccmr1 |= (TIM_ICFilter << 4U);
7451
7452 /* Select the Polarity and set the CC1E Bit */
7453 tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
7454 tmpccer |= TIM_ICPolarity;
7455
7456 /* Write to TIMx CCMR1 and CCER registers */
7457 TIMx->CCMR1 = tmpccmr1;
7458 TIMx->CCER = tmpccer;
7459 }
7460
7461 /**
7462 * @brief Configure the TI2 as Input.
7463 * @param TIMx to select the TIM peripheral
7464 * @param TIM_ICPolarity The Input Polarity.
7465 * This parameter can be one of the following values:
7466 * @arg TIM_ICPOLARITY_RISING
7467 * @arg TIM_ICPOLARITY_FALLING
7468 * @arg TIM_ICPOLARITY_BOTHEDGE
7469 * @param TIM_ICSelection specifies the input to be used.
7470 * This parameter can be one of the following values:
7471 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 2 is selected to be connected to IC2.
7472 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
7473 * @arg TIM_ICSELECTION_TRC: TIM Input 2 is selected to be connected to TRC.
7474 * @param TIM_ICFilter Specifies the Input Capture Filter.
7475 * This parameter must be a value between 0x00 and 0x0F.
7476 * @retval None
7477 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
7478 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be
7479 * protected against un-initialized filter and polarity values.
7480 */
TIM_TI2_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7481 static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7482 uint32_t TIM_ICFilter)
7483 {
7484 uint32_t tmpccmr1;
7485 uint32_t tmpccer;
7486
7487 /* Disable the Channel 2: Reset the CC2E Bit */
7488 TIMx->CCER &= ~TIM_CCER_CC2E;
7489 tmpccmr1 = TIMx->CCMR1;
7490 tmpccer = TIMx->CCER;
7491
7492 /* Select the Input */
7493 tmpccmr1 &= ~TIM_CCMR1_CC2S;
7494 tmpccmr1 |= (TIM_ICSelection << 8U);
7495
7496 /* Set the filter */
7497 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7498 tmpccmr1 |= ((TIM_ICFilter << 12U) & TIM_CCMR1_IC2F);
7499
7500 /* Select the Polarity and set the CC2E Bit */
7501 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7502 tmpccer |= ((TIM_ICPolarity << 4U) & (TIM_CCER_CC2P | TIM_CCER_CC2NP));
7503
7504 /* Write to TIMx CCMR1 and CCER registers */
7505 TIMx->CCMR1 = tmpccmr1 ;
7506 TIMx->CCER = tmpccer;
7507 }
7508
7509 /**
7510 * @brief Configure the Polarity and Filter for TI2.
7511 * @param TIMx to select the TIM peripheral.
7512 * @param TIM_ICPolarity The Input Polarity.
7513 * This parameter can be one of the following values:
7514 * @arg TIM_ICPOLARITY_RISING
7515 * @arg TIM_ICPOLARITY_FALLING
7516 * @arg TIM_ICPOLARITY_BOTHEDGE
7517 * @param TIM_ICFilter Specifies the Input Capture Filter.
7518 * This parameter must be a value between 0x00 and 0x0F.
7519 * @retval None
7520 */
TIM_TI2_ConfigInputStage(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICFilter)7521 static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
7522 {
7523 uint32_t tmpccmr1;
7524 uint32_t tmpccer;
7525
7526 /* Disable the Channel 2: Reset the CC2E Bit */
7527 TIMx->CCER &= ~TIM_CCER_CC2E;
7528 tmpccmr1 = TIMx->CCMR1;
7529 tmpccer = TIMx->CCER;
7530
7531 /* Set the filter */
7532 tmpccmr1 &= ~TIM_CCMR1_IC2F;
7533 tmpccmr1 |= (TIM_ICFilter << 12U);
7534
7535 /* Select the Polarity and set the CC2E Bit */
7536 tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
7537 tmpccer |= (TIM_ICPolarity << 4U);
7538
7539 /* Write to TIMx CCMR1 and CCER registers */
7540 TIMx->CCMR1 = tmpccmr1 ;
7541 TIMx->CCER = tmpccer;
7542 }
7543
7544 /**
7545 * @brief Configure the TI3 as Input.
7546 * @param TIMx to select the TIM peripheral
7547 * @param TIM_ICPolarity The Input Polarity.
7548 * This parameter can be one of the following values:
7549 * @arg TIM_ICPOLARITY_RISING
7550 * @arg TIM_ICPOLARITY_FALLING
7551 * @arg TIM_ICPOLARITY_BOTHEDGE
7552 * @param TIM_ICSelection specifies the input to be used.
7553 * This parameter can be one of the following values:
7554 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 3 is selected to be connected to IC3.
7555 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
7556 * @arg TIM_ICSELECTION_TRC: TIM Input 3 is selected to be connected to TRC.
7557 * @param TIM_ICFilter Specifies the Input Capture Filter.
7558 * This parameter must be a value between 0x00 and 0x0F.
7559 * @retval None
7560 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
7561 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7562 * protected against un-initialized filter and polarity values.
7563 */
TIM_TI3_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7564 static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7565 uint32_t TIM_ICFilter)
7566 {
7567 uint32_t tmpccmr2;
7568 uint32_t tmpccer;
7569
7570 /* Disable the Channel 3: Reset the CC3E Bit */
7571 TIMx->CCER &= ~TIM_CCER_CC3E;
7572 tmpccmr2 = TIMx->CCMR2;
7573 tmpccer = TIMx->CCER;
7574
7575 /* Select the Input */
7576 tmpccmr2 &= ~TIM_CCMR2_CC3S;
7577 tmpccmr2 |= TIM_ICSelection;
7578
7579 /* Set the filter */
7580 tmpccmr2 &= ~TIM_CCMR2_IC3F;
7581 tmpccmr2 |= ((TIM_ICFilter << 4U) & TIM_CCMR2_IC3F);
7582
7583 /* Select the Polarity and set the CC3E Bit */
7584 tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
7585 tmpccer |= ((TIM_ICPolarity << 8U) & (TIM_CCER_CC3P | TIM_CCER_CC3NP));
7586
7587 /* Write to TIMx CCMR2 and CCER registers */
7588 TIMx->CCMR2 = tmpccmr2;
7589 TIMx->CCER = tmpccer;
7590 }
7591
7592 /**
7593 * @brief Configure the TI4 as Input.
7594 * @param TIMx to select the TIM peripheral
7595 * @param TIM_ICPolarity The Input Polarity.
7596 * This parameter can be one of the following values:
7597 * @arg TIM_ICPOLARITY_RISING
7598 * @arg TIM_ICPOLARITY_FALLING
7599 * @arg TIM_ICPOLARITY_BOTHEDGE
7600 * @param TIM_ICSelection specifies the input to be used.
7601 * This parameter can be one of the following values:
7602 * @arg TIM_ICSELECTION_DIRECTTI: TIM Input 4 is selected to be connected to IC4.
7603 * @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
7604 * @arg TIM_ICSELECTION_TRC: TIM Input 4 is selected to be connected to TRC.
7605 * @param TIM_ICFilter Specifies the Input Capture Filter.
7606 * This parameter must be a value between 0x00 and 0x0F.
7607 * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
7608 * (on channel1 path) is used as the input signal. Therefore CCMR2 must be
7609 * protected against un-initialized filter and polarity values.
7610 * @retval None
7611 */
TIM_TI4_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ICPolarity,uint32_t TIM_ICSelection,uint32_t TIM_ICFilter)7612 static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
7613 uint32_t TIM_ICFilter)
7614 {
7615 uint32_t tmpccmr2;
7616 uint32_t tmpccer;
7617
7618 /* Disable the Channel 4: Reset the CC4E Bit */
7619 TIMx->CCER &= ~TIM_CCER_CC4E;
7620 tmpccmr2 = TIMx->CCMR2;
7621 tmpccer = TIMx->CCER;
7622
7623 /* Select the Input */
7624 tmpccmr2 &= ~TIM_CCMR2_CC4S;
7625 tmpccmr2 |= (TIM_ICSelection << 8U);
7626
7627 /* Set the filter */
7628 tmpccmr2 &= ~TIM_CCMR2_IC4F;
7629 tmpccmr2 |= ((TIM_ICFilter << 12U) & TIM_CCMR2_IC4F);
7630
7631 /* Select the Polarity and set the CC4E Bit */
7632 tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
7633 tmpccer |= ((TIM_ICPolarity << 12U) & (TIM_CCER_CC4P | TIM_CCER_CC4NP));
7634
7635 /* Write to TIMx CCMR2 and CCER registers */
7636 TIMx->CCMR2 = tmpccmr2;
7637 TIMx->CCER = tmpccer ;
7638 }
7639
7640 /**
7641 * @brief Selects the Input Trigger source
7642 * @param TIMx to select the TIM peripheral
7643 * @param InputTriggerSource The Input Trigger source.
7644 * This parameter can be one of the following values:
7645 * @arg TIM_TS_ITR0: Internal Trigger 0
7646 * @arg TIM_TS_ITR1: Internal Trigger 1
7647 * @arg TIM_TS_ITR2: Internal Trigger 2
7648 * @arg TIM_TS_ITR3: Internal Trigger 3
7649 * @arg TIM_TS_TI1F_ED: TI1 Edge Detector
7650 * @arg TIM_TS_TI1FP1: Filtered Timer Input 1
7651 * @arg TIM_TS_TI2FP2: Filtered Timer Input 2
7652 * @arg TIM_TS_ETRF: External Trigger input
7653 * @arg TIM_TS_ITR4: Internal Trigger 4 (*)
7654 * @arg TIM_TS_ITR5: Internal Trigger 5
7655 * @arg TIM_TS_ITR6: Internal Trigger 6
7656 * @arg TIM_TS_ITR7: Internal Trigger 7
7657 * @arg TIM_TS_ITR8: Internal Trigger 8
7658 * @arg TIM_TS_ITR9: Internal Trigger 9 (*)
7659 * @arg TIM_TS_ITR10: Internal Trigger 10
7660 * @arg TIM_TS_ITR11: Internal Trigger 11
7661 *
7662 * (*) Value not defined in all devices.
7663 *
7664 * @retval None
7665 */
TIM_ITRx_SetConfig(TIM_TypeDef * TIMx,uint32_t InputTriggerSource)7666 static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint32_t InputTriggerSource)
7667 {
7668 uint32_t tmpsmcr;
7669
7670 /* Get the TIMx SMCR register value */
7671 tmpsmcr = TIMx->SMCR;
7672 /* Reset the TS Bits */
7673 tmpsmcr &= ~TIM_SMCR_TS;
7674 /* Set the Input Trigger source and the slave mode*/
7675 tmpsmcr |= (InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1);
7676 /* Write to TIMx SMCR */
7677 TIMx->SMCR = tmpsmcr;
7678 }
7679 /**
7680 * @brief Configures the TIMx External Trigger (ETR).
7681 * @param TIMx to select the TIM peripheral
7682 * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
7683 * This parameter can be one of the following values:
7684 * @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
7685 * @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
7686 * @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
7687 * @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
7688 * @param TIM_ExtTRGPolarity The external Trigger Polarity.
7689 * This parameter can be one of the following values:
7690 * @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
7691 * @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
7692 * @param ExtTRGFilter External Trigger Filter.
7693 * This parameter must be a value between 0x00 and 0x0F
7694 * @retval None
7695 */
TIM_ETR_SetConfig(TIM_TypeDef * TIMx,uint32_t TIM_ExtTRGPrescaler,uint32_t TIM_ExtTRGPolarity,uint32_t ExtTRGFilter)7696 void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler,
7697 uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
7698 {
7699 uint32_t tmpsmcr;
7700
7701 tmpsmcr = TIMx->SMCR;
7702
7703 /* Reset the ETR Bits */
7704 tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
7705
7706 /* Set the Prescaler, the Filter value and the Polarity */
7707 tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8U)));
7708
7709 /* Write to TIMx SMCR */
7710 TIMx->SMCR = tmpsmcr;
7711 }
7712
7713 /**
7714 * @brief Enables or disables the TIM Capture Compare Channel x.
7715 * @param TIMx to select the TIM peripheral
7716 * @param Channel specifies the TIM Channel
7717 * This parameter can be one of the following values:
7718 * @arg TIM_CHANNEL_1: TIM Channel 1
7719 * @arg TIM_CHANNEL_2: TIM Channel 2
7720 * @arg TIM_CHANNEL_3: TIM Channel 3
7721 * @arg TIM_CHANNEL_4: TIM Channel 4
7722 * @arg TIM_CHANNEL_5: TIM Channel 5 selected
7723 * @arg TIM_CHANNEL_6: TIM Channel 6 selected
7724 * @param ChannelState specifies the TIM Channel CCxE bit new state.
7725 * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_DISABLE.
7726 * @retval None
7727 */
TIM_CCxChannelCmd(TIM_TypeDef * TIMx,uint32_t Channel,uint32_t ChannelState)7728 void TIM_CCxChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ChannelState)
7729 {
7730 uint32_t tmp;
7731
7732 /* Check the parameters */
7733 assert_param(IS_TIM_CC1_INSTANCE(TIMx));
7734 assert_param(IS_TIM_CHANNELS(Channel));
7735
7736 tmp = TIM_CCER_CC1E << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
7737
7738 /* Reset the CCxE Bit */
7739 TIMx->CCER &= ~tmp;
7740
7741 /* Set or reset the CCxE Bit */
7742 TIMx->CCER |= (uint32_t)(ChannelState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
7743 }
7744
7745 #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
7746 /**
7747 * @brief Reset interrupt callbacks to the legacy weak callbacks.
7748 * @param htim pointer to a TIM_HandleTypeDef structure that contains
7749 * the configuration information for TIM module.
7750 * @retval None
7751 */
TIM_ResetCallback(TIM_HandleTypeDef * htim)7752 void TIM_ResetCallback(TIM_HandleTypeDef *htim)
7753 {
7754 /* Reset the TIM callback to the legacy weak callbacks */
7755 htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
7756 htim->PeriodElapsedHalfCpltCallback = HAL_TIM_PeriodElapsedHalfCpltCallback; /* Legacy weak PeriodElapsedHalfCpltCallback */
7757 htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
7758 htim->TriggerHalfCpltCallback = HAL_TIM_TriggerHalfCpltCallback; /* Legacy weak TriggerHalfCpltCallback */
7759 htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
7760 htim->IC_CaptureHalfCpltCallback = HAL_TIM_IC_CaptureHalfCpltCallback; /* Legacy weak IC_CaptureHalfCpltCallback */
7761 htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
7762 htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
7763 htim->PWM_PulseFinishedHalfCpltCallback = HAL_TIM_PWM_PulseFinishedHalfCpltCallback; /* Legacy weak PWM_PulseFinishedHalfCpltCallback */
7764 htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
7765 htim->CommutationCallback = HAL_TIMEx_CommutCallback; /* Legacy weak CommutationCallback */
7766 htim->CommutationHalfCpltCallback = HAL_TIMEx_CommutHalfCpltCallback; /* Legacy weak CommutationHalfCpltCallback */
7767 htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
7768 htim->Break2Callback = HAL_TIMEx_Break2Callback; /* Legacy weak Break2Callback */
7769 htim->EncoderIndexCallback = HAL_TIMEx_EncoderIndexCallback; /* Legacy weak Encoder Index Callback */
7770 htim->DirectionChangeCallback = HAL_TIMEx_DirectionChangeCallback; /* Legacy weak Direction Change Callback */
7771 htim->IndexErrorCallback = HAL_TIMEx_IndexErrorCallback; /* Legacy weak Index Error Callback */
7772 htim->TransitionErrorCallback = HAL_TIMEx_TransitionErrorCallback; /* Legacy weak Transition Error Callback */
7773 }
7774 #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
7775
7776 /**
7777 * @}
7778 */
7779
7780 #endif /* HAL_TIM_MODULE_ENABLED */
7781 /**
7782 * @}
7783 */
7784
7785 /**
7786 * @}
7787 */
7788 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
7789