1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include <uapi/drm/i915_drm.h>
34
35 #include <linux/pm_qos.h>
36
37 #include <drm/ttm/ttm_device.h>
38
39 #include "vga.h"
40
41 struct inteldrm_softc;
42 #define drm_i915_private inteldrm_softc
43
44 #include "display/intel_display_limits.h"
45 #include "display/intel_display_core.h"
46
47 #include "gem/i915_gem_context_types.h"
48 #include "gem/i915_gem_shrinker.h"
49 #include "gem/i915_gem_stolen.h"
50
51 #include "gt/intel_engine.h"
52 #include "gt/intel_gt_types.h"
53 #include "gt/intel_region_lmem.h"
54 #include "gt/intel_workarounds.h"
55 #include "gt/uc/intel_uc.h"
56
57 #include "soc/intel_pch.h"
58
59 #include "i915_drm_client.h"
60 #include "i915_gem.h"
61 #include "i915_gpu_error.h"
62 #include "i915_params.h"
63 #include "i915_perf_types.h"
64 #include "i915_scheduler.h"
65 #include "i915_utils.h"
66 #include "intel_device_info.h"
67 #include "intel_memory_region.h"
68 #include "intel_runtime_pm.h"
69 #include "intel_step.h"
70 #include "intel_uncore.h"
71
72 #include "drm.h"
73
74 #include <dev/ic/mc6845reg.h>
75 #include <dev/ic/pcdisplayvar.h>
76 #include <dev/ic/vgareg.h>
77 #include <dev/ic/vgavar.h>
78
79 #include <sys/task.h>
80 #include <dev/pci/vga_pcivar.h>
81 #include <dev/wscons/wsconsio.h>
82 #include <dev/wscons/wsdisplayvar.h>
83 #include <dev/rasops/rasops.h>
84
85 struct drm_i915_clock_gating_funcs;
86 struct vlv_s0ix_state;
87 struct intel_pxp;
88
89 #define GEM_QUIRK_PIN_SWIZZLED_PAGES BIT(0)
90
91 /* Data Stolen Memory (DSM) aka "i915 stolen memory" */
92 struct i915_dsm {
93 /*
94 * The start and end of DSM which we can optionally use to create GEM
95 * objects backed by stolen memory.
96 *
97 * Note that usable_size tells us exactly how much of this we are
98 * actually allowed to use, given that some portion of it is in fact
99 * reserved for use by hardware functions.
100 */
101 struct resource stolen;
102
103 /*
104 * Reserved portion of DSM.
105 */
106 struct resource reserved;
107
108 /*
109 * Total size minus reserved ranges.
110 *
111 * DSM is segmented in hardware with different portions offlimits to
112 * certain functions.
113 *
114 * The drm_mm is initialised to the total accessible range, as found
115 * from the PCI config. On Broadwell+, this is further restricted to
116 * avoid the first page! The upper end of DSM is reserved for hardware
117 * functions and similarly removed from the accessible range.
118 */
119 resource_size_t usable_size;
120 };
121
122 struct i915_suspend_saved_registers {
123 u32 saveDSPARB;
124 u32 saveSWF0[16];
125 u32 saveSWF1[16];
126 u32 saveSWF3[3];
127 u16 saveGCDGMBUS;
128 };
129
130 #define MAX_L3_SLICES 2
131 struct intel_l3_parity {
132 u32 *remap_info[MAX_L3_SLICES];
133 struct work_struct error_work;
134 int which_slice;
135 };
136
137 struct i915_gem_mm {
138 /*
139 * Shortcut for the stolen region. This points to either
140 * INTEL_REGION_STOLEN_SMEM for integrated platforms, or
141 * INTEL_REGION_STOLEN_LMEM for discrete, or NULL if the device doesn't
142 * support stolen.
143 */
144 struct intel_memory_region *stolen_region;
145 /** Memory allocator for GTT stolen memory */
146 struct drm_mm stolen;
147 /** Protects the usage of the GTT stolen memory allocator. This is
148 * always the inner lock when overlapping with struct_mutex. */
149 struct rwlock stolen_lock;
150
151 /* Protects bound_list/unbound_list and #drm_i915_gem_object.mm.link */
152 spinlock_t obj_lock;
153
154 /**
155 * List of objects which are purgeable.
156 */
157 struct list_head purge_list;
158
159 /**
160 * List of objects which have allocated pages and are shrinkable.
161 */
162 struct list_head shrink_list;
163
164 /**
165 * List of objects which are pending destruction.
166 */
167 struct llist_head free_list;
168 struct work_struct free_work;
169 /**
170 * Count of objects pending destructions. Used to skip needlessly
171 * waiting on an RCU barrier if no objects are waiting to be freed.
172 */
173 atomic_t free_count;
174
175 /**
176 * tmpfs instance used for shmem backed objects
177 */
178 struct vfsmount *gemfs;
179
180 struct intel_memory_region *regions[INTEL_REGION_UNKNOWN];
181
182 struct notifier_block oom_notifier;
183 struct notifier_block vmap_notifier;
184 struct shrinker shrinker;
185
186 #ifdef CONFIG_MMU_NOTIFIER
187 /**
188 * notifier_lock for mmu notifiers, memory may not be allocated
189 * while holding this lock.
190 */
191 rwlock_t notifier_lock;
192 #endif
193
194 /* shrinker accounting, also useful for userland debugging */
195 u64 shrink_memory;
196 u32 shrink_count;
197 };
198
199 struct i915_virtual_gpu {
200 struct rwlock lock; /* serialises sending of g2v_notify command pkts */
201 bool active;
202 u32 caps;
203 u32 *initial_mmio;
204 u8 *initial_cfg_space;
205 struct list_head entry;
206 };
207
208 struct i915_selftest_stash {
209 atomic_t counter;
210 struct ida mock_region_instances;
211 };
212
213
214 struct inteldrm_softc {
215 #ifdef __OpenBSD__
216 struct device sc_dev;
217 bus_dma_tag_t dmat;
218 bus_space_tag_t iot;
219 bus_space_tag_t bst;
220 bus_space_handle_t opregion_ioh;
221 bus_space_handle_t opregion_rvda_ioh;
222 bus_size_t opregion_rvda_size;
223 #endif
224
225 struct drm_device drm;
226
227 struct intel_display display;
228
229 /* FIXME: Device release actions should all be moved to drmm_ */
230 bool do_release;
231
232 /* i915 device parameters */
233 struct i915_params params;
234
235 const struct intel_device_info *__info; /* Use INTEL_INFO() to access. */
236 struct intel_runtime_info __runtime; /* Use RUNTIME_INFO() to access. */
237 struct intel_driver_caps caps;
238
239 struct i915_dsm dsm;
240
241 #ifdef __OpenBSD__
242 pci_chipset_tag_t pc;
243 pcitag_t tag;
244 struct extent *memex;
245 pci_intr_handle_t ih;
246 irqreturn_t(*irq_handler) (int, void *);
247 void *irqh;
248
249 struct vga_pci_bar bar;
250 struct vga_pci_bar *vga_regs;
251
252 const struct pci_device_id *id;
253
254 int console;
255 int primary;
256 int nscreens;
257 void (*switchcb)(void *, int, int);
258 void *switchcbarg;
259 void *switchcookie;
260 struct task switchtask;
261 struct rasops_info ro;
262
263 struct task burner_task;
264 int burner_fblank;
265
266 struct backlight_device *backlight;
267
268 union flush {
269 struct {
270 bus_space_tag_t bst;
271 bus_space_handle_t bsh;
272 } i9xx;
273 struct {
274 bus_dma_segment_t seg;
275 caddr_t kva;
276 } i8xx;
277 } ifp;
278 struct vm_page *pgs;
279 #endif
280
281 struct intel_uncore uncore;
282 struct intel_uncore_mmio_debug mmio_debug;
283
284 struct i915_virtual_gpu vgpu;
285
286 struct intel_gvt *gvt;
287
288 struct {
289 struct pci_dev *pdev;
290 struct resource mch_res;
291 bool mchbar_need_disable;
292 } gmch;
293
294 struct rb_root uabi_engines;
295 unsigned int engine_uabi_class_count[I915_LAST_UABI_ENGINE_CLASS + 1];
296
297 /* protects the irq masks */
298 spinlock_t irq_lock;
299
300 bool display_irqs_enabled;
301
302 /* Sideband mailbox protection */
303 struct rwlock sb_lock;
304 struct pm_qos_request sb_qos;
305
306 /** Cached value of IMR to avoid reads in updating the bitfield */
307 union {
308 u32 irq_mask;
309 u32 de_irq_mask[I915_MAX_PIPES];
310 };
311 u32 pipestat_irq_mask[I915_MAX_PIPES];
312
313 bool preserve_bios_swizzle;
314
315 unsigned int fsb_freq, mem_freq, is_ddr3;
316 unsigned int skl_preferred_vco_freq;
317
318 unsigned int max_dotclk_freq;
319 unsigned int hpll_freq;
320 unsigned int czclk_freq;
321
322 /**
323 * wq - Driver workqueue for GEM.
324 *
325 * NOTE: Work items scheduled here are not allowed to grab any modeset
326 * locks, for otherwise the flushing done in the pageflip code will
327 * result in deadlocks.
328 */
329 struct workqueue_struct *wq;
330
331 /**
332 * unordered_wq - internal workqueue for unordered work
333 *
334 * This workqueue should be used for all unordered work
335 * scheduling within i915, which used to be scheduled on the
336 * system_wq before moving to a driver instance due
337 * deprecation of flush_scheduled_work().
338 */
339 struct workqueue_struct *unordered_wq;
340
341 /* pm private clock gating functions */
342 const struct drm_i915_clock_gating_funcs *clock_gating_funcs;
343
344 /* PCH chipset type */
345 enum intel_pch pch_type;
346 unsigned short pch_id;
347
348 unsigned long gem_quirks;
349
350 struct i915_gem_mm mm;
351
352 struct intel_l3_parity l3_parity;
353
354 /*
355 * edram size in MB.
356 * Cannot be determined by PCIID. You must always read a register.
357 */
358 u32 edram_size_mb;
359
360 struct i915_gpu_error gpu_error;
361
362 u32 suspend_count;
363 struct i915_suspend_saved_registers regfile;
364 struct vlv_s0ix_state *vlv_s0ix_state;
365
366 struct dram_info {
367 bool wm_lv_0_adjust_needed;
368 u8 num_channels;
369 bool symmetric_memory;
370 enum intel_dram_type {
371 INTEL_DRAM_UNKNOWN,
372 INTEL_DRAM_DDR3,
373 INTEL_DRAM_DDR4,
374 INTEL_DRAM_LPDDR3,
375 INTEL_DRAM_LPDDR4,
376 INTEL_DRAM_DDR5,
377 INTEL_DRAM_LPDDR5,
378 } type;
379 u8 num_qgv_points;
380 u8 num_psf_gv_points;
381 } dram_info;
382
383 struct intel_runtime_pm runtime_pm;
384
385 struct i915_perf perf;
386
387 struct i915_hwmon *hwmon;
388
389 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
390 struct intel_gt gt0;
391
392 /*
393 * i915->gt[0] == &i915->gt0
394 */
395 struct intel_gt *gt[I915_MAX_GT];
396
397 struct kobject *sysfs_gt;
398
399 /* Quick lookup of media GT (current platforms only have one) */
400 struct intel_gt *media_gt;
401
402 struct {
403 struct i915_gem_contexts {
404 spinlock_t lock; /* locks list */
405 struct list_head list;
406 } contexts;
407
408 /*
409 * We replace the local file with a global mappings as the
410 * backing storage for the mmap is on the device and not
411 * on the struct file, and we do not want to prolong the
412 * lifetime of the local fd. To minimise the number of
413 * anonymous inodes we create, we use a global singleton to
414 * share the global mapping.
415 */
416 struct file *mmap_singleton;
417 } gem;
418
419 struct intel_pxp *pxp;
420
421 /* For i915gm/i945gm vblank irq workaround */
422 u8 vblank_enabled;
423
424 bool irq_enabled;
425
426 struct i915_pmu pmu;
427
428 /* The TTM device structure. */
429 struct ttm_device bdev;
430
431 I915_SELFTEST_DECLARE(struct i915_selftest_stash selftest;)
432
433 /*
434 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
435 * will be rejected. Instead look for a better place.
436 */
437 };
438
to_i915(const struct drm_device * dev)439 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
440 {
441 return container_of(dev, struct drm_i915_private, drm);
442 }
443
kdev_to_i915(struct device * kdev)444 static inline struct drm_i915_private *kdev_to_i915(struct device *kdev)
445 {
446 return dev_get_drvdata(kdev);
447 }
448
pdev_to_i915(struct pci_dev * pdev)449 static inline struct drm_i915_private *pdev_to_i915(struct pci_dev *pdev)
450 {
451 STUB();
452 return NULL;
453 #ifdef notyet
454 return pci_get_drvdata(pdev);
455 #endif
456 }
457
to_gt(struct drm_i915_private * i915)458 static inline struct intel_gt *to_gt(struct drm_i915_private *i915)
459 {
460 return &i915->gt0;
461 }
462
463 /* Simple iterator over all initialised engines */
464 #define for_each_engine(engine__, gt__, id__) \
465 for ((id__) = 0; \
466 (id__) < I915_NUM_ENGINES; \
467 (id__)++) \
468 for_each_if ((engine__) = (gt__)->engine[(id__)])
469
470 /* Iterator over subset of engines selected by mask */
471 #define for_each_engine_masked(engine__, gt__, mask__, tmp__) \
472 for ((tmp__) = (mask__) & (gt__)->info.engine_mask; \
473 (tmp__) ? \
474 ((engine__) = (gt__)->engine[__mask_next_bit(tmp__)]), 1 : \
475 0;)
476
477 #define rb_to_uabi_engine(rb) \
478 rb_entry_safe(rb, struct intel_engine_cs, uabi_node)
479
480 #define for_each_uabi_engine(engine__, i915__) \
481 for ((engine__) = rb_to_uabi_engine(rb_first(&(i915__)->uabi_engines));\
482 (engine__); \
483 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
484
485 #define for_each_uabi_class_engine(engine__, class__, i915__) \
486 for ((engine__) = intel_engine_lookup_user((i915__), (class__), 0); \
487 (engine__) && (engine__)->uabi_class == (class__); \
488 (engine__) = rb_to_uabi_engine(rb_next(&(engine__)->uabi_node)))
489
490 #define INTEL_INFO(i915) ((i915)->__info)
491 #define RUNTIME_INFO(i915) (&(i915)->__runtime)
492 #define DISPLAY_INFO(i915) ((i915)->display.info.__device_info)
493 #define DISPLAY_RUNTIME_INFO(i915) (&(i915)->display.info.__runtime_info)
494 #define DRIVER_CAPS(i915) (&(i915)->caps)
495
496 #define INTEL_DEVID(i915) (RUNTIME_INFO(i915)->device_id)
497
498 #define IP_VER(ver, rel) ((ver) << 8 | (rel))
499
500 #define GRAPHICS_VER(i915) (RUNTIME_INFO(i915)->graphics.ip.ver)
501 #define GRAPHICS_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->graphics.ip.ver, \
502 RUNTIME_INFO(i915)->graphics.ip.rel)
503 #define IS_GRAPHICS_VER(i915, from, until) \
504 (GRAPHICS_VER(i915) >= (from) && GRAPHICS_VER(i915) <= (until))
505
506 #define MEDIA_VER(i915) (RUNTIME_INFO(i915)->media.ip.ver)
507 #define MEDIA_VER_FULL(i915) IP_VER(RUNTIME_INFO(i915)->media.ip.ver, \
508 RUNTIME_INFO(i915)->media.ip.rel)
509 #define IS_MEDIA_VER(i915, from, until) \
510 (MEDIA_VER(i915) >= (from) && MEDIA_VER(i915) <= (until))
511
512 #define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver)
513 #define IS_DISPLAY_VER(i915, from, until) \
514 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until))
515
516 #define INTEL_REVID(i915) ((i915)->drm.pdev->revision)
517
518 #define INTEL_DISPLAY_STEP(__i915) (RUNTIME_INFO(__i915)->step.display_step)
519 #define INTEL_GRAPHICS_STEP(__i915) (RUNTIME_INFO(__i915)->step.graphics_step)
520 #define INTEL_MEDIA_STEP(__i915) (RUNTIME_INFO(__i915)->step.media_step)
521 #define INTEL_BASEDIE_STEP(__i915) (RUNTIME_INFO(__i915)->step.basedie_step)
522
523 #define IS_DISPLAY_STEP(__i915, since, until) \
524 (drm_WARN_ON(&(__i915)->drm, INTEL_DISPLAY_STEP(__i915) == STEP_NONE), \
525 INTEL_DISPLAY_STEP(__i915) >= (since) && INTEL_DISPLAY_STEP(__i915) < (until))
526
527 #define IS_GRAPHICS_STEP(__i915, since, until) \
528 (drm_WARN_ON(&(__i915)->drm, INTEL_GRAPHICS_STEP(__i915) == STEP_NONE), \
529 INTEL_GRAPHICS_STEP(__i915) >= (since) && INTEL_GRAPHICS_STEP(__i915) < (until))
530
531 #define IS_MEDIA_STEP(__i915, since, until) \
532 (drm_WARN_ON(&(__i915)->drm, INTEL_MEDIA_STEP(__i915) == STEP_NONE), \
533 INTEL_MEDIA_STEP(__i915) >= (since) && INTEL_MEDIA_STEP(__i915) < (until))
534
535 #define IS_BASEDIE_STEP(__i915, since, until) \
536 (drm_WARN_ON(&(__i915)->drm, INTEL_BASEDIE_STEP(__i915) == STEP_NONE), \
537 INTEL_BASEDIE_STEP(__i915) >= (since) && INTEL_BASEDIE_STEP(__i915) < (until))
538
539 static __always_inline unsigned int
__platform_mask_index(const struct intel_runtime_info * info,enum intel_platform p)540 __platform_mask_index(const struct intel_runtime_info *info,
541 enum intel_platform p)
542 {
543 const unsigned int pbits =
544 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
545
546 /* Expand the platform_mask array if this fails. */
547 BUILD_BUG_ON(INTEL_MAX_PLATFORMS >
548 pbits * ARRAY_SIZE(info->platform_mask));
549
550 return p / pbits;
551 }
552
553 static __always_inline unsigned int
__platform_mask_bit(const struct intel_runtime_info * info,enum intel_platform p)554 __platform_mask_bit(const struct intel_runtime_info *info,
555 enum intel_platform p)
556 {
557 const unsigned int pbits =
558 BITS_PER_TYPE(info->platform_mask[0]) - INTEL_SUBPLATFORM_BITS;
559
560 return p % pbits + INTEL_SUBPLATFORM_BITS;
561 }
562
563 static inline u32
intel_subplatform(const struct intel_runtime_info * info,enum intel_platform p)564 intel_subplatform(const struct intel_runtime_info *info, enum intel_platform p)
565 {
566 const unsigned int pi = __platform_mask_index(info, p);
567
568 return info->platform_mask[pi] & INTEL_SUBPLATFORM_MASK;
569 }
570
571 static __always_inline bool
IS_PLATFORM(const struct drm_i915_private * i915,enum intel_platform p)572 IS_PLATFORM(const struct drm_i915_private *i915, enum intel_platform p)
573 {
574 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
575 const unsigned int pi = __platform_mask_index(info, p);
576 const unsigned int pb = __platform_mask_bit(info, p);
577
578 #ifdef notyet
579 BUILD_BUG_ON(!__builtin_constant_p(p));
580 #endif
581
582 return info->platform_mask[pi] & BIT(pb);
583 }
584
585 static __always_inline bool
IS_SUBPLATFORM(const struct drm_i915_private * i915,enum intel_platform p,unsigned int s)586 IS_SUBPLATFORM(const struct drm_i915_private *i915,
587 enum intel_platform p, unsigned int s)
588 {
589 const struct intel_runtime_info *info = RUNTIME_INFO(i915);
590 const unsigned int pi = __platform_mask_index(info, p);
591 const unsigned int pb = __platform_mask_bit(info, p);
592 const unsigned int msb = BITS_PER_TYPE(info->platform_mask[0]) - 1;
593 const u32 mask = info->platform_mask[pi];
594
595 #ifdef notyet
596 BUILD_BUG_ON(!__builtin_constant_p(p));
597 BUILD_BUG_ON(!__builtin_constant_p(s));
598 BUILD_BUG_ON((s) >= INTEL_SUBPLATFORM_BITS);
599 #endif
600
601 /* Shift and test on the MSB position so sign flag can be used. */
602 return ((mask << (msb - pb)) & (mask << (msb - s))) & BIT(msb);
603 }
604
605 #define IS_MOBILE(i915) (INTEL_INFO(i915)->is_mobile)
606 #define IS_DGFX(i915) (INTEL_INFO(i915)->is_dgfx)
607
608 #define IS_I830(i915) IS_PLATFORM(i915, INTEL_I830)
609 #define IS_I845G(i915) IS_PLATFORM(i915, INTEL_I845G)
610 #define IS_I85X(i915) IS_PLATFORM(i915, INTEL_I85X)
611 #define IS_I865G(i915) IS_PLATFORM(i915, INTEL_I865G)
612 #define IS_I915G(i915) IS_PLATFORM(i915, INTEL_I915G)
613 #define IS_I915GM(i915) IS_PLATFORM(i915, INTEL_I915GM)
614 #define IS_I945G(i915) IS_PLATFORM(i915, INTEL_I945G)
615 #define IS_I945GM(i915) IS_PLATFORM(i915, INTEL_I945GM)
616 #define IS_I965G(i915) IS_PLATFORM(i915, INTEL_I965G)
617 #define IS_I965GM(i915) IS_PLATFORM(i915, INTEL_I965GM)
618 #define IS_G45(i915) IS_PLATFORM(i915, INTEL_G45)
619 #define IS_GM45(i915) IS_PLATFORM(i915, INTEL_GM45)
620 #define IS_G4X(i915) (IS_G45(i915) || IS_GM45(i915))
621 #define IS_PINEVIEW(i915) IS_PLATFORM(i915, INTEL_PINEVIEW)
622 #define IS_G33(i915) IS_PLATFORM(i915, INTEL_G33)
623 #define IS_IRONLAKE(i915) IS_PLATFORM(i915, INTEL_IRONLAKE)
624 #define IS_IRONLAKE_M(i915) \
625 (IS_PLATFORM(i915, INTEL_IRONLAKE) && IS_MOBILE(i915))
626 #define IS_SANDYBRIDGE(i915) IS_PLATFORM(i915, INTEL_SANDYBRIDGE)
627 #define IS_IVYBRIDGE(i915) IS_PLATFORM(i915, INTEL_IVYBRIDGE)
628 #define IS_IVB_GT1(i915) (IS_IVYBRIDGE(i915) && \
629 INTEL_INFO(i915)->gt == 1)
630 #define IS_VALLEYVIEW(i915) IS_PLATFORM(i915, INTEL_VALLEYVIEW)
631 #define IS_CHERRYVIEW(i915) IS_PLATFORM(i915, INTEL_CHERRYVIEW)
632 #define IS_HASWELL(i915) IS_PLATFORM(i915, INTEL_HASWELL)
633 #define IS_BROADWELL(i915) IS_PLATFORM(i915, INTEL_BROADWELL)
634 #define IS_SKYLAKE(i915) IS_PLATFORM(i915, INTEL_SKYLAKE)
635 #define IS_BROXTON(i915) IS_PLATFORM(i915, INTEL_BROXTON)
636 #define IS_KABYLAKE(i915) IS_PLATFORM(i915, INTEL_KABYLAKE)
637 #define IS_GEMINILAKE(i915) IS_PLATFORM(i915, INTEL_GEMINILAKE)
638 #define IS_COFFEELAKE(i915) IS_PLATFORM(i915, INTEL_COFFEELAKE)
639 #define IS_COMETLAKE(i915) IS_PLATFORM(i915, INTEL_COMETLAKE)
640 #define IS_ICELAKE(i915) IS_PLATFORM(i915, INTEL_ICELAKE)
641 #define IS_JASPERLAKE(i915) IS_PLATFORM(i915, INTEL_JASPERLAKE)
642 #define IS_ELKHARTLAKE(i915) IS_PLATFORM(i915, INTEL_ELKHARTLAKE)
643 #define IS_TIGERLAKE(i915) IS_PLATFORM(i915, INTEL_TIGERLAKE)
644 #define IS_ROCKETLAKE(i915) IS_PLATFORM(i915, INTEL_ROCKETLAKE)
645 #define IS_DG1(i915) IS_PLATFORM(i915, INTEL_DG1)
646 #define IS_ALDERLAKE_S(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_S)
647 #define IS_ALDERLAKE_P(i915) IS_PLATFORM(i915, INTEL_ALDERLAKE_P)
648 #define IS_XEHPSDV(i915) IS_PLATFORM(i915, INTEL_XEHPSDV)
649 #define IS_DG2(i915) IS_PLATFORM(i915, INTEL_DG2)
650 #define IS_PONTEVECCHIO(i915) IS_PLATFORM(i915, INTEL_PONTEVECCHIO)
651 #define IS_METEORLAKE(i915) IS_PLATFORM(i915, INTEL_METEORLAKE)
652
653 #define IS_METEORLAKE_M(i915) \
654 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_M)
655 #define IS_METEORLAKE_P(i915) \
656 IS_SUBPLATFORM(i915, INTEL_METEORLAKE, INTEL_SUBPLATFORM_P)
657 #define IS_DG2_G10(i915) \
658 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G10)
659 #define IS_DG2_G11(i915) \
660 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G11)
661 #define IS_DG2_G12(i915) \
662 IS_SUBPLATFORM(i915, INTEL_DG2, INTEL_SUBPLATFORM_G12)
663 #define IS_RAPTORLAKE_S(i915) \
664 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_S, INTEL_SUBPLATFORM_RPL)
665 #define IS_ALDERLAKE_P_N(i915) \
666 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_N)
667 #define IS_RAPTORLAKE_P(i915) \
668 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPL)
669 #define IS_RAPTORLAKE_U(i915) \
670 IS_SUBPLATFORM(i915, INTEL_ALDERLAKE_P, INTEL_SUBPLATFORM_RPLU)
671 #define IS_HASWELL_EARLY_SDV(i915) (IS_HASWELL(i915) && \
672 (INTEL_DEVID(i915) & 0xFF00) == 0x0C00)
673 #define IS_BROADWELL_ULT(i915) \
674 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULT)
675 #define IS_BROADWELL_ULX(i915) \
676 IS_SUBPLATFORM(i915, INTEL_BROADWELL, INTEL_SUBPLATFORM_ULX)
677 #define IS_BROADWELL_GT3(i915) (IS_BROADWELL(i915) && \
678 INTEL_INFO(i915)->gt == 3)
679 #define IS_HASWELL_ULT(i915) \
680 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULT)
681 #define IS_HASWELL_GT3(i915) (IS_HASWELL(i915) && \
682 INTEL_INFO(i915)->gt == 3)
683 #define IS_HASWELL_GT1(i915) (IS_HASWELL(i915) && \
684 INTEL_INFO(i915)->gt == 1)
685 /* ULX machines are also considered ULT. */
686 #define IS_HASWELL_ULX(i915) \
687 IS_SUBPLATFORM(i915, INTEL_HASWELL, INTEL_SUBPLATFORM_ULX)
688 #define IS_SKYLAKE_ULT(i915) \
689 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULT)
690 #define IS_SKYLAKE_ULX(i915) \
691 IS_SUBPLATFORM(i915, INTEL_SKYLAKE, INTEL_SUBPLATFORM_ULX)
692 #define IS_KABYLAKE_ULT(i915) \
693 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULT)
694 #define IS_KABYLAKE_ULX(i915) \
695 IS_SUBPLATFORM(i915, INTEL_KABYLAKE, INTEL_SUBPLATFORM_ULX)
696 #define IS_SKYLAKE_GT2(i915) (IS_SKYLAKE(i915) && \
697 INTEL_INFO(i915)->gt == 2)
698 #define IS_SKYLAKE_GT3(i915) (IS_SKYLAKE(i915) && \
699 INTEL_INFO(i915)->gt == 3)
700 #define IS_SKYLAKE_GT4(i915) (IS_SKYLAKE(i915) && \
701 INTEL_INFO(i915)->gt == 4)
702 #define IS_KABYLAKE_GT2(i915) (IS_KABYLAKE(i915) && \
703 INTEL_INFO(i915)->gt == 2)
704 #define IS_KABYLAKE_GT3(i915) (IS_KABYLAKE(i915) && \
705 INTEL_INFO(i915)->gt == 3)
706 #define IS_COFFEELAKE_ULT(i915) \
707 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULT)
708 #define IS_COFFEELAKE_ULX(i915) \
709 IS_SUBPLATFORM(i915, INTEL_COFFEELAKE, INTEL_SUBPLATFORM_ULX)
710 #define IS_COFFEELAKE_GT2(i915) (IS_COFFEELAKE(i915) && \
711 INTEL_INFO(i915)->gt == 2)
712 #define IS_COFFEELAKE_GT3(i915) (IS_COFFEELAKE(i915) && \
713 INTEL_INFO(i915)->gt == 3)
714
715 #define IS_COMETLAKE_ULT(i915) \
716 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULT)
717 #define IS_COMETLAKE_ULX(i915) \
718 IS_SUBPLATFORM(i915, INTEL_COMETLAKE, INTEL_SUBPLATFORM_ULX)
719 #define IS_COMETLAKE_GT2(i915) (IS_COMETLAKE(i915) && \
720 INTEL_INFO(i915)->gt == 2)
721
722 #define IS_ICL_WITH_PORT_F(i915) \
723 IS_SUBPLATFORM(i915, INTEL_ICELAKE, INTEL_SUBPLATFORM_PORTF)
724
725 #define IS_TIGERLAKE_UY(i915) \
726 IS_SUBPLATFORM(i915, INTEL_TIGERLAKE, INTEL_SUBPLATFORM_UY)
727
728
729
730
731
732
733
734
735 #define IS_XEHPSDV_GRAPHICS_STEP(__i915, since, until) \
736 (IS_XEHPSDV(__i915) && IS_GRAPHICS_STEP(__i915, since, until))
737
738 #define IS_MTL_DISPLAY_STEP(__i915, since, until) \
739 (IS_METEORLAKE(__i915) && \
740 IS_DISPLAY_STEP(__i915, since, until))
741
742 #define IS_MTL_MEDIA_STEP(__i915, since, until) \
743 (IS_METEORLAKE(__i915) && \
744 IS_MEDIA_STEP(__i915, since, until))
745
746 /*
747 * DG2 hardware steppings are a bit unusual. The hardware design was forked to
748 * create three variants (G10, G11, and G12) which each have distinct
749 * workaround sets. The G11 and G12 forks of the DG2 design reset the GT
750 * stepping back to "A0" for their first iterations, even though they're more
751 * similar to a G10 B0 stepping and G10 C0 stepping respectively in terms of
752 * functionality and workarounds. However the display stepping does not reset
753 * in the same manner --- a specific stepping like "B0" has a consistent
754 * meaning regardless of whether it belongs to a G10, G11, or G12 DG2.
755 *
756 * TLDR: All GT workarounds and stepping-specific logic must be applied in
757 * relation to a specific subplatform (G10/G11/G12), whereas display workarounds
758 * and stepping-specific logic will be applied with a general DG2-wide stepping
759 * number.
760 */
761 #define IS_DG2_GRAPHICS_STEP(__i915, variant, since, until) \
762 (IS_SUBPLATFORM(__i915, INTEL_DG2, INTEL_SUBPLATFORM_##variant) && \
763 IS_GRAPHICS_STEP(__i915, since, until))
764
765 #define IS_DG2_DISPLAY_STEP(__i915, since, until) \
766 (IS_DG2(__i915) && \
767 IS_DISPLAY_STEP(__i915, since, until))
768
769 #define IS_PVC_BD_STEP(__i915, since, until) \
770 (IS_PONTEVECCHIO(__i915) && \
771 IS_BASEDIE_STEP(__i915, since, until))
772
773 #define IS_PVC_CT_STEP(__i915, since, until) \
774 (IS_PONTEVECCHIO(__i915) && \
775 IS_GRAPHICS_STEP(__i915, since, until))
776
777 #define IS_LP(i915) (INTEL_INFO(i915)->is_lp)
778 #define IS_GEN9_LP(i915) (GRAPHICS_VER(i915) == 9 && IS_LP(i915))
779 #define IS_GEN9_BC(i915) (GRAPHICS_VER(i915) == 9 && !IS_LP(i915))
780
781 #define __HAS_ENGINE(engine_mask, id) ((engine_mask) & BIT(id))
782 #define HAS_ENGINE(gt, id) __HAS_ENGINE((gt)->info.engine_mask, id)
783
784 #define __ENGINE_INSTANCES_MASK(mask, first, count) ({ \
785 unsigned int first__ = (first); \
786 unsigned int count__ = (count); \
787 ((mask) & GENMASK(first__ + count__ - 1, first__)) >> first__; \
788 })
789
790 #define ENGINE_INSTANCES_MASK(gt, first, count) \
791 __ENGINE_INSTANCES_MASK((gt)->info.engine_mask, first, count)
792
793 #define RCS_MASK(gt) \
794 ENGINE_INSTANCES_MASK(gt, RCS0, I915_MAX_RCS)
795 #define BCS_MASK(gt) \
796 ENGINE_INSTANCES_MASK(gt, BCS0, I915_MAX_BCS)
797 #define VDBOX_MASK(gt) \
798 ENGINE_INSTANCES_MASK(gt, VCS0, I915_MAX_VCS)
799 #define VEBOX_MASK(gt) \
800 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
801 #define CCS_MASK(gt) \
802 ENGINE_INSTANCES_MASK(gt, CCS0, I915_MAX_CCS)
803
804 #define HAS_MEDIA_RATIO_MODE(i915) (INTEL_INFO(i915)->has_media_ratio_mode)
805
806 /*
807 * The Gen7 cmdparser copies the scanned buffer to the ggtt for execution
808 * All later gens can run the final buffer from the ppgtt
809 */
810 #define CMDPARSER_USES_GGTT(i915) (GRAPHICS_VER(i915) == 7)
811
812 #define HAS_LLC(i915) (INTEL_INFO(i915)->has_llc)
813 #define HAS_4TILE(i915) (INTEL_INFO(i915)->has_4tile)
814 #define HAS_SNOOP(i915) (INTEL_INFO(i915)->has_snoop)
815 #define HAS_EDRAM(i915) ((i915)->edram_size_mb)
816 #define HAS_SECURE_BATCHES(i915) (GRAPHICS_VER(i915) < 6)
817 #define HAS_WT(i915) HAS_EDRAM(i915)
818
819 #define HWS_NEEDS_PHYSICAL(i915) (INTEL_INFO(i915)->hws_needs_physical)
820
821 #define HAS_LOGICAL_RING_CONTEXTS(i915) \
822 (INTEL_INFO(i915)->has_logical_ring_contexts)
823 #define HAS_LOGICAL_RING_ELSQ(i915) \
824 (INTEL_INFO(i915)->has_logical_ring_elsq)
825
826 #define HAS_EXECLISTS(i915) HAS_LOGICAL_RING_CONTEXTS(i915)
827
828 #define INTEL_PPGTT(i915) (RUNTIME_INFO(i915)->ppgtt_type)
829 #define HAS_PPGTT(i915) \
830 (INTEL_PPGTT(i915) != INTEL_PPGTT_NONE)
831 #define HAS_FULL_PPGTT(i915) \
832 (INTEL_PPGTT(i915) >= INTEL_PPGTT_FULL)
833
834 #define HAS_PAGE_SIZES(i915, sizes) ({ \
835 GEM_BUG_ON((sizes) == 0); \
836 ((sizes) & ~RUNTIME_INFO(i915)->page_sizes) == 0; \
837 })
838
839 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
840 #define HAS_BROKEN_CS_TLB(i915) (IS_I830(i915) || IS_I845G(i915))
841
842 #define NEEDS_RC6_CTX_CORRUPTION_WA(i915) \
843 (IS_BROADWELL(i915) || GRAPHICS_VER(i915) == 9)
844
845 /* WaRsDisableCoarsePowerGating:skl,cnl */
846 #define NEEDS_WaRsDisableCoarsePowerGating(i915) \
847 (IS_SKYLAKE_GT3(i915) || IS_SKYLAKE_GT4(i915))
848
849 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
850 * rows, which changed the alignment requirements and fence programming.
851 */
852 #define HAS_128_BYTE_Y_TILING(i915) (GRAPHICS_VER(i915) != 2 && \
853 !(IS_I915G(i915) || IS_I915GM(i915)))
854
855 #define HAS_RC6(i915) (INTEL_INFO(i915)->has_rc6)
856 #define HAS_RC6p(i915) (INTEL_INFO(i915)->has_rc6p)
857 #define HAS_RC6pp(i915) (false) /* HW was never validated */
858
859 #define HAS_RPS(i915) (INTEL_INFO(i915)->has_rps)
860
861 #define HAS_HECI_PXP(i915) \
862 (INTEL_INFO(i915)->has_heci_pxp)
863
864 #define HAS_HECI_GSCFI(i915) \
865 (INTEL_INFO(i915)->has_heci_gscfi)
866
867 #define HAS_HECI_GSC(i915) (HAS_HECI_PXP(i915) || HAS_HECI_GSCFI(i915))
868
869 #define HAS_RUNTIME_PM(i915) (INTEL_INFO(i915)->has_runtime_pm)
870 #define HAS_64BIT_RELOC(i915) (INTEL_INFO(i915)->has_64bit_reloc)
871
872 #define HAS_OA_BPC_REPORTING(i915) \
873 (INTEL_INFO(i915)->has_oa_bpc_reporting)
874 #define HAS_OA_SLICE_CONTRIB_LIMITS(i915) \
875 (INTEL_INFO(i915)->has_oa_slice_contrib_limits)
876 #define HAS_OAM(i915) \
877 (INTEL_INFO(i915)->has_oam)
878
879 /*
880 * Set this flag, when platform requires 64K GTT page sizes or larger for
881 * device local memory access.
882 */
883 #define HAS_64K_PAGES(i915) (INTEL_INFO(i915)->has_64k_pages)
884
885 #define HAS_REGION(i915, i) (INTEL_INFO(i915)->memory_regions & (i))
886 #define HAS_LMEM(i915) HAS_REGION(i915, REGION_LMEM)
887
888 #define HAS_EXTRA_GT_LIST(i915) (INTEL_INFO(i915)->extra_gt_list)
889
890 /*
891 * Platform has the dedicated compression control state for each lmem surfaces
892 * stored in lmem to support the 3D and media compression formats.
893 */
894 #define HAS_FLAT_CCS(i915) (INTEL_INFO(i915)->has_flat_ccs)
895
896 #define HAS_GT_UC(i915) (INTEL_INFO(i915)->has_gt_uc)
897
898 #define HAS_POOLED_EU(i915) (RUNTIME_INFO(i915)->has_pooled_eu)
899
900 #define HAS_GLOBAL_MOCS_REGISTERS(i915) (INTEL_INFO(i915)->has_global_mocs)
901
902 #define HAS_GMD_ID(i915) (INTEL_INFO(i915)->has_gmd_id)
903
904 #define HAS_L3_CCS_READ(i915) (INTEL_INFO(i915)->has_l3_ccs_read)
905
906 /* DPF == dynamic parity feature */
907 #define HAS_L3_DPF(i915) (INTEL_INFO(i915)->has_l3_dpf)
908 #define NUM_L3_SLICES(i915) (IS_HASWELL_GT3(i915) ? \
909 2 : HAS_L3_DPF(i915))
910
911 /* Only valid when HAS_DISPLAY() is true */
912 #define INTEL_DISPLAY_ENABLED(i915) \
913 (drm_WARN_ON(&(i915)->drm, !HAS_DISPLAY(i915)), \
914 !(i915)->params.disable_display && \
915 !intel_opregion_headless_sku(i915))
916
917 #define HAS_GUC_DEPRIVILEGE(i915) \
918 (INTEL_INFO(i915)->has_guc_deprivilege)
919
920 #define HAS_3D_PIPELINE(i915) (INTEL_INFO(i915)->has_3d_pipeline)
921
922 #define HAS_ONE_EU_PER_FUSE_BIT(i915) (INTEL_INFO(i915)->has_one_eu_per_fuse_bit)
923
924 #define HAS_LMEMBAR_SMEM_STOLEN(i915) (!HAS_LMEM(i915) && \
925 GRAPHICS_VER_FULL(i915) >= IP_VER(12, 70))
926
927 #endif
928