1 /* 2 * Copyright (c) 1988 Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * Advanced Computer Communications. 7 * 8 * %sccs.include.redist.c% 9 * 10 * @(#)if_hdhreg.h 7.3 (Berkeley) 06/28/90 11 */ 12 13 /* 14 * ACC IF-11/HDH interface 15 */ 16 17 struct hdhregs { /* device registers */ 18 u_short csr; /* control and status register */ 19 u_char iochn; /* logical channel */ 20 u_char ioadx; /* address extension (A16,A17) */ 21 u_short ioadl; /* buffer address (A0-A15) */ 22 u_short iocnt; /* byte count */ 23 u_char iofcn; /* UMC funciton code */ 24 u_char iosbf; /* UMC subfunction code */ 25 u_char ioini; /* comm regs valid flag */ 26 u_char staack; /* interrupt acknowledge flag */ 27 u_char ionmi; /* NMI routine active flag */ 28 u_char ioxfrg; /* UMR transfer grant flag */ 29 u_char stachn; /* interrupt channel number */ 30 u_char statyp; /* interrupt type code */ 31 u_char stacc; /* completion function code */ 32 u_char stacs; /* completion subfunction code */ 33 u_short stacnt; /* completion byte count */ 34 }; 35 36 /* defines for CSR */ 37 38 #define HDH_UER 0100000 /* UMC error condition */ 39 #define HDH_NXM 0040000 /* non-existent memory error */ 40 #define HDH_PER 0020000 /* UNIBUS parity error */ 41 #define HDH_ZRUN 0010000 /* Z80 running */ 42 #define HDH_ZGO 0004000 /* Z80 not in wait state */ 43 #define HDH_MBLK 0000200 /* memory swap state (0=main, 1=srv) */ 44 #define HDH_SRV 0000100 /* select UMC service memory */ 45 #define HDH_MAIN 0000040 /* select UMC main memory */ 46 #define HDH_DMA 0000020 /* DMA enable */ 47 #define HDH_WRT 0000010 /* DMA write enable */ 48 #define HDH_IEN 0000004 /* interrupt enable */ 49 #define HDH_RST 0000002 /* reset */ 50 #define HDH_NMI 0000001 /* cause NMI */ 51 52 #define HDH_BITS \ 53 "\10\20UER\17NXM\16PER\15ZRUN\14ZGO\10MBLK\7SRV\6MAIN\5DMA\4WRT\3IEN\2RST\1NMI" 54 55 /* start i/o function code definitions */ 56 57 #define HDHWRT 0 /* write to if-11 */ 58 #define HDHRDB 1 /* read from if-11 */ 59 #define HDHSTR 2 /* stream flag */ 60 #define HDHEOS 6 /* end of stream flag */ 61 #define HDHABT 8 /* abort flag */ 62 #define HDHUMR 16 /* UMR protocol flag */ 63 64 /* interrupt type definitions */ 65 66 #define HDHSACK 0 /* start i/o ack */ 67 #define HDHDONE 1 /* i/o completion */ 68 #define HDHXREQ 2 /* UMR protocol transfer request */ 69 70 /* i/o completion codes */ 71 72 #define HDHIOCOK 0001 /* successful completion */ 73 #define HDHIOCOKP 0002 /* successful completion, more data pending */ 74 #define HDHIOCABT 0361 /* i/o aborted */ 75 #define HDHIOCERR 0321 /* program error */ 76 #define HDHIOCOVR 0363 /* overrun error */ 77 #define HDHIOCUBE 0374 /* non-existant memory or unibus error */ 78 79 /* UMR protocol transfer grant code definitions */ 80 81 #define HDHXEVN 1 /* start with even address */ 82 #define HDHXODD 2 /* start with odd address */ 83 #define HDHNUMR 4 /* non-UMR transfer */ 84 #define HDHXABT 8 /* abort transfer */ 85 86 /* HDH supervisor request code definitions */ 87 #define HDHINIT 0x42 /* SYSINIT opcode */ 88 89 #define HDHSUP 0xf0 /* supervisor HDH status/line control prefix */ 90 #define HDHIMP 0x400 /* IMP line up modifier */ 91 #define HDHREFL 0x800 /* reflect mode modifier */ 92 #define HDHINLB 0x1000 /* internal loopback modifier */ 93 #define HDHEXLP 0x2000 /* external loopback modifier */ 94 #define HDHRQST (HDHSUP+0x0000) /* line status request */ 95 #define HDHRQUP (HDHSUP+0x0100) /* line up request */ 96 #define HDHRQDN (HDHSUP+0x0200) /* line down request */ 97 98 /* HDH supervisor reply code definitions */ 99 100 #define HDHIACK (HDHSUP+0x4200) /* line init ack */ 101 #define HDHLNUP (HDHSUP+0x0100) /* line up reply */ 102 #define HDHLNDN (HDHSUP+0x0200) /* line down reply */ 103 #define HDHLNACK (HDHSUP+0x0300) /* ack line up request (but line is down now) */ 104 #define HDHTIMO (HDHSUP+0x0400) /* line timeout */ 105 #define HDHLOOP (HDHSUP+0x0500) /* loopback message */ 106 #define HDHDTERR (HDHSUP+0x0600) /* host data error detected */ 107 #define HDHSQRCV (HDHSUP+0x0700) /* HDLC sequence error detected by IMP */ 108 #define HDHSQERR (HDHSUP+0x0800) /* HDLC sequence error detected by if-11 */ 109