1 /* $OpenBSD: cpu.h,v 1.105 2024/06/09 21:15:29 jca Exp $ */
2
3 /*
4 * Copyright (c) 2000-2004 Michael Shalayeff
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28 /*
29 * Copyright (c) 1988-1994, The University of Utah and
30 * the Computer Systems Laboratory at the University of Utah (CSL).
31 * All rights reserved.
32 *
33 * Permission to use, copy, modify and distribute this software is hereby
34 * granted provided that (1) source code retains these copyright, permission,
35 * and disclaimer notices, and (2) redistributions including binaries
36 * reproduce the notices in supporting documentation, and (3) all advertising
37 * materials mentioning features or use of this software display the following
38 * acknowledgement: ``This product includes software developed by the
39 * Computer Systems Laboratory at the University of Utah.''
40 *
41 * THE UNIVERSITY OF UTAH AND CSL ALLOW FREE USE OF THIS SOFTWARE IN ITS "AS
42 * IS" CONDITION. THE UNIVERSITY OF UTAH AND CSL DISCLAIM ANY LIABILITY OF
43 * ANY KIND FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
44 *
45 * CSL requests users of this software to return to csl-dist@cs.utah.edu any
46 * improvements that they make and grant CSL redistribution rights.
47 *
48 * Utah $Hdr: cpu.h 1.19 94/12/16$
49 */
50
51 #ifndef _MACHINE_CPU_H_
52 #define _MACHINE_CPU_H_
53
54 #ifdef _KERNEL
55 #include <machine/trap.h>
56 #include <machine/frame.h>
57 #include <machine/reg.h>
58 #endif /* _KERNEL */
59
60 /*
61 * CPU types and features
62 */
63 #define HPPA_FTRS_TLBU 0x00000001
64 #define HPPA_FTRS_BTLBU 0x00000002
65 #define HPPA_FTRS_HVT 0x00000004
66 #define HPPA_FTRS_W32B 0x00000008
67
68 #ifndef _LOCORE
69 #ifdef _KERNEL
70 #include <sys/clockintr.h>
71 #include <sys/device.h>
72 #include <sys/queue.h>
73 #include <sys/sched.h>
74 #include <sys/srp.h>
75
76 #include <machine/mutex.h>
77
78 /*
79 * Note that the alignment of ci_trap_save is important since we want to keep
80 * it within a single cache line. As a result, it must be kept as the first
81 * entry within the cpu_info struct.
82 */
83 struct cpu_info {
84 register_t ci_trap_save[16];
85
86 struct device *ci_dev;
87 int ci_cpuid;
88 hppa_hpa_t ci_hpa;
89 volatile int ci_flags;
90
91 struct proc *ci_curproc;
92 paddr_t ci_fpu_state; /* Process FPU state. */
93 paddr_t ci_stack;
94
95 #if defined(MULTIPROCESSOR)
96 struct srp_hazard ci_srp_hazards[SRP_HAZARD_NUM];
97 #endif
98
99 register_t ci_psw; /* Processor Status Word. */
100 volatile int ci_cpl;
101 volatile u_long ci_mask; /* Hardware interrupt mask. */
102 volatile u_long ci_ipending;
103 volatile int ci_in_intr;
104 int ci_want_resched;
105
106 volatile u_long ci_ipi; /* IPIs pending. */
107 struct mutex ci_ipi_mtx;
108
109 struct schedstate_percpu ci_schedstate;
110 u_int32_t ci_randseed;
111 #ifdef DIAGNOSTIC
112 int ci_mutex_level;
113 #endif
114 #ifdef GPROF
115 struct gmonparam *ci_gmon;
116 struct clockintr ci_gmonclock;
117 #endif
118 struct clockqueue ci_queue;
119 char ci_panicbuf[512];
120 } __attribute__((__aligned__(64)));
121
122 #define CPUF_RUNNING 0x0001 /* CPU is running. */
123
124 #ifdef MULTIPROCESSOR
125 #define HPPA_MAXCPUS 4
126 #else
127 #define HPPA_MAXCPUS 1
128 #endif
129
130 extern struct cpu_info cpu_info[HPPA_MAXCPUS];
131
132 #define MAXCPUS HPPA_MAXCPUS
133
134 #ifdef MULTIPROCESSOR
135
136 static __inline struct cpu_info *
curcpu(void)137 curcpu(void)
138 {
139 struct cpu_info *ci;
140
141 asm volatile ("mfctl %%cr29, %0" : "=r"(ci));
142
143 return ci;
144 }
145
146 #define cpu_number() (curcpu()->ci_cpuid)
147
148 #define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0)
149 #define CPU_IS_PRIMARY(ci) ((ci)->ci_cpuid == 0)
150 #define CPU_IS_RUNNING(ci) ((ci)->ci_flags & CPUF_RUNNING)
151
152 #else
153
154 #define curcpu() (&cpu_info[0])
155
156 #define cpu_number() 0
157
158 #define CPU_INFO_UNIT(ci) 0
159 #define CPU_IS_PRIMARY(ci) 1
160 #define CPU_IS_RUNNING(ci) 1
161
162 #endif
163
164 #define CPU_INFO_ITERATOR int
165 #define CPU_INFO_FOREACH(cii, ci) \
166 for (cii = 0, ci = &cpu_info[0]; cii < ncpus; cii++, ci++)
167
168 #define CPU_BUSY_CYCLE() __asm volatile ("" ::: "memory")
169
170 /* types */
171 enum hppa_cpu_type {
172 hpcxs, hpcxt, hpcxta, hpcxl, hpcxl2, hpcxu, hpcxu2, hpcxw
173 };
174 extern enum hppa_cpu_type cpu_type;
175 extern const char *cpu_typename;
176 extern int cpu_hvers;
177 #endif
178 #endif
179
180 /*
181 * COPR/SFUs
182 */
183 #define HPPA_FPUS 0xc0
184 #define HPPA_FPUVER(w) (((w) & 0x003ff800) >> 11)
185 #define HPPA_FPU_OP(w) ((w) >> 26)
186 #define HPPA_FPU_UNMPL 0x01 /* exception reg, the rest is << 1 */
187 #define HPPA_FPU_ILL 0x80 /* software-only */
188 #define HPPA_FPU_I 0x01
189 #define HPPA_FPU_U 0x02
190 #define HPPA_FPU_O 0x04
191 #define HPPA_FPU_Z 0x08
192 #define HPPA_FPU_V 0x10
193 #define HPPA_FPU_D 0x20
194 #define HPPA_FPU_T 0x40
195 #define HPPA_FPU_XMASK 0x7f
196 #define HPPA_FPU_T_POS 25
197 #define HPPA_FPU_RM 0x00000600
198 #define HPPA_FPU_CQ 0x00fff800
199 #define HPPA_FPU_C 0x04000000
200 #define HPPA_FPU_FLSH 27
201 #define HPPA_FPU_INIT (0)
202 #define HPPA_FPU_FORK(s) ((s) & ~((u_int64_t)(HPPA_FPU_XMASK)<<32))
203 #define HPPA_PMSFUS 0x20 /* ??? */
204
205 /*
206 * Exported definitions unique to hp700/PA-RISC cpu support.
207 */
208
209 #define HPPA_PGALIAS 0x00400000
210 #define HPPA_PGAOFF 0x003fffff
211
212 #define HPPA_IOBEGIN 0xf0000000
213 #define HPPA_IOLEN 0x10000000
214 #define HPPA_PDC_LOW 0xef000000
215 #define HPPA_PDC_HIGH 0xf1000000
216 #define HPPA_IOBCAST 0xfffc0000
217 #define HPPA_LBCAST 0xfffc0000
218 #define HPPA_GBCAST 0xfffe0000
219 #define HPPA_FPA 0xfff80000
220 #define HPPA_FLEX_DATA 0xfff80001
221 #define HPPA_DMA_ENABLE 0x00000001
222 #define HPPA_FLEX_MASK 0xfffc0000
223 #define HPPA_FLEX_SIZE (1 + ~HPPA_FLEX_MASK)
224 #define HPPA_FLEX(a) (((a) & HPPA_FLEX_MASK) >> 18)
225 #define HPPA_SPA_ENABLE 0x00000020
226 #define HPPA_NMODSPBUS 64
227
228 #define clockframe trapframe
229 #define CLKF_PC(framep) ((framep)->tf_iioq_head)
230 #define CLKF_INTR(framep) ((framep)->tf_flags & TFF_INTR)
231 #define CLKF_USERMODE(framep) ((framep)->tf_flags & T_USER)
232 #define CLKF_SYSCALL(framep) ((framep)->tf_flags & TFF_SYS)
233
234 #define need_proftick(p) setsoftast(p)
235 #define PROC_PC(p) ((p)->p_md.md_regs->tf_iioq_head & ~HPPA_PC_PRIV_MASK)
236 #define PROC_STACK(p) ((p)->p_md.md_regs->tf_sp)
237
238 #ifndef _LOCORE
239 #ifdef _KERNEL
240
241 #define DELAY(x) delay(x)
242
243 extern int (*cpu_desidhash)(void);
244
245 void signotify(struct proc *);
246 void delay(u_int us);
247 void hppa_init(paddr_t start);
248 void trap(int type, struct trapframe *frame);
249 int spcopy(pa_space_t ssp, const void *src,
250 pa_space_t dsp, void *dst, size_t size);
251 int spcopy32(pa_space_t ssp, const uint32_t *src,
252 pa_space_t dsp, uint32_t *dst);
253 int spstrcpy(pa_space_t ssp, const void *src,
254 pa_space_t dsp, void *dst, size_t size, size_t *rsize);
255 int copy_on_fault(void);
256 void proc_trampoline(void);
257 int cpu_dumpsize(void);
258 int cpu_dump(void);
259
260 static inline unsigned int
cpu_rnd_messybits(void)261 cpu_rnd_messybits(void)
262 {
263 unsigned int __itmr;
264
265 __asm volatile("mfctl %1,%0": "=r" (__itmr) : "i" (CR_ITMR));
266
267 return (__itmr);
268 }
269
270 #ifdef MULTIPROCESSOR
271 void cpu_boot_secondary_processors(void);
272 void cpu_hw_init(void);
273 void cpu_hatch(void);
274 void cpu_unidle(struct cpu_info *);
275 #else
276 #define cpu_unidle(ci)
277 #endif
278
279 extern void need_resched(struct cpu_info *);
280 #define clear_resched(ci) (ci)->ci_want_resched = 0
281
282 #endif
283
284 /*
285 * Boot arguments stuff
286 */
287
288 #define BOOTARG_LEN PAGE_SIZE
289 #define BOOTARG_OFF 0x10000
290
291 /*
292 * CTL_MACHDEP definitions.
293 */
294 #define CPU_CONSDEV 1 /* dev_t: console terminal device */
295 #define CPU_FPU 2 /* int: fpu present/enabled */
296 #define CPU_LED_BLINK 3 /* int: twiddle heartbeat LED/LCD */
297 #define CPU_MAXID 4 /* number of valid machdep ids */
298
299 #define CTL_MACHDEP_NAMES { \
300 { 0, 0 }, \
301 { "console_device", CTLTYPE_STRUCT }, \
302 { "fpu", CTLTYPE_INT }, \
303 { "led_blink", CTLTYPE_INT }, \
304 }
305
306 #ifdef _KERNEL
307 #include <sys/queue.h>
308
309 #ifdef MULTIPROCESSOR
310 #include <sys/mplock.h>
311 #endif
312
313 struct blink_led {
314 void (*bl_func)(void *, int);
315 void *bl_arg;
316 SLIST_ENTRY(blink_led) bl_next;
317 };
318
319 extern void blink_led_register(struct blink_led *);
320 #endif
321
322 #define copyinsn(p, v, ip) copyin32((v), (ip))
323
324 #endif
325
326 #endif /* _MACHINE_CPU_H_ */
327