1 #ifndef MMU_HASH64_H
2 #define MMU_HASH64_H
3
4 #ifndef CONFIG_USER_ONLY
5
6 #ifdef TARGET_PPC64
7 void dump_slb(PowerPCCPU *cpu);
8 int ppc_store_slb(PowerPCCPU *cpu, target_ulong slot,
9 target_ulong esid, target_ulong vsid);
10 bool ppc_hash64_xlate(PowerPCCPU *cpu, vaddr eaddr, MMUAccessType access_type,
11 hwaddr *raddrp, int *psizep, int *protp, int mmu_idx,
12 bool guest_visible);
13 void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu,
14 target_ulong pte_index,
15 target_ulong pte0, target_ulong pte1);
16 unsigned ppc_hash64_hpte_page_shift_noslb(PowerPCCPU *cpu,
17 uint64_t pte0, uint64_t pte1);
18 void ppc_hash64_init(PowerPCCPU *cpu);
19 void ppc_hash64_finalize(PowerPCCPU *cpu);
20 #endif
21
22 /*
23 * SLB definitions
24 */
25
26 /* Bits in the SLB ESID word */
27 #define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
28 #define SLB_ESID_V 0x0000000008000000ULL /* valid */
29
30 /* Bits in the SLB VSID word */
31 #define SLB_VSID_SHIFT 12
32 #define SLB_VSID_SHIFT_1T 24
33 #define SLB_VSID_SSIZE_SHIFT 62
34 #define SLB_VSID_B 0xc000000000000000ULL
35 #define SLB_VSID_B_256M 0x0000000000000000ULL
36 #define SLB_VSID_B_1T 0x4000000000000000ULL
37 #define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
38 #define SLB_VSID_VRMA (0x0001FFFFFF000000ULL | SLB_VSID_B_1T)
39 #define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
40 #define SLB_VSID_KS 0x0000000000000800ULL
41 #define SLB_VSID_KP 0x0000000000000400ULL
42 #define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
43 #define SLB_VSID_L 0x0000000000000100ULL
44 #define SLB_VSID_L_SHIFT PPC_BIT_NR(55)
45 #define SLB_VSID_C 0x0000000000000080ULL /* class */
46 #define SLB_VSID_LP 0x0000000000000030ULL
47 #define SLB_VSID_LP_SHIFT PPC_BIT_NR(59)
48 #define SLB_VSID_ATTR 0x0000000000000FFFULL
49 #define SLB_VSID_LLP_MASK (SLB_VSID_L | SLB_VSID_LP)
50 #define SLB_VSID_4K 0x0000000000000000ULL
51 #define SLB_VSID_64K 0x0000000000000110ULL
52 #define SLB_VSID_16M 0x0000000000000100ULL
53 #define SLB_VSID_16G 0x0000000000000120ULL
54
55 /*
56 * Hash page table definitions
57 */
58
59 #define SDR_64_HTABORG 0x0FFFFFFFFFFC0000ULL
60 #define SDR_64_HTABSIZE 0x000000000000001FULL
61
62 #define PATE0_HTABORG 0x0FFFFFFFFFFC0000ULL
63 #define PATE0_PS PPC_BITMASK(56, 58)
64 #define PATE0_GET_PS(dw0) (((dw0) & PATE0_PS) >> PPC_BIT_NR(58))
65
66 #define HPTES_PER_GROUP 8
67 #define HASH_PTE_SIZE_64 16
68 #define HASH_PTEG_SIZE_64 (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)
69
70 #define HPTE64_V_SSIZE SLB_VSID_B
71 #define HPTE64_V_SSIZE_256M SLB_VSID_B_256M
72 #define HPTE64_V_SSIZE_1T SLB_VSID_B_1T
73 #define HPTE64_V_SSIZE_SHIFT 62
74 #define HPTE64_V_AVPN_SHIFT 7
75 #define HPTE64_V_AVPN 0x3fffffffffffff80ULL
76 #define HPTE64_V_AVPN_VAL(x) (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
77 #define HPTE64_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff83ULL))
78 #define HPTE64_V_BOLTED 0x0000000000000010ULL
79 #define HPTE64_V_LARGE 0x0000000000000004ULL
80 #define HPTE64_V_SECONDARY 0x0000000000000002ULL
81 #define HPTE64_V_VALID 0x0000000000000001ULL
82
83 #define HPTE64_R_PP0 0x8000000000000000ULL
84 #define HPTE64_R_TS 0x4000000000000000ULL
85 #define HPTE64_R_KEY_HI 0x3000000000000000ULL
86 #define HPTE64_R_RPN_SHIFT 12
87 #define HPTE64_R_RPN 0x0ffffffffffff000ULL
88 #define HPTE64_R_FLAGS 0x00000000000003ffULL
89 #define HPTE64_R_PP 0x0000000000000003ULL
90 #define HPTE64_R_N 0x0000000000000004ULL
91 #define HPTE64_R_G 0x0000000000000008ULL
92 #define HPTE64_R_M 0x0000000000000010ULL
93 #define HPTE64_R_I 0x0000000000000020ULL
94 #define HPTE64_R_W 0x0000000000000040ULL
95 #define HPTE64_R_WIMG 0x0000000000000078ULL
96 #define HPTE64_R_C 0x0000000000000080ULL
97 #define HPTE64_R_R 0x0000000000000100ULL
98 #define HPTE64_R_KEY_LO 0x0000000000000e00ULL
99 #define HPTE64_R_KEY(x) ((((x) & HPTE64_R_KEY_HI) >> 57) | \
100 (((x) & HPTE64_R_KEY_LO) >> 9))
101
102 #define HPTE64_V_1TB_SEG 0x4000000000000000ULL
103 #define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
104
105 /* PTE offsets */
106 #define HPTE64_DW1 (HASH_PTE_SIZE_64 / 2)
107 #define HPTE64_DW1_R (HPTE64_DW1 + 6)
108 #define HPTE64_DW1_C (HPTE64_DW1 + 7)
109
110 /* Format changes for ARCH v3 */
111 #define HPTE64_V_COMMON_BITS 0x000fffffffffffffULL
112 #define HPTE64_R_3_0_SSIZE_SHIFT 58
113 #define HPTE64_R_3_0_SSIZE_MASK (3ULL << HPTE64_R_3_0_SSIZE_SHIFT)
114
115 struct ppc_hash_pte64 {
116 uint64_t pte0, pte1;
117 };
118
119 const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
120 hwaddr ptex, int n);
121 void ppc_hash64_unmap_hptes(PowerPCCPU *cpu, const ppc_hash_pte64_t *hptes,
122 hwaddr ptex, int n);
123
ppc_hash64_hpte0(PowerPCCPU * cpu,const ppc_hash_pte64_t * hptes,int i)124 static inline uint64_t ppc_hash64_hpte0(PowerPCCPU *cpu,
125 const ppc_hash_pte64_t *hptes, int i)
126 {
127 return ldq_p(&(hptes[i].pte0));
128 }
129
ppc_hash64_hpte1(PowerPCCPU * cpu,const ppc_hash_pte64_t * hptes,int i)130 static inline uint64_t ppc_hash64_hpte1(PowerPCCPU *cpu,
131 const ppc_hash_pte64_t *hptes, int i)
132 {
133 return ldq_p(&(hptes[i].pte1));
134 }
135
136 /*
137 * MMU Options
138 */
139
140 struct PPCHash64PageSize {
141 uint32_t page_shift; /* Page shift (or 0) */
142 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
143 };
144 typedef struct PPCHash64PageSize PPCHash64PageSize;
145
146 struct PPCHash64SegmentPageSizes {
147 uint32_t page_shift; /* Base page shift of segment (or 0) */
148 uint32_t slb_enc; /* SLB encoding for BookS */
149 PPCHash64PageSize enc[PPC_PAGE_SIZES_MAX_SZ];
150 };
151
152 struct PPCHash64Options {
153 #define PPC_HASH64_1TSEG 0x00001
154 #define PPC_HASH64_AMR 0x00002
155 #define PPC_HASH64_CI_LARGEPAGE 0x00004
156 unsigned flags;
157 unsigned slb_size;
158 PPCHash64SegmentPageSizes sps[PPC_PAGE_SIZES_MAX_SZ];
159 };
160
161 extern const PPCHash64Options ppc_hash64_opts_basic;
162 extern const PPCHash64Options ppc_hash64_opts_POWER7;
163
ppc_hash64_has(PowerPCCPU * cpu,unsigned feature)164 static inline bool ppc_hash64_has(PowerPCCPU *cpu, unsigned feature)
165 {
166 return !!(cpu->hash64_opts->flags & feature);
167 }
168
169 #endif /* CONFIG_USER_ONLY */
170
171 #if defined(CONFIG_USER_ONLY) || !defined(TARGET_PPC64)
ppc_hash64_init(PowerPCCPU * cpu)172 static inline void ppc_hash64_init(PowerPCCPU *cpu)
173 {
174 }
ppc_hash64_finalize(PowerPCCPU * cpu)175 static inline void ppc_hash64_finalize(PowerPCCPU *cpu)
176 {
177 }
178 #endif
179
180 #endif /* MMU_HASH64_H */
181