1 /******************************************************************************* 2 3 Copyright (c) 2001-2005, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 *******************************************************************************/ 33 34 /* $OpenBSD: if_em_hw.h,v 1.98 2024/10/22 05:11:14 jsg Exp $ */ 35 /* $FreeBSD: if_em_hw.h,v 1.15 2005/05/26 23:32:02 tackerman Exp $ */ 36 37 /* if_em_hw.h 38 * Structures, enums, and macros for the MAC 39 */ 40 41 #ifndef _EM_HW_H_ 42 #define _EM_HW_H_ 43 44 #include <dev/pci/if_em_osdep.h> 45 46 /* Forward declarations of structures used by the shared code */ 47 struct em_hw; 48 struct em_hw_stats; 49 50 /* Enumerated types specific to the e1000 hardware */ 51 /* Media Access Controllers */ 52 typedef enum { 53 em_undefined = 0, 54 em_82542_rev2_0, 55 em_82542_rev2_1, 56 em_82543, 57 em_82544, 58 em_82540, 59 em_82545, 60 em_82545_rev_3, 61 em_icp_xxxx, 62 em_82546, 63 em_82546_rev_3, 64 em_82541, 65 em_82541_rev_2, 66 em_82547, 67 em_82547_rev_2, 68 em_82571, 69 em_82572, 70 em_82573, 71 em_82574, 72 em_82575, 73 em_82576, 74 em_82580, 75 em_i350, 76 em_i210, 77 em_80003es2lan, 78 em_ich8lan, 79 em_ich9lan, 80 em_ich10lan, 81 em_pchlan, 82 em_pch2lan, 83 em_pch_lpt, 84 em_pch_spt, 85 em_pch_cnp, 86 em_pch_tgp, 87 em_pch_adp, 88 em_num_macs 89 } em_mac_type; 90 91 #define IS_ICH8(t) \ 92 (t == em_ich8lan || t == em_ich9lan || t == em_ich10lan || \ 93 t == em_pchlan || t == em_pch2lan || t == em_pch_lpt || \ 94 t == em_pch_spt || t == em_pch_cnp || t == em_pch_tgp || \ 95 t == em_pch_adp) 96 97 typedef enum { 98 em_eeprom_uninitialized = 0, 99 em_eeprom_spi, 100 em_eeprom_microwire, 101 em_eeprom_flash, 102 em_eeprom_ich8, 103 em_eeprom_invm, 104 em_eeprom_none, /* No NVM support */ 105 em_num_eeprom_types 106 } em_eeprom_type; 107 108 /* Media Types */ 109 typedef enum { 110 em_media_type_copper = 0, 111 em_media_type_fiber = 1, 112 em_media_type_internal_serdes = 2, 113 em_media_type_oem = 3, 114 em_num_media_types 115 } em_media_type; 116 117 typedef enum { 118 em_10_half = 0, 119 em_10_full = 1, 120 em_100_half = 2, 121 em_100_full = 3 122 } em_speed_duplex_type; 123 124 struct em_shadow_ram { 125 uint16_t eeprom_word; 126 boolean_t modified; 127 }; 128 129 /* PCI bus types */ 130 typedef enum { 131 em_bus_type_unknown = 0, 132 em_bus_type_pci, 133 em_bus_type_pcix, 134 em_bus_type_pci_express, 135 em_bus_type_cpp, 136 em_bus_type_reserved 137 } em_bus_type; 138 139 /* PCI bus speeds */ 140 typedef enum { 141 em_bus_speed_unknown = 0, 142 em_bus_speed_33, 143 em_bus_speed_66, 144 em_bus_speed_100, 145 em_bus_speed_120, 146 em_bus_speed_133, 147 em_bus_speed_2500, 148 em_bus_speed_reserved 149 } em_bus_speed; 150 151 /* PCI bus widths */ 152 typedef enum { 153 em_bus_width_unknown = 0, 154 /* These PCIe values should literally match the possible return values 155 * from config space */ 156 em_bus_width_pciex_1 = 1, 157 em_bus_width_pciex_2 = 2, 158 em_bus_width_pciex_4 = 4, 159 em_bus_width_32, 160 em_bus_width_64, 161 em_bus_width_reserved 162 } em_bus_width; 163 164 /* PHY status info structure and supporting enums */ 165 typedef enum { 166 em_cable_length_50 = 0, 167 em_cable_length_50_80, 168 em_cable_length_80_110, 169 em_cable_length_110_140, 170 em_cable_length_140, 171 em_cable_length_undefined = 0xFF 172 } em_cable_length; 173 174 typedef enum { 175 em_gg_cable_length_60 = 0, 176 em_gg_cable_length_60_115 = 1, 177 em_gg_cable_length_115_150 = 2, 178 em_gg_cable_length_150 = 4 179 } em_gg_cable_length; 180 181 typedef enum { 182 em_igp_cable_length_10 = 10, 183 em_igp_cable_length_20 = 20, 184 em_igp_cable_length_30 = 30, 185 em_igp_cable_length_40 = 40, 186 em_igp_cable_length_50 = 50, 187 em_igp_cable_length_60 = 60, 188 em_igp_cable_length_70 = 70, 189 em_igp_cable_length_80 = 80, 190 em_igp_cable_length_90 = 90, 191 em_igp_cable_length_100 = 100, 192 em_igp_cable_length_110 = 110, 193 em_igp_cable_length_115 = 115, 194 em_igp_cable_length_120 = 120, 195 em_igp_cable_length_130 = 130, 196 em_igp_cable_length_140 = 140, 197 em_igp_cable_length_150 = 150, 198 em_igp_cable_length_160 = 160, 199 em_igp_cable_length_170 = 170, 200 em_igp_cable_length_180 = 180 201 } em_igp_cable_length; 202 203 typedef enum { 204 em_10bt_ext_dist_enable_normal = 0, 205 em_10bt_ext_dist_enable_lower, 206 em_10bt_ext_dist_enable_undefined = 0xFF 207 } em_10bt_ext_dist_enable; 208 209 typedef enum { 210 em_rev_polarity_normal = 0, 211 em_rev_polarity_reversed, 212 em_rev_polarity_undefined = 0xFF 213 } em_rev_polarity; 214 215 typedef enum { 216 em_downshift_normal = 0, 217 em_downshift_activated, 218 em_downshift_undefined = 0xFF 219 } em_downshift; 220 221 typedef enum { 222 em_smart_speed_default = 0, 223 em_smart_speed_on, 224 em_smart_speed_off 225 } em_smart_speed; 226 227 typedef enum { 228 em_polarity_reversal_enabled = 0, 229 em_polarity_reversal_disabled, 230 em_polarity_reversal_undefined = 0xFF 231 } em_polarity_reversal; 232 233 typedef enum { 234 em_auto_x_mode_manual_mdi = 0, 235 em_auto_x_mode_manual_mdix, 236 em_auto_x_mode_auto1, 237 em_auto_x_mode_auto2, 238 em_auto_x_mode_undefined = 0xFF 239 } em_auto_x_mode; 240 241 typedef enum { 242 em_1000t_rx_status_not_ok = 0, 243 em_1000t_rx_status_ok, 244 em_1000t_rx_status_undefined = 0xFF 245 } em_1000t_rx_status; 246 247 typedef enum { 248 em_phy_m88 = 0, 249 em_phy_igp, 250 em_phy_igp_2, 251 em_phy_gg82563, 252 em_phy_igp_3, 253 em_phy_ife, 254 em_phy_bm, /* phy used in i82574L, ICH10 and some ICH9 */ 255 em_phy_oem, 256 em_phy_82577, 257 em_phy_82578, 258 em_phy_82579, 259 em_phy_i217, 260 em_phy_82580, 261 em_phy_rtl8211, 262 em_phy_undefined = 0xFF 263 } em_phy_type; 264 265 typedef enum { 266 em_ms_hw_default = 0, 267 em_ms_force_master, 268 em_ms_force_slave, 269 em_ms_auto 270 } em_ms_type; 271 272 typedef enum { 273 em_ffe_config_enabled = 0, 274 em_ffe_config_active, 275 em_ffe_config_blocked 276 } em_ffe_config; 277 278 typedef enum { 279 em_dsp_config_disabled = 0, 280 em_dsp_config_enabled, 281 em_dsp_config_activated, 282 em_dsp_config_undefined = 0xFF 283 } em_dsp_config; 284 285 struct em_phy_info { 286 em_cable_length cable_length; 287 em_10bt_ext_dist_enable extended_10bt_distance; 288 em_rev_polarity cable_polarity; 289 em_downshift downshift; 290 em_polarity_reversal polarity_correction; 291 em_auto_x_mode mdix_mode; 292 em_1000t_rx_status local_rx; 293 em_1000t_rx_status remote_rx; 294 }; 295 296 struct em_phy_stats { 297 uint32_t idle_errors; 298 uint32_t receive_errors; 299 }; 300 301 struct em_eeprom_info { 302 em_eeprom_type type; 303 uint16_t word_size; 304 uint16_t opcode_bits; 305 uint16_t address_bits; 306 uint16_t delay_usec; 307 uint16_t page_size; 308 boolean_t use_eerd; 309 boolean_t use_eewr; 310 }; 311 312 /* Flex ASF Information */ 313 #define E1000_HOST_IF_MAX_SIZE 2048 314 315 typedef enum { 316 em_byte_align = 0, 317 em_word_align = 1, 318 em_dword_align = 2 319 } em_align_type; 320 321 /* Error Codes */ 322 #define E1000_SUCCESS 0 323 #define E1000_ERR_EEPROM 1 324 #define E1000_ERR_PHY 2 325 #define E1000_ERR_CONFIG 3 326 #define E1000_ERR_PARAM 4 327 #define E1000_ERR_MAC_TYPE 5 328 #define E1000_ERR_PHY_TYPE 6 329 #define E1000_ERR_RESET 9 330 #define E1000_ERR_MASTER_REQUESTS_PENDING 10 331 #define E1000_ERR_HOST_INTERFACE_COMMAND 11 332 #define E1000_BLK_PHY_RESET 12 333 #define E1000_ERR_SWFW_SYNC 13 334 #define E1000_NOT_IMPLEMENTED 14 335 #define E1000_DEFER_INIT 15 336 337 #define E1000_BYTE_SWAP_WORD(_value) ((((_value) & 0x00ff) << 8) | \ 338 (((_value) & 0xff00) >> 8)) 339 340 /* Function prototypes */ 341 /* Initialization */ 342 struct em_softc; 343 int32_t em_reset_hw(struct em_hw *hw); 344 int32_t em_init_hw(struct em_softc *sc); 345 int32_t em_set_mac_type(struct em_hw *hw); 346 void em_set_media_type(struct em_hw *hw); 347 348 /* Link Configuration */ 349 int32_t em_setup_link(struct em_hw *hw); 350 int32_t em_phy_setup_autoneg(struct em_hw *hw); 351 void em_config_collision_dist(struct em_hw *hw); 352 int32_t em_check_for_link(struct em_hw *hw); 353 int32_t em_get_speed_and_duplex(struct em_hw *hw, uint16_t *speed, uint16_t *duplex); 354 int32_t em_force_mac_fc(struct em_hw *hw); 355 int32_t em_copper_link_autoneg(struct em_hw *hw); 356 int32_t em_copper_link_postconfig(struct em_hw *hw); 357 358 /* PHY */ 359 int32_t em_read_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t *phy_data); 360 int32_t em_write_phy_reg(struct em_hw *hw, uint32_t reg_addr, uint16_t data); 361 int32_t em_phy_hw_reset(struct em_hw *hw); 362 int32_t em_phy_reset(struct em_hw *hw); 363 int em_sgmii_uses_mdio_82575(struct em_hw *); 364 int32_t em_read_phy_reg_i2c(struct em_hw *, uint32_t, uint16_t *); 365 int32_t em_write_phy_reg_i2c(struct em_hw *, uint32_t, uint16_t); 366 int32_t em_read_sfp_data_byte(struct em_hw *, uint16_t, uint8_t *); 367 368 /* EEPROM Functions */ 369 int32_t em_init_eeprom_params(struct em_hw *hw); 370 371 #define E1000_MNG_DHCP_TX_PAYLOAD_CMD 64 372 #define E1000_HI_MAX_MNG_DATA_LENGTH 0x6F8 /* Host Interface data length */ 373 374 #define E1000_MNG_DHCP_COMMAND_TIMEOUT 10 /* Time in ms to process MNG command */ 375 #define E1000_MNG_DHCP_COOKIE_OFFSET 0x6F0 /* Cookie offset */ 376 #define E1000_MNG_DHCP_COOKIE_LENGTH 0x10 /* Cookie length */ 377 #define E1000_MNG_IAMT_MODE 0x3 378 #define E1000_MNG_ICH_IAMT_MODE 0x2 379 #define E1000_IAMT_SIGNATURE 0x544D4149 /* Intel(R) Active Management Technology signature */ 380 381 #define E1000_MNG_DHCP_COOKIE_STATUS_PARSING_SUPPORT 0x1 /* DHCP parsing enabled */ 382 #define E1000_MNG_DHCP_COOKIE_STATUS_VLAN_SUPPORT 0x2 /* DHCP parsing enabled */ 383 #define E1000_VFTA_ENTRY_SHIFT 0x5 384 #define E1000_VFTA_ENTRY_MASK 0x7F 385 #define E1000_VFTA_ENTRY_BIT_SHIFT_MASK 0x1F 386 387 struct em_host_mng_command_header { 388 uint8_t command_id; 389 uint8_t checksum; 390 uint16_t reserved1; 391 uint16_t reserved2; 392 uint16_t command_length; 393 }; 394 395 struct em_host_mng_command_info { 396 struct em_host_mng_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 397 uint8_t command_data[E1000_HI_MAX_MNG_DATA_LENGTH]; /* Command data can length 0..0x658*/ 398 }; 399 struct em_host_mng_dhcp_cookie{ 400 uint32_t signature; 401 uint8_t status; 402 uint8_t reserved0; 403 uint16_t vlan_id; 404 uint32_t reserved1; 405 uint16_t reserved2; 406 uint8_t reserved3; 407 uint8_t checksum; 408 }; 409 410 int32_t em_read_part_num(struct em_hw *hw, uint32_t *part_num); 411 boolean_t em_check_mng_mode(struct em_hw *hw); 412 boolean_t em_enable_tx_pkt_filtering(struct em_hw *hw); 413 int32_t em_read_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 414 int32_t em_validate_eeprom_checksum(struct em_hw *hw); 415 int32_t em_update_eeprom_checksum(struct em_hw *hw); 416 int32_t em_write_eeprom(struct em_hw *hw, uint16_t reg, uint16_t words, uint16_t *data); 417 int32_t em_read_mac_addr(struct em_hw * hw); 418 boolean_t em_get_flash_presence_i210(struct em_hw *); 419 420 /* Filters (multicast, vlan, receive) */ 421 void em_mc_addr_list_update(struct em_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, 422 uint32_t pad); 423 uint32_t em_hash_mc_addr(struct em_hw *hw, uint8_t *mc_addr); 424 void em_mta_set(struct em_hw *hw, uint32_t hash_value); 425 void em_rar_set(struct em_hw *hw, uint8_t *mc_addr, uint32_t rar_index); 426 427 /* Adaptive IFS Functions */ 428 429 /* Everything else */ 430 void em_clear_hw_cntrs(struct em_hw *hw); 431 void em_get_bus_info(struct em_hw *hw); 432 void em_pci_set_mwi(struct em_hw *hw); 433 void em_pci_clear_mwi(struct em_hw *hw); 434 void em_read_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value); 435 void em_write_pci_cfg(struct em_hw *hw, uint32_t reg, uint16_t *value); 436 int32_t em_read_pcie_cap_reg(struct em_hw *hw, uint32_t reg, uint16_t *value); 437 /* Port I/O is only supported on 82544 and newer */ 438 int32_t em_disable_pciex_master(struct em_hw *hw); 439 int32_t em_check_phy_reset_block(struct em_hw *hw); 440 uint32_t em_translate_82542_register(uint32_t); 441 442 #ifndef E1000_READ_REG_IO 443 #define E1000_READ_REG_IO(a, reg) \ 444 em_read_reg_io((a), E1000_##reg) 445 #define E1000_WRITE_REG_IO(a, reg, val) \ 446 em_write_reg_io((a), E1000_##reg, val) 447 #endif 448 449 /* PCI Device IDs */ 450 #define E1000_DEV_ID_82542 0x1000 451 #define E1000_DEV_ID_82543GC_FIBER 0x1001 452 #define E1000_DEV_ID_82543GC_COPPER 0x1004 453 #define E1000_DEV_ID_82544EI_COPPER 0x1008 454 #define E1000_DEV_ID_82544EI_FIBER 0x1009 455 #define E1000_DEV_ID_82544GC_COPPER 0x100C 456 #define E1000_DEV_ID_82544GC_LOM 0x100D 457 #define E1000_DEV_ID_82540EM 0x100E 458 #define E1000_DEV_ID_82540EM_LOM 0x1015 459 #define E1000_DEV_ID_82540EP_LOM 0x1016 460 #define E1000_DEV_ID_82540EP 0x1017 461 #define E1000_DEV_ID_82540EP_LP 0x101E 462 #define E1000_DEV_ID_82545EM_COPPER 0x100F 463 #define E1000_DEV_ID_82545EM_FIBER 0x1011 464 #define E1000_DEV_ID_82545GM_COPPER 0x1026 465 #define E1000_DEV_ID_82545GM_FIBER 0x1027 466 #define E1000_DEV_ID_82545GM_SERDES 0x1028 467 #define E1000_DEV_ID_82546EB_COPPER 0x1010 468 #define E1000_DEV_ID_82546EB_FIBER 0x1012 469 #define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D 470 #define E1000_DEV_ID_82541EI 0x1013 471 #define E1000_DEV_ID_82541EI_MOBILE 0x1018 472 #define E1000_DEV_ID_82541ER_LOM 0x1014 473 #define E1000_DEV_ID_82541ER 0x1078 474 #define E1000_DEV_ID_82547GI 0x1075 475 #define E1000_DEV_ID_82541GI 0x1076 476 #define E1000_DEV_ID_82541GI_MOBILE 0x1077 477 #define E1000_DEV_ID_82541GI_LF 0x107C 478 #define E1000_DEV_ID_82546GB_COPPER 0x1079 479 #define E1000_DEV_ID_82546GB_FIBER 0x107A 480 #define E1000_DEV_ID_82546GB_SERDES 0x107B 481 #define E1000_DEV_ID_82546GB_PCIE 0x108A 482 #define E1000_DEV_ID_82546GB_QUAD_COPPER 0x1099 483 #define E1000_DEV_ID_82547EI 0x1019 484 #define E1000_DEV_ID_82547EI_MOBILE 0x101A 485 #define E1000_DEV_ID_82571EB_COPPER 0x105E 486 #define E1000_DEV_ID_82571EB_FIBER 0x105F 487 #define E1000_DEV_ID_82571EB_SERDES 0x1060 488 #define E1000_DEV_ID_82571EB_SERDES_DUAL 0x10D9 489 #define E1000_DEV_ID_82571EB_SERDES_QUAD 0x10DA 490 #define E1000_DEV_ID_82571EB_QUAD_COPPER 0x10A4 491 #define E1000_DEV_ID_82571EB_QUAD_FIBER 0x10A5 492 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP 0x10BC 493 #define E1000_DEV_ID_82571PT_QUAD_COPPER 0x10D5 494 #define E1000_DEV_ID_82572EI_COPPER 0x107D 495 #define E1000_DEV_ID_82572EI_FIBER 0x107E 496 #define E1000_DEV_ID_82572EI_SERDES 0x107F 497 #define E1000_DEV_ID_82572EI 0x10B9 498 #define E1000_DEV_ID_82573E 0x108B 499 #define E1000_DEV_ID_82573E_IAMT 0x108C 500 #define E1000_DEV_ID_82573L 0x109A 501 #define E1000_DEV_ID_82574L 0x10D3 502 #define E1000_DEV_ID_82574LA 0x10F6 503 #define E1000_DEV_ID_82546GB_2 0x109B 504 #define E1000_DEV_ID_82571EB_AT 0x10A0 505 #define E1000_DEV_ID_82571EB_AF 0x10A1 506 #define E1000_DEV_ID_82573L_PL_1 0x10B0 507 #define E1000_DEV_ID_82573V_PM 0x10B2 508 #define E1000_DEV_ID_82573E_PM 0x10B3 509 #define E1000_DEV_ID_82573L_PL_2 0x10B4 510 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3 0x10B5 511 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT 0x1096 512 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT 0x1098 513 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT 0x10BA 514 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT 0x10BB 515 #define E1000_DEV_ID_ICH8_82567V_3 0x1501 516 #define E1000_DEV_ID_ICH8_IGP_M_AMT 0x1049 517 #define E1000_DEV_ID_ICH8_IGP_AMT 0x104A 518 #define E1000_DEV_ID_ICH8_IGP_C 0x104B 519 #define E1000_DEV_ID_ICH8_IFE 0x104C 520 #define E1000_DEV_ID_ICH8_IFE_GT 0x10C4 521 #define E1000_DEV_ID_ICH8_IFE_G 0x10C5 522 #define E1000_DEV_ID_ICH8_IGP_M 0x104D 523 #define E1000_DEV_ID_ICH9_IGP_M 0x10BF 524 #define E1000_DEV_ID_ICH9_IGP_M_AMT 0x10F5 525 #define E1000_DEV_ID_ICH9_IGP_M_V 0x10CB 526 #define E1000_DEV_ID_ICH9_IGP_AMT 0x10BD 527 #define E1000_DEV_ID_ICH9_BM 0x10E5 528 #define E1000_DEV_ID_ICH9_IGP_C 0x294C 529 #define E1000_DEV_ID_ICH9_IFE 0x10C0 530 #define E1000_DEV_ID_ICH9_IFE_GT 0x10C3 531 #define E1000_DEV_ID_ICH9_IFE_G 0x10C2 532 #define E1000_DEV_ID_ICH10_R_BM_LM 0x10CC 533 #define E1000_DEV_ID_ICH10_R_BM_LF 0x10CD 534 #define E1000_DEV_ID_ICH10_R_BM_V 0x10CE 535 #define E1000_DEV_ID_ICH10_D_BM_LM 0x10DE 536 #define E1000_DEV_ID_ICH10_D_BM_LF 0x10DF 537 #define E1000_DEV_ID_ICH10_D_BM_V 0x1525 538 #define E1000_DEV_ID_PCH_M_HV_LM 0x10EA 539 #define E1000_DEV_ID_PCH_M_HV_LC 0x10EB 540 #define E1000_DEV_ID_PCH_D_HV_DM 0x10EF 541 #define E1000_DEV_ID_PCH_D_HV_DC 0x10F0 542 #define E1000_DEV_ID_PCH2_LV_LM 0x1502 543 #define E1000_DEV_ID_PCH2_LV_V 0x1503 544 #define E1000_DEV_ID_PCH_LPT_I217_LM 0x153A 545 #define E1000_DEV_ID_PCH_LPT_I217_V 0x153B 546 #define E1000_DEV_ID_PCH_LPTLP_I218_LM 0x155A 547 #define E1000_DEV_ID_PCH_LPTLP_I218_V 0x1559 548 #define E1000_DEV_ID_PCH_I218_LM2 0x15A0 549 #define E1000_DEV_ID_PCH_I218_V2 0x15A1 550 #define E1000_DEV_ID_PCH_I218_LM3 0x15A2 551 #define E1000_DEV_ID_PCH_I218_V3 0x15A3 552 #define E1000_DEV_ID_PCH_SPT_I219_LM 0x156F 553 #define E1000_DEV_ID_PCH_SPT_I219_V 0x1570 554 #define E1000_DEV_ID_PCH_SPT_I219_LM2 0x15B7 555 #define E1000_DEV_ID_PCH_SPT_I219_V2 0x15B8 556 #define E1000_DEV_ID_PCH_LBG_I219_LM3 0x15B9 557 #define E1000_DEV_ID_PCH_SPT_I219_LM4 0x15D7 558 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 559 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 560 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 561 #define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD 562 #define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE 563 #define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB 564 #define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC 565 #define E1000_DEV_ID_PCH_ICP_I219_LM8 0x15DF 566 #define E1000_DEV_ID_PCH_ICP_I219_V8 0x15E0 567 #define E1000_DEV_ID_PCH_ICP_I219_LM9 0x15E1 568 #define E1000_DEV_ID_PCH_ICP_I219_V9 0x15E2 569 #define E1000_DEV_ID_PCH_CMP_I219_LM10 0x0D4E 570 #define E1000_DEV_ID_PCH_CMP_I219_V10 0x0D4F 571 #define E1000_DEV_ID_PCH_CMP_I219_LM11 0x0D4C 572 #define E1000_DEV_ID_PCH_CMP_I219_V11 0x0D4D 573 #define E1000_DEV_ID_PCH_CMP_I219_LM12 0x0D53 574 #define E1000_DEV_ID_PCH_CMP_I219_V12 0x0D55 575 #define E1000_DEV_ID_PCH_TGP_I219_LM13 0x15FB 576 #define E1000_DEV_ID_PCH_TGP_I219_V13 0x15FC 577 #define E1000_DEV_ID_PCH_TGP_I219_LM14 0x15F9 578 #define E1000_DEV_ID_PCH_TGP_I219_V14 0x15FA 579 #define E1000_DEV_ID_PCH_TGP_I219_LM15 0x15F4 580 #define E1000_DEV_ID_PCH_TGP_I219_V15 0x15F5 581 #define E1000_DEV_ID_PCH_ADP_I219_LM16 0x1A1E 582 #define E1000_DEV_ID_PCH_ADP_I219_V16 0x1A1F 583 #define E1000_DEV_ID_PCH_ADP_I219_LM17 0x1A1C 584 #define E1000_DEV_ID_PCH_ADP_I219_V17 0x1A1D 585 #define E1000_DEV_ID_PCH_MTP_I219_LM18 0x550A 586 #define E1000_DEV_ID_PCH_MTP_I219_V18 0x550B 587 #define E1000_DEV_ID_PCH_MTP_I219_LM19 0x550C 588 #define E1000_DEV_ID_PCH_MTP_I219_V19 0x550D 589 #define E1000_DEV_ID_PCH_LNP_I219_LM20 0x550E 590 #define E1000_DEV_ID_PCH_LNP_I219_V20 0x550F 591 #define E1000_DEV_ID_PCH_LNP_I219_LM21 0x5510 592 #define E1000_DEV_ID_PCH_LNP_I219_V21 0x5511 593 #define E1000_DEV_ID_PCH_RPL_I219_LM22 0x0DC7 594 #define E1000_DEV_ID_PCH_RPL_I219_V22 0x0DC8 595 #define E1000_DEV_ID_PCH_RPL_I219_LM23 0x0DC5 596 #define E1000_DEV_ID_PCH_RPL_I219_V23 0x0DC6 597 #define E1000_DEV_ID_PCH_ARL_I219_LM24 0x57A0 598 #define E1000_DEV_ID_PCH_ARL_I219_V24 0x57A1 599 #define E1000_DEV_ID_82575EB_PT 0x10A7 600 #define E1000_DEV_ID_82575EB_PF 0x10A9 601 #define E1000_DEV_ID_82575GB_QP 0x10D6 602 #define E1000_DEV_ID_82575GB_QP_PM 0x10E2 603 #define E1000_DEV_ID_82576 0x10C9 604 #define E1000_DEV_ID_82576_FIBER 0x10E6 605 #define E1000_DEV_ID_82576_SERDES 0x10E7 606 #define E1000_DEV_ID_82576_QUAD_COPPER 0x10E8 607 #define E1000_DEV_ID_82576_NS 0x150A 608 #define E1000_DEV_ID_82583V 0x150C 609 #define E1000_DEV_ID_82576_NS_SERDES 0x1518 610 #define E1000_DEV_ID_82576_SERDES_QUAD 0x150D 611 #define E1000_DEV_ID_82580_COPPER 0x150E 612 #define E1000_DEV_ID_82580_FIBER 0x150F 613 #define E1000_DEV_ID_82580_SERDES 0x1510 614 #define E1000_DEV_ID_82580_SGMII 0x1511 615 #define E1000_DEV_ID_82580_COPPER_DUAL 0x1516 616 #define E1000_DEV_ID_82580_QUAD_FIBER 0x1527 617 #define E1000_DEV_ID_DH89XXCC_SGMII 0x0438 618 #define E1000_DEV_ID_DH89XXCC_SERDES 0x043A 619 #define E1000_DEV_ID_DH89XXCC_BACKPLANE 0x043C 620 #define E1000_DEV_ID_DH89XXCC_SFP 0x0440 621 #define E1000_DEV_ID_I350_COPPER 0x1521 622 #define E1000_DEV_ID_I350_FIBER 0x1522 623 #define E1000_DEV_ID_I350_SERDES 0x1523 624 #define E1000_DEV_ID_I350_SGMII 0x1524 625 #define E1000_DEV_ID_82576_QUAD_CU_ET2 0x1526 626 #define E1000_DEV_ID_I210_COPPER 0x1533 627 #define E1000_DEV_ID_I210_COPPER_OEM1 0x1534 628 #define E1000_DEV_ID_I210_COPPER_IT 0x1535 629 #define E1000_DEV_ID_I210_FIBER 0x1536 630 #define E1000_DEV_ID_I210_SERDES 0x1537 631 #define E1000_DEV_ID_I210_SGMII 0x1538 632 #define E1000_DEV_ID_I210_COPPER_FLASHLESS 0x157B 633 #define E1000_DEV_ID_I210_SERDES_FLASHLESS 0x157C 634 #define E1000_DEV_ID_I211_COPPER 0x1539 635 #define E1000_DEV_ID_I350_DA4 0x1546 636 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS 0x1F40 637 #define E1000_DEV_ID_I354_SGMII 0x1F41 638 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS 0x1F45 639 #define E1000_DEV_ID_EP80579_LAN_1 0x5040 640 #define E1000_DEV_ID_EP80579_LAN_2 0x5044 641 #define E1000_DEV_ID_EP80579_LAN_3 0x5048 642 #define E1000_DEV_ID_EP80579_LAN_4 0x5041 643 #define E1000_DEV_ID_EP80579_LAN_5 0x5045 644 #define E1000_DEV_ID_EP80579_LAN_6 0x5049 645 646 #define NODE_ADDRESS_SIZE 6 647 #define ETH_LENGTH_OF_ADDRESS 6 648 649 /* MAC decode size is 128K - This is the size of BAR0 */ 650 #define MAC_DECODE_SIZE (128 * 1024) 651 652 #define E1000_82542_2_0_REV_ID 2 653 #define E1000_82542_2_1_REV_ID 3 654 #define E1000_REVISION_0 0 655 #define E1000_REVISION_1 1 656 #define E1000_REVISION_2 2 657 #define E1000_REVISION_3 3 658 659 #define SPEED_10 10 660 #define SPEED_100 100 661 #define SPEED_1000 1000 662 #define HALF_DUPLEX 1 663 #define FULL_DUPLEX 2 664 665 /* The sizes (in bytes) of a ethernet packet */ 666 #define ENET_HEADER_SIZE 14 667 #define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */ 668 #define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */ 669 #define ETHERNET_FCS_SIZE 4 670 #define MAXIMUM_ETHERNET_PACKET_SIZE \ 671 (MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 672 #define MINIMUM_ETHERNET_PACKET_SIZE \ 673 (MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE) 674 #define CRC_LENGTH ETHERNET_FCS_SIZE 675 #define MAX_JUMBO_FRAME_SIZE 0x3F00 676 677 /* 802.1q VLAN Packet Sizes */ 678 #define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */ 679 680 /* Ethertype field values */ 681 #define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */ 682 #define ETHERNET_IP_TYPE 0x0800 /* IP packets */ 683 #define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */ 684 685 /* Packet Header defines */ 686 #define IP_PROTOCOL_TCP 6 687 #define IP_PROTOCOL_UDP 0x11 688 689 /* This defines the bits that are set in the Interrupt Mask 690 * Set/Read Register. Each bit is documented below: 691 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 692 * o RXSEQ = Receive Sequence Error 693 */ 694 #define POLL_IMS_ENABLE_MASK ( \ 695 E1000_IMS_RXDMT0 | \ 696 E1000_IMS_RXSEQ) 697 698 /* This defines the bits that are set in the Interrupt Mask 699 * Set/Read Register. Each bit is documented below: 700 * o RXT0 = Receiver Timer Interrupt (ring 0) 701 * o TXDW = Transmit Descriptor Written Back 702 * o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0) 703 * o RXSEQ = Receive Sequence Error 704 * o RXO = Receive Overrun 705 * o LSC = Link Status Change 706 */ 707 #define IMS_ENABLE_MASK ( \ 708 E1000_IMS_RXT0 | \ 709 E1000_IMS_TXDW | \ 710 E1000_IMS_RXDMT0 | \ 711 E1000_IMS_RXSEQ | \ 712 E1000_IMS_RXO | \ 713 E1000_IMS_LSC) 714 715 /* Additional interrupts need to be handled for em_ich8lan: 716 DSW = The FW changed the status of the DISSW bit in FWSM 717 PHYINT = The LAN connected device generates an interrupt 718 EPRST = Manageability reset event */ 719 #define IMS_ICH8LAN_ENABLE_MASK (\ 720 E1000_IMS_DSW | \ 721 E1000_IMS_PHYINT | \ 722 E1000_IMS_EPRST) 723 724 /* Number of high/low register pairs in the RAR. The RAR (Receive Address 725 * Registers) holds the directed and multicast addresses that we monitor. We 726 * reserve one of these spots for our directed address, allowing us room for 727 * E1000_RAR_ENTRIES - 1 multicast addresses. 728 */ 729 #define E1000_RAR_ENTRIES 15 730 #define E1000_RAR_ENTRIES_ICH8LAN 7 731 #define E1000_RAR_ENTRIES_82575 16 732 #define E1000_RAR_ENTRIES_82576 24 733 #define E1000_RAR_ENTRIES_82580 24 734 #define E1000_RAR_ENTRIES_I350 32 735 736 #define MIN_NUMBER_OF_DESCRIPTORS 8 737 #define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 738 739 /* Receive Descriptor */ 740 struct em_rx_desc { 741 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 742 uint16_t length; /* Length of data DMAed into data buffer */ 743 uint16_t csum; /* Packet checksum */ 744 uint8_t status; /* Descriptor status */ 745 uint8_t errors; /* Descriptor Errors */ 746 uint16_t special; 747 }; 748 749 /* Receive Descriptor - Extended */ 750 union em_rx_desc_extended { 751 struct { 752 uint64_t buffer_addr; 753 uint64_t reserved; 754 } read; 755 struct { 756 struct { 757 uint32_t mrq; /* Multiple Rx Queues */ 758 union { 759 uint32_t rss; /* RSS Hash */ 760 struct { 761 uint16_t ip_id; /* IP id */ 762 uint16_t csum; /* Packet Checksum */ 763 } csum_ip; 764 } hi_dword; 765 } lower; 766 struct { 767 uint32_t status_error; /* ext status/error */ 768 uint16_t length; 769 uint16_t vlan; /* VLAN tag */ 770 } upper; 771 } wb; /* writeback */ 772 }; 773 774 #define MAX_PS_BUFFERS 4 775 /* Receive Descriptor - Packet Split */ 776 union em_rx_desc_packet_split { 777 struct { 778 /* one buffer for protocol header(s), three data buffers */ 779 uint64_t buffer_addr[MAX_PS_BUFFERS]; 780 } read; 781 struct { 782 struct { 783 uint32_t mrq; /* Multiple Rx Queues */ 784 union { 785 uint32_t rss; /* RSS Hash */ 786 struct { 787 uint16_t ip_id; /* IP id */ 788 uint16_t csum; /* Packet Checksum */ 789 } csum_ip; 790 } hi_dword; 791 } lower; 792 struct { 793 uint32_t status_error; /* ext status/error */ 794 uint16_t length0; /* length of buffer 0 */ 795 uint16_t vlan; /* VLAN tag */ 796 } middle; 797 struct { 798 uint16_t header_status; 799 uint16_t length[3]; /* length of buffers 1-3 */ 800 } upper; 801 uint64_t reserved; 802 } wb; /* writeback */ 803 }; 804 805 /* Receive Descriptor bit definitions */ 806 #define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */ 807 #define E1000_RXD_STAT_EOP 0x02 /* End of Packet */ 808 #define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */ 809 #define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 810 #define E1000_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 811 #define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */ 812 #define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 813 #define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 814 #define E1000_RXD_STAT_IPIDV 0x200 /* IP identification valid */ 815 #define E1000_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 816 #define E1000_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 817 #define E1000_RXD_STAT_STRIPCRC 0x1000 /* CRC has been stripped */ 818 #define E1000_RXD_ERR_CE 0x01 /* CRC Error */ 819 #define E1000_RXD_ERR_SE 0x02 /* Symbol Error */ 820 #define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */ 821 #define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */ 822 #define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */ 823 #define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */ 824 #define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */ 825 #define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 826 #define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 827 #define E1000_RXD_SPC_PRI_SHIFT 13 828 #define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */ 829 #define E1000_RXD_SPC_CFI_SHIFT 12 830 831 #define E1000_RXDEXT_STATERR_CE 0x01000000 832 #define E1000_RXDEXT_STATERR_SE 0x02000000 833 #define E1000_RXDEXT_STATERR_SEQ 0x04000000 834 #define E1000_RXDEXT_STATERR_CXE 0x10000000 835 #define E1000_RXDEXT_STATERR_TCPE 0x20000000 836 #define E1000_RXDEXT_STATERR_IPE 0x40000000 837 #define E1000_RXDEXT_STATERR_RXE 0x80000000 838 839 #define E1000_RXDPS_HDRSTAT_HDRSP 0x00008000 840 #define E1000_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 841 842 /* mask to determine if packets should be dropped due to frame errors */ 843 #define E1000_RXD_ERR_FRAME_ERR_MASK ( \ 844 E1000_RXD_ERR_CE | \ 845 E1000_RXD_ERR_SE | \ 846 E1000_RXD_ERR_SEQ | \ 847 E1000_RXD_ERR_CXE | \ 848 E1000_RXD_ERR_RXE) 849 850 /* Same mask, but for extended and packet split descriptors */ 851 #define E1000_RXDEXT_ERR_FRAME_ERR_MASK ( \ 852 E1000_RXDEXT_STATERR_CE | \ 853 E1000_RXDEXT_STATERR_SE | \ 854 E1000_RXDEXT_STATERR_SEQ | \ 855 E1000_RXDEXT_STATERR_CXE | \ 856 E1000_RXDEXT_STATERR_RXE) 857 858 /* Transmit Descriptor */ 859 struct em_tx_desc { 860 uint64_t buffer_addr; /* Address of the descriptor's data buffer */ 861 union { 862 uint32_t data; 863 struct { 864 uint16_t length; /* Data buffer length */ 865 uint8_t cso; /* Checksum offset */ 866 uint8_t cmd; /* Descriptor control */ 867 } flags; 868 } lower; 869 union { 870 uint32_t data; 871 struct { 872 uint8_t status; /* Descriptor status */ 873 uint8_t css; /* Checksum start */ 874 uint16_t special; 875 } fields; 876 } upper; 877 }; 878 879 /* Transmit Descriptor bit definitions */ 880 #define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */ 881 #define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */ 882 #define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 883 #define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 884 #define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */ 885 #define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 886 #define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 887 #define E1000_TXD_CMD_RS 0x08000000 /* Report Status */ 888 #define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */ 889 #define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */ 890 #define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 891 #define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */ 892 #define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 893 #define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */ 894 #define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */ 895 #define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */ 896 #define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */ 897 #define E1000_TXD_CMD_IP 0x02000000 /* IP packet */ 898 #define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */ 899 #define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */ 900 901 /* Offload Context Descriptor */ 902 struct em_context_desc { 903 union { 904 uint32_t ip_config; 905 struct { 906 uint8_t ipcss; /* IP checksum start */ 907 uint8_t ipcso; /* IP checksum offset */ 908 uint16_t ipcse; /* IP checksum end */ 909 } ip_fields; 910 } lower_setup; 911 union { 912 uint32_t tcp_config; 913 struct { 914 uint8_t tucss; /* TCP checksum start */ 915 uint8_t tucso; /* TCP checksum offset */ 916 uint16_t tucse; /* TCP checksum end */ 917 } tcp_fields; 918 } upper_setup; 919 uint32_t cmd_and_length; /* */ 920 union { 921 uint32_t data; 922 struct { 923 uint8_t status; /* Descriptor status */ 924 uint8_t hdr_len; /* Header length */ 925 uint16_t mss; /* Maximum segment size */ 926 } fields; 927 } tcp_seg_setup; 928 }; 929 930 /* Offload data descriptor */ 931 struct em_data_desc { 932 uint64_t buffer_addr; /* Address of the descriptor's buffer address */ 933 union { 934 uint32_t data; 935 struct { 936 uint16_t length; /* Data buffer length */ 937 uint8_t typ_len_ext; /* */ 938 uint8_t cmd; /* */ 939 } flags; 940 } lower; 941 union { 942 uint32_t data; 943 struct { 944 uint8_t status; /* Descriptor status */ 945 uint8_t popts; /* Packet Options */ 946 uint16_t special; /* */ 947 } fields; 948 } upper; 949 }; 950 951 /* Filters */ 952 #define E1000_NUM_UNICAST 16 /* Unicast filter entries */ 953 #define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 954 #define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 955 956 #define E1000_NUM_UNICAST_ICH8LAN 7 957 #define E1000_MC_TBL_SIZE_ICH8LAN 32 958 959 /* Receive Address Register */ 960 struct em_rar { 961 volatile uint32_t low; /* receive address low */ 962 volatile uint32_t high; /* receive address high */ 963 }; 964 965 /* Number of entries in the Multicast Table Array (MTA). */ 966 #define E1000_NUM_MTA_REGISTERS 128 967 #define E1000_NUM_MTA_REGISTERS_ICH8LAN 32 968 969 /* IPv4 Address Table Entry */ 970 struct em_ipv4_at_entry { 971 volatile uint32_t ipv4_addr; /* IP Address (RW) */ 972 volatile uint32_t reserved; 973 }; 974 975 /* Four wakeup IP addresses are supported */ 976 #define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4 977 #define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 978 #define E1000_IP4AT_SIZE_ICH8LAN 3 979 #define E1000_IP6AT_SIZE 1 980 981 /* IPv6 Address Table Entry */ 982 struct em_ipv6_at_entry { 983 volatile uint8_t ipv6_addr[16]; 984 }; 985 986 /* Flexible Filter Length Table Entry */ 987 struct em_fflt_entry { 988 volatile uint32_t length; /* Flexible Filter Length (RW) */ 989 volatile uint32_t reserved; 990 }; 991 992 /* Flexible Filter Mask Table Entry */ 993 struct em_ffmt_entry { 994 volatile uint32_t mask; /* Flexible Filter Mask (RW) */ 995 volatile uint32_t reserved; 996 }; 997 998 /* Flexible Filter Value Table Entry */ 999 struct em_ffvt_entry { 1000 volatile uint32_t value; /* Flexible Filter Value (RW) */ 1001 volatile uint32_t reserved; 1002 }; 1003 1004 /* Four Flexible Filters are supported */ 1005 #define E1000_FLEXIBLE_FILTER_COUNT_MAX 4 1006 1007 /* Each Flexible Filter is at most 128 (0x80) bytes in length */ 1008 #define E1000_FLEXIBLE_FILTER_SIZE_MAX 128 1009 1010 #define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX 1011 #define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 1012 #define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX 1013 1014 #define E1000_DISABLE_SERDES_LOOPBACK 0x0400 1015 1016 /* Register Set. (82543, 82544) 1017 * 1018 * Registers are defined to be 32 bits and should be accessed as 32 bit values. 1019 * These registers are physically located on the NIC, but are mapped into the 1020 * host memory address space. 1021 * 1022 * RW - register is both readable and writable 1023 * RO - register is read only 1024 * WO - register is write only 1025 * R/clr - register is read only and is cleared when read 1026 * A - register array 1027 */ 1028 #define E1000_CTRL 0x00000 /* Device Control - RW */ 1029 #define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */ 1030 #define E1000_STATUS 0x00008 /* Device Status - RO */ 1031 #define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */ 1032 #define E1000_EERD 0x00014 /* EEPROM Read - RW */ 1033 #define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */ 1034 #define E1000_FLA 0x0001C /* Flash Access - RW */ 1035 #define E1000_MDIC 0x00020 /* MDI Control - RW */ 1036 #define E1000_MDICNFG 0x00E04 /* MDI Config - RW */ 1037 #define E1000_SCTL 0x00024 /* SerDes Control - RW */ 1038 #define E1000_FEXTNVM 0x00028 /* Future Extended NVM register */ 1039 #define E1000_FEXTNVM3 0x0003C /* Future Extended NVM 3 - RW */ 1040 #define E1000_FEXTNVM4 0x00024 /* Future Extended NVM 4 - RW */ 1041 #define E1000_FEXTNVM6 0x00010 /* Future Extended NVM 6 - RW */ 1042 #define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */ 1043 #define E1000_FCAH 0x0002C /* Flow Control Address High -RW */ 1044 #define E1000_FCT 0x00030 /* Flow Control Type - RW */ 1045 #define E1000_CONNSW 0x00034 /* Copper/Fiber switch control - RW */ 1046 #define E1000_VET 0x00038 /* VLAN Ether Type - RW */ 1047 #define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */ 1048 #define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */ 1049 #define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */ 1050 #define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */ 1051 #define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */ 1052 #define E1000_IAM 0x000E0 /* Interrupt Acknowledge Auto Mask */ 1053 #define E1000_RCTL 0x00100 /* RX Control - RW */ 1054 #define E1000_GPIE 0x01514 /* General Purpose Interrupt Enable - RW */ 1055 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */ 1056 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */ 1057 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */ 1058 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */ 1059 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */ 1060 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */ 1061 #define E1000_EITR(_n) (0x01680 + (0x4 * (_n))) 1062 #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */ 1063 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */ 1064 #define E1000_RDTR1 0x02820 /* RX Delay Timer (1) - RW */ 1065 #define E1000_RDBAL1 0x02900 /* RX Descriptor Base Address Low (1) - RW */ 1066 #define E1000_RDBAH1 0x02904 /* RX Descriptor Base Address High (1) - RW */ 1067 #define E1000_RDLEN1 0x02908 /* RX Descriptor Length (1) - RW */ 1068 #define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */ 1069 #define E1000_TXCW 0x00178 /* TX Configuration Word - RW */ 1070 #define E1000_RXCW 0x00180 /* RX Configuration Word - RO */ 1071 #define E1000_TCTL 0x00400 /* TX Control - RW */ 1072 #define E1000_TCTL_EXT 0x00404 /* Extended TX Control - RW */ 1073 #define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */ 1074 #define E1000_TBT 0x00448 /* TX Burst Timer - RW */ 1075 #define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */ 1076 #define E1000_LEDCTL 0x00E00 /* LED Control - RW */ 1077 #define E1000_EXTCNF_CTRL 0x00F00 /* Extended Configuration Control */ 1078 #define E1000_EXTCNF_SIZE 0x00F08 /* Extended Configuration Size */ 1079 #define E1000_PHY_CTRL 0x00F10 /* PHY Control Register in CSR */ 1080 #define FEXTNVM_SW_CONFIG 1 1081 #define FEXTNVM_SW_CONFIG_ICH8M (1 << 27) /* Bit redefined for ICH8M :/ */ 1082 #define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */ 1083 #define E1000_PBS 0x01008 /* Packet Buffer Size */ 1084 #define E1000_IOSFPC 0x00F28 /* TX corrupted data */ 1085 #define E1000_EEMNGCTL 0x01010 /* MNG EEprom Control */ 1086 #define E1000_FLASH_UPDATES 1000 1087 #define E1000_EEARBC 0x01024 /* EEPROM Auto Read Bus Control */ 1088 #define E1000_FLASHT 0x01028 /* FLASH Timer Register */ 1089 #define E1000_EEWR 0x0102C /* EEPROM Write Register - RW */ 1090 #define E1000_FLSWCTL 0x01030 /* FLASH control register */ 1091 #define E1000_FLSWDATA 0x01034 /* FLASH data register */ 1092 #define E1000_FLSWCNT 0x01038 /* FLASH Access Counter */ 1093 #define E1000_FLOP 0x0103C /* FLASH Opcode Register */ 1094 #define E1000_I2CCMD 0x01028 /* SFPI2C Command Register - RW */ 1095 #define E1000_ERT 0x02008 /* Early Rx Threshold - RW */ 1096 #define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */ 1097 #define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */ 1098 #define E1000_PSRCTL 0x02170 /* Packet Split Receive Control - RW */ 1099 /* RX Descriptor Base Address Low - RW */ 1100 #define E1000_RDBAL(_n) ((_n) < 4 ? (0x02800 + ((_n) * 0x100)) : \ 1101 (0x0C000 + ((_n) * 0x40))) 1102 /* RX Descriptor Base Address High - RW */ 1103 #define E1000_RDBAH(_n) ((_n) < 4 ? (0x02804 + ((_n) * 0x100)) : \ 1104 (0x0C004 + ((_n) * 0x40))) 1105 /* RX Descriptor Length - RW */ 1106 #define E1000_RDLEN(_n) ((_n) < 4 ? (0x02808 + ((_n) * 0x100)) : \ 1107 (0x0C008 + ((_n) * 0x40))) 1108 /* Split and Replication Receive CTRL - RW */ 1109 #define E1000_SRRCTL(_n) ((_n) < 4 ? (0x0280C + ((_n) * 0x100)) : \ 1110 (0x0C00C + ((_n) * 0x40))) 1111 /* RX Descriptor Head - RW */ 1112 #define E1000_RDH(_n) ((_n) < 4 ? (0x02810 + ((_n) * 0x100)) : \ 1113 (0x0C010 + ((_n) * 0x40))) 1114 /* RX Descriptor Tail - RW */ 1115 #define E1000_RDT(_n) ((_n) < 4 ? (0x02818 + ((_n) * 0x100)) : \ 1116 (0x0C018 + ((_n) * 0x40))) 1117 #define E1000_RDTR 0x02820 /* RX Delay Timer - RW */ 1118 #define E1000_RDBAL0 E1000_RDBAL /* RX Desc Base Address Low (0) - RW */ 1119 #define E1000_RDBAH0 E1000_RDBAH /* RX Desc Base Address High (0) - RW */ 1120 #define E1000_RDLEN0 E1000_RDLEN /* RX Desc Length (0) - RW */ 1121 #define E1000_RDTR0 E1000_RDTR /* RX Delay Timer (0) - RW */ 1122 #define E1000_RXDCTL(_n) ((_n) < 4 ? (0x02828 + ((_n) * 0x100)) : \ 1123 (0x0C028 + ((_n) * 0x40))) 1124 #define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */ 1125 #define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */ 1126 #define E1000_RAID 0x02C08 /* Receive Ack Interrupt Delay - RW */ 1127 #define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */ 1128 #define E1000_KABGTXD 0x03004 /* AFE Band Gap Transmit Ref Data */ 1129 #define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */ 1130 #define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */ 1131 #define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */ 1132 #define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */ 1133 #define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */ 1134 /* TX Descriptor Base Address Low - RW */ 1135 #define E1000_TDBAL(_n) ((_n) < 4 ? (0x03800 + ((_n) * 0x100)) : \ 1136 (0x0E000 + ((_n) * 0x40))) 1137 /* TX Descriptor Base Address High - RW */ 1138 #define E1000_TDBAH(_n) ((_n) < 4 ? (0x03804 + ((_n) * 0x100)) : \ 1139 (0x0E004 + ((_n) * 0x40))) 1140 /* TX Descriptor Length - RW */ 1141 #define E1000_TDLEN(_n) ((_n) < 4 ? (0x03808 + ((_n) * 0x100)) : \ 1142 (0x0E008 + ((_n) * 0x40))) 1143 /* TX Descriptor Head - RW */ 1144 #define E1000_TDH(_n) ((_n) < 4 ? (0x03810 + ((_n) * 0x100)) : \ 1145 (0x0E010 + ((_n) * 0x40))) 1146 /* TX Descriptor Tail - RW */ 1147 #define E1000_TDT(_n) ((_n) < 4 ? (0x03818 + ((_n) * 0x100)) : \ 1148 (0x0E018 + ((_n) * 0x40))) 1149 #define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */ 1150 #define E1000_TXDCTL(_n) ((_n) < 4 ? (0x03828 + ((_n) * 0x100)) : \ 1151 (0x0E028 + ((_n) * 0x40))) 1152 #define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */ 1153 #define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */ 1154 #define E1000_TARC0 0x03840 /* TX Arbitration Count (0) */ 1155 #define E1000_TDBAL1 0x03900 /* TX Desc Base Address Low (1) - RW */ 1156 #define E1000_TDBAH1 0x03904 /* TX Desc Base Address High (1) - RW */ 1157 #define E1000_TDLEN1 0x03908 /* TX Desc Length (1) - RW */ 1158 #define E1000_TDH1 0x03910 /* TX Desc Head (1) - RW */ 1159 #define E1000_TDT1 0x03918 /* TX Desc Tail (1) - RW */ 1160 #define E1000_TARC1 0x03940 /* TX Arbitration Count (1) */ 1161 #define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */ 1162 #define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */ 1163 #define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */ 1164 #define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */ 1165 #define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */ 1166 #define E1000_SCC 0x04014 /* Single Collision Count - R/clr */ 1167 #define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */ 1168 #define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */ 1169 #define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */ 1170 #define E1000_COLC 0x04028 /* Collision Count - R/clr */ 1171 #define E1000_DC 0x04030 /* Defer Count - R/clr */ 1172 #define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */ 1173 #define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */ 1174 #define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */ 1175 #define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */ 1176 #define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */ 1177 #define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */ 1178 #define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */ 1179 #define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */ 1180 #define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */ 1181 #define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */ 1182 #define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */ 1183 #define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */ 1184 #define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */ 1185 #define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */ 1186 #define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */ 1187 #define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */ 1188 #define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */ 1189 #define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */ 1190 #define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */ 1191 #define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */ 1192 #define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */ 1193 #define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */ 1194 #define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */ 1195 #define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */ 1196 #define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */ 1197 #define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */ 1198 #define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */ 1199 #define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */ 1200 #define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */ 1201 #define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */ 1202 #define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */ 1203 #define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */ 1204 #define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */ 1205 #define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */ 1206 #define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */ 1207 #define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */ 1208 #define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */ 1209 #define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */ 1210 #define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */ 1211 #define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */ 1212 #define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */ 1213 #define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */ 1214 #define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */ 1215 #define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */ 1216 #define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */ 1217 #define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */ 1218 #define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */ 1219 #define E1000_IAC 0x04100 /* Interrupt Assertion Count */ 1220 #define E1000_RPTHC 0x04104 /* CONFLICT Rx Packets to Host Count */ 1221 #define E1000_ICRXPTC 0x04104 /* Interrupt Cause Rx Packet Timer Expire Count */ 1222 #define E1000_ICRXATC 0x04108 /* Interrupt Cause Rx Absolute Timer Expire Count */ 1223 #define E1000_ICTXPTC 0x0410C /* Interrupt Cause Tx Packet Timer Expire Count */ 1224 #define E1000_ICTXATC 0x04110 /* Interrupt Cause Tx Absolute Timer Expire Count */ 1225 #define E1000_ICTXQEC 0x04118 /* Interrupt Cause Tx Queue Empty Count */ 1226 #define E1000_ICTXQMTC 0x0411C /* Interrupt Cause Tx Queue Minimum Threshold Count */ 1227 #define E1000_ICRXDMTC 0x04120 /* Interrupt Cause Rx Descriptor Minimum Threshold Count */ 1228 #define E1000_ICRXOC 0x04124 /* Interrupt Cause Receiver Overrun Count */ 1229 #define E1000_SDPC 0x041A4 /* Switch Drop Packet Count */ 1230 #define E1000_PCS_CFG0 0x04200 /* PCS Configuration 0 - RW */ 1231 #define E1000_PCS_LCTL 0x04208 /* PCS Link Control - RW */ 1232 #define E1000_PCS_LSTAT 0x0420C /* PCS Link Status - RO */ 1233 #define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */ 1234 #define E1000_RFCTL 0x05008 /* Receive Filter Control*/ 1235 #define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */ 1236 #define E1000_RA 0x05400 /* Receive Address - RW Array */ 1237 #define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */ 1238 #define E1000_WUC 0x05800 /* Wakeup Control - RW */ 1239 #define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */ 1240 #define E1000_WUS 0x05810 /* Wakeup Status - RO */ 1241 #define E1000_MANC 0x05820 /* Management Control - RW */ 1242 #define E1000_IPAV 0x05838 /* IP Address Valid - RW */ 1243 #define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */ 1244 #define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */ 1245 #define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */ 1246 #define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */ 1247 #define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */ 1248 #define E1000_FCRTV_PCH 0x05F40 /* PCH Flow Control Refresh Timer Value */ 1249 #define E1000_CRC_OFFSET 0x05F50 /* CRC Offset Register */ 1250 #define E1000_HOST_IF 0x08800 /* Host Interface */ 1251 #define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */ 1252 #define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */ 1253 1254 #define E1000_KUMCTRLSTA 0x00034 /* MAC-PHY interface - RW */ 1255 #define E1000_MDPHYA 0x0003C /* PHY address - RW */ 1256 #define E1000_MANC2H 0x05860 /* Management Control To Host - RW */ 1257 #define E1000_SW_FW_SYNC 0x05B5C /* Software-Firmware Synchronization - RW */ 1258 1259 #define E1000_GCR 0x05B00 /* PCI-Ex Control */ 1260 #define E1000_GSCL_1 0x05B10 /* PCI-Ex Statistic Control #1 */ 1261 #define E1000_GSCL_2 0x05B14 /* PCI-Ex Statistic Control #2 */ 1262 #define E1000_GSCL_3 0x05B18 /* PCI-Ex Statistic Control #3 */ 1263 #define E1000_GSCL_4 0x05B1C /* PCI-Ex Statistic Control #4 */ 1264 #define E1000_FACTPS 0x05B30 /* Function Active and Power State to MNG */ 1265 #define E1000_SWSM 0x05B50 /* SW Semaphore */ 1266 #define E1000_H2ME E1000_SWSM /* Host to ME */ 1267 #define E1000_FWSM 0x05B54 /* FW Semaphore */ 1268 #define E1000_FFLT_DBG 0x05F04 /* Debug Register */ 1269 #define E1000_HICR 0x08F00 /* Host Interface Control */ 1270 1271 /* RSS registers */ 1272 #define E1000_CPUVEC 0x02C10 /* CPU Vector Register - RW */ 1273 #define E1000_MRQC 0x05818 /* Multiple Receive Control - RW */ 1274 #define E1000_RETA(_i) (0x05C00 + ((_i) * 4))/* Redirection Table - RW Array */ 1275 #define E1000_RSSRK(_i) (0x05C80 + ((_i) * 4))/* RSS Random Key - RW Array */ 1276 #define E1000_RSSIM 0x05864 /* RSS Interrupt Mask */ 1277 #define E1000_RSSIR 0x05868 /* RSS Interrupt Request */ 1278 1279 /* BMC2OS Registers */ 1280 #define E1000_B2OSPC 0x8FE0 1281 #define E1000_B2OGPRC 0x4158 1282 #define E1000_O2BGPTC 0x8FE4 1283 #define E1000_O2BSPC 0x415C 1284 1285 /* Per Queue Packets Count */ 1286 #define E1000_PQGPRC(_i) (0x010010 + ((_i) * 0x100)) 1287 #define E1000_PQGPTC(_i) (0x010014 + ((_i) * 0x100)) 1288 1289 /* Phy Power Management (i210 8.27.2 pag 542) */ 1290 #define E1000_PHPM 0x0E14 1291 #define E1000_PHPM_SPD_EN (1 << 0) 1292 #define E1000_PHPM_D0LPLU (1 << 1) 1293 #define E1000_PHPM_LPLU (1 << 2) 1294 #define E1000_PHPM_DIS_1000_ND0 (1 << 3) 1295 #define E1000_PHPM_LINK_ED (1 << 4) 1296 #define E1000_PHPM_GOLINK_DISC (1 << 5) 1297 #define E1000_PHPM_DIS_1000 (1 << 6) 1298 #define E1000_PHPM_SPD_B2B_EN (1 << 7) 1299 #define E1000_PHPM_RST_COMPL (1 << 8) 1300 #define E1000_PHPM_DIS_100_ND0 (1 << 9) 1301 1302 /* Energy Efficient Ethernet "EEE" registers */ 1303 #define E1000_IPCNFG 0x0E38 /* Internal PHY Configuration */ 1304 #define E1000_LTRC 0x01A0 /* Latency Tolerance Reporting Control */ 1305 #define E1000_EEER 0x0E30 /* Energy Efficient Ethernet "EEE" */ 1306 #define E1000_EEE_SU 0x0E34 /* EEE Setup */ 1307 #define E1000_TLPIC 0x4148 /* EEE Tx LPI Count - TLPIC */ 1308 #define E1000_RLPIC 0x414C /* EEE Rx LPI Count - RLPIC */ 1309 1310 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_MASK 0x0C000000 1311 #define E1000_FEXTNVM3_PHY_CFG_COUNTER_50MSEC 0x08000000 1312 1313 #define E1000_FEXTNVM4_BEACON_DURATION_MASK 0x7 1314 #define E1000_FEXTNVM4_BEACON_DURATION_8USEC 0x7 1315 #define E1000_FEXTNVM4_BEACON_DURATION_16USEC 0x3 1316 1317 #define E1000_FEXTNVM6_REQ_PLL_CLK 0x00000100 1318 #define E1000_FEXTNVM6_ENABLE_K1_ENTRY_CONDITION 0x00000200 1319 1320 /* Statistics counters collected by the MAC */ 1321 struct em_hw_stats { 1322 uint64_t crcerrs; 1323 uint64_t algnerrc; 1324 uint64_t symerrs; 1325 uint64_t rxerrc; 1326 uint64_t mpc; 1327 uint64_t scc; 1328 uint64_t ecol; 1329 uint64_t mcc; 1330 uint64_t latecol; 1331 uint64_t colc; 1332 uint64_t dc; 1333 uint64_t tncrs; 1334 uint64_t sec; 1335 uint64_t cexterr; 1336 uint64_t rlec; 1337 uint64_t xonrxc; 1338 uint64_t xontxc; 1339 uint64_t xoffrxc; 1340 uint64_t xofftxc; 1341 uint64_t fcruc; 1342 uint64_t prc64; 1343 uint64_t prc127; 1344 uint64_t prc255; 1345 uint64_t prc511; 1346 uint64_t prc1023; 1347 uint64_t prc1522; 1348 uint64_t gprc; 1349 uint64_t bprc; 1350 uint64_t mprc; 1351 uint64_t gptc; 1352 uint64_t gorcl; 1353 uint64_t gorch; 1354 uint64_t gotcl; 1355 uint64_t gotch; 1356 uint64_t rnbc; 1357 uint64_t ruc; 1358 uint64_t rfc; 1359 uint64_t roc; 1360 uint64_t rjc; 1361 uint64_t mgprc; 1362 uint64_t mgpdc; 1363 uint64_t mgptc; 1364 uint64_t torl; 1365 uint64_t torh; 1366 uint64_t totl; 1367 uint64_t toth; 1368 uint64_t tpr; 1369 uint64_t tpt; 1370 uint64_t ptc64; 1371 uint64_t ptc127; 1372 uint64_t ptc255; 1373 uint64_t ptc511; 1374 uint64_t ptc1023; 1375 uint64_t ptc1522; 1376 uint64_t mptc; 1377 uint64_t bptc; 1378 uint64_t tsctc; 1379 uint64_t tsctfc; 1380 uint64_t iac; 1381 uint64_t icrxptc; 1382 uint64_t icrxatc; 1383 uint64_t ictxptc; 1384 uint64_t ictxatc; 1385 uint64_t ictxqec; 1386 uint64_t ictxqmtc; 1387 uint64_t icrxdmtc; 1388 uint64_t icrxoc; 1389 uint64_t sdpc; 1390 uint64_t mngpdc; 1391 uint64_t mngptc; 1392 uint64_t mngprc; 1393 uint64_t b2ospc; 1394 uint64_t o2bgptc; 1395 uint64_t b2ogprc; 1396 uint64_t o2bspc; 1397 uint64_t rpthc; 1398 }; 1399 1400 /* Structure containing variables used by the shared code (em_hw.c) */ 1401 struct em_hw { 1402 uint8_t *hw_addr; 1403 uint8_t *flash_address; 1404 em_mac_type mac_type; 1405 em_phy_type phy_type; 1406 uint32_t phy_init_script; 1407 em_media_type media_type; 1408 void *back; 1409 struct em_shadow_ram *eeprom_shadow_ram; 1410 uint32_t flash_bank_size; 1411 uint32_t flash_base_addr; 1412 uint32_t fc; 1413 em_bus_speed bus_speed; 1414 em_bus_width bus_width; 1415 em_bus_type bus_type; 1416 struct em_eeprom_info eeprom; 1417 em_ms_type master_slave; 1418 em_ms_type original_master_slave; 1419 em_ffe_config ffe_config_state; 1420 uint32_t asf_firmware_present; 1421 uint32_t eeprom_semaphore_present; 1422 uint32_t swfw_sync_present; 1423 uint32_t swfwhw_semaphore_present; 1424 unsigned long io_base; 1425 uint32_t phy_id; 1426 uint32_t phy_revision; 1427 uint32_t phy_addr; 1428 uint32_t original_fc; 1429 uint32_t txcw; 1430 uint32_t autoneg_failed; 1431 uint32_t max_frame_size; 1432 uint32_t min_frame_size; 1433 uint32_t mc_filter_type; 1434 uint32_t num_mc_addrs; 1435 uint32_t collision_delta; 1436 uint32_t tx_packet_delta; 1437 uint32_t ledctl_default; 1438 uint32_t ledctl_mode1; 1439 uint32_t ledctl_mode2; 1440 boolean_t tx_pkt_filtering; 1441 struct em_host_mng_dhcp_cookie mng_cookie; 1442 uint16_t phy_spd_default; 1443 uint16_t autoneg_advertised; 1444 uint16_t pci_cmd_word; 1445 uint16_t fc_high_water; 1446 uint16_t fc_low_water; 1447 uint16_t fc_pause_time; 1448 uint16_t current_ifs_val; 1449 uint16_t ifs_min_val; 1450 uint16_t ifs_max_val; 1451 uint16_t ifs_step_size; 1452 uint16_t ifs_ratio; 1453 uint16_t device_id; 1454 uint16_t vendor_id; 1455 uint16_t subsystem_id; 1456 uint16_t subsystem_vendor_id; 1457 uint8_t revision_id; 1458 uint8_t autoneg; 1459 uint8_t mdix; 1460 uint8_t forced_speed_duplex; 1461 uint8_t wait_autoneg_complete; 1462 uint8_t dma_fairness; 1463 uint8_t mac_addr[NODE_ADDRESS_SIZE]; 1464 uint8_t perm_mac_addr[NODE_ADDRESS_SIZE]; 1465 boolean_t disable_polarity_correction; 1466 boolean_t speed_downgraded; 1467 em_smart_speed smart_speed; 1468 em_dsp_config dsp_config_state; 1469 boolean_t get_link_status; 1470 boolean_t serdes_link_down; 1471 boolean_t tbi_compatibility_en; 1472 boolean_t tbi_compatibility_on; 1473 boolean_t laa_is_present; 1474 boolean_t phy_reset_disable; 1475 boolean_t initialize_hw_bits_disable; 1476 boolean_t fc_send_xon; 1477 boolean_t fc_strict_ieee; 1478 boolean_t report_tx_early; 1479 boolean_t adaptive_ifs; 1480 boolean_t ifs_params_forced; 1481 boolean_t in_ifs_mode; 1482 boolean_t mng_reg_access_disabled; 1483 boolean_t leave_av_bit_off; 1484 boolean_t kmrn_lock_loss_workaround_disabled; 1485 boolean_t icp_xxxx_is_link_up; 1486 uint32_t icp_xxxx_port_num; 1487 struct gcu_softc * gcu; 1488 uint8_t bus_func; 1489 uint16_t swfw; 1490 boolean_t eee_enable; 1491 int sw_flag; 1492 boolean_t sgmii_active; 1493 }; 1494 1495 #define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */ 1496 #define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */ 1497 #define E1000_EEPROM_RW_REG_DATA 16 /* Offset to data in EEPROM read/write registers */ 1498 #define E1000_EEPROM_RW_REG_DONE 2 /* Offset to READ/WRITE done bit */ 1499 #define E1000_EEPROM_RW_REG_START 1 /* First bit for telling part to start operation */ 1500 #define E1000_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 1501 #define E1000_EEPROM_POLL_WRITE 1 /* Flag for polling for write complete */ 1502 #define E1000_EEPROM_POLL_READ 0 /* Flag for polling for read complete */ 1503 /* Register Bit Masks */ 1504 /* Device Control */ 1505 #define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */ 1506 #define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */ 1507 #define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */ 1508 #define E1000_CTRL_GIO_MASTER_DISABLE 0x00000004 /*Blocks new Master requests */ 1509 #define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */ 1510 #define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */ 1511 #define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */ 1512 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */ 1513 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */ 1514 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */ 1515 #define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */ 1516 #define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */ 1517 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */ 1518 #define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */ 1519 #define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */ 1520 #define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */ 1521 #define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */ 1522 #define E1000_CTRL_D_UD_EN 0x00002000 /* Dock/Undock enable */ 1523 #define E1000_CTRL_D_UD_POLARITY 0x00004000 /* Defined polarity of Dock/Undock indication in SDP[0] */ 1524 #define E1000_CTRL_FORCE_PHY_RESET 0x00008000 /* Reset both PHY ports, through PHYRST_N pin */ 1525 #define E1000_CTRL_LANPHYPC_OVERRIDE 0x00010000 /* SW control of LANPHYPC */ 1526 #define E1000_CTRL_LANPHYPC_VALUE 0x00020000 /* SW value of LANPHYPC */ 1527 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */ 1528 #define E1000_CTRL_EXT_PHYPDEN 0x00100000 1529 #define E1000_I2CCMD_REG_ADDR_SHIFT 16 1530 #define E1000_I2CCMD_PHY_ADDR_SHIFT 24 1531 #define E1000_I2CCMD_OPCODE_READ 0x08000000 1532 #define E1000_I2CCMD_OPCODE_WRITE 0x00000000 1533 #define E1000_I2CCMD_READY 0x20000000 1534 #define E1000_I2CCMD_ERROR 0x80000000 1535 #define E1000_I2CCMD_SFP_DATA_ADDR(a) (0x0000 + (a)) 1536 #define E1000_I2CCMD_SFP_DIAG_ADDR(a) (0x0100 + (a)) 1537 #define E1000_MAX_SGMII_PHY_REG_ADDR 255 1538 #define E1000_I2CCMD_PHY_TIMEOUT 200 1539 1540 #define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */ 1541 #define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */ 1542 #define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */ 1543 #define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */ 1544 #define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */ 1545 #define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */ 1546 #define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */ 1547 #define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */ 1548 #define E1000_CTRL_RST 0x04000000 /* Global reset */ 1549 #define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */ 1550 #define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */ 1551 #define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */ 1552 #define E1000_CTRL_DEV_RST 0x20000000 /* Device Reset */ 1553 #define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */ 1554 #define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */ 1555 #define E1000_CTRL_SW2FW_INT 0x02000000 /* Initiate an interrupt to manageability engine */ 1556 #define E1000_CTRL_I2C_ENA 0x02000000 /* I2C enable */ 1557 1558 #define E1000_CONNSW_ENRGSRC 0x4 1559 #define E1000_PCS_CFG_PCS_EN 8 1560 #define E1000_PCS_LCTL_FSV_1000 4 1561 #define E1000_PCS_LCTL_FDV_FULL 8 1562 #define E1000_PCS_LCTL_FSD 0x10 1563 #define E1000_PCS_LCTL_FORCE_FCTRL 0x80 1564 1565 #define E1000_PCS_LSTS_LINK_OK 0x01 1566 #define E1000_PCS_LSTS_SPEED_100 0x02 1567 #define E1000_PCS_LSTS_SPEED_1000 0x04 1568 #define E1000_PCS_LSTS_DUPLEX_FULL 0x08 1569 #define E1000_PCS_LSTS_SYNK_OK 0x10 1570 1571 /* Device Status */ 1572 #define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */ 1573 #define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */ 1574 #define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */ 1575 #define E1000_STATUS_FUNC_SHIFT 2 1576 #define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */ 1577 #define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */ 1578 #define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */ 1579 #define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */ 1580 #define E1000_STATUS_SPEED_MASK 0x000000C0 1581 #define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */ 1582 #define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */ 1583 #define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */ 1584 #define E1000_STATUS_LAN_INIT_DONE 0x00000200 /* Lan Init Completion 1585 by EEPROM/Flash */ 1586 #define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */ 1587 #define E1000_STATUS_DOCK_CI 0x00000800 /* Change in Dock/Undock state. Clear on write '0'. */ 1588 #define E1000_STATUS_GIO_MASTER_ENABLE 0x00080000 /* Status of Master requests. */ 1589 #define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */ 1590 #define E1000_STATUS_PCI66 0x00000800 /* In 66MHz slot */ 1591 #define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */ 1592 #define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */ 1593 #define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */ 1594 #define E1000_STATUS_BMC_SKU_0 0x00100000 /* BMC USB redirect disabled */ 1595 #define E1000_STATUS_DEV_RST_SET 0x00100000 1596 #define E1000_STATUS_BMC_SKU_1 0x00200000 /* BMC SRAM disabled */ 1597 #define E1000_STATUS_BMC_SKU_2 0x00400000 /* BMC SDRAM disabled */ 1598 #define E1000_STATUS_BMC_CRYPTO 0x00800000 /* BMC crypto disabled */ 1599 #define E1000_STATUS_BMC_LITE 0x01000000 /* BMC external code execution disabled */ 1600 #define E1000_STATUS_RGMII_ENABLE 0x02000000 /* RGMII disabled */ 1601 #define E1000_STATUS_FUSE_8 0x04000000 1602 #define E1000_STATUS_FUSE_9 0x08000000 1603 #define E1000_STATUS_SERDES0_DIS 0x10000000 /* SERDES disabled on port 0 */ 1604 #define E1000_STATUS_SERDES1_DIS 0x20000000 /* SERDES disabled on port 1 */ 1605 1606 /* Constants used to interpret the masked PCI-X bus speed. */ 1607 #define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */ 1608 #define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */ 1609 #define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */ 1610 1611 /* EEPROM/Flash Control */ 1612 #define E1000_EECD_SK 0x00000001 /* EEPROM Clock */ 1613 #define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */ 1614 #define E1000_EECD_DI 0x00000004 /* EEPROM Data In */ 1615 #define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */ 1616 #define E1000_EECD_FWE_MASK 0x00000030 1617 #define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */ 1618 #define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */ 1619 #define E1000_EECD_FWE_SHIFT 4 1620 #define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */ 1621 #define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */ 1622 #define E1000_EECD_PRES 0x00000100 /* EEPROM Present */ 1623 #define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */ 1624 #define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type 1625 * (0-small, 1-large) */ 1626 #define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */ 1627 #ifndef E1000_EEPROM_GRANT_ATTEMPTS 1628 #define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */ 1629 #endif 1630 #define E1000_EECD_AUTO_RD 0x00000200 /* EEPROM Auto Read done */ 1631 #define E1000_EECD_SIZE_EX_MASK 0x00007800 /* EEprom Size */ 1632 #define E1000_EECD_SIZE_EX_SHIFT 11 1633 #define E1000_EECD_NVADDS 0x00018000 /* NVM Address Size */ 1634 #define E1000_EECD_SELSHAD 0x00020000 /* Select Shadow RAM */ 1635 #define E1000_EECD_INITSRAM 0x00040000 /* Initialize Shadow RAM */ 1636 #define E1000_EECD_FLUPD 0x00080000 /* Update FLASH */ 1637 #define E1000_EECD_AUPDEN 0x00100000 /* Enable Autonomous FLASH update */ 1638 #define E1000_EECD_SHADV 0x00200000 /* Shadow RAM Data Valid */ 1639 #define E1000_EECD_SEC1VAL 0x00400000 /* Sector One Valid */ 1640 #define E1000_EECD_SEC1VAL_VALID_MASK (E1000_EECD_AUTO_RD | E1000_EECD_PRES) 1641 #define E1000_EECD_SECVAL_SHIFT 22 1642 #define E1000_STM_OPCODE 0xDB00 1643 #define E1000_HICR_FW_RESET 0xC0 1644 1645 #define E1000_SHADOW_RAM_WORDS 2048 1646 #define E1000_ICH_NVM_SIG_WORD 0x13 1647 #define E1000_ICH_NVM_SIG_MASK 0xC000 1648 #define E1000_ICH_NVM_VALID_SIG_MASK 0xC0 1649 #define E1000_ICH_NVM_SIG_VALUE 0x80 1650 1651 /* EEPROM Read */ 1652 #define E1000_EERD_START 0x00000001 /* Start Read */ 1653 #define E1000_EERD_DONE 0x00000010 /* Read Done */ 1654 #define E1000_EERD_ADDR_SHIFT 8 1655 #define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */ 1656 #define E1000_EERD_DATA_SHIFT 16 1657 #define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */ 1658 1659 /* SPI EEPROM Status Register */ 1660 #define EEPROM_STATUS_RDY_SPI 0x01 1661 #define EEPROM_STATUS_WEN_SPI 0x02 1662 #define EEPROM_STATUS_BP0_SPI 0x04 1663 #define EEPROM_STATUS_BP1_SPI 0x08 1664 #define EEPROM_STATUS_WPEN_SPI 0x80 1665 1666 /* Extended Device Control */ 1667 #define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */ 1668 #define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */ 1669 #define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN 1670 #define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */ 1671 #define E1000_CTRL_EXT_LPCD 0x00000004 /* LCD Power Cycle Done */ 1672 #define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */ 1673 #define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Definable Pin 4 */ 1674 #define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Definable Pin 5 */ 1675 #define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA 1676 #define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Definable Pin 6 */ 1677 #define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Definable Pin 7 */ 1678 #define E1000_CTRL_EXT_SDP3_DATA 0x00000080 /* Value of SW Definable Pin 3 */ 1679 #define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */ 1680 #define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */ 1681 #define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */ 1682 #define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */ 1683 #define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */ 1684 #define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */ 1685 #define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */ 1686 #define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */ 1687 #define E1000_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 1688 #define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000 1689 #define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000 1690 #define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000 1691 #define E1000_CTRL_EXT_LINK_MODE_KMRN 0x00000000 1692 #define E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES 0x00C00000 1693 #define E1000_CTRL_EXT_LINK_MODE_1000BASE_KX 0x00400000 1694 #define E1000_CTRL_EXT_LINK_MODE_SGMII 0x00800000 1695 #define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000 1696 #define E1000_CTRL_EXT_WR_WMARK_256 0x00000000 1697 #define E1000_CTRL_EXT_WR_WMARK_320 0x01000000 1698 #define E1000_CTRL_EXT_WR_WMARK_384 0x02000000 1699 #define E1000_CTRL_EXT_WR_WMARK_448 0x03000000 1700 #define E1000_CTRL_EXT_EXT_VLAN 0x04000000 1701 #define E1000_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1702 #define E1000_CTRL_EXT_IAME 0x08000000 /* Interrupt acknowledge Auto-mask */ 1703 #define E1000_CTRL_EXT_INT_TIMER_CLR 0x20000000 /* Clear Interrupt timers after IMS clear */ 1704 #define E1000_CRTL_EXT_PB_PAREN 0x01000000 /* packet buffer parity error detection enabled */ 1705 #define E1000_CTRL_EXT_DF_PAREN 0x02000000 /* descriptor FIFO parity error detection enable */ 1706 #define E1000_CTRL_EXT_GHOST_PAREN 0x40000000 1707 1708 /* MDI Control */ 1709 #define E1000_MDIC_DATA_MASK 0x0000FFFF 1710 #define E1000_MDIC_REG_MASK 0x001F0000 1711 #define E1000_MDIC_REG_SHIFT 16 1712 #define E1000_MDIC_PHY_MASK 0x03E00000 1713 #define E1000_MDIC_PHY_SHIFT 21 1714 #define E1000_MDIC_OP_WRITE 0x04000000 1715 #define E1000_MDIC_OP_READ 0x08000000 1716 #define E1000_MDIC_READY 0x10000000 1717 #define E1000_MDIC_INT_EN 0x20000000 1718 #define E1000_MDIC_ERROR 0x40000000 1719 #define E1000_MDIC_DEST 0x80000000 1720 1721 #define E1000_KUMCTRLSTA_MASK 0x0000FFFF 1722 #define E1000_KUMCTRLSTA_OFFSET 0x001F0000 1723 #define E1000_KUMCTRLSTA_OFFSET_SHIFT 16 1724 #define E1000_KUMCTRLSTA_REN 0x00200000 1725 1726 #define E1000_KUMCTRLSTA_OFFSET_FIFO_CTRL 0x00000000 1727 #define E1000_KUMCTRLSTA_OFFSET_CTRL 0x00000001 1728 #define E1000_KUMCTRLSTA_OFFSET_INB_CTRL 0x00000002 1729 #define E1000_KUMCTRLSTA_OFFSET_DIAG 0x00000003 1730 #define E1000_KUMCTRLSTA_OFFSET_TIMEOUTS 0x00000004 1731 #define E1000_KUMCTRLSTA_OFFSET_INB_PARAM 0x00000009 1732 #define E1000_KUMCTRLSTA_OFFSET_HD_CTRL 0x00000010 1733 #define E1000_KUMCTRLSTA_OFFSET_M2P_SERDES 0x0000001E 1734 #define E1000_KUMCTRLSTA_OFFSET_M2P_MODES 0x0000001F 1735 1736 /* FIFO Control */ 1737 #define E1000_KUMCTRLSTA_FIFO_CTRL_RX_BYPASS 0x00000008 1738 #define E1000_KUMCTRLSTA_FIFO_CTRL_TX_BYPASS 0x00000800 1739 1740 /* In-Band Control */ 1741 #define E1000_KUMCTRLSTA_INB_CTRL_LINK_STATUS_TX_TIMEOUT_DEFAULT 0x00000500 1742 #define E1000_KUMCTRLSTA_INB_CTRL_DIS_PADDING 0x00000010 1743 1744 /* Half-Duplex Control */ 1745 #define E1000_KUMCTRLSTA_HD_CTRL_10_100_DEFAULT 0x00000004 1746 #define E1000_KUMCTRLSTA_HD_CTRL_1000_DEFAULT 0x00000000 1747 1748 #define E1000_KUMCTRLSTA_OFFSET_K0S_CTRL 0x0000001E 1749 1750 #define E1000_KUMCTRLSTA_DIAG_FELPBK 0x2000 1751 #define E1000_KUMCTRLSTA_DIAG_NELPBK 0x1000 1752 1753 #define E1000_KUMCTRLSTA_K0S_100_EN 0x2000 1754 #define E1000_KUMCTRLSTA_K0S_GBE_EN 0x1000 1755 #define E1000_KUMCTRLSTA_K0S_ENTRY_LATENCY_MASK 0x0003 1756 1757 #define E1000_KABGTXD_BGSQLBIAS 0x00050000 1758 1759 #define E1000_PHY_CTRL_SPD_EN 0x00000001 1760 #define E1000_PHY_CTRL_D0A_LPLU 0x00000002 1761 #define E1000_PHY_CTRL_NOND0A_LPLU 0x00000004 1762 #define E1000_PHY_CTRL_NOND0A_GBE_DISABLE 0x00000008 1763 #define E1000_PHY_CTRL_GBE_DISABLE 0x00000040 1764 #define E1000_PHY_CTRL_B2B_EN 0x00000080 1765 #define E1000_PHY_CTRL_LOOPBACK 0x00004000 1766 1767 /* LED Control */ 1768 #define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F 1769 #define E1000_LEDCTL_LED0_MODE_SHIFT 0 1770 #define E1000_LEDCTL_LED0_BLINK_RATE 0x0000020 1771 #define E1000_LEDCTL_LED0_IVRT 0x00000040 1772 #define E1000_LEDCTL_LED0_BLINK 0x00000080 1773 #define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00 1774 #define E1000_LEDCTL_LED1_MODE_SHIFT 8 1775 #define E1000_LEDCTL_LED1_BLINK_RATE 0x0002000 1776 #define E1000_LEDCTL_LED1_IVRT 0x00004000 1777 #define E1000_LEDCTL_LED1_BLINK 0x00008000 1778 #define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000 1779 #define E1000_LEDCTL_LED2_MODE_SHIFT 16 1780 #define E1000_LEDCTL_LED2_BLINK_RATE 0x00200000 1781 #define E1000_LEDCTL_LED2_IVRT 0x00400000 1782 #define E1000_LEDCTL_LED2_BLINK 0x00800000 1783 #define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000 1784 #define E1000_LEDCTL_LED3_MODE_SHIFT 24 1785 #define E1000_LEDCTL_LED3_BLINK_RATE 0x20000000 1786 #define E1000_LEDCTL_LED3_IVRT 0x40000000 1787 #define E1000_LEDCTL_LED3_BLINK 0x80000000 1788 1789 #define E1000_LEDCTL_MODE_LINK_10_1000 0x0 1790 #define E1000_LEDCTL_MODE_LINK_100_1000 0x1 1791 #define E1000_LEDCTL_MODE_LINK_UP 0x2 1792 #define E1000_LEDCTL_MODE_ACTIVITY 0x3 1793 #define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4 1794 #define E1000_LEDCTL_MODE_LINK_10 0x5 1795 #define E1000_LEDCTL_MODE_LINK_100 0x6 1796 #define E1000_LEDCTL_MODE_LINK_1000 0x7 1797 #define E1000_LEDCTL_MODE_PCIX_MODE 0x8 1798 #define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9 1799 #define E1000_LEDCTL_MODE_COLLISION 0xA 1800 #define E1000_LEDCTL_MODE_BUS_SPEED 0xB 1801 #define E1000_LEDCTL_MODE_BUS_SIZE 0xC 1802 #define E1000_LEDCTL_MODE_PAUSED 0xD 1803 #define E1000_LEDCTL_MODE_LED_ON 0xE 1804 #define E1000_LEDCTL_MODE_LED_OFF 0xF 1805 1806 /* Receive Address */ 1807 #define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */ 1808 1809 /* Interrupt Cause Read */ 1810 #define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */ 1811 #define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */ 1812 #define E1000_ICR_LSC 0x00000004 /* Link Status Change */ 1813 #define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */ 1814 #define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */ 1815 #define E1000_ICR_RXO 0x00000040 /* rx overrun */ 1816 #define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */ 1817 #define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */ 1818 #define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */ 1819 #define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */ 1820 #define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */ 1821 #define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */ 1822 #define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */ 1823 #define E1000_ICR_TXD_LOW 0x00008000 1824 #define E1000_ICR_SRPD 0x00010000 1825 #define E1000_ICR_ACK 0x00020000 /* Receive Ack frame */ 1826 #define E1000_ICR_MNG 0x00040000 /* Manageability event */ 1827 #define E1000_ICR_DOCK 0x00080000 /* Dock/Undock */ 1828 #define E1000_ICR_INT_ASSERTED 0x80000000 /* If this bit asserted, the driver should claim the interrupt */ 1829 #define E1000_ICR_RXD_FIFO_PAR0 0x00100000 /* queue 0 Rx descriptor FIFO parity error */ 1830 #define E1000_ICR_TXD_FIFO_PAR0 0x00200000 /* queue 0 Tx descriptor FIFO parity error */ 1831 #define E1000_ICR_HOST_ARB_PAR 0x00400000 /* host arb read buffer parity error */ 1832 #define E1000_ICR_PB_PAR 0x00800000 /* packet buffer parity error */ 1833 #define E1000_ICR_RXD_FIFO_PAR1 0x01000000 /* queue 1 Rx descriptor FIFO parity error */ 1834 #define E1000_ICR_TXD_FIFO_PAR1 0x02000000 /* queue 1 Tx descriptor FIFO parity error */ 1835 #define E1000_ICR_ALL_PARITY 0x03F00000 /* all parity error bits */ 1836 #define E1000_ICR_DSW 0x00000020 /* FW changed the status of DISSW bit in the FWSM */ 1837 #define E1000_ICR_PHYINT 0x00001000 /* LAN connected device generates an interrupt */ 1838 #define E1000_ICR_EPRST 0x00100000 /* ME hardware reset occurs */ 1839 #define E1000_ICR_DRSTA 0x40000000 /* Device Reset Asserted */ 1840 1841 /* Interrupt Cause Set */ 1842 #define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1843 #define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1844 #define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */ 1845 #define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1846 #define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1847 #define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */ 1848 #define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1849 #define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1850 #define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1851 #define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1852 #define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1853 #define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1854 #define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1855 #define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW 1856 #define E1000_ICS_SRPD E1000_ICR_SRPD 1857 #define E1000_ICS_ACK E1000_ICR_ACK /* Receive Ack frame */ 1858 #define E1000_ICS_MNG E1000_ICR_MNG /* Manageability event */ 1859 #define E1000_ICS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1860 #define E1000_ICS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1861 #define E1000_ICS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1862 #define E1000_ICS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1863 #define E1000_ICS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1864 #define E1000_ICS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1865 #define E1000_ICS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1866 #define E1000_ICS_DSW E1000_ICR_DSW 1867 #define E1000_ICS_PHYINT E1000_ICR_PHYINT 1868 #define E1000_ICS_EPRST E1000_ICR_EPRST 1869 #define E1000_ICS_DRSTA E1000_ICR_DRSTA 1870 1871 /* Interrupt Mask Set */ 1872 #define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1873 #define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1874 #define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */ 1875 #define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1876 #define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1877 #define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */ 1878 #define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1879 #define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1880 #define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1881 #define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1882 #define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1883 #define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1884 #define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1885 #define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW 1886 #define E1000_IMS_SRPD E1000_ICR_SRPD 1887 #define E1000_IMS_ACK E1000_ICR_ACK /* Receive Ack frame */ 1888 #define E1000_IMS_MNG E1000_ICR_MNG /* Manageability event */ 1889 #define E1000_IMS_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1890 #define E1000_IMS_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1891 #define E1000_IMS_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1892 #define E1000_IMS_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1893 #define E1000_IMS_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1894 #define E1000_IMS_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1895 #define E1000_IMS_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1896 #define E1000_IMS_DSW E1000_ICR_DSW 1897 #define E1000_IMS_PHYINT E1000_ICR_PHYINT 1898 #define E1000_IMS_EPRST E1000_ICR_EPRST 1899 #define E1000_IMS_DRSTA E1000_ICR_DRSTA 1900 1901 /* Interrupt Mask Clear */ 1902 #define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */ 1903 #define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */ 1904 #define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */ 1905 #define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */ 1906 #define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */ 1907 #define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */ 1908 #define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */ 1909 #define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */ 1910 #define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */ 1911 #define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */ 1912 #define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */ 1913 #define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */ 1914 #define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */ 1915 #define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW 1916 #define E1000_IMC_SRPD E1000_ICR_SRPD 1917 #define E1000_IMC_ACK E1000_ICR_ACK /* Receive Ack frame */ 1918 #define E1000_IMC_MNG E1000_ICR_MNG /* Manageability event */ 1919 #define E1000_IMC_DOCK E1000_ICR_DOCK /* Dock/Undock */ 1920 #define E1000_IMC_RXD_FIFO_PAR0 E1000_ICR_RXD_FIFO_PAR0 /* queue 0 Rx descriptor FIFO parity error */ 1921 #define E1000_IMC_TXD_FIFO_PAR0 E1000_ICR_TXD_FIFO_PAR0 /* queue 0 Tx descriptor FIFO parity error */ 1922 #define E1000_IMC_HOST_ARB_PAR E1000_ICR_HOST_ARB_PAR /* host arb read buffer parity error */ 1923 #define E1000_IMC_PB_PAR E1000_ICR_PB_PAR /* packet buffer parity error */ 1924 #define E1000_IMC_RXD_FIFO_PAR1 E1000_ICR_RXD_FIFO_PAR1 /* queue 1 Rx descriptor FIFO parity error */ 1925 #define E1000_IMC_TXD_FIFO_PAR1 E1000_ICR_TXD_FIFO_PAR1 /* queue 1 Tx descriptor FIFO parity error */ 1926 #define E1000_IMC_DSW E1000_ICR_DSW 1927 #define E1000_IMC_PHYINT E1000_ICR_PHYINT 1928 #define E1000_IMC_EPRST E1000_ICR_EPRST 1929 #define E1000_IMC_DRSTA E1000_ICR_DRSTA 1930 1931 /* Receive Control */ 1932 #define E1000_RCTL_RST 0x00000001 /* Software reset */ 1933 #define E1000_RCTL_EN 0x00000002 /* enable */ 1934 #define E1000_RCTL_SBP 0x00000004 /* store bad packet */ 1935 #define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */ 1936 #define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */ 1937 #define E1000_RCTL_LPE 0x00000020 /* long packet enable */ 1938 #define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */ 1939 #define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */ 1940 #define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */ 1941 #define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */ 1942 #define E1000_RCTL_DTYP_MASK 0x00000C00 /* Descriptor type mask */ 1943 #define E1000_RCTL_DTYP_PS 0x00000400 /* Packet Split descriptor */ 1944 #define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */ 1945 #define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */ 1946 #define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */ 1947 #define E1000_RCTL_RDMTS_HEX 0x00010000 1948 #define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */ 1949 #define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */ 1950 #define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */ 1951 #define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */ 1952 #define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */ 1953 #define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */ 1954 #define E1000_RCTL_BAM 0x00008000 /* broadcast enable */ 1955 /* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */ 1956 #define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */ 1957 #define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */ 1958 #define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */ 1959 #define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */ 1960 /* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */ 1961 #define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */ 1962 #define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */ 1963 #define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */ 1964 #define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */ 1965 #define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */ 1966 #define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */ 1967 #define E1000_RCTL_DPF 0x00400000 /* discard pause frames */ 1968 #define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */ 1969 #define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */ 1970 #define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */ 1971 #define E1000_RCTL_FLXBUF_MASK 0x78000000 /* Flexible buffer size */ 1972 #define E1000_RCTL_FLXBUF_SHIFT 27 /* Flexible buffer shift */ 1973 1974 /* Use byte values for the following shift parameters 1975 * Usage: 1976 * psrctl |= (((ROUNDUP(value0, 128) >> E1000_PSRCTL_BSIZE0_SHIFT) & 1977 * E1000_PSRCTL_BSIZE0_MASK) | 1978 * ((ROUNDUP(value1, 1024) >> E1000_PSRCTL_BSIZE1_SHIFT) & 1979 * E1000_PSRCTL_BSIZE1_MASK) | 1980 * ((ROUNDUP(value2, 1024) << E1000_PSRCTL_BSIZE2_SHIFT) & 1981 * E1000_PSRCTL_BSIZE2_MASK) | 1982 * ((ROUNDUP(value3, 1024) << E1000_PSRCTL_BSIZE3_SHIFT) |; 1983 * E1000_PSRCTL_BSIZE3_MASK)) 1984 * where value0 = [128..16256], default=256 1985 * value1 = [1024..64512], default=4096 1986 * value2 = [0..64512], default=4096 1987 * value3 = [0..64512], default=0 1988 */ 1989 1990 #define E1000_PSRCTL_BSIZE0_MASK 0x0000007F 1991 #define E1000_PSRCTL_BSIZE1_MASK 0x00003F00 1992 #define E1000_PSRCTL_BSIZE2_MASK 0x003F0000 1993 #define E1000_PSRCTL_BSIZE3_MASK 0x3F000000 1994 1995 #define E1000_PSRCTL_BSIZE0_SHIFT 7 /* Shift _right_ 7 */ 1996 #define E1000_PSRCTL_BSIZE1_SHIFT 2 /* Shift _right_ 2 */ 1997 #define E1000_PSRCTL_BSIZE2_SHIFT 6 /* Shift _left_ 6 */ 1998 #define E1000_PSRCTL_BSIZE3_SHIFT 14 /* Shift _left_ 14 */ 1999 2000 /* SW_W_SYNC definitions */ 2001 #define E1000_SWFW_EEP_SM 0x0001 2002 #define E1000_SWFW_PHY0_SM 0x0002 2003 #define E1000_SWFW_PHY1_SM 0x0004 2004 #define E1000_SWFW_MAC_CSR_SM 0x0008 2005 #define E1000_SWFW_PHY2_SM 0x0020 2006 #define E1000_SWFW_PHY3_SM 0x0040 2007 2008 /* Receive Descriptor */ 2009 #define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */ 2010 #define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */ 2011 #define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */ 2012 #define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */ 2013 #define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */ 2014 2015 /* Flow Control */ 2016 #define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */ 2017 #define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */ 2018 #define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */ 2019 #define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */ 2020 2021 /* Flow Control Settings */ 2022 #define E1000_FC_NONE 0 2023 #define E1000_FC_RX_PAUSE 1 2024 #define E1000_FC_TX_PAUSE 2 2025 #define E1000_FC_FULL 3 2026 #define E1000_FC_DEFAULT 0xFF 2027 2028 /* Header split receive */ 2029 #define E1000_RFCTL_ISCSI_DIS 0x00000001 2030 #define E1000_RFCTL_ISCSI_DWC_MASK 0x0000003E 2031 #define E1000_RFCTL_ISCSI_DWC_SHIFT 1 2032 #define E1000_RFCTL_NFSW_DIS 0x00000040 2033 #define E1000_RFCTL_NFSR_DIS 0x00000080 2034 #define E1000_RFCTL_NFS_VER_MASK 0x00000300 2035 #define E1000_RFCTL_NFS_VER_SHIFT 8 2036 #define E1000_RFCTL_IPV6_DIS 0x00000400 2037 #define E1000_RFCTL_IPV6_XSUM_DIS 0x00000800 2038 #define E1000_RFCTL_ACK_DIS 0x00001000 2039 #define E1000_RFCTL_ACKD_DIS 0x00002000 2040 #define E1000_RFCTL_IPFRSP_DIS 0x00004000 2041 #define E1000_RFCTL_EXTEN 0x00008000 2042 #define E1000_RFCTL_IPV6_EX_DIS 0x00010000 2043 #define E1000_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 2044 2045 /* Receive Descriptor Control */ 2046 #define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */ 2047 #define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */ 2048 #define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */ 2049 #define E1000_RXDCTL_THRESH_UNIT_DESC 0x1000000 2050 #define E1000_RXDCTL_QUEUE_ENABLE 0x2000000 2051 2052 #define E1000_EITR_ITR_INT_MASK 0x0000FFFF 2053 /* E1000_EITR_CNT_IGNR is only for 82576 and newer */ 2054 #define E1000_EITR_CNT_IGNR 0x80000000 /* Don't reset counters on write */ 2055 #define E1000_EITR_INTERVAL 0x00007FFC 2056 2057 /* Transmit Descriptor Control */ 2058 #define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */ 2059 #define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */ 2060 #define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */ 2061 #define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */ 2062 #define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */ 2063 #define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */ 2064 #define E1000_TXDCTL_COUNT_DESC 0x00400000 /* Enable the counting of desc. 2065 still to be processed. */ 2066 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 2067 2068 /* Transmit Configuration Word */ 2069 #define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */ 2070 #define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */ 2071 #define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */ 2072 #define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */ 2073 #define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */ 2074 #define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */ 2075 #define E1000_TXCW_NP 0x00008000 /* TXCW next page */ 2076 #define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */ 2077 #define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */ 2078 #define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */ 2079 2080 /* Receive Configuration Word */ 2081 #define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */ 2082 #define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */ 2083 #define E1000_RXCW_IV 0x08000000 /* Receive config invalid */ 2084 #define E1000_RXCW_CC 0x10000000 /* Receive config change */ 2085 #define E1000_RXCW_C 0x20000000 /* Receive config */ 2086 #define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */ 2087 #define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */ 2088 2089 /* Transmit Control */ 2090 #define E1000_TCTL_RST 0x00000001 /* software reset */ 2091 #define E1000_TCTL_EN 0x00000002 /* enable tx */ 2092 #define E1000_TCTL_BCE 0x00000004 /* busy check enable */ 2093 #define E1000_TCTL_PSP 0x00000008 /* pad short packets */ 2094 #define E1000_TCTL_CT 0x00000ff0 /* collision threshold */ 2095 #define E1000_TCTL_COLD 0x003ff000 /* collision distance */ 2096 #define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */ 2097 #define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */ 2098 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */ 2099 #define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */ 2100 #define E1000_TCTL_MULR 0x10000000 /* Multiple request support */ 2101 /* Extended Transmit Control */ 2102 #define E1000_TCTL_EXT_BST_MASK 0x000003FF /* Backoff Slot Time */ 2103 #define E1000_TCTL_EXT_GCEX_MASK 0x000FFC00 /* Gigabit Carry Extend Padding */ 2104 2105 #define DEFAULT_80003ES2LAN_TCTL_EXT_GCEX 0x00010000 2106 2107 /* Receive Checksum Control */ 2108 #define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */ 2109 #define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */ 2110 #define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */ 2111 #define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */ 2112 #define E1000_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 2113 #define E1000_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 2114 2115 /* Context descriptors */ 2116 struct e1000_adv_tx_context_desc { 2117 uint32_t vlan_macip_lens; 2118 union { 2119 uint32_t launch_time; 2120 uint32_t seqnum_seed; 2121 } u; 2122 uint32_t type_tucmd_mlhl; 2123 uint32_t mss_l4len_idx; 2124 }; 2125 2126 /* Adv Transmit Descriptor Config Masks */ 2127 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */ 2128 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */ 2129 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 2130 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */ 2131 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */ 2132 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 2133 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 2134 2135 /* Adv Transmit Descriptor Config Masks */ 2136 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 2137 #define E1000_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 2138 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 2139 #define E1000_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 2140 #define E1000_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 2141 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 2142 2143 /* Req requires Markers and CRC */ 2144 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 2145 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 2146 2147 /* Multiple Receive Queue Control */ 2148 #define E1000_MRQC_ENABLE_MASK 0x00000003 2149 #define E1000_MRQC_ENABLE_RSS_2Q 0x00000001 2150 #define E1000_MRQC_ENABLE_RSS_INT 0x00000004 2151 #define E1000_MRQC_RSS_FIELD_MASK 0xFFFF0000 2152 #define E1000_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 2153 #define E1000_MRQC_RSS_FIELD_IPV4 0x00020000 2154 #define E1000_MRQC_RSS_FIELD_IPV6_TCP_EX 0x00040000 2155 #define E1000_MRQC_RSS_FIELD_IPV6_EX 0x00080000 2156 #define E1000_MRQC_RSS_FIELD_IPV6 0x00100000 2157 #define E1000_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 2158 2159 /* Definitions for power management and wakeup registers */ 2160 /* Wake Up Control */ 2161 #define E1000_WUC_APME 0x00000001 /* APM Enable */ 2162 #define E1000_WUC_PME_EN 0x00000002 /* PME Enable */ 2163 #define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */ 2164 #define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */ 2165 #define E1000_WUC_SPM 0x80000000 /* Enable SPM */ 2166 /* Flexible Host Filter Table */ 2167 #define E1000_FHFT(_n) (0x09000 + ((_n) * 0x100)) 2168 /* Ext Flexible Host Filter Table */ 2169 #define E1000_FHFT_EXT(_n) (0x09A00 + ((_n) * 0x100)) 2170 2171 /* Wake Up Filter Control */ 2172 #define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 2173 #define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 2174 #define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 2175 #define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 2176 #define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 2177 #define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 2178 #define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 2179 #define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 2180 #define E1000_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 2181 #define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 2182 #define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 2183 #define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 2184 #define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 2185 #define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */ 2186 #define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 2187 #define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 2188 2189 /* Wake Up Status */ 2190 #define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */ 2191 #define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */ 2192 #define E1000_WUS_EX 0x00000004 /* Directed Exact Received */ 2193 #define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */ 2194 #define E1000_WUS_BC 0x00000010 /* Broadcast Received */ 2195 #define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */ 2196 #define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */ 2197 #define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */ 2198 #define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */ 2199 #define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */ 2200 #define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */ 2201 #define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */ 2202 #define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */ 2203 2204 /* TRAC0 bits */ 2205 #define E1000_TARC0_CB_MULTIQ_2_REQ (1 << 29) 2206 #define E1000_TARC0_CB_MULTIQ_3_REQ (1 << 28 | 1 << 29) 2207 2208 /* Management Control */ 2209 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */ 2210 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */ 2211 #define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */ 2212 #define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */ 2213 #define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */ 2214 #define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */ 2215 #define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */ 2216 #define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */ 2217 #define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */ 2218 #define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery 2219 * Filtering */ 2220 #define E1000_MANC_ARP_RES_EN 0x00008000 /* Enable ARP response Filtering */ 2221 #define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */ 2222 #define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */ 2223 #define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */ 2224 #define E1000_MANC_RCV_ALL 0x00080000 /* Receive All Enabled */ 2225 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */ 2226 #define E1000_MANC_EN_MAC_ADDR_FILTER 0x00100000 /* Enable MAC address 2227 * filtering */ 2228 #define E1000_MANC_EN_MNG2HOST 0x00200000 /* Enable MNG packets to host 2229 * memory */ 2230 #define E1000_MANC_EN_IP_ADDR_FILTER 0x00400000 /* Enable IP address 2231 * filtering */ 2232 #define E1000_MANC_EN_XSUM_FILTER 0x00800000 /* Enable checksum filtering */ 2233 #define E1000_MANC_BR_EN 0x01000000 /* Enable broadcast filtering */ 2234 #define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */ 2235 #define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */ 2236 #define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */ 2237 #define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */ 2238 #define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */ 2239 #define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */ 2240 2241 #define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */ 2242 #define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */ 2243 2244 /* SW Semaphore Register */ 2245 #define E1000_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 2246 #define E1000_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 2247 #define E1000_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 2248 #define E1000_SWSM_DRV_LOAD 0x00000008 /* Driver Loaded Bit */ 2249 /* Host to ME */ 2250 #define E1000_H2ME_ULP 0x00000800 /* ULP Indication Bit */ 2251 #define E1000_H2ME_ENFORCE_SETTINGS 0x00001000 /* Enforce Settings */ 2252 2253 /* FW Semaphore Register */ 2254 #define E1000_FWSM_MODE_MASK 0x0000000E /* FW mode */ 2255 #define E1000_FWSM_MODE_SHIFT 1 2256 #define E1000_FWSM_ULP_CFG_DONE 0x00000400 /* Low power cfg done */ 2257 #define E1000_FWSM_FW_VALID 0x00008000 /* FW established a valid mode */ 2258 2259 #define E1000_FWSM_RSPCIPHY 0x00000040 /* Reset PHY on PCI reset */ 2260 #define E1000_FWSM_DISSW 0x10000000 /* FW disable SW Write Access */ 2261 #define E1000_FWSM_SKUSEL_MASK 0x60000000 /* LAN SKU select */ 2262 #define E1000_FWSM_SKUEL_SHIFT 29 2263 #define E1000_FWSM_SKUSEL_EMB 0x0 /* Embedded SKU */ 2264 #define E1000_FWSM_SKUSEL_CONS 0x1 /* Consumer SKU */ 2265 #define E1000_FWSM_SKUSEL_PERF_100 0x2 /* Perf & Corp 10/100 SKU */ 2266 #define E1000_FWSM_SKUSEL_PERF_GBE 0x3 /* Perf & Copr GbE SKU */ 2267 2268 /* FFLT Debug Register */ 2269 #define E1000_FFLT_DBG_INVC 0x00100000 /* Invalid /C/ code handling */ 2270 2271 typedef enum { 2272 em_mng_mode_none = 0, 2273 em_mng_mode_asf, 2274 em_mng_mode_pt, 2275 em_mng_mode_ipmi, 2276 em_mng_mode_host_interface_only 2277 } em_mng_mode; 2278 2279 /* Host Interface Control Register */ 2280 #define E1000_HICR_EN 0x00000001 /* Enable Bit - RO */ 2281 #define E1000_HICR_C 0x00000002 /* Driver sets this bit when done 2282 * to put command in RAM */ 2283 #define E1000_HICR_SV 0x00000004 /* Status Validity */ 2284 #define E1000_HICR_FWR 0x00000080 /* FW reset. Set by the Host */ 2285 2286 /* Host Interface Command Interface - Address range 0x8800-0x8EFF */ 2287 #define E1000_HI_MAX_DATA_LENGTH 252 /* Host Interface data length */ 2288 #define E1000_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Number of bytes in range */ 2289 #define E1000_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Number of dwords in range */ 2290 #define E1000_HI_COMMAND_TIMEOUT 500 /* Time in ms to process HI command */ 2291 2292 struct em_host_command_header { 2293 uint8_t command_id; 2294 uint8_t command_length; 2295 uint8_t command_options; /* I/F bits for command, status for return */ 2296 uint8_t checksum; 2297 }; 2298 struct em_host_command_info { 2299 struct em_host_command_header command_header; /* Command Head/Command Result Head has 4 bytes */ 2300 uint8_t command_data[E1000_HI_MAX_DATA_LENGTH]; /* Command data can length 0..252 */ 2301 }; 2302 2303 /* Host SMB register #0 */ 2304 #define E1000_HSMC0R_CLKIN 0x00000001 /* SMB Clock in */ 2305 #define E1000_HSMC0R_DATAIN 0x00000002 /* SMB Data in */ 2306 #define E1000_HSMC0R_DATAOUT 0x00000004 /* SMB Data out */ 2307 #define E1000_HSMC0R_CLKOUT 0x00000008 /* SMB Clock out */ 2308 2309 /* Host SMB register #1 */ 2310 #define E1000_HSMC1R_CLKIN E1000_HSMC0R_CLKIN 2311 #define E1000_HSMC1R_DATAIN E1000_HSMC0R_DATAIN 2312 #define E1000_HSMC1R_DATAOUT E1000_HSMC0R_DATAOUT 2313 #define E1000_HSMC1R_CLKOUT E1000_HSMC0R_CLKOUT 2314 2315 /* FW Status Register */ 2316 #define E1000_FWSTS_FWS_MASK 0x000000FF /* FW Status */ 2317 2318 /* Wake Up Packet Length */ 2319 #define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */ 2320 2321 #define E1000_MDALIGN 4096 2322 2323 #define E1000_MDICNFG_EXT_MDIO 0x80000000 /* MDI ext/int destination */ 2324 #define E1000_MDICNFG_COM_MDIO 0x40000000 /* MDI shared w/ lan 0 */ 2325 #define E1000_MDICNFG_PHY_MASK 0x03E00000 2326 #define E1000_MDICNFG_PHY_SHIFT 21 2327 2328 /* I350 EEE defines */ 2329 #define E1000_IPCNFG_EEE_1G_AN 0x00000008 /* IPCNFG EEE Ena 1G AN */ 2330 #define E1000_IPCNFG_EEE_100M_AN 0x00000004 /* IPCNFG EEE Ena 100M AN */ 2331 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEER Tx LPI Enable */ 2332 #define E1000_EEER_RX_LPI_EN 0x00020000 /* EEER Rx LPI Enable */ 2333 #define E1000_EEER_LPI_FC 0x00040000 /* EEER Ena on Flow Cntrl */ 2334 /* EEE status */ 2335 #define E1000_EEER_EEE_NEG 0x20000000 /* EEE capability nego */ 2336 #define E1000_EEER_RX_LPI_STATUS 0x40000000 /* Rx in LPI state */ 2337 #define E1000_EEER_TX_LPI_STATUS 0x80000000 /* Tx in LPI state */ 2338 2339 /* PCI-Ex registers*/ 2340 2341 /* PCI-Ex Control Register */ 2342 #define E1000_GCR_RXD_NO_SNOOP 0x00000001 2343 #define E1000_GCR_RXDSCW_NO_SNOOP 0x00000002 2344 #define E1000_GCR_RXDSCR_NO_SNOOP 0x00000004 2345 #define E1000_GCR_TXD_NO_SNOOP 0x00000008 2346 #define E1000_GCR_TXDSCW_NO_SNOOP 0x00000010 2347 #define E1000_GCR_TXDSCR_NO_SNOOP 0x00000020 2348 2349 #define E1000_GCR_CMPL_TMOUT_MASK 0x0000F000 2350 #define E1000_GCR_CMPL_TMOUT_10ms 0x00001000 2351 #define E1000_GCR_CMPL_TMOUT_RESEND 0x00010000 2352 #define E1000_GCR_CAP_VER2 0x00040000 2353 2354 #define PCI_EX_NO_SNOOP_ALL (E1000_GCR_RXD_NO_SNOOP | \ 2355 E1000_GCR_RXDSCW_NO_SNOOP | \ 2356 E1000_GCR_RXDSCR_NO_SNOOP | \ 2357 E1000_GCR_TXD_NO_SNOOP | \ 2358 E1000_GCR_TXDSCW_NO_SNOOP | \ 2359 E1000_GCR_TXDSCR_NO_SNOOP) 2360 2361 #define PCI_EX_82566_SNOOP_ALL PCI_EX_NO_SNOOP_ALL 2362 2363 #define E1000_GCR_L1_ACT_WITHOUT_L0S_RX 0x08000000 2364 /* Function Active and Power State to MNG */ 2365 #define E1000_FACTPS_FUNC0_POWER_STATE_MASK 0x00000003 2366 #define E1000_FACTPS_LAN0_VALID 0x00000004 2367 #define E1000_FACTPS_FUNC0_AUX_EN 0x00000008 2368 #define E1000_FACTPS_FUNC1_POWER_STATE_MASK 0x000000C0 2369 #define E1000_FACTPS_FUNC1_POWER_STATE_SHIFT 6 2370 #define E1000_FACTPS_LAN1_VALID 0x00000100 2371 #define E1000_FACTPS_FUNC1_AUX_EN 0x00000200 2372 #define E1000_FACTPS_FUNC2_POWER_STATE_MASK 0x00003000 2373 #define E1000_FACTPS_FUNC2_POWER_STATE_SHIFT 12 2374 #define E1000_FACTPS_IDE_ENABLE 0x00004000 2375 #define E1000_FACTPS_FUNC2_AUX_EN 0x00008000 2376 #define E1000_FACTPS_FUNC3_POWER_STATE_MASK 0x000C0000 2377 #define E1000_FACTPS_FUNC3_POWER_STATE_SHIFT 18 2378 #define E1000_FACTPS_SP_ENABLE 0x00100000 2379 #define E1000_FACTPS_FUNC3_AUX_EN 0x00200000 2380 #define E1000_FACTPS_FUNC4_POWER_STATE_MASK 0x03000000 2381 #define E1000_FACTPS_FUNC4_POWER_STATE_SHIFT 24 2382 #define E1000_FACTPS_IPMI_ENABLE 0x04000000 2383 #define E1000_FACTPS_FUNC4_AUX_EN 0x08000000 2384 #define E1000_FACTPS_MNGCG 0x20000000 2385 #define E1000_FACTPS_LAN_FUNC_SEL 0x40000000 2386 #define E1000_FACTPS_PM_STATE_CHANGED 0x80000000 2387 2388 /* IVAR0 bit definitions */ 2389 #define E1000_IVAR_VALID 0x80 2390 2391 /* GPIE bit definitions */ 2392 #define E1000_GPIE_NSICR 0x00000001 2393 #define E1000_GPIE_MSIX_MODE 0x00000010 2394 #define E1000_GPIE_EIAME 0x40000000 2395 #define E1000_GPIE_PBA 0x80000000 2396 2397 /* MRQC bit definitions */ 2398 #define E1000_MRQC_ENABLE_RSS_4Q 0x00000002 2399 #define E1000_MRQC_ENABLE_VMDQ 0x00000003 2400 #define E1000_MRQC_ENABLE_VMDQ_RSS_2Q 0x00000005 2401 #define E1000_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 2402 #define E1000_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 2403 #define E1000_MRQC_RSS_FIELD_IPV6_UDP_EX 0x01000000 2404 #define E1000_MRQC_ENABLE_RSS_8Q 0x00000002 2405 2406 /* SRRCTL bit definitions */ 2407 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */ 2408 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00 2409 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */ 2410 #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000 2411 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 2412 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 2413 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 2414 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000 2415 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 2416 #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000 2417 #define E1000_SRRCTL_TIMESTAMP 0x40000000 2418 #define E1000_SRRCTL_DROP_EN 0x80000000 2419 2420 /* WUFC bit definitions */ 2421 #define E1000_WUFC_FLX(_n) (1 << (16 + _n)) 2422 #define E1000_WUFC_FLEX_HQ (1 << 14) 2423 2424 /* PCI-Ex Config Space */ 2425 #define PCI_EX_LINK_STATUS 0x12 2426 #define PCI_EX_LINK_WIDTH_MASK 0x3F0 2427 #define PCI_EX_LINK_WIDTH_SHIFT 4 2428 2429 #define PCI_EX_DEVICE_CONTROL2 0x28 2430 #define PCI_EX_DEVICE_CONTROL2_16ms 0x0005 2431 2432 /* EEPROM Commands - Microwire */ 2433 #define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */ 2434 #define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */ 2435 #define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */ 2436 #define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */ 2437 #define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erase/write disable */ 2438 2439 /* EEPROM Commands - SPI */ 2440 #define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */ 2441 #define EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 2442 #define EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 2443 #define EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */ 2444 #define EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Enable latch */ 2445 #define EEPROM_WRDI_OPCODE_SPI 0x04 /* EEPROM reset Write Enable latch */ 2446 #define EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status register */ 2447 #define EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status register */ 2448 #define EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 2449 #define EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 2450 #define EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 2451 2452 /* EEPROM Size definitions */ 2453 #define EEPROM_WORD_SIZE_SHIFT 6 2454 #define EEPROM_WORD_SIZE_SHIFT_MAX 14 2455 #define EEPROM_SIZE_SHIFT 10 2456 #define EEPROM_SIZE_MASK 0x1C00 2457 2458 /* EEPROM Word Offsets */ 2459 #define EEPROM_MAC_ADDR_WORD0 0x0000 2460 #define EEPROM_MAC_ADDR_WORD1 0x0001 2461 #define EEPROM_MAC_ADDR_WORD2 0x0002 2462 #define EEPROM_COMPAT 0x0003 2463 #define EEPROM_ID_LED_SETTINGS 0x0004 2464 #define EEPROM_VERSION 0x0005 2465 #define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */ 2466 #define EEPROM_PHY_CLASS_WORD 0x0007 2467 #define EEPROM_INIT_CONTROL1_REG 0x000A 2468 #define EEPROM_INIT_CONTROL2_REG 0x000F 2469 #define EEPROM_SWDEF_PINS_CTRL_PORT_1 0x0010 2470 #define EEPROM_INIT_CONTROL4_REG 0x0013 2471 #define EEPROM_INIT_CONTROL3_PORT_B 0x0014 2472 #define EEPROM_INIT_3GIO_3 0x001A 2473 #define EEPROM_LED_1_CFG 0x001C 2474 #define EEPROM_LED_0_2_CFG 0x001F 2475 #define EEPROM_SWDEF_PINS_CTRL_PORT_0 0x0020 2476 #define EEPROM_INIT_CONTROL3_PORT_A 0x0024 2477 #define EEPROM_CFG 0x0012 2478 #define EEPROM_FLASH_VERSION 0x0032 2479 #define EEPROM_CHECKSUM_REG 0x003F 2480 2481 #define EEPROM_COMPAT_VALID_CSUM 0x0001 2482 #define EEPROM_FUTURE_INIT_WORD1 0x0019 2483 #define EEPROM_FUTURE_INIT_WORD1_VALID_CSUM 0x0040 2484 2485 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */ 2486 #define E1000_NVM_CFG_DONE_PORT_1 0x080000 /* ...for second port */ 2487 #define E1000_NVM_CFG_DONE_PORT_2 0x100000 /* ...for third port */ 2488 #define E1000_NVM_CFG_DONE_PORT_3 0x200000 /* ...for fourth port */ 2489 2490 #define NVM_82580_LAN_FUNC_OFFSET(a) (a ? (0x40 + (0x40 * a)) : 0) 2491 2492 /* Mask bits for fields in Word 0x24 of the NVM */ 2493 #define NVM_WORD24_COM_MDIO 0x0008 /* MDIO interface shared */ 2494 #define NVM_WORD24_EXT_MDIO 0x0004 /* MDIO accesses routed external */ 2495 2496 /* Word definitions for ID LED Settings */ 2497 #define ID_LED_RESERVED_0000 0x0000 2498 #define ID_LED_RESERVED_FFFF 0xFFFF 2499 #define ID_LED_RESERVED_82573 0xF746 2500 #define ID_LED_DEFAULT_82573 0x1811 2501 #define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \ 2502 (ID_LED_OFF1_OFF2 << 8) | \ 2503 (ID_LED_DEF1_DEF2 << 4) | \ 2504 (ID_LED_DEF1_DEF2)) 2505 #define ID_LED_DEFAULT_ICH8LAN ((ID_LED_DEF1_DEF2 << 12) | \ 2506 (ID_LED_DEF1_OFF2 << 8) | \ 2507 (ID_LED_DEF1_ON2 << 4) | \ 2508 (ID_LED_DEF1_DEF2)) 2509 #define ID_LED_DEF1_DEF2 0x1 2510 #define ID_LED_DEF1_ON2 0x2 2511 #define ID_LED_DEF1_OFF2 0x3 2512 #define ID_LED_ON1_DEF2 0x4 2513 #define ID_LED_ON1_ON2 0x5 2514 #define ID_LED_ON1_OFF2 0x6 2515 #define ID_LED_OFF1_DEF2 0x7 2516 #define ID_LED_OFF1_ON2 0x8 2517 #define ID_LED_OFF1_OFF2 0x9 2518 2519 #define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF 2520 #define IGP_ACTIVITY_LED_ENABLE 0x0300 2521 #define IGP_LED3_MODE 0x07000000 2522 2523 /* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */ 2524 #define EEPROM_SERDES_AMPLITUDE_MASK 0x000F 2525 2526 /* Mask bit for PHY class in Word 7 of the EEPROM */ 2527 #define EEPROM_PHY_CLASS_A 0x8000 2528 2529 /* Mask bits for fields in Word 0x0a of the EEPROM */ 2530 #define EEPROM_WORD0A_ILOS 0x0010 2531 #define EEPROM_WORD0A_SWDPIO 0x01E0 2532 #define EEPROM_WORD0A_LRST 0x0200 2533 #define EEPROM_WORD0A_FD 0x0400 2534 #define EEPROM_WORD0A_66MHZ 0x0800 2535 2536 /* Mask bits for fields in Word 0x0f of the EEPROM */ 2537 #define EEPROM_WORD0F_PAUSE_MASK 0x3000 2538 #define EEPROM_WORD0F_PAUSE 0x1000 2539 #define EEPROM_WORD0F_ASM_DIR 0x2000 2540 #define EEPROM_WORD0F_ANE 0x0800 2541 #define EEPROM_WORD0F_SWPDIO_EXT 0x00F0 2542 #define EEPROM_WORD0F_LPLU 0x0001 2543 2544 /* Mask bits for fields in Word 0x10/0x20 of the EEPROM */ 2545 #define EEPROM_WORD1020_GIGA_DISABLE 0x0010 2546 #define EEPROM_WORD1020_GIGA_DISABLE_NON_D0A 0x0008 2547 2548 /* Mask bits for fields in Word 0x1a of the EEPROM */ 2549 #define EEPROM_WORD1A_ASPM_MASK 0x000C 2550 2551 /* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */ 2552 #define EEPROM_SUM 0xBABA 2553 2554 /* EEPROM Map defines (WORD OFFSETS)*/ 2555 #define EEPROM_NODE_ADDRESS_BYTE_0 0 2556 #define EEPROM_PBA_BYTE_1 8 2557 2558 #define EEPROM_RESERVED_WORD 0xFFFF 2559 2560 /* EEPROM Map Sizes (Byte Counts) */ 2561 #define PBA_SIZE 4 2562 2563 /* Collision related configuration parameters */ 2564 #define E1000_COLLISION_THRESHOLD 15 2565 #define E1000_CT_SHIFT 4 2566 /* Collision distance is a 0-based value that applies to 2567 * half-duplex-capable hardware only. */ 2568 #define E1000_COLLISION_DISTANCE 63 2569 #define E1000_COLLISION_DISTANCE_82542 64 2570 #define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE 2571 #define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE 2572 #define E1000_COLD_SHIFT 12 2573 2574 /* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 2575 #define REQ_TX_DESCRIPTOR_MULTIPLE 8 2576 #define REQ_RX_DESCRIPTOR_MULTIPLE 8 2577 2578 /* Default values for the transmit IPG register */ 2579 #define DEFAULT_82542_TIPG_IPGT 10 2580 #define DEFAULT_82543_TIPG_IPGT_FIBER 9 2581 #define DEFAULT_82543_TIPG_IPGT_COPPER 8 2582 2583 #define E1000_TIPG_IPGT_MASK 0x000003FF 2584 #define E1000_TIPG_IPGR1_MASK 0x000FFC00 2585 #define E1000_TIPG_IPGR2_MASK 0x3FF00000 2586 2587 #define DEFAULT_82542_TIPG_IPGR1 2 2588 #define DEFAULT_82543_TIPG_IPGR1 8 2589 #define E1000_TIPG_IPGR1_SHIFT 10 2590 2591 #define DEFAULT_82542_TIPG_IPGR2 10 2592 #define DEFAULT_82543_TIPG_IPGR2 6 2593 #define DEFAULT_80003ES2LAN_TIPG_IPGR2 7 2594 #define E1000_TIPG_IPGR2_SHIFT 20 2595 2596 #define DEFAULT_80003ES2LAN_TIPG_IPGT_10_100 0x00000009 2597 #define DEFAULT_80003ES2LAN_TIPG_IPGT_1000 0x00000008 2598 #define E1000_TXDMAC_DPP 0x00000001 2599 2600 /* Adaptive IFS defines */ 2601 #define TX_THRESHOLD_START 8 2602 #define TX_THRESHOLD_INCREMENT 10 2603 #define TX_THRESHOLD_DECREMENT 1 2604 #define TX_THRESHOLD_STOP 190 2605 #define TX_THRESHOLD_DISABLE 0 2606 #define TX_THRESHOLD_TIMER_MS 10000 2607 #define MIN_NUM_XMITS 1000 2608 #define IFS_MAX 80 2609 #define IFS_STEP 10 2610 #define IFS_MIN 40 2611 #define IFS_RATIO 4 2612 2613 /* Extended Configuration Control and Size */ 2614 #define E1000_EXTCNF_CTRL_PCIE_WRITE_ENABLE 0x00000001 2615 #define E1000_EXTCNF_CTRL_PHY_WRITE_ENABLE 0x00000002 2616 #define E1000_EXTCNF_CTRL_D_UD_ENABLE 0x00000004 2617 #define E1000_EXTCNF_CTRL_D_UD_LATENCY 0x00000008 2618 #define E1000_EXTCNF_CTRL_D_UD_OWNER 0x00000010 2619 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 2620 #define E1000_EXTCNF_CTRL_MDIO_HW_OWNERSHIP 0x00000040 2621 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER 0x0FFF0000 2622 2623 #define E1000_EXTCNF_SIZE_EXT_PHY_LENGTH 0x000000FF 2624 #define E1000_EXTCNF_SIZE_EXT_DOCK_LENGTH 0x0000FF00 2625 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH 0x00FF0000 2626 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 2627 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 2628 #define E1000_EXTCNF_CTRL_GATE_PHY_CFG 0x00000080 2629 2630 /* PBA constants */ 2631 #define E1000_PBA_8K 0x0008 /* 8KB, default Rx allocation */ 2632 #define E1000_PBA_10K 0x000A 2633 #define E1000_PBA_12K 0x000C /* 12KB, default Rx allocation */ 2634 #define E1000_PBA_14K 0x000E /* 14KB */ 2635 #define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */ 2636 #define E1000_PBA_20K 0x0014 2637 #define E1000_PBA_22K 0x0016 2638 #define E1000_PBA_24K 0x0018 2639 #define E1000_PBA_26K 0x001A 2640 #define E1000_PBA_30K 0x001E 2641 #define E1000_PBA_32K 0x0020 2642 #define E1000_PBA_34K 0x0022 2643 #define E1000_PBA_38K 0x0026 2644 #define E1000_PBA_40K 0x0028 2645 #define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */ 2646 2647 #define E1000_PBS_16K E1000_PBA_16K 2648 2649 /* Flow Control Constants */ 2650 #define FLOW_CONTROL_ADDRESS_LOW 0x00C28001 2651 #define FLOW_CONTROL_ADDRESS_HIGH 0x00000100 2652 #define FLOW_CONTROL_TYPE 0x8808 2653 2654 /* The historical defaults for the flow control values are given below. */ 2655 #define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ 2656 #define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ 2657 #define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ 2658 2659 /* PCIX Config space */ 2660 #define PCIX_COMMAND_REGISTER 0xE6 2661 #define PCIX_STATUS_REGISTER_LO 0xE8 2662 #define PCIX_STATUS_REGISTER_HI 0xEA 2663 2664 #define PCIX_COMMAND_MMRBC_MASK 0x000C 2665 #define PCIX_COMMAND_MMRBC_SHIFT 0x2 2666 #define PCIX_STATUS_HI_MMRBC_MASK 0x0060 2667 #define PCIX_STATUS_HI_MMRBC_SHIFT 0x5 2668 #define PCIX_STATUS_HI_MMRBC_4K 0x3 2669 #define PCIX_STATUS_HI_MMRBC_2K 0x2 2670 2671 /* Number of bits required to shift right the "pause" bits from the 2672 * EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register. 2673 */ 2674 #define PAUSE_SHIFT 5 2675 2676 /* Number of bits required to shift left the "SWDPIO" bits from the 2677 * EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register. 2678 */ 2679 #define SWDPIO_SHIFT 17 2680 2681 /* Number of bits required to shift left the "SWDPIO_EXT" bits from the 2682 * EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register. 2683 */ 2684 #define SWDPIO__EXT_SHIFT 4 2685 2686 /* Number of bits required to shift left the "ILOS" bit from the EEPROM 2687 * (bit 4) to the "ILOS" (bit 7) field in the CTRL register. 2688 */ 2689 #define ILOS_SHIFT 3 2690 2691 #define RECEIVE_BUFFER_ALIGN_SIZE (256) 2692 2693 /* Number of milliseconds we wait for auto-negotiation to complete */ 2694 #define LINK_UP_TIMEOUT 500 2695 2696 /* Number of 100 microseconds we wait for PCI Express master disable */ 2697 #define MASTER_DISABLE_TIMEOUT 800 2698 /* Number of milliseconds we wait for Eeprom auto read bit done after MAC reset */ 2699 #define AUTO_READ_DONE_TIMEOUT 10 2700 /* Number of milliseconds we wait for PHY configuration done after MAC reset */ 2701 #define PHY_CFG_TIMEOUT 100 2702 /* SW Semaphore flag timeout in ms */ 2703 #define SW_FLAG_TIMEOUT 1000 2704 2705 #define E1000_TX_BUFFER_SIZE ((uint32_t)1514) 2706 2707 /* The carrier extension symbol, as received by the NIC. */ 2708 #define CARRIER_EXTENSION 0x0F 2709 2710 /* TBI_ACCEPT macro definition: 2711 * 2712 * This macro requires: 2713 * sc = a pointer to struct em_hw 2714 * status = the 8 bit status field of the RX descriptor with EOP set 2715 * error = the 8 bit error field of the RX descriptor with EOP set 2716 * length = the sum of all the length fields of the RX descriptors that 2717 * make up the current frame 2718 * last_byte = the last byte of the frame DMAed by the hardware 2719 * max_frame_length = the maximum frame length we want to accept. 2720 * min_frame_length = the minimum frame length we want to accept. 2721 * 2722 * This macro is a conditional that should be used in the interrupt 2723 * handler's Rx processing routine when RxErrors have been detected. 2724 * 2725 * Typical use: 2726 * ... 2727 * if (TBI_ACCEPT) { 2728 * accept_frame = TRUE; 2729 * em_tbi_adjust_stats(sc, MacAddress); 2730 * frame_length--; 2731 * } else { 2732 * accept_frame = FALSE; 2733 * } 2734 * ... 2735 */ 2736 2737 #define TBI_ACCEPT(sc, status, errors, length, last_byte) \ 2738 ((sc)->tbi_compatibility_on && \ 2739 (((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \ 2740 ((last_byte) == CARRIER_EXTENSION) && \ 2741 (((status) & E1000_RXD_STAT_VP) ? \ 2742 (((length) > ((sc)->min_frame_size - VLAN_TAG_SIZE)) && \ 2743 ((length) <= ((sc)->max_frame_size + 1))) : \ 2744 (((length) > (sc)->min_frame_size) && \ 2745 ((length) <= ((sc)->max_frame_size + VLAN_TAG_SIZE + 1))))) 2746 2747 /* Structures, enums, and macros for the PHY */ 2748 2749 /* Bit definitions for the Management Data IO (MDIO) and Management Data 2750 * Clock (MDC) pins in the Device Control Register. 2751 */ 2752 #define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0 2753 #define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0 2754 #define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2 2755 #define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2 2756 #define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3 2757 #define E1000_CTRL_MDC E1000_CTRL_SWDPIN3 2758 #define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR 2759 #define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA 2760 2761 /* PHY 1000 MII Register/Bit Definitions */ 2762 /* PHY Registers defined by IEEE */ 2763 #define PHY_CTRL 0x00 /* Control Register */ 2764 #define PHY_STATUS 0x01 /* Status Register */ 2765 #define PHY_ID1 0x02 /* Phy Id Reg (word 1) */ 2766 #define PHY_ID2 0x03 /* Phy Id Reg (word 2) */ 2767 #define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */ 2768 #define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */ 2769 #define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */ 2770 #define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */ 2771 #define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */ 2772 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */ 2773 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */ 2774 #define PHY_EXT_STATUS 0x0F /* Extended Status Reg */ 2775 2776 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ 2777 #define MAX_PHY_MULTI_PAGE_REG 0xF /* Registers equal on all pages */ 2778 2779 /* M88E1000 Specific Registers */ 2780 #define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */ 2781 #define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */ 2782 #define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */ 2783 #define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */ 2784 #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ 2785 #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ 2786 2787 #define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */ 2788 #define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */ 2789 #define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */ 2790 #define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */ 2791 #define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */ 2792 2793 #define M88E1543_PAGE_ADDR 0x16 /* Page Offset Register */ 2794 #define M88E1543_EEE_CTRL_1 0x0 2795 #define M88E1543_EEE_CTRL_1_MS 0x0001 /* EEE Master/Slave */ 2796 2797 #define M88E1512_CFG_REG_1 0x0010 2798 #define M88E1512_CFG_REG_2 0x0011 2799 #define M88E1512_CFG_REG_3 0x0007 2800 #define M88E1512_MODE 0x0014 2801 2802 /* BME1000 PHY Specific Control Register */ 2803 #define BME1000_PSCR_ENABLE_DOWNSHIFT 0x0800 /* 1 = enable downshift */ 2804 #define BM_PHY_PAGE_SELECT 22 /* Page Select for BM */ 2805 #define BM_REG_BIAS1 29 2806 #define BM_REG_BIAS2 30 2807 #define BM_PORT_CTRL_PAGE 769 2808 2809 #define IGP01E1000_IEEE_REGS_PAGE 0x0000 2810 #define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 2811 #define IGP01E1000_IEEE_FORCE_GIGA 0x0140 2812 2813 /* IGP01E1000 Specific Registers */ 2814 #define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ 2815 #define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ 2816 #define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ 2817 #define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ 2818 #define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ 2819 #define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ 2820 #define IGP02E1000_PHY_POWER_MGMT 0x19 2821 #define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ 2822 2823 /* IGP01E1000 AGC Registers - stores the cable length values*/ 2824 #define IGP01E1000_PHY_AGC_A 0x1172 2825 #define IGP01E1000_PHY_AGC_B 0x1272 2826 #define IGP01E1000_PHY_AGC_C 0x1472 2827 #define IGP01E1000_PHY_AGC_D 0x1872 2828 2829 /* IGP02E1000 AGC Registers for cable length values */ 2830 #define IGP02E1000_PHY_AGC_A 0x11B1 2831 #define IGP02E1000_PHY_AGC_B 0x12B1 2832 #define IGP02E1000_PHY_AGC_C 0x14B1 2833 #define IGP02E1000_PHY_AGC_D 0x18B1 2834 2835 /* IGP01E1000 DSP Reset Register */ 2836 #define IGP01E1000_PHY_DSP_RESET 0x1F33 2837 #define IGP01E1000_PHY_DSP_SET 0x1F71 2838 #define IGP01E1000_PHY_DSP_FFE 0x1F35 2839 2840 #define IGP01E1000_PHY_CHANNEL_NUM 4 2841 #define IGP02E1000_PHY_CHANNEL_NUM 4 2842 2843 #define IGP01E1000_PHY_AGC_PARAM_A 0x1171 2844 #define IGP01E1000_PHY_AGC_PARAM_B 0x1271 2845 #define IGP01E1000_PHY_AGC_PARAM_C 0x1471 2846 #define IGP01E1000_PHY_AGC_PARAM_D 0x1871 2847 2848 #define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000 2849 #define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000 2850 2851 #define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890 2852 #define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000 2853 #define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004 2854 #define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069 2855 2856 #define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A 2857 /* IGP01E1000 PCS Initialization register - stores the polarity status when 2858 * speed = 1000 Mbps. */ 2859 #define IGP01E1000_PHY_PCS_INIT_REG 0x00B4 2860 #define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5 2861 2862 #define IGP01E1000_ANALOG_REGS_PAGE 0x20C0 2863 2864 /* 82580 specific PHY registers */ 2865 #define I82580_ADDR_REG 16 2866 #define I82580_CFG_REG 22 2867 #define I82580_CFG_ASSERT_CRS_ON_TX (1 << 15) 2868 #define I82580_CFG_ENABLE_DOWNSHIFT (3 << 10) /* auto downshift 100/10 */ 2869 #define I82580_CTRL_REG 23 2870 #define I82580_CTRL_DOWNSHIFT_MASK (7 << 10) 2871 2872 /* Bits... 2873 * 15-5: page 2874 * 4-0: register offset 2875 */ 2876 #define GG82563_PAGE_SHIFT 5 2877 #define GG82563_REG(page, reg) \ 2878 (((page) << GG82563_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 2879 #define GG82563_MIN_ALT_REG 30 2880 2881 /* GG82563 Specific Registers */ 2882 #define GG82563_PHY_SPEC_CTRL \ 2883 GG82563_REG(0, 16) /* PHY Specific Control */ 2884 #define GG82563_PHY_SPEC_STATUS \ 2885 GG82563_REG(0, 17) /* PHY Specific Status */ 2886 #define GG82563_PHY_INT_ENABLE \ 2887 GG82563_REG(0, 18) /* Interrupt Enable */ 2888 #define GG82563_PHY_SPEC_STATUS_2 \ 2889 GG82563_REG(0, 19) /* PHY Specific Status 2 */ 2890 #define GG82563_PHY_RX_ERR_CNTR \ 2891 GG82563_REG(0, 21) /* Receive Error Counter */ 2892 #define GG82563_PHY_PAGE_SELECT \ 2893 GG82563_REG(0, 22) /* Page Select */ 2894 #define GG82563_PHY_SPEC_CTRL_2 \ 2895 GG82563_REG(0, 26) /* PHY Specific Control 2 */ 2896 #define GG82563_PHY_PAGE_SELECT_ALT \ 2897 GG82563_REG(0, 29) /* Alternate Page Select */ 2898 #define GG82563_PHY_TEST_CLK_CTRL \ 2899 GG82563_REG(0, 30) /* Test Clock Control (use reg. 29 to select) */ 2900 2901 #define GG82563_PHY_MAC_SPEC_CTRL \ 2902 GG82563_REG(2, 21) /* MAC Specific Control Register */ 2903 #define GG82563_PHY_MAC_SPEC_CTRL_2 \ 2904 GG82563_REG(2, 26) /* MAC Specific Control 2 */ 2905 2906 #define GG82563_PHY_DSP_DISTANCE \ 2907 GG82563_REG(5, 26) /* DSP Distance */ 2908 2909 /* Page 193 - Port Control Registers */ 2910 #define GG82563_PHY_KMRN_MODE_CTRL \ 2911 GG82563_REG(193, 16) /* Kumeran Mode Control */ 2912 #define GG82563_PHY_PORT_RESET \ 2913 GG82563_REG(193, 17) /* Port Reset */ 2914 #define GG82563_PHY_REVISION_ID \ 2915 GG82563_REG(193, 18) /* Revision ID */ 2916 #define GG82563_PHY_DEVICE_ID \ 2917 GG82563_REG(193, 19) /* Device ID */ 2918 #define GG82563_PHY_PWR_MGMT_CTRL \ 2919 GG82563_REG(193, 20) /* Power Management Control */ 2920 #define GG82563_PHY_RATE_ADAPT_CTRL \ 2921 GG82563_REG(193, 25) /* Rate Adaptation Control */ 2922 2923 /* Page 194 - KMRN Registers */ 2924 #define GG82563_PHY_KMRN_FIFO_CTRL_STAT \ 2925 GG82563_REG(194, 16) /* FIFO's Control/Status */ 2926 #define GG82563_PHY_KMRN_CTRL \ 2927 GG82563_REG(194, 17) /* Control */ 2928 #define GG82563_PHY_INBAND_CTRL \ 2929 GG82563_REG(194, 18) /* Inband Control */ 2930 #define GG82563_PHY_KMRN_DIAGNOSTIC \ 2931 GG82563_REG(194, 19) /* Diagnostic */ 2932 #define GG82563_PHY_ACK_TIMEOUTS \ 2933 GG82563_REG(194, 20) /* Acknowledge Timeouts */ 2934 #define GG82563_PHY_ADV_ABILITY \ 2935 GG82563_REG(194, 21) /* Advertised Ability */ 2936 #define GG82563_PHY_LINK_PARTNER_ADV_ABILITY \ 2937 GG82563_REG(194, 23) /* Link Partner Advertised Ability */ 2938 #define GG82563_PHY_ADV_NEXT_PAGE \ 2939 GG82563_REG(194, 24) /* Advertised Next Page */ 2940 #define GG82563_PHY_LINK_PARTNER_ADV_NEXT_PAGE \ 2941 GG82563_REG(194, 25) /* Link Partner Advertised Next page */ 2942 #define GG82563_PHY_KMRN_MISC \ 2943 GG82563_REG(194, 26) /* Misc. */ 2944 2945 /* I82577 Specific Registers */ 2946 #define I82577_PHY_ADDR_REG 16 2947 #define I82577_PHY_CFG_REG 22 2948 #define I82577_PHY_CTRL_REG 23 2949 2950 /* I82577 Config Register */ 2951 #define I82577_PHY_CFG_ENABLE_CRS_ON_TX (1 << 15) 2952 #define I82577_PHY_CFG_ENABLE_DOWNSHIFT ((1 << 10) + (1 << 11)) 2953 2954 /* I82578 Specific Registers */ 2955 #define I82578_PHY_ADDR_REG 29 2956 2957 /* I82578 Downshift settings (Extended PHY Specific Control Register) */ 2958 #define I82578_EPSCR_DOWNSHIFT_ENABLE 0x0020 2959 #define I82578_EPSCR_DOWNSHIFT_COUNTER_MASK 0x001C 2960 2961 /* PHY Control Register */ 2962 #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ 2963 #define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */ 2964 #define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */ 2965 #define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */ 2966 #define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */ 2967 #define MII_CR_POWER_DOWN 0x0800 /* Power down */ 2968 #define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */ 2969 #define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */ 2970 #define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */ 2971 #define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */ 2972 2973 /* PHY Status Register */ 2974 #define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */ 2975 #define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */ 2976 #define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */ 2977 #define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */ 2978 #define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */ 2979 #define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */ 2980 #define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */ 2981 #define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */ 2982 #define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */ 2983 #define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */ 2984 #define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */ 2985 #define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */ 2986 #define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */ 2987 #define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */ 2988 #define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */ 2989 2990 /* Autoneg Advertisement Register */ 2991 #define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */ 2992 #define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */ 2993 #define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */ 2994 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */ 2995 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */ 2996 #define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */ 2997 #define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */ 2998 #define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */ 2999 #define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */ 3000 #define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 3001 3002 /* Link Partner Ability Register (Base Page) */ 3003 #define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */ 3004 #define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */ 3005 #define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */ 3006 #define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */ 3007 #define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */ 3008 #define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */ 3009 #define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */ 3010 #define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */ 3011 #define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */ 3012 #define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */ 3013 #define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */ 3014 3015 /* Autoneg Expansion Register */ 3016 #define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */ 3017 #define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */ 3018 #define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */ 3019 #define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */ 3020 #define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */ 3021 3022 /* Next Page TX Register */ 3023 #define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 3024 #define NPTX_TOGGLE 0x0800 /* Toggles between exchanges 3025 * of different NP 3026 */ 3027 #define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 3028 * 0 = cannot comply with msg 3029 */ 3030 #define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 3031 #define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 3032 * 0 = sending last NP 3033 */ 3034 3035 /* Link Partner Next Page Register */ 3036 #define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */ 3037 #define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges 3038 * of different NP 3039 */ 3040 #define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg 3041 * 0 = cannot comply with msg 3042 */ 3043 #define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */ 3044 #define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */ 3045 #define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow 3046 * 0 = sending last NP 3047 */ 3048 3049 /* 1000BASE-T Control Register */ 3050 #define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */ 3051 #define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */ 3052 #define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */ 3053 #define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */ 3054 /* 0=DTE device */ 3055 #define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */ 3056 /* 0=Configure PHY as Slave */ 3057 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */ 3058 /* 0=Automatic Master/Slave config */ 3059 #define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */ 3060 #define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */ 3061 #define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */ 3062 #define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */ 3063 #define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */ 3064 3065 /* 1000BASE-T Status Register */ 3066 #define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */ 3067 #define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */ 3068 #define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */ 3069 #define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */ 3070 #define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */ 3071 #define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */ 3072 #define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */ 3073 #define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */ 3074 #define SR_1000T_REMOTE_RX_STATUS_SHIFT 12 3075 #define SR_1000T_LOCAL_RX_STATUS_SHIFT 13 3076 #define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5 3077 #define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20 3078 #define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100 3079 3080 /* Extended Status Register */ 3081 #define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */ 3082 #define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */ 3083 #define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */ 3084 #define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */ 3085 3086 #define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */ 3087 #define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */ 3088 3089 #define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */ 3090 /* (0=enable, 1=disable) */ 3091 3092 /* M88E1000 PHY Specific Control Register */ 3093 #define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */ 3094 #define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */ 3095 #define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */ 3096 #define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low, 3097 * 0=CLK125 toggling 3098 */ 3099 #define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */ 3100 /* Manual MDI configuration */ 3101 #define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */ 3102 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover, 3103 * 100BASE-TX/10BASE-T: 3104 * MDI Mode 3105 */ 3106 #define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled 3107 * all speeds. 3108 */ 3109 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080 3110 /* 1=Enable Extended 10BASE-T distance 3111 * (Lower 10BASE-T RX Threshold) 3112 * 0=Normal 10BASE-T RX Threshold */ 3113 #define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100 3114 /* 1=5-Bit interface in 100BASE-TX 3115 * 0=MII interface in 100BASE-TX */ 3116 #define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */ 3117 #define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */ 3118 #define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */ 3119 3120 #define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1 3121 #define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5 3122 #define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7 3123 3124 /* M88E1000 PHY Specific Status Register */ 3125 #define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */ 3126 #define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */ 3127 #define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */ 3128 #define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */ 3129 #define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M; 3130 * 3=110-140M;4=>140M */ 3131 #define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */ 3132 #define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */ 3133 #define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */ 3134 #define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */ 3135 #define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */ 3136 #define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */ 3137 #define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */ 3138 #define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */ 3139 3140 #define M88E1000_PSSR_REV_POLARITY_SHIFT 1 3141 #define M88E1000_PSSR_DOWNSHIFT_SHIFT 5 3142 #define M88E1000_PSSR_MDIX_SHIFT 6 3143 #define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7 3144 3145 /* M88E1000 Extended PHY Specific Control Register */ 3146 #define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */ 3147 #define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled. 3148 * Will assert lost lock and bring 3149 * link down if idle not seen 3150 * within 1ms in 1000BASE-T 3151 */ 3152 /* Number of times we will attempt to autonegotiate before downshifting if we 3153 * are the master */ 3154 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00 3155 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000 3156 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400 3157 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800 3158 #define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00 3159 /* Number of times we will attempt to autonegotiate before downshifting if we 3160 * are the slave */ 3161 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300 3162 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000 3163 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100 3164 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200 3165 #define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300 3166 #define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */ 3167 #define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */ 3168 #define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */ 3169 3170 /* M88EC018 Rev 2 specific DownShift settings */ 3171 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_MASK 0x0E00 3172 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_1X 0x0000 3173 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_2X 0x0200 3174 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_3X 0x0400 3175 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_4X 0x0600 3176 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_5X 0x0800 3177 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_6X 0x0A00 3178 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_7X 0x0C00 3179 #define M88EC018_EPSCR_DOWNSHIFT_COUNTER_8X 0x0E00 3180 3181 /* M88E1141 specific */ 3182 #define M88E1000_EPSCR_TX_TIME_CTRL 0x0002 /* Add Delay */ 3183 #define M88E1000_EPSCR_RX_TIME_CTRL 0x0080 /* Add Delay */ 3184 3185 /* IGP01E1000 Specific Port Config Register - R/W */ 3186 #define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010 3187 #define IGP01E1000_PSCFR_PRE_EN 0x0020 3188 #define IGP01E1000_PSCFR_SMART_SPEED 0x0080 3189 #define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100 3190 #define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400 3191 #define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000 3192 3193 /* IGP01E1000 Specific Port Status Register - R/O */ 3194 #define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */ 3195 #define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002 3196 #define IGP01E1000_PSSR_CABLE_LENGTH 0x007C 3197 #define IGP01E1000_PSSR_FULL_DUPLEX 0x0200 3198 #define IGP01E1000_PSSR_LINK_UP 0x0400 3199 #define IGP01E1000_PSSR_MDIX 0x0800 3200 #define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */ 3201 #define IGP01E1000_PSSR_SPEED_10MBPS 0x4000 3202 #define IGP01E1000_PSSR_SPEED_100MBPS 0x8000 3203 #define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000 3204 #define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */ 3205 #define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */ 3206 3207 /* IGP01E1000 Specific Port Control Register - R/W */ 3208 #define IGP01E1000_PSCR_TP_LOOPBACK 0x0010 3209 #define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200 3210 #define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400 3211 #define IGP01E1000_PSCR_FLIP_CHIP 0x0800 3212 #define IGP01E1000_PSCR_AUTO_MDIX 0x1000 3213 #define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */ 3214 3215 /* IGP01E1000 Specific Port Link Health Register */ 3216 #define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000 3217 #define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000 3218 #define IGP01E1000_PLHR_MASTER_FAULT 0x2000 3219 #define IGP01E1000_PLHR_MASTER_RESOLUTION 0x1000 3220 #define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */ 3221 #define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */ 3222 #define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */ 3223 #define IGP01E1000_PLHR_DATA_ERR_0 0x0100 3224 #define IGP01E1000_PLHR_AUTONEG_FAULT 0x0040 3225 #define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0010 3226 #define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0008 3227 #define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0004 3228 #define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0002 3229 #define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0001 3230 3231 /* IGP01E1000 Channel Quality Register */ 3232 #define IGP01E1000_MSE_CHANNEL_D 0x000F 3233 #define IGP01E1000_MSE_CHANNEL_C 0x00F0 3234 #define IGP01E1000_MSE_CHANNEL_B 0x0F00 3235 #define IGP01E1000_MSE_CHANNEL_A 0xF000 3236 3237 #define IGP02E1000_PM_SPD 0x0001 /* Smart Power Down */ 3238 #define IGP02E1000_PM_D3_LPLU 0x0004 /* Enable LPLU in non-D0a modes */ 3239 #define IGP02E1000_PM_D0_LPLU 0x0002 /* Enable LPLU in D0a mode */ 3240 3241 /* IGP01E1000 DSP reset macros */ 3242 #define DSP_RESET_ENABLE 0x0 3243 #define DSP_RESET_DISABLE 0x2 3244 #define E1000_MAX_DSP_RESETS 10 3245 3246 /* IGP01E1000 & IGP02E1000 AGC Registers */ 3247 3248 #define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */ 3249 #define IGP02E1000_AGC_LENGTH_SHIFT 9 /* Coarse - 15:13, Fine - 12:9 */ 3250 3251 /* IGP02E1000 AGC Register Length 9-bit mask */ 3252 #define IGP02E1000_AGC_LENGTH_MASK 0x7F 3253 3254 /* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */ 3255 #define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128 3256 #define IGP02E1000_AGC_LENGTH_TABLE_SIZE 113 3257 3258 /* The precision error of the cable length is +/- 10 meters */ 3259 #define IGP01E1000_AGC_RANGE 10 3260 #define IGP02E1000_AGC_RANGE 15 3261 3262 /* IGP01E1000 PCS Initialization register */ 3263 /* bits 3:6 in the PCS registers stores the channels polarity */ 3264 #define IGP01E1000_PHY_POLARITY_MASK 0x0078 3265 3266 /* IGP01E1000 GMII FIFO Register */ 3267 #define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed 3268 * on Link-Up */ 3269 #define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */ 3270 3271 /* IGP01E1000 Analog Register */ 3272 #define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1 3273 #define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0 3274 #define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC 3275 #define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE 3276 3277 #define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000 3278 #define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80 3279 #define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070 3280 #define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100 3281 #define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002 3282 3283 #define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040 3284 #define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010 3285 #define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080 3286 #define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500 3287 3288 /* GG82563 PHY Specific Status Register (Page 0, Register 16 */ 3289 #define GG82563_PSCR_DISABLE_JABBER 0x0001 /* 1=Disable Jabber */ 3290 #define GG82563_PSCR_POLARITY_REVERSAL_DISABLE 0x0002 /* 1=Polarity Reversal Disabled */ 3291 #define GG82563_PSCR_POWER_DOWN 0x0004 /* 1=Power Down */ 3292 #define GG82563_PSCR_COPPER_TRANSMITER_DISABLE 0x0008 /* 1=Transmitter Disabled */ 3293 #define GG82563_PSCR_CROSSOVER_MODE_MASK 0x0060 3294 #define GG82563_PSCR_CROSSOVER_MODE_MDI 0x0000 /* 00=Manual MDI configuration */ 3295 #define GG82563_PSCR_CROSSOVER_MODE_MDIX 0x0020 /* 01=Manual MDIX configuration */ 3296 #define GG82563_PSCR_CROSSOVER_MODE_AUTO 0x0060 /* 11=Automatic crossover */ 3297 #define GG82563_PSCR_ENALBE_EXTENDED_DISTANCE 0x0080 /* 1=Enable Extended Distance */ 3298 #define GG82563_PSCR_ENERGY_DETECT_MASK 0x0300 3299 #define GG82563_PSCR_ENERGY_DETECT_OFF 0x0000 /* 00,01=Off */ 3300 #define GG82563_PSCR_ENERGY_DETECT_RX 0x0200 /* 10=Sense on Rx only (Energy Detect) */ 3301 #define GG82563_PSCR_ENERGY_DETECT_RX_TM 0x0300 /* 11=Sense and Tx NLP */ 3302 #define GG82563_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force Link Good */ 3303 #define GG82563_PSCR_DOWNSHIFT_ENABLE 0x0800 /* 1=Enable Downshift */ 3304 #define GG82563_PSCR_DOWNSHIFT_COUNTER_MASK 0x7000 3305 #define GG82563_PSCR_DOWNSHIFT_COUNTER_SHIFT 12 3306 3307 /* PHY Specific Status Register (Page 0, Register 17) */ 3308 #define GG82563_PSSR_JABBER 0x0001 /* 1=Jabber */ 3309 #define GG82563_PSSR_POLARITY 0x0002 /* 1=Polarity Reversed */ 3310 #define GG82563_PSSR_LINK 0x0008 /* 1=Link is Up */ 3311 #define GG82563_PSSR_ENERGY_DETECT 0x0010 /* 1=Sleep, 0=Active */ 3312 #define GG82563_PSSR_DOWNSHIFT 0x0020 /* 1=Downshift */ 3313 #define GG82563_PSSR_CROSSOVER_STATUS 0x0040 /* 1=MDIX, 0=MDI */ 3314 #define GG82563_PSSR_RX_PAUSE_ENABLED 0x0100 /* 1=Receive Pause Enabled */ 3315 #define GG82563_PSSR_TX_PAUSE_ENABLED 0x0200 /* 1=Transmit Pause Enabled */ 3316 #define GG82563_PSSR_LINK_UP 0x0400 /* 1=Link Up */ 3317 #define GG82563_PSSR_SPEED_DUPLEX_RESOLVED 0x0800 /* 1=Resolved */ 3318 #define GG82563_PSSR_PAGE_RECEIVED 0x1000 /* 1=Page Received */ 3319 #define GG82563_PSSR_DUPLEX 0x2000 /* 1-Full-Duplex */ 3320 #define GG82563_PSSR_SPEED_MASK 0xC000 3321 #define GG82563_PSSR_SPEED_10MBPS 0x0000 /* 00=10Mbps */ 3322 #define GG82563_PSSR_SPEED_100MBPS 0x4000 /* 01=100Mbps */ 3323 #define GG82563_PSSR_SPEED_1000MBPS 0x8000 /* 10=1000Mbps */ 3324 3325 /* PHY Specific Status Register 2 (Page 0, Register 19) */ 3326 #define GG82563_PSSR2_JABBER 0x0001 /* 1=Jabber */ 3327 #define GG82563_PSSR2_POLARITY_CHANGED 0x0002 /* 1=Polarity Changed */ 3328 #define GG82563_PSSR2_ENERGY_DETECT_CHANGED 0x0010 /* 1=Energy Detect Changed */ 3329 #define GG82563_PSSR2_DOWNSHIFT_INTERRUPT 0x0020 /* 1=Downshift Detected */ 3330 #define GG82563_PSSR2_MDI_CROSSOVER_CHANGE 0x0040 /* 1=Crossover Changed */ 3331 #define GG82563_PSSR2_FALSE_CARRIER 0x0100 /* 1=False Carrier */ 3332 #define GG82563_PSSR2_SYMBOL_ERROR 0x0200 /* 1=Symbol Error */ 3333 #define GG82563_PSSR2_LINK_STATUS_CHANGED 0x0400 /* 1=Link Status Changed */ 3334 #define GG82563_PSSR2_AUTO_NEG_COMPLETED 0x0800 /* 1=Auto-Neg Completed */ 3335 #define GG82563_PSSR2_PAGE_RECEIVED 0x1000 /* 1=Page Received */ 3336 #define GG82563_PSSR2_DUPLEX_CHANGED 0x2000 /* 1=Duplex Changed */ 3337 #define GG82563_PSSR2_SPEED_CHANGED 0x4000 /* 1=Speed Changed */ 3338 #define GG82563_PSSR2_AUTO_NEG_ERROR 0x8000 /* 1=Auto-Neg Error */ 3339 3340 /* PHY Specific Control Register 2 (Page 0, Register 26) */ 3341 #define GG82563_PSCR2_10BT_POLARITY_FORCE 0x0002 /* 1=Force Negative Polarity */ 3342 #define GG82563_PSCR2_1000MB_TEST_SELECT_MASK 0x000C 3343 #define GG82563_PSCR2_1000MB_TEST_SELECT_NORMAL 0x0000 /* 00,01=Normal Operation */ 3344 #define GG82563_PSCR2_1000MB_TEST_SELECT_112NS 0x0008 /* 10=Select 112ns Sequence */ 3345 #define GG82563_PSCR2_1000MB_TEST_SELECT_16NS 0x000C /* 11=Select 16ns Sequence */ 3346 #define GG82563_PSCR2_REVERSE_AUTO_NEG 0x2000 /* 1=Reverse Auto-Negotiation */ 3347 #define GG82563_PSCR2_1000BT_DISABLE 0x4000 /* 1=Disable 1000BASE-T */ 3348 #define GG82563_PSCR2_TRANSMITER_TYPE_MASK 0x8000 3349 #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_B 0x0000 /* 0=Class B */ 3350 #define GG82563_PSCR2_TRANSMITTER_TYPE_CLASS_A 0x8000 /* 1=Class A */ 3351 3352 /* MAC Specific Control Register (Page 2, Register 21) */ 3353 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */ 3354 #define GG82563_MSCR_TX_CLK_MASK 0x0007 3355 #define GG82563_MSCR_TX_CLK_10MBPS_2_5MHZ 0x0004 3356 #define GG82563_MSCR_TX_CLK_100MBPS_25MHZ 0x0005 3357 #define GG82563_MSCR_TX_CLK_1000MBPS_2_5MHZ 0x0006 3358 #define GG82563_MSCR_TX_CLK_1000MBPS_25MHZ 0x0007 3359 3360 #define GG82563_MSCR_ASSERT_CRS_ON_TX 0x0010 /* 1=Assert */ 3361 3362 /* DSP Distance Register (Page 5, Register 26) */ 3363 #define GG82563_DSPD_CABLE_LENGTH 0x0007 /* 0 = <50M; 3364 1 = 50-80M; 3365 2 = 80-110M; 3366 3 = 110-140M; 3367 4 = >140M */ 3368 3369 /* Kumeran Mode Control Register (Page 193, Register 16) */ 3370 #define GG82563_KMCR_PHY_LEDS_EN 0x0020 /* 1=PHY LEDs, 0=Kumeran Inband LEDs */ 3371 #define GG82563_KMCR_FORCE_LINK_UP 0x0040 /* 1=Force Link Up */ 3372 #define GG82563_KMCR_SUPPRESS_SGMII_EPD_EXT 0x0080 3373 #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT_MASK 0x0400 3374 #define GG82563_KMCR_MDIO_BUS_SPEED_SELECT 0x0400 /* 1=6.25MHz, 0=0.8MHz */ 3375 #define GG82563_KMCR_PASS_FALSE_CARRIER 0x0800 3376 3377 /* Power Management Control Register (Page 193, Register 20) */ 3378 #define GG82563_PMCR_ENABLE_ELECTRICAL_IDLE 0x0001 /* 1=Enable SERDES Electrical Idle */ 3379 #define GG82563_PMCR_DISABLE_PORT 0x0002 /* 1=Disable Port */ 3380 #define GG82563_PMCR_DISABLE_SERDES 0x0004 /* 1=Disable SERDES */ 3381 #define GG82563_PMCR_REVERSE_AUTO_NEG 0x0008 /* 1=Enable Reverse Auto-Negotiation */ 3382 #define GG82563_PMCR_DISABLE_1000_NON_D0 0x0010 /* 1=Disable 1000Mbps Auto-Neg in non D0 */ 3383 #define GG82563_PMCR_DISABLE_1000 0x0020 /* 1=Disable 1000Mbps Auto-Neg Always */ 3384 #define GG82563_PMCR_REVERSE_AUTO_NEG_D0A 0x0040 /* 1=Enable D0a Reverse Auto-Negotiation */ 3385 #define GG82563_PMCR_FORCE_POWER_STATE 0x0080 /* 1=Force Power State */ 3386 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_MASK 0x0300 3387 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_DR 0x0000 /* 00=Dr */ 3388 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0U 0x0100 /* 01=D0u */ 3389 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D0A 0x0200 /* 10=D0a */ 3390 #define GG82563_PMCR_PROGRAMMED_POWER_STATE_D3 0x0300 /* 11=D3 */ 3391 3392 /* In-Band Control Register (Page 194, Register 18) */ 3393 #define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */ 3394 3395 /* Bit definitions for valid PHY IDs. */ 3396 /* I = Integrated 3397 * E = External 3398 */ 3399 #define M88_VENDOR 0x0141 3400 #define M88E1000_E_PHY_ID 0x01410C50 3401 #define M88E1000_I_PHY_ID 0x01410C30 3402 #define M88E1011_I_PHY_ID 0x01410C20 3403 #define IGP01E1000_I_PHY_ID 0x02A80380 3404 #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID 3405 #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID 3406 #define M88E1011_I_REV_4 0x04 3407 #define M88E1111_I_PHY_ID 0x01410CC0 3408 #define M88E1112_E_PHY_ID 0x01410C90 3409 #define I347AT4_E_PHY_ID 0x01410DC0 3410 #define L1LXT971A_PHY_ID 0x001378E0 3411 #define GG82563_E_PHY_ID 0x01410CA0 3412 #define BME1000_E_PHY_ID 0x01410CB0 3413 #define BME1000_E_PHY_ID_R2 0x01410CB1 3414 #define M88E1543_E_PHY_ID 0x01410EA0 3415 #define I82577_E_PHY_ID 0x01540050 3416 #define I82578_E_PHY_ID 0x004DD040 3417 #define I82579_E_PHY_ID 0x01540090 3418 #define I217_E_PHY_ID 0x015400A0 3419 #define I82580_I_PHY_ID 0x015403A0 3420 #define I350_I_PHY_ID 0x015403B0 3421 #define I210_I_PHY_ID 0x01410C00 3422 #define IGP04E1000_E_PHY_ID 0x02A80391 3423 #define M88E1141_E_PHY_ID 0x01410CD0 3424 #define M88E1512_E_PHY_ID 0x01410DD0 3425 3426 /* Bits... 3427 * 15-5: page 3428 * 4-0: register offset 3429 */ 3430 #define PHY_PAGE_SHIFT 5 3431 #define PHY_REG(page, reg) \ 3432 (((page) << PHY_PAGE_SHIFT) | ((reg) & MAX_PHY_REG_ADDRESS)) 3433 3434 #define IGP3_PHY_PORT_CTRL \ 3435 PHY_REG(769, 17) /* Port General Configuration */ 3436 #define IGP3_PHY_RATE_ADAPT_CTRL \ 3437 PHY_REG(769, 25) /* Rate Adapter Control Register */ 3438 3439 #define IGP3_KMRN_FIFO_CTRL_STATS \ 3440 PHY_REG(770, 16) /* KMRN FIFO's control/status register */ 3441 #define IGP3_KMRN_POWER_MNG_CTRL \ 3442 PHY_REG(770, 17) /* KMRN Power Management Control Register */ 3443 #define IGP3_KMRN_INBAND_CTRL \ 3444 PHY_REG(770, 18) /* KMRN Inband Control Register */ 3445 #define IGP3_KMRN_DIAG \ 3446 PHY_REG(770, 19) /* KMRN Diagnostic register */ 3447 #define IGP3_KMRN_DIAG_PCS_LOCK_LOSS 0x0002 /* RX PCS is not synced */ 3448 #define IGP3_KMRN_ACK_TIMEOUT \ 3449 PHY_REG(770, 20) /* KMRN Acknowledge Timeouts register */ 3450 3451 #define IGP3_VR_CTRL \ 3452 PHY_REG(776, 18) /* Voltage regulator control register */ 3453 #define IGP3_VR_CTRL_MODE_SHUT 0x0200 /* Enter powerdown, shutdown VRs */ 3454 #define IGP3_VR_CTRL_MODE_MASK 0x0300 /* Shutdown VR Mask */ 3455 3456 #define IGP3_CAPABILITY \ 3457 PHY_REG(776, 19) /* IGP3 Capability Register */ 3458 3459 /* Capabilities for SKU Control */ 3460 #define IGP3_CAP_INITIATE_TEAM 0x0001 /* Able to initiate a team */ 3461 #define IGP3_CAP_WFM 0x0002 /* Support WoL and PXE */ 3462 #define IGP3_CAP_ASF 0x0004 /* Support ASF */ 3463 #define IGP3_CAP_LPLU 0x0008 /* Support Low Power Link Up */ 3464 #define IGP3_CAP_DC_AUTO_SPEED 0x0010 /* Support AC/DC Auto Link Speed */ 3465 #define IGP3_CAP_SPD 0x0020 /* Support Smart Power Down */ 3466 #define IGP3_CAP_MULT_QUEUE 0x0040 /* Support 2 tx & 2 rx queues */ 3467 #define IGP3_CAP_RSS 0x0080 /* Support RSS */ 3468 #define IGP3_CAP_8021PQ 0x0100 /* Support 802.1Q & 802.1p */ 3469 #define IGP3_CAP_AMT_CB 0x0200 /* Support active manageability and circuit breaker */ 3470 3471 #define IGP3_PPC_JORDAN_EN 0x0001 3472 #define IGP3_PPC_JORDAN_GIGA_SPEED 0x0002 3473 3474 #define IGP3_KMRN_PMC_EE_IDLE_LINK_DIS 0x0001 3475 #define IGP3_KMRN_PMC_K0S_ENTRY_LATENCY_MASK 0x001E 3476 #define IGP3_KMRN_PMC_K0S_MODE1_EN_GIGA 0x0020 3477 #define IGP3_KMRN_PMC_K0S_MODE1_EN_100 0x0040 3478 3479 #define IGP3E1000_PHY_MISC_CTRL 0x1B /* Misc. Ctrl register */ 3480 #define IGP3_PHY_MISC_DUPLEX_MANUAL_SET 0x1000 /* Duplex Manual Set */ 3481 3482 #define IGP3_KMRN_EXT_CTRL PHY_REG(770, 18) 3483 #define IGP3_KMRN_EC_DIS_INBAND 0x0080 3484 3485 #define IGP03E1000_E_PHY_ID 0x02A80390 3486 #define IFE_E_PHY_ID 0x02A80330 /* 10/100 PHY */ 3487 #define IFE_PLUS_E_PHY_ID 0x02A80320 3488 #define IFE_C_E_PHY_ID 0x02A80310 3489 3490 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10 /* 100BaseTx Extended Status, Control and Address */ 3491 #define IFE_PHY_SPECIAL_CONTROL 0x11 /* 100BaseTx PHY special control register */ 3492 #define IFE_PHY_RCV_FALSE_CARRIER 0x13 /* 100BaseTx Receive False Carrier Counter */ 3493 #define IFE_PHY_RCV_DISCONNECT 0x14 /* 100BaseTx Receive Disconnect Counter */ 3494 #define IFE_PHY_RCV_ERROT_FRAME 0x15 /* 100BaseTx Receive Error Frame Counter */ 3495 #define IFE_PHY_RCV_SYMBOL_ERR 0x16 /* Receive Symbol Error Counter */ 3496 #define IFE_PHY_PREM_EOF_ERR 0x17 /* 100BaseTx Receive Premature End Of Frame Error Counter */ 3497 #define IFE_PHY_RCV_EOF_ERR 0x18 /* 10BaseT Receive End Of Frame Error Counter */ 3498 #define IFE_PHY_TX_JABBER_DETECT 0x19 /* 10BaseT Transmit Jabber Detect Counter */ 3499 #define IFE_PHY_EQUALIZER 0x1A /* PHY Equalizer Control and Status */ 3500 #define IFE_PHY_SPECIAL_CONTROL_LED 0x1B /* PHY special control and LED configuration */ 3501 #define IFE_PHY_MDIX_CONTROL 0x1C /* MDI/MDI-X Control register */ 3502 #define IFE_PHY_HWI_CONTROL 0x1D /* Hardware Integrity Control (HWI) */ 3503 3504 #define IFE_PESC_REDUCED_POWER_DOWN_DISABLE 0x2000 /* Default 1 = Disable auto reduced power down */ 3505 #define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */ 3506 #define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */ 3507 #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */ 3508 #define IFE_PESC_PHY_ADDR_MASK 0x007C /* Bit 6:2 for sampled PHY address */ 3509 #define IFE_PESC_SPEED 0x0002 /* Auto-negotiation speed result 1=100Mbs, 0=10Mbs */ 3510 #define IFE_PESC_DUPLEX 0x0001 /* Auto-negotiation duplex result 1=Full, 0=Half */ 3511 #define IFE_PESC_POLARITY_REVERSED_SHIFT 8 3512 3513 #define IFE_PSC_DISABLE_DYNAMIC_POWER_DOWN 0x0100 /* 1 = Dynamic Power Down disabled */ 3514 #define IFE_PSC_FORCE_POLARITY 0x0020 /* 1=Reversed Polarity, 0=Normal */ 3515 #define IFE_PSC_AUTO_POLARITY_DISABLE 0x0010 /* 1=Auto Polarity Disabled, 0=Enabled */ 3516 #define IFE_PSC_JABBER_FUNC_DISABLE 0x0001 /* 1=Jabber Disabled, 0=Normal Jabber Operation */ 3517 #define IFE_PSC_FORCE_POLARITY_SHIFT 5 3518 #define IFE_PSC_AUTO_POLARITY_DISABLE_SHIFT 4 3519 3520 #define IFE_PMC_AUTO_MDIX 0x0080 /* 1=enable MDI/MDI-X feature, default 0=disabled */ 3521 #define IFE_PMC_FORCE_MDIX 0x0040 /* 1=force MDIX-X, 0=force MDI */ 3522 #define IFE_PMC_MDIX_STATUS 0x0020 /* 1=MDI-X, 0=MDI */ 3523 #define IFE_PMC_AUTO_MDIX_COMPLETE 0x0010 /* Resolution algorithm is completed */ 3524 #define IFE_PMC_MDIX_MODE_SHIFT 6 3525 #define IFE_PHC_MDIX_RESET_ALL_MASK 0x0000 /* Disable auto MDI-X */ 3526 3527 #define IFE_PHC_HWI_ENABLE 0x8000 /* Enable the HWI feature */ 3528 #define IFE_PHC_ABILITY_CHECK 0x4000 /* 1= Test Passed, 0=failed */ 3529 #define IFE_PHC_TEST_EXEC 0x2000 /* PHY launch test pulses on the wire */ 3530 #define IFE_PHC_HIGHZ 0x0200 /* 1 = Open Circuit */ 3531 #define IFE_PHC_LOWZ 0x0400 /* 1 = Short Circuit */ 3532 #define IFE_PHC_LOW_HIGH_Z_MASK 0x0600 /* Mask for indication type of problem on the line */ 3533 #define IFE_PHC_DISTANCE_MASK 0x01FF /* Mask for distance to the cable problem, in 80cm granularity */ 3534 #define IFE_PHC_RESET_ALL_MASK 0x0000 /* Disable HWI */ 3535 #define IFE_PSCL_PROBE_MODE 0x0020 /* LED Probe mode */ 3536 #define IFE_PSCL_PROBE_LEDS_OFF 0x0006 /* Force LEDs 0 and 2 off */ 3537 #define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */ 3538 3539 #define ICH_FLASH_COMMAND_TIMEOUT 5000 /* 5000 uSecs - adjusted */ 3540 #define ICH_FLASH_ERASE_TIMEOUT 3000000 /* Up to 3 seconds - worst case */ 3541 #define ICH_FLASH_CYCLE_REPEAT_COUNT 10 /* 10 cycles */ 3542 #define ICH_FLASH_SEG_SIZE_256 256 3543 #define ICH_FLASH_SEG_SIZE_4K 4096 3544 #define ICH_FLASH_SEG_SIZE_8K 8192 3545 #define ICH_FLASH_SEG_SIZE_64K 65536 3546 3547 #define ICH_CYCLE_READ 0x0 3548 #define ICH_CYCLE_RESERVED 0x1 3549 #define ICH_CYCLE_WRITE 0x2 3550 #define ICH_CYCLE_ERASE 0x3 3551 3552 #define ICH_FLASH_GFPREG 0x0000 3553 #define ICH_FLASH_HSFSTS 0x0004 3554 #define ICH_FLASH_HSFCTL 0x0006 3555 #define ICH_FLASH_FADDR 0x0008 3556 #define ICH_FLASH_FDATA0 0x0010 3557 #define ICH_FLASH_FRACC 0x0050 3558 #define ICH_FLASH_FREG0 0x0054 3559 #define ICH_FLASH_FREG1 0x0058 3560 #define ICH_FLASH_FREG2 0x005C 3561 #define ICH_FLASH_FREG3 0x0060 3562 #define ICH_FLASH_FPR0 0x0074 3563 #define ICH_FLASH_FPR1 0x0078 3564 #define ICH_FLASH_SSFSTS 0x0090 3565 #define ICH_FLASH_SSFCTL 0x0092 3566 #define ICH_FLASH_PREOP 0x0094 3567 #define ICH_FLASH_OPTYPE 0x0096 3568 #define ICH_FLASH_OPMENU 0x0098 3569 3570 #define ICH_FLASH_REG_MAPSIZE 0x00A0 3571 #define ICH_FLASH_SECTOR_SIZE 4096 3572 #define ICH_GFPREG_BASE_MASK 0x1FFF 3573 #define ICH_FLASH_LINEAR_ADDR_MASK 0x00FFFFFF 3574 #define ICH_FLASH_SECT_ADDR_SHIFT 12 3575 3576 /* ICH8 GbE Flash Hardware Sequencing Flash Status Register bit breakdown */ 3577 /* Offset 04h HSFSTS */ 3578 union ich8_hws_flash_status { 3579 struct ich8_hsfsts { 3580 uint16_t flcdone :1; /* bit 0 Flash Cycle Done */ 3581 uint16_t flcerr :1; /* bit 1 Flash Cycle Error */ 3582 uint16_t dael :1; /* bit 2 Direct Access error Log */ 3583 uint16_t berasesz :2; /* bit 4:3 Block/Sector Erase Size */ 3584 uint16_t flcinprog :1; /* bit 5 flash SPI cycle in Progress */ 3585 uint16_t reserved1 :2; /* bit 13:6 Reserved */ 3586 uint16_t reserved2 :6; /* bit 13:6 Reserved */ 3587 uint16_t fldesvalid :1; /* bit 14 Flash Descriptor Valid */ 3588 uint16_t flockdn :1; /* bit 15 Flash Configuration Lock-Down */ 3589 } hsf_status; 3590 uint16_t regval; 3591 }; 3592 3593 /* ICH8 GbE Flash Hardware Sequencing Flash control Register bit breakdown */ 3594 /* Offset 06h FLCTL */ 3595 union ich8_hws_flash_ctrl { 3596 struct ich8_hsflctl { 3597 uint16_t flcgo :1; /* 0 Flash Cycle Go */ 3598 uint16_t flcycle :2; /* 2:1 Flash Cycle */ 3599 uint16_t reserved :5; /* 7:3 Reserved */ 3600 uint16_t fldbcount :2; /* 9:8 Flash Data Byte Count */ 3601 uint16_t flockdn :6; /* 15:10 Reserved */ 3602 } hsf_ctrl; 3603 uint16_t regval; 3604 }; 3605 3606 /* ICH8 Flash Region Access Permissions */ 3607 union ich8_hws_flash_regacc { 3608 struct ich8_flracc { 3609 uint32_t grra :8; /* 0:7 GbE region Read Access */ 3610 uint32_t grwa :8; /* 8:15 GbE region Write Access */ 3611 uint32_t gmrag :8; /* 23:16 GbE Master Read Access Grant */ 3612 uint32_t gmwag :8; /* 31:24 GbE Master Write Access Grant */ 3613 } hsf_flregacc; 3614 uint16_t regval; 3615 }; 3616 3617 /* Miscellaneous PHY bit definitions. */ 3618 #define PHY_PREAMBLE 0xFFFFFFFF 3619 #define PHY_SOF 0x01 3620 #define PHY_OP_READ 0x02 3621 #define PHY_OP_WRITE 0x01 3622 #define PHY_TURNAROUND 0x02 3623 #define PHY_PREAMBLE_SIZE 32 3624 #define MII_CR_SPEED_1000 0x0040 3625 #define MII_CR_SPEED_100 0x2000 3626 #define MII_CR_SPEED_10 0x0000 3627 #define E1000_PHY_ADDRESS 0x01 3628 #define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 3629 #define PHY_FORCE_TIME 20 /* 2.0 Seconds */ 3630 #define PHY_REVISION_MASK 0xFFFFFFF0 3631 #define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */ 3632 #define REG4_SPEED_MASK 0x01E0 3633 #define REG9_SPEED_MASK 0x0300 3634 #define ADVERTISE_10_HALF 0x0001 3635 #define ADVERTISE_10_FULL 0x0002 3636 #define ADVERTISE_100_HALF 0x0004 3637 #define ADVERTISE_100_FULL 0x0008 3638 #define ADVERTISE_1000_HALF 0x0010 3639 #define ADVERTISE_1000_FULL 0x0020 3640 #define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */ 3641 #define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/ 3642 #define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/ 3643 3644 /* ICP PCI Dev ID xxxx macros to calculate word offsets for IA, IPv4 and IPv6 */ 3645 #define EEPROM_MGMT_CONTROL_ICP_xxxx(device_num) (((device_num) + 1) << 4) 3646 #define EEPROM_INIT_CONTROL3_ICP_xxxx(device_num) ((((device_num) + 1) << 4) + 1) 3647 #define EEPROM_IA_START_ICP_xxxx(device_num) ((((device_num) + 1) << 4) + 2) 3648 #define EEPROM_IPV4_START_ICP_xxxx(device_num) ((((device_num) + 1) << 4) + 5) 3649 #define EEPROM_IPV6_START_ICP_xxxx(device_num) ((((device_num) + 1) << 4) + 7) 3650 #define EEPROM_CHECKSUM_REG_ICP_xxxx EEPROM_CHECKSUM_REG 3651 #define PCI_CAP_ID_ST 0x09 3652 #define PCI_ST_SMIA_OFFSET 0x04 3653 3654 #define E1000_IMC1 0x008D8 /* Interrupt Mask Clear 1 - RW */ 3655 #define E1000_IMC2 0x008F8 /* Interrupt Mask Clear 2 - RW */ 3656 #define E1000_82542_IMC1 E1000_IMC1 3657 #define E1000_82542_IMC2 E1000_IMC2 3658 3659 #define E1000_NVM_K1_CONFIG 0x1B /* NVM K1 Config Word */ 3660 #define E1000_NVM_K1_ENABLE 0x1 /* NVM Enable K1 bit */ 3661 3662 #define E1000_KMRNCTRLSTA_OFFSET 0x001F0000 3663 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT 16 3664 #define E1000_KMRNCTRLSTA_REN 0x00200000 3665 #define E1000_KMRNCTRLSTA_DIAG_OFFSET 0x3 /* Diagnostic */ 3666 #define E1000_KMRNCTRLSTA_TIMEOUTS 0x4 /* Timeouts */ 3667 #define E1000_KMRNCTRLSTA_INBAND_PARAM 0x9 /* InBand Parameters */ 3668 #define E1000_KMRNCTRLSTA_DIAG_NELPBK 0x1000 /* Loopback mode */ 3669 #define E1000_KMRNCTRLSTA_K1_CONFIG 0x7 3670 #define E1000_KMRNCTRLSTA_K1_ENABLE 0x0002 3671 3672 3673 /* Extended Configuration Control and Size */ 3674 #define E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP 0x00000020 3675 #define E1000_EXTCNF_CTRL_LCD_WRITE_ENABLE 0x00000001 3676 #define E1000_EXTCNF_CTRL_OEM_WRITE_ENABLE 0x00000008 3677 #define E1000_EXTCNF_CTRL_SWFLAG 0x00000020 3678 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_MASK 0x00FF0000 3679 #define E1000_EXTCNF_SIZE_EXT_PCIE_LENGTH_SHIFT 16 3680 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_MASK 0x0FFF0000 3681 #define E1000_EXTCNF_CTRL_EXT_CNF_POINTER_SHIFT 16 3682 3683 /* SMBus Control Phy Register */ 3684 #define CV_SMB_CTRL PHY_REG(769, 23) 3685 #define CV_SMB_CTRL_FORCE_SMBUS 0x0001 3686 3687 /* I218 Ultra Low Power Configuration 1 Register */ 3688 #define I218_ULP_CONFIG1 PHY_REG(779, 16) 3689 #define I218_ULP_CONFIG1_START 0x0001 /* Start auto ULP config */ 3690 #define I218_ULP_CONFIG1_IND 0x0004 /* Pwr up from ULP indication */ 3691 #define I218_ULP_CONFIG1_STICKY_ULP 0x0010 /* Set sticky ULP mode */ 3692 #define I218_ULP_CONFIG1_INBAND_EXIT 0x0020 /* Inband on ULP exit */ 3693 #define I218_ULP_CONFIG1_WOL_HOST 0x0040 /* WoL Host on ULP exit */ 3694 #define I218_ULP_CONFIG1_RESET_TO_SMBUS 0x0100 /* Reset to SMBus mode */ 3695 /* enable ULP even if when phy powered down via lanphypc */ 3696 #define I218_ULP_CONFIG1_EN_ULP_LANPHYPC 0x0400 3697 /* disable clear of sticky ULP on PERST */ 3698 #define I218_ULP_CONFIG1_DIS_CLR_STICKY_ON_PERST 0x0800 3699 #define I218_ULP_CONFIG1_DISABLE_SMB_PERST 0x1000 /* Disable on PERST# */ 3700 3701 /* Hanksville definitions */ 3702 #define HV_INTC_FC_PAGE_START 768 3703 3704 #define HV_SCC_UPPER PHY_REG(778, 16) /* Single Collision Count */ 3705 #define HV_SCC_LOWER PHY_REG(778, 17) 3706 #define HV_ECOL_UPPER PHY_REG(778, 18) /* Excessive Collision Count */ 3707 #define HV_ECOL_LOWER PHY_REG(778, 19) 3708 #define HV_MCC_UPPER PHY_REG(778, 20) /* Multiple Collision Count */ 3709 #define HV_MCC_LOWER PHY_REG(778, 21) 3710 #define HV_LATECOL_UPPER PHY_REG(778, 23) /* Late Collision Count */ 3711 #define HV_LATECOL_LOWER PHY_REG(778, 24) 3712 #define HV_COLC_UPPER PHY_REG(778, 25) /* Collision Count */ 3713 #define HV_COLC_LOWER PHY_REG(778, 26) 3714 #define HV_DC_UPPER PHY_REG(778, 27) /* Defer Count */ 3715 #define HV_DC_LOWER PHY_REG(778, 28) 3716 #define HV_TNCRS_UPPER PHY_REG(778, 29) /* Transmit with no CRS */ 3717 #define HV_TNCRS_LOWER PHY_REG(778, 30) 3718 3719 /* OEM Bits Phy Register */ 3720 #define HV_OEM_BITS PHY_REG(768, 25) 3721 #define HV_OEM_BITS_LPLU 0x0004 /* Low Power Link Up */ 3722 #define HV_OEM_BITS_GBE_DIS 0x0040 /* Gigabit Disable */ 3723 #define HV_OEM_BITS_RESTART_AN 0x0400 /* Restart Auto-negotiation */ 3724 3725 #define HV_MUX_DATA_CTRL PHY_REG(776, 16) 3726 #define HV_MUX_DATA_CTRL_GEN_TO_MAC 0x0400 3727 #define HV_MUX_DATA_CTRL_FORCE_SPEED 0x0004 3728 3729 #define HV_KMRN_MODE_CTRL PHY_REG(769, 16) 3730 #define HV_KMRN_MDIO_SLOW 0x0400 3731 3732 /* PHY Power Management Control */ 3733 #define HV_PM_CTRL PHY_REG(770, 17) 3734 #define HV_PM_CTRL_K1_CLK_REQ 0x200 3735 #define HV_PM_CTRL_K1_ENABLE 0x4000 3736 3737 /* I217 definitions */ 3738 #define I2_DFT_CTRL PHY_REG(769, 20) 3739 #define I2_SMBUS_CTRL PHY_REG(769, 23) 3740 #define I2_MODE_CTRL HV_KMRN_MODE_CTRL 3741 #define I2_PCIE_POWER_CTRL IGP3_KMRN_POWER_MNG_CTRL 3742 3743 /* FEXTNVM registers */ 3744 #define E1000_FEXTNVM7 0xe4UL 3745 #define E1000_FEXTNVM7_SIDE_CLK_UNGATE 0x04UL 3746 #define E1000_FEXTNVM7_DISABLE_SMB_PERST 0x00000020 3747 #define E1000_FEXTNVM9 0x5bb4UL 3748 #define E1000_FEXTNVM9_IOSFSB_CLKGATE_DIS 0x0800UL 3749 #define E1000_FEXTNVM9_IOSFSB_CLKREQ_DIS 0x1000UL 3750 #define E1000_FEXTNVM11 0x05bbc 3751 #define E1000_FEXTNVM11_DISABLE_MULR_FIX 0x00002000 3752 3753 /* BM/HV Specific Registers */ 3754 #define BM_PORT_CTRL_PAGE 769 3755 #define BM_PCIE_PAGE 770 3756 #define BM_WUC_PAGE 800 3757 #define BM_WUC_ADDRESS_OPCODE 0x11 3758 #define BM_WUC_DATA_OPCODE 0x12 3759 #define BM_WUC_ENABLE_PAGE BM_PORT_CTRL_PAGE 3760 #define BM_WUC_ENABLE_REG 17 3761 #define BM_WUC_ENABLE_BIT (1 << 2) 3762 #define BM_WUC_HOST_WU_BIT (1 << 4) 3763 3764 /* BM PHY Copper Specific Status */ 3765 #define BM_CS_STATUS 17 3766 #define BM_CS_STATUS_ENERGY_DETECT 0x0010 /* Energy Detect Status */ 3767 #define BM_CS_STATUS_LINK_UP 0x0400 3768 #define BM_CS_STATUS_RESOLVED 0x0800 3769 #define BM_CS_STATUS_SPEED_MASK 0xC000 3770 #define BM_CS_STATUS_SPEED_1000 0x8000 3771 3772 /* 82577 Mobile Phy Status Register */ 3773 #define HV_M_STATUS 26 3774 #define HV_M_STATUS_AUTONEG_COMPLETE 0x1000 3775 #define HV_M_STATUS_SPEED_MASK 0x0300 3776 #define HV_M_STATUS_SPEED_1000 0x0200 3777 #define HV_M_STATUS_LINK_UP 0x0040 3778 3779 /* Inband Control */ 3780 #define I217_INBAND_CTRL PHY_REG(770, 18) 3781 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_MASK 0x3F00 3782 #define I217_INBAND_CTRL_LINK_STAT_TX_TIMEOUT_SHIFT 8 3783 3784 /* PHY Low Power Idle Control */ 3785 #define I82579_LPI_CTRL PHY_REG(772, 20) 3786 #define I82579_LPI_CTRL_ENABLE_MASK 0x6000 3787 #define I82579_LPI_CTRL_FORCE_PLL_LOCK_COUNT 0x80 3788 3789 /* EMI Registers */ 3790 #define I82579_EMI_ADDR 0x10 3791 #define I82579_EMI_DATA 0x11 3792 #define I82579_LPI_UPDATE_TIMER 0x4805 /* in 40ns units + 40 ns base value */ 3793 #define I82579_MSE_THRESHOLD 0x084F /* Mean Square Error Threshold */ 3794 #define I82579_MSE_LINK_DOWN 0x2411 /* MSE count before dropping link */ 3795 3796 /* INVM Registers for i210 */ 3797 #define E1000_INVM_DATA_REG(reg) (0x12120 + 4*(reg)) 3798 #define INVM_SIZE 64 /* Number of INVM Data Registers */ 3799 3800 /* NVM offset defaults for i211 */ 3801 #define NVM_INIT_CTRL_2_DEFAULT_I211 0x7243 3802 #define NVM_INIT_CTRL_4_DEFAULT_I211 0x00C1 3803 #define NVM_LED_1_CFG_DEFAULT_I211 0x0184 3804 #define NVM_LED_0_2_CFG_DEFAULT_I211 0x200C 3805 #define NVM_RESERVED_WORD 0xFFFF 3806 3807 #define INVM_DWORD_TO_RECORD_TYPE(dword) ((dword) & 0x7) 3808 #define INVM_DWORD_TO_WORD_ADDRESS(dword) (((dword) & 0x0000FE00) >> 9) 3809 #define INVM_DWORD_TO_WORD_DATA(dword) (((dword) & 0xFFFF0000) >> 16) 3810 3811 #define INVM_UNINITIALIZED_STRUCTURE 0x0 3812 #define INVM_WORD_AUTOLOAD_STRUCTURE 0x1 3813 #define INVM_CSR_AUTOLOAD_STRUCTURE 0x2 3814 #define INVM_PHY_REGISTER_AUTOLOAD_STRUCTURE 0x3 3815 #define INVM_RSA_KEY_SHA256_STRUCTURE 0x4 3816 #define INVM_INVALIDATED_STRUCTURE 0x5 3817 3818 #define INVM_RSA_KEY_SHA256_DATA_SIZE_IN_DWORDS 8 3819 #define INVM_CSR_AUTOLOAD_DATA_SIZE_IN_DWORDS 1 3820 3821 #define PHY_UPPER_SHIFT 21 3822 #define BM_PHY_REG(page, reg) \ 3823 (((reg) & MAX_PHY_REG_ADDRESS) |\ 3824 (((page) & 0xFFFF) << PHY_PAGE_SHIFT) |\ 3825 (((reg) & ~MAX_PHY_REG_ADDRESS) << (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT))) 3826 #define BM_PHY_REG_PAGE(offset) \ 3827 ((uint16_t)(((offset) >> PHY_PAGE_SHIFT) & 0xFFFF)) 3828 #define BM_PHY_REG_NUM(offset) \ 3829 ((uint16_t)(((offset) & MAX_PHY_REG_ADDRESS) |\ 3830 (((offset) >> (PHY_UPPER_SHIFT - PHY_PAGE_SHIFT)) &\ 3831 ~MAX_PHY_REG_ADDRESS))) 3832 3833 /* SFP modules ID memory locations */ 3834 #define E1000_SFF_IDENTIFIER_OFFSET 0x00 3835 #define E1000_SFF_IDENTIFIER_SFF 0x02 3836 #define E1000_SFF_IDENTIFIER_SFP 0x03 3837 3838 #define E1000_SFF_ETH_FLAGS_OFFSET 0x06 3839 /* Flags for SFP modules compatible with ETH up to 1Gb */ 3840 struct sfp_e1000_flags { 3841 uint8_t e1000_base_sx:1; 3842 uint8_t e1000_base_lx:1; 3843 uint8_t e1000_base_cx:1; 3844 uint8_t e1000_base_t:1; 3845 uint8_t e100_base_lx:1; 3846 uint8_t e100_base_fx:1; 3847 uint8_t e10_base_bx10:1; 3848 uint8_t e10_base_px:1; 3849 }; 3850 3851 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */ 3852 #define E1000_SFF_VENDOR_OUI_TYCO 0x00407600 3853 #define E1000_SFF_VENDOR_OUI_FTL 0x00906500 3854 #define E1000_SFF_VENDOR_OUI_AVAGO 0x00176A00 3855 #define E1000_SFF_VENDOR_OUI_INTEL 0x001B2100 3856 3857 #endif /* _EM_HW_H_ */ 3858