1 /* Definitions of target machine GNU compiler. IA-64 version. 2 Copyright (C) 1999, 2000, 2001, 2002 Free Software Foundation, Inc. 3 Contributed by James E. Wilson <wilson@cygnus.com> and 4 David Mosberger <davidm@hpl.hp.com>. 5 6 This file is part of GNU CC. 7 8 GNU CC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 2, or (at your option) 11 any later version. 12 13 GNU CC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GNU CC; see the file COPYING. If not, write to 20 the Free Software Foundation, 59 Temple Place - Suite 330, 21 Boston, MA 02111-1307, USA. */ 22 23 /* ??? Look at ABI group documents for list of preprocessor macros and 24 other features required for ABI compliance. */ 25 26 /* ??? Functions containing a non-local goto target save many registers. Why? 27 See for instance execute/920428-2.c. */ 28 29 /* ??? Add support for short data/bss sections. */ 30 31 32 /* Run-time target specifications */ 33 34 /* Target CPU builtins. */ 35 #define TARGET_CPU_CPP_BUILTINS() \ 36 do { \ 37 builtin_assert("cpu=ia64"); \ 38 builtin_assert("machine=ia64"); \ 39 builtin_define("__ia64"); \ 40 builtin_define("__ia64__"); \ 41 builtin_define("__itanium__"); \ 42 builtin_define("__ELF__"); \ 43 if (!TARGET_ILP32) \ 44 { \ 45 builtin_define("_LP64"); \ 46 builtin_define("__LP64__"); \ 47 } \ 48 if (TARGET_BIG_ENDIAN) \ 49 builtin_define("__BIG_ENDIAN__"); \ 50 } while (0) 51 52 #define EXTRA_SPECS \ 53 { "asm_extra", ASM_EXTRA_SPEC }, 54 55 #define CC1_SPEC "%(cc1_cpu) " 56 57 #define ASM_EXTRA_SPEC "" 58 59 60 /* This declaration should be present. */ 61 extern int target_flags; 62 63 /* This series of macros is to allow compiler command arguments to enable or 64 disable the use of optional features of the target machine. */ 65 66 #define MASK_BIG_ENDIAN 0x00000001 /* Generate big endian code. */ 67 68 #define MASK_GNU_AS 0x00000002 /* Generate code for GNU as. */ 69 70 #define MASK_GNU_LD 0x00000004 /* Generate code for GNU ld. */ 71 72 #define MASK_NO_PIC 0x00000008 /* Generate code without GP reg. */ 73 74 #define MASK_VOL_ASM_STOP 0x00000010 /* Emit stop bits for vol ext asm. */ 75 76 #define MASK_ILP32 0x00000020 /* Generate ILP32 code. */ 77 78 #define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */ 79 80 #define MASK_REG_NAMES 0x00000080 /* Use in/loc/out register names. */ 81 82 #define MASK_NO_SDATA 0x00000100 /* Disable sdata/scommon/sbss. */ 83 84 #define MASK_CONST_GP 0x00000200 /* treat gp as program-wide constant */ 85 86 #define MASK_AUTO_PIC 0x00000400 /* generate automatically PIC */ 87 88 #define MASK_INLINE_FLOAT_DIV_LAT 0x00000800 /* inline div, min latency. */ 89 90 #define MASK_INLINE_FLOAT_DIV_THR 0x00001000 /* inline div, max throughput. */ 91 92 #define MASK_INLINE_INT_DIV_LAT 0x00000800 /* inline div, min latency. */ 93 94 #define MASK_INLINE_INT_DIV_THR 0x00001000 /* inline div, max throughput. */ 95 96 #define MASK_DWARF2_ASM 0x40000000 /* test dwarf2 line info via gas. */ 97 98 #define TARGET_BIG_ENDIAN (target_flags & MASK_BIG_ENDIAN) 99 100 #define TARGET_GNU_AS (target_flags & MASK_GNU_AS) 101 102 #define TARGET_GNU_LD (target_flags & MASK_GNU_LD) 103 104 #define TARGET_NO_PIC (target_flags & MASK_NO_PIC) 105 106 #define TARGET_VOL_ASM_STOP (target_flags & MASK_VOL_ASM_STOP) 107 108 #define TARGET_ILP32 (target_flags & MASK_ILP32) 109 110 #define TARGET_B_STEP (target_flags & MASK_B_STEP) 111 112 #define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES) 113 114 #define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA) 115 116 #define TARGET_CONST_GP (target_flags & MASK_CONST_GP) 117 118 #define TARGET_AUTO_PIC (target_flags & MASK_AUTO_PIC) 119 120 #define TARGET_INLINE_FLOAT_DIV_LAT (target_flags & MASK_INLINE_FLOAT_DIV_LAT) 121 122 #define TARGET_INLINE_FLOAT_DIV_THR (target_flags & MASK_INLINE_FLOAT_DIV_THR) 123 124 #define TARGET_INLINE_INT_DIV_LAT (target_flags & MASK_INLINE_INT_DIV_LAT) 125 126 #define TARGET_INLINE_INT_DIV_THR (target_flags & MASK_INLINE_INT_DIV_THR) 127 128 #define TARGET_INLINE_FLOAT_DIV \ 129 (target_flags & (MASK_INLINE_FLOAT_DIV_LAT | MASK_INLINE_FLOAT_DIV_THR)) 130 131 #define TARGET_INLINE_INT_DIV \ 132 (target_flags & (MASK_INLINE_INT_DIV_LAT | MASK_INLINE_INT_DIV_THR)) 133 134 #define TARGET_DWARF2_ASM (target_flags & MASK_DWARF2_ASM) 135 136 /* If the assembler supports thread-local storage, assume that the 137 system does as well. If a particular target system has an 138 assembler that supports TLS -- but the rest of the system does not 139 support TLS -- that system should explicit define TARGET_HAVE_TLS 140 to false in its own configuration file. */ 141 #if !defined(TARGET_HAVE_TLS) && defined(HAVE_AS_TLS) 142 #define TARGET_HAVE_TLS true 143 #endif 144 145 extern int ia64_tls_size; 146 #define TARGET_TLS14 (ia64_tls_size == 14) 147 #define TARGET_TLS22 (ia64_tls_size == 22) 148 #define TARGET_TLS64 (ia64_tls_size == 64) 149 150 #define TARGET_HPUX_LD 0 151 152 #ifndef HAVE_AS_LTOFFX_LDXMOV_RELOCS 153 #define HAVE_AS_LTOFFX_LDXMOV_RELOCS 0 154 #endif 155 156 /* This macro defines names of command options to set and clear bits in 157 `target_flags'. Its definition is an initializer with a subgrouping for 158 each command option. */ 159 160 #define TARGET_SWITCHES \ 161 { \ 162 { "big-endian", MASK_BIG_ENDIAN, \ 163 N_("Generate big endian code") }, \ 164 { "little-endian", -MASK_BIG_ENDIAN, \ 165 N_("Generate little endian code") }, \ 166 { "gnu-as", MASK_GNU_AS, \ 167 N_("Generate code for GNU as") }, \ 168 { "no-gnu-as", -MASK_GNU_AS, \ 169 N_("Generate code for Intel as") }, \ 170 { "gnu-ld", MASK_GNU_LD, \ 171 N_("Generate code for GNU ld") }, \ 172 { "no-gnu-ld", -MASK_GNU_LD, \ 173 N_("Generate code for Intel ld") }, \ 174 { "no-pic", MASK_NO_PIC, \ 175 N_("Generate code without GP reg") }, \ 176 { "volatile-asm-stop", MASK_VOL_ASM_STOP, \ 177 N_("Emit stop bits before and after volatile extended asms") }, \ 178 { "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \ 179 N_("Don't emit stop bits before and after volatile extended asms") }, \ 180 { "b-step", MASK_B_STEP, \ 181 N_("Emit code for Itanium (TM) processor B step")}, \ 182 { "register-names", MASK_REG_NAMES, \ 183 N_("Use in/loc/out register names")}, \ 184 { "no-sdata", MASK_NO_SDATA, \ 185 N_("Disable use of sdata/scommon/sbss")}, \ 186 { "sdata", -MASK_NO_SDATA, \ 187 N_("Enable use of sdata/scommon/sbss")}, \ 188 { "constant-gp", MASK_CONST_GP, \ 189 N_("gp is constant (but save/restore gp on indirect calls)") }, \ 190 { "auto-pic", MASK_AUTO_PIC, \ 191 N_("Generate self-relocatable code") }, \ 192 { "inline-float-divide-min-latency", MASK_INLINE_FLOAT_DIV_LAT, \ 193 N_("Generate inline floating point division, optimize for latency") },\ 194 { "inline-float-divide-max-throughput", MASK_INLINE_FLOAT_DIV_THR, \ 195 N_("Generate inline floating point division, optimize for throughput") },\ 196 { "inline-int-divide-min-latency", MASK_INLINE_INT_DIV_LAT, \ 197 N_("Generate inline integer division, optimize for latency") }, \ 198 { "inline-int-divide-max-throughput", MASK_INLINE_INT_DIV_THR, \ 199 N_("Generate inline integer division, optimize for throughput") },\ 200 { "dwarf2-asm", MASK_DWARF2_ASM, \ 201 N_("Enable Dwarf 2 line debug info via GNU as")}, \ 202 { "no-dwarf2-asm", -MASK_DWARF2_ASM, \ 203 N_("Disable Dwarf 2 line debug info via GNU as")}, \ 204 SUBTARGET_SWITCHES \ 205 { "", TARGET_DEFAULT | TARGET_CPU_DEFAULT, \ 206 NULL } \ 207 } 208 209 /* Default target_flags if no switches are specified */ 210 211 #ifndef TARGET_DEFAULT 212 #define TARGET_DEFAULT MASK_DWARF2_ASM 213 #endif 214 215 #ifndef TARGET_CPU_DEFAULT 216 #define TARGET_CPU_DEFAULT 0 217 #endif 218 219 #ifndef SUBTARGET_SWITCHES 220 #define SUBTARGET_SWITCHES 221 #endif 222 223 /* This macro is similar to `TARGET_SWITCHES' but defines names of command 224 options that have values. Its definition is an initializer with a 225 subgrouping for each command option. */ 226 227 extern const char *ia64_fixed_range_string; 228 extern const char *ia64_tls_size_string; 229 #define TARGET_OPTIONS \ 230 { \ 231 { "fixed-range=", &ia64_fixed_range_string, \ 232 N_("Specify range of registers to make fixed")}, \ 233 { "tls-size=", &ia64_tls_size_string, \ 234 N_("Specify bit size of immediate TLS offsets")}, \ 235 } 236 237 /* Sometimes certain combinations of command options do not make sense on a 238 particular target machine. You can define a macro `OVERRIDE_OPTIONS' to 239 take account of this. This macro, if defined, is executed once just after 240 all the command options have been parsed. */ 241 242 #define OVERRIDE_OPTIONS ia64_override_options () 243 244 /* Some machines may desire to change what optimizations are performed for 245 various optimization levels. This macro, if defined, is executed once just 246 after the optimization level is determined and before the remainder of the 247 command options have been parsed. Values set in this macro are used as the 248 default values for the other command line options. */ 249 250 /* #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) */ 251 252 /* Driver configuration */ 253 254 /* A C string constant that tells the GNU CC driver program options to pass to 255 `cc1'. It can also specify how to translate options you give to GNU CC into 256 options for GNU CC to pass to the `cc1'. */ 257 258 #undef CC1_SPEC 259 #define CC1_SPEC "%{G*}" 260 261 /* A C string constant that tells the GNU CC driver program options to pass to 262 `cc1plus'. It can also specify how to translate options you give to GNU CC 263 into options for GNU CC to pass to the `cc1plus'. */ 264 265 /* #define CC1PLUS_SPEC "" */ 266 267 /* Storage Layout */ 268 269 /* Define this macro to have the value 1 if the most significant bit in a byte 270 has the lowest number; otherwise define it to have the value zero. */ 271 272 #define BITS_BIG_ENDIAN 0 273 274 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 275 276 /* Define this macro to have the value 1 if, in a multiword object, the most 277 significant word has the lowest number. */ 278 279 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN != 0) 280 281 #if defined(__BIG_ENDIAN__) 282 #define LIBGCC2_WORDS_BIG_ENDIAN 1 283 #else 284 #define LIBGCC2_WORDS_BIG_ENDIAN 0 285 #endif 286 287 #define UNITS_PER_WORD 8 288 289 #define POINTER_SIZE (TARGET_ILP32 ? 32 : 64) 290 291 /* A C expression whose value is zero if pointers that need to be extended 292 from being `POINTER_SIZE' bits wide to `Pmode' are sign-extended and one if 293 they are zero-extended and negative one if there is an ptr_extend operation. 294 295 You need not define this macro if the `POINTER_SIZE' is equal to the width 296 of `Pmode'. */ 297 /* Need this for 32 bit pointers, see hpux.h for setting it. */ 298 /* #define POINTERS_EXTEND_UNSIGNED */ 299 300 /* A macro to update MODE and UNSIGNEDP when an object whose type is TYPE and 301 which has the specified mode and signedness is to be stored in a register. 302 This macro is only called when TYPE is a scalar type. */ 303 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 304 do \ 305 { \ 306 if (GET_MODE_CLASS (MODE) == MODE_INT \ 307 && GET_MODE_SIZE (MODE) < 4) \ 308 (MODE) = SImode; \ 309 } \ 310 while (0) 311 312 /* ??? ABI doesn't allow us to define this. */ 313 /* #define PROMOTE_FUNCTION_ARGS */ 314 315 /* ??? ABI doesn't allow us to define this. */ 316 /* #define PROMOTE_FUNCTION_RETURN */ 317 318 #define PARM_BOUNDARY 64 319 320 /* Define this macro if you wish to preserve a certain alignment for the stack 321 pointer. The definition is a C expression for the desired alignment 322 (measured in bits). */ 323 324 #define STACK_BOUNDARY 128 325 326 /* Align frames on double word boundaries */ 327 #ifndef IA64_STACK_ALIGN 328 #define IA64_STACK_ALIGN(LOC) (((LOC) + 15) & ~15) 329 #endif 330 331 #define FUNCTION_BOUNDARY 128 332 333 /* Optional x86 80-bit float, quad-precision 128-bit float, and quad-word 334 128 bit integers all require 128 bit alignment. */ 335 #define BIGGEST_ALIGNMENT 128 336 337 /* If defined, a C expression to compute the alignment for a static variable. 338 TYPE is the data type, and ALIGN is the alignment that the object 339 would ordinarily have. The value of this macro is used instead of that 340 alignment to align the object. */ 341 342 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 343 (TREE_CODE (TYPE) == ARRAY_TYPE \ 344 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 345 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 346 347 /* If defined, a C expression to compute the alignment given to a constant that 348 is being placed in memory. CONSTANT is the constant and ALIGN is the 349 alignment that the object would ordinarily have. The value of this macro is 350 used instead of that alignment to align the object. */ 351 352 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 353 (TREE_CODE (EXP) == STRING_CST \ 354 && (ALIGN) < BITS_PER_WORD ? BITS_PER_WORD : (ALIGN)) 355 356 #define STRICT_ALIGNMENT 1 357 358 /* Define this if you wish to imitate the way many other C compilers handle 359 alignment of bitfields and the structures that contain them. 360 The behavior is that the type written for a bit-field (`int', `short', or 361 other integer type) imposes an alignment for the entire structure, as if the 362 structure really did contain an ordinary field of that type. In addition, 363 the bit-field is placed within the structure so that it would fit within such 364 a field, not crossing a boundary for it. */ 365 #define PCC_BITFIELD_TYPE_MATTERS 1 366 367 /* An integer expression for the size in bits of the largest integer machine 368 mode that should actually be used. */ 369 370 /* Allow pairs of registers to be used, which is the intent of the default. */ 371 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TImode) 372 373 /* By default, the C++ compiler will use function addresses in the 374 vtable entries. Setting this nonzero tells the compiler to use 375 function descriptors instead. The value of this macro says how 376 many words wide the descriptor is (normally 2). It is assumed 377 that the address of a function descriptor may be treated as a 378 pointer to a function. 379 380 For reasons known only to HP, the vtable entries (as opposed to 381 normal function descriptors) are 16 bytes wide in 32-bit mode as 382 well, even though the 3rd and 4th words are unused. */ 383 #define TARGET_VTABLE_USES_DESCRIPTORS (TARGET_ILP32 ? 4 : 2) 384 385 /* Due to silliness in the HPUX linker, vtable entries must be 386 8-byte aligned even in 32-bit mode. Rather than create multiple 387 ABIs, force this restriction on everyone else too. */ 388 #define TARGET_VTABLE_ENTRY_ALIGN 64 389 390 /* Due to the above, we need extra padding for the data entries below 0 391 to retain the alignment of the descriptors. */ 392 #define TARGET_VTABLE_DATA_ENTRY_DISTANCE (TARGET_ILP32 ? 2 : 1) 393 394 /* Layout of Source Language Data Types */ 395 396 #define INT_TYPE_SIZE 32 397 398 #define SHORT_TYPE_SIZE 16 399 400 #define LONG_TYPE_SIZE (TARGET_ILP32 ? 32 : 64) 401 402 #define MAX_LONG_TYPE_SIZE 64 403 404 #define LONG_LONG_TYPE_SIZE 64 405 406 #define FLOAT_TYPE_SIZE 32 407 408 #define DOUBLE_TYPE_SIZE 64 409 410 #define LONG_DOUBLE_TYPE_SIZE 128 411 412 /* By default we use the 80-bit Intel extended float format packaged 413 in a 128-bit entity. */ 414 #define INTEL_EXTENDED_IEEE_FORMAT 1 415 416 #define DEFAULT_SIGNED_CHAR 1 417 418 /* A C expression for a string describing the name of the data type to use for 419 size values. The typedef name `size_t' is defined using the contents of the 420 string. */ 421 /* ??? Needs to be defined for P64 code. */ 422 /* #define SIZE_TYPE */ 423 424 /* A C expression for a string describing the name of the data type to use for 425 the result of subtracting two pointers. The typedef name `ptrdiff_t' is 426 defined using the contents of the string. See `SIZE_TYPE' above for more 427 information. */ 428 /* ??? Needs to be defined for P64 code. */ 429 /* #define PTRDIFF_TYPE */ 430 431 /* A C expression for a string describing the name of the data type to use for 432 wide characters. The typedef name `wchar_t' is defined using the contents 433 of the string. See `SIZE_TYPE' above for more information. */ 434 /* #define WCHAR_TYPE */ 435 436 /* A C expression for the size in bits of the data type for wide characters. 437 This is used in `cpp', which cannot make use of `WCHAR_TYPE'. */ 438 /* #define WCHAR_TYPE_SIZE */ 439 440 441 /* Register Basics */ 442 443 /* Number of hardware registers known to the compiler. 444 We have 128 general registers, 128 floating point registers, 445 64 predicate registers, 8 branch registers, one frame pointer, 446 and several "application" registers. */ 447 448 #define FIRST_PSEUDO_REGISTER 334 449 450 /* Ranges for the various kinds of registers. */ 451 #define ADDL_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 3) 452 #define GR_REGNO_P(REGNO) ((unsigned HOST_WIDE_INT) (REGNO) <= 127) 453 #define FR_REGNO_P(REGNO) ((REGNO) >= 128 && (REGNO) <= 255) 454 #define PR_REGNO_P(REGNO) ((REGNO) >= 256 && (REGNO) <= 319) 455 #define BR_REGNO_P(REGNO) ((REGNO) >= 320 && (REGNO) <= 327) 456 #define GENERAL_REGNO_P(REGNO) \ 457 (GR_REGNO_P (REGNO) || (REGNO) == FRAME_POINTER_REGNUM) 458 459 #define GR_REG(REGNO) ((REGNO) + 0) 460 #define FR_REG(REGNO) ((REGNO) + 128) 461 #define PR_REG(REGNO) ((REGNO) + 256) 462 #define BR_REG(REGNO) ((REGNO) + 320) 463 #define OUT_REG(REGNO) ((REGNO) + 120) 464 #define IN_REG(REGNO) ((REGNO) + 112) 465 #define LOC_REG(REGNO) ((REGNO) + 32) 466 467 #define AR_CCV_REGNUM 329 468 #define AR_UNAT_REGNUM 330 469 #define AR_PFS_REGNUM 331 470 #define AR_LC_REGNUM 332 471 #define AR_EC_REGNUM 333 472 473 #define IN_REGNO_P(REGNO) ((REGNO) >= IN_REG (0) && (REGNO) <= IN_REG (7)) 474 #define LOC_REGNO_P(REGNO) ((REGNO) >= LOC_REG (0) && (REGNO) <= LOC_REG (79)) 475 #define OUT_REGNO_P(REGNO) ((REGNO) >= OUT_REG (0) && (REGNO) <= OUT_REG (7)) 476 477 #define AR_M_REGNO_P(REGNO) ((REGNO) == AR_CCV_REGNUM \ 478 || (REGNO) == AR_UNAT_REGNUM) 479 #define AR_I_REGNO_P(REGNO) ((REGNO) >= AR_PFS_REGNUM \ 480 && (REGNO) < FIRST_PSEUDO_REGISTER) 481 #define AR_REGNO_P(REGNO) ((REGNO) >= AR_CCV_REGNUM \ 482 && (REGNO) < FIRST_PSEUDO_REGISTER) 483 484 485 /* ??? Don't really need two sets of macros. I like this one better because 486 it is less typing. */ 487 #define R_GR(REGNO) GR_REG (REGNO) 488 #define R_FR(REGNO) FR_REG (REGNO) 489 #define R_PR(REGNO) PR_REG (REGNO) 490 #define R_BR(REGNO) BR_REG (REGNO) 491 492 /* An initializer that says which registers are used for fixed purposes all 493 throughout the compiled code and are therefore not available for general 494 allocation. 495 496 r0: constant 0 497 r1: global pointer (gp) 498 r12: stack pointer (sp) 499 r13: thread pointer (tp) 500 f0: constant 0.0 501 f1: constant 1.0 502 p0: constant true 503 fp: eliminable frame pointer */ 504 505 /* The last 16 stacked regs are reserved for the 8 input and 8 output 506 registers. */ 507 508 #define FIXED_REGISTERS \ 509 { /* General registers. */ \ 510 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 0, 0, \ 511 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 512 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 513 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 514 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 515 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 516 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 517 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 518 /* Floating-point registers. */ \ 519 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 520 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 521 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 522 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 523 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 524 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 525 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 526 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 527 /* Predicate registers. */ \ 528 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 529 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 530 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 531 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 532 /* Branch registers. */ \ 533 0, 0, 0, 0, 0, 0, 0, 0, \ 534 /*FP CCV UNAT PFS LC EC */ \ 535 1, 1, 1, 1, 0, 1 \ 536 } 537 538 /* Like `FIXED_REGISTERS' but has 1 for each register that is clobbered 539 (in general) by function calls as well as for fixed registers. This 540 macro therefore identifies the registers that are not available for 541 general allocation of values that must live across function calls. */ 542 543 #define CALL_USED_REGISTERS \ 544 { /* General registers. */ \ 545 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ 546 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 547 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 548 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 549 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 550 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 551 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 552 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ 553 /* Floating-point registers. */ \ 554 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 555 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 556 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 557 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 558 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 559 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 560 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 561 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 562 /* Predicate registers. */ \ 563 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 564 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 565 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 566 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 567 /* Branch registers. */ \ 568 1, 0, 0, 0, 0, 0, 1, 1, \ 569 /*FP CCV UNAT PFS LC EC */ \ 570 1, 1, 1, 1, 0, 1 \ 571 } 572 573 /* Like `CALL_USED_REGISTERS' but used to overcome a historical 574 problem which makes CALL_USED_REGISTERS *always* include 575 all the FIXED_REGISTERS. Until this problem has been 576 resolved this macro can be used to overcome this situation. 577 In particular, block_propagate() requires this list 578 be acurate, or we can remove registers which should be live. 579 This macro is used in regs_invalidated_by_call. */ 580 581 #define CALL_REALLY_USED_REGISTERS \ 582 { /* General registers. */ \ 583 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 1, 1, 1, \ 584 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 585 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 586 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 587 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 588 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 589 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 590 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, \ 591 /* Floating-point registers. */ \ 592 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 593 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 594 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 595 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 596 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 597 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 598 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 599 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 600 /* Predicate registers. */ \ 601 1, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \ 602 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 603 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 604 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 605 /* Branch registers. */ \ 606 1, 0, 0, 0, 0, 0, 1, 1, \ 607 /*FP CCV UNAT PFS LC EC */ \ 608 0, 1, 0, 1, 0, 0 \ 609 } 610 611 612 /* Define this macro if the target machine has register windows. This C 613 expression returns the register number as seen by the called function 614 corresponding to the register number OUT as seen by the calling function. 615 Return OUT if register number OUT is not an outbound register. */ 616 617 #define INCOMING_REGNO(OUT) \ 618 ((unsigned) ((OUT) - OUT_REG (0)) < 8 ? IN_REG ((OUT) - OUT_REG (0)) : (OUT)) 619 620 /* Define this macro if the target machine has register windows. This C 621 expression returns the register number as seen by the calling function 622 corresponding to the register number IN as seen by the called function. 623 Return IN if register number IN is not an inbound register. */ 624 625 #define OUTGOING_REGNO(IN) \ 626 ((unsigned) ((IN) - IN_REG (0)) < 8 ? OUT_REG ((IN) - IN_REG (0)) : (IN)) 627 628 /* Define this macro if the target machine has register windows. This 629 C expression returns true if the register is call-saved but is in the 630 register window. */ 631 632 #define LOCAL_REGNO(REGNO) \ 633 (IN_REGNO_P (REGNO) || LOC_REGNO_P (REGNO)) 634 635 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 636 return the mode to be used for the comparison. Must be defined if 637 EXTRA_CC_MODES is defined. */ 638 639 #define SELECT_CC_MODE(OP,X,Y) CCmode 640 641 /* Order of allocation of registers */ 642 643 /* If defined, an initializer for a vector of integers, containing the numbers 644 of hard registers in the order in which GNU CC should prefer to use them 645 (from most preferred to least). 646 647 If this macro is not defined, registers are used lowest numbered first (all 648 else being equal). 649 650 One use of this macro is on machines where the highest numbered registers 651 must always be saved and the save-multiple-registers instruction supports 652 only sequences of consecutive registers. On such machines, define 653 `REG_ALLOC_ORDER' to be an initializer that lists the highest numbered 654 allocatable register first. */ 655 656 /* ??? Should the GR return value registers come before or after the rest 657 of the caller-save GRs? */ 658 659 #define REG_ALLOC_ORDER \ 660 { \ 661 /* Caller-saved general registers. */ \ 662 R_GR (14), R_GR (15), R_GR (16), R_GR (17), \ 663 R_GR (18), R_GR (19), R_GR (20), R_GR (21), R_GR (22), R_GR (23), \ 664 R_GR (24), R_GR (25), R_GR (26), R_GR (27), R_GR (28), R_GR (29), \ 665 R_GR (30), R_GR (31), \ 666 /* Output registers. */ \ 667 R_GR (120), R_GR (121), R_GR (122), R_GR (123), R_GR (124), R_GR (125), \ 668 R_GR (126), R_GR (127), \ 669 /* Caller-saved general registers, also used for return values. */ \ 670 R_GR (8), R_GR (9), R_GR (10), R_GR (11), \ 671 /* addl caller-saved general registers. */ \ 672 R_GR (2), R_GR (3), \ 673 /* Caller-saved FP registers. */ \ 674 R_FR (6), R_FR (7), \ 675 /* Caller-saved FP registers, used for parameters and return values. */ \ 676 R_FR (8), R_FR (9), R_FR (10), R_FR (11), \ 677 R_FR (12), R_FR (13), R_FR (14), R_FR (15), \ 678 /* Rotating caller-saved FP registers. */ \ 679 R_FR (32), R_FR (33), R_FR (34), R_FR (35), \ 680 R_FR (36), R_FR (37), R_FR (38), R_FR (39), R_FR (40), R_FR (41), \ 681 R_FR (42), R_FR (43), R_FR (44), R_FR (45), R_FR (46), R_FR (47), \ 682 R_FR (48), R_FR (49), R_FR (50), R_FR (51), R_FR (52), R_FR (53), \ 683 R_FR (54), R_FR (55), R_FR (56), R_FR (57), R_FR (58), R_FR (59), \ 684 R_FR (60), R_FR (61), R_FR (62), R_FR (63), R_FR (64), R_FR (65), \ 685 R_FR (66), R_FR (67), R_FR (68), R_FR (69), R_FR (70), R_FR (71), \ 686 R_FR (72), R_FR (73), R_FR (74), R_FR (75), R_FR (76), R_FR (77), \ 687 R_FR (78), R_FR (79), R_FR (80), R_FR (81), R_FR (82), R_FR (83), \ 688 R_FR (84), R_FR (85), R_FR (86), R_FR (87), R_FR (88), R_FR (89), \ 689 R_FR (90), R_FR (91), R_FR (92), R_FR (93), R_FR (94), R_FR (95), \ 690 R_FR (96), R_FR (97), R_FR (98), R_FR (99), R_FR (100), R_FR (101), \ 691 R_FR (102), R_FR (103), R_FR (104), R_FR (105), R_FR (106), R_FR (107), \ 692 R_FR (108), R_FR (109), R_FR (110), R_FR (111), R_FR (112), R_FR (113), \ 693 R_FR (114), R_FR (115), R_FR (116), R_FR (117), R_FR (118), R_FR (119), \ 694 R_FR (120), R_FR (121), R_FR (122), R_FR (123), R_FR (124), R_FR (125), \ 695 R_FR (126), R_FR (127), \ 696 /* Caller-saved predicate registers. */ \ 697 R_PR (6), R_PR (7), R_PR (8), R_PR (9), R_PR (10), R_PR (11), \ 698 R_PR (12), R_PR (13), R_PR (14), R_PR (15), \ 699 /* Rotating caller-saved predicate registers. */ \ 700 R_PR (16), R_PR (17), \ 701 R_PR (18), R_PR (19), R_PR (20), R_PR (21), R_PR (22), R_PR (23), \ 702 R_PR (24), R_PR (25), R_PR (26), R_PR (27), R_PR (28), R_PR (29), \ 703 R_PR (30), R_PR (31), R_PR (32), R_PR (33), R_PR (34), R_PR (35), \ 704 R_PR (36), R_PR (37), R_PR (38), R_PR (39), R_PR (40), R_PR (41), \ 705 R_PR (42), R_PR (43), R_PR (44), R_PR (45), R_PR (46), R_PR (47), \ 706 R_PR (48), R_PR (49), R_PR (50), R_PR (51), R_PR (52), R_PR (53), \ 707 R_PR (54), R_PR (55), R_PR (56), R_PR (57), R_PR (58), R_PR (59), \ 708 R_PR (60), R_PR (61), R_PR (62), R_PR (63), \ 709 /* Caller-saved branch registers. */ \ 710 R_BR (6), R_BR (7), \ 711 \ 712 /* Stacked callee-saved general registers. */ \ 713 R_GR (32), R_GR (33), R_GR (34), R_GR (35), \ 714 R_GR (36), R_GR (37), R_GR (38), R_GR (39), R_GR (40), R_GR (41), \ 715 R_GR (42), R_GR (43), R_GR (44), R_GR (45), R_GR (46), R_GR (47), \ 716 R_GR (48), R_GR (49), R_GR (50), R_GR (51), R_GR (52), R_GR (53), \ 717 R_GR (54), R_GR (55), R_GR (56), R_GR (57), R_GR (58), R_GR (59), \ 718 R_GR (60), R_GR (61), R_GR (62), R_GR (63), R_GR (64), R_GR (65), \ 719 R_GR (66), R_GR (67), R_GR (68), R_GR (69), R_GR (70), R_GR (71), \ 720 R_GR (72), R_GR (73), R_GR (74), R_GR (75), R_GR (76), R_GR (77), \ 721 R_GR (78), R_GR (79), R_GR (80), R_GR (81), R_GR (82), R_GR (83), \ 722 R_GR (84), R_GR (85), R_GR (86), R_GR (87), R_GR (88), R_GR (89), \ 723 R_GR (90), R_GR (91), R_GR (92), R_GR (93), R_GR (94), R_GR (95), \ 724 R_GR (96), R_GR (97), R_GR (98), R_GR (99), R_GR (100), R_GR (101), \ 725 R_GR (102), R_GR (103), R_GR (104), R_GR (105), R_GR (106), R_GR (107), \ 726 R_GR (108), \ 727 /* Input registers. */ \ 728 R_GR (112), R_GR (113), R_GR (114), R_GR (115), R_GR (116), R_GR (117), \ 729 R_GR (118), R_GR (119), \ 730 /* Callee-saved general registers. */ \ 731 R_GR (4), R_GR (5), R_GR (6), R_GR (7), \ 732 /* Callee-saved FP registers. */ \ 733 R_FR (2), R_FR (3), R_FR (4), R_FR (5), R_FR (16), R_FR (17), \ 734 R_FR (18), R_FR (19), R_FR (20), R_FR (21), R_FR (22), R_FR (23), \ 735 R_FR (24), R_FR (25), R_FR (26), R_FR (27), R_FR (28), R_FR (29), \ 736 R_FR (30), R_FR (31), \ 737 /* Callee-saved predicate registers. */ \ 738 R_PR (1), R_PR (2), R_PR (3), R_PR (4), R_PR (5), \ 739 /* Callee-saved branch registers. */ \ 740 R_BR (1), R_BR (2), R_BR (3), R_BR (4), R_BR (5), \ 741 \ 742 /* ??? Stacked registers reserved for fp, rp, and ar.pfs. */ \ 743 R_GR (109), R_GR (110), R_GR (111), \ 744 \ 745 /* Special general registers. */ \ 746 R_GR (0), R_GR (1), R_GR (12), R_GR (13), \ 747 /* Special FP registers. */ \ 748 R_FR (0), R_FR (1), \ 749 /* Special predicate registers. */ \ 750 R_PR (0), \ 751 /* Special branch registers. */ \ 752 R_BR (0), \ 753 /* Other fixed registers. */ \ 754 FRAME_POINTER_REGNUM, \ 755 AR_CCV_REGNUM, AR_UNAT_REGNUM, AR_PFS_REGNUM, AR_LC_REGNUM, \ 756 AR_EC_REGNUM \ 757 } 758 759 /* How Values Fit in Registers */ 760 761 /* A C expression for the number of consecutive hard registers, starting at 762 register number REGNO, required to hold a value of mode MODE. */ 763 764 /* ??? We say that BImode PR values require two registers. This allows us to 765 easily store the normal and inverted values. We use CCImode to indicate 766 a single predicate register. */ 767 768 #define HARD_REGNO_NREGS(REGNO, MODE) \ 769 ((REGNO) == PR_REG (0) && (MODE) == DImode ? 64 \ 770 : PR_REGNO_P (REGNO) && (MODE) == BImode ? 2 \ 771 : PR_REGNO_P (REGNO) && (MODE) == CCImode ? 1 \ 772 : FR_REGNO_P (REGNO) && (MODE) == TFmode && INTEL_EXTENDED_IEEE_FORMAT ? 1 \ 773 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 774 775 /* A C expression that is nonzero if it is permissible to store a value of mode 776 MODE in hard register number REGNO (or in several registers starting with 777 that one). */ 778 779 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 780 (FR_REGNO_P (REGNO) ? \ 781 GET_MODE_CLASS (MODE) != MODE_CC && \ 782 (MODE) != TImode && \ 783 (MODE) != BImode && \ 784 ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT) \ 785 : PR_REGNO_P (REGNO) ? \ 786 (MODE) == BImode || GET_MODE_CLASS (MODE) == MODE_CC \ 787 : GR_REGNO_P (REGNO) ? (MODE) != CCImode && (MODE) != TFmode \ 788 : AR_REGNO_P (REGNO) ? (MODE) == DImode \ 789 : BR_REGNO_P (REGNO) ? (MODE) == DImode \ 790 : 0) 791 792 /* A C expression that is nonzero if it is desirable to choose register 793 allocation so as to avoid move instructions between a value of mode MODE1 794 and a value of mode MODE2. 795 796 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, MODE2)' are 797 ever different for any R, then `MODES_TIEABLE_P (MODE1, MODE2)' must be 798 zero. */ 799 /* Don't tie integer and FP modes, as that causes us to get integer registers 800 allocated for FP instructions. TFmode only supported in FP registers so 801 we can't tie it with any other modes. */ 802 #define MODES_TIEABLE_P(MODE1, MODE2) \ 803 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2) \ 804 && (((MODE1) == TFmode) == ((MODE2) == TFmode)) \ 805 && (((MODE1) == BImode) == ((MODE2) == BImode))) 806 807 /* Handling Leaf Functions */ 808 809 /* A C initializer for a vector, indexed by hard register number, which 810 contains 1 for a register that is allowable in a candidate for leaf function 811 treatment. */ 812 /* ??? This might be useful. */ 813 /* #define LEAF_REGISTERS */ 814 815 /* A C expression whose value is the register number to which REGNO should be 816 renumbered, when a function is treated as a leaf function. */ 817 /* ??? This might be useful. */ 818 /* #define LEAF_REG_REMAP(REGNO) */ 819 820 821 /* Register Classes */ 822 823 /* An enumeral type that must be defined with all the register class names as 824 enumeral values. `NO_REGS' must be first. `ALL_REGS' must be the last 825 register class, followed by one more enumeral value, `LIM_REG_CLASSES', 826 which is not a register class but rather tells how many classes there 827 are. */ 828 /* ??? When compiling without optimization, it is possible for the only use of 829 a pseudo to be a parameter load from the stack with a REG_EQUIV note. 830 Regclass handles this case specially and does not assign any costs to the 831 pseudo. The pseudo then ends up using the last class before ALL_REGS. 832 Thus we must not let either PR_REGS or BR_REGS be the last class. The 833 testcase for this is gcc.c-torture/execute/va-arg-7.c. */ 834 enum reg_class 835 { 836 NO_REGS, 837 PR_REGS, 838 BR_REGS, 839 AR_M_REGS, 840 AR_I_REGS, 841 ADDL_REGS, 842 GR_REGS, 843 FR_REGS, 844 GR_AND_BR_REGS, 845 GR_AND_FR_REGS, 846 ALL_REGS, 847 LIM_REG_CLASSES 848 }; 849 850 #define GENERAL_REGS GR_REGS 851 852 /* The number of distinct register classes. */ 853 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 854 855 /* An initializer containing the names of the register classes as C string 856 constants. These names are used in writing some of the debugging dumps. */ 857 #define REG_CLASS_NAMES \ 858 { "NO_REGS", "PR_REGS", "BR_REGS", "AR_M_REGS", "AR_I_REGS", \ 859 "ADDL_REGS", "GR_REGS", "FR_REGS", \ 860 "GR_AND_BR_REGS", "GR_AND_FR_REGS", "ALL_REGS" } 861 862 /* An initializer containing the contents of the register classes, as integers 863 which are bit masks. The Nth integer specifies the contents of class N. 864 The way the integer MASK is interpreted is that register R is in the class 865 if `MASK & (1 << R)' is 1. */ 866 #define REG_CLASS_CONTENTS \ 867 { \ 868 /* NO_REGS. */ \ 869 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 870 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 871 0x00000000, 0x00000000, 0x0000 }, \ 872 /* PR_REGS. */ \ 873 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 874 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 875 0xFFFFFFFF, 0xFFFFFFFF, 0x0000 }, \ 876 /* BR_REGS. */ \ 877 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 878 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 879 0x00000000, 0x00000000, 0x00FF }, \ 880 /* AR_M_REGS. */ \ 881 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 882 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 883 0x00000000, 0x00000000, 0x0600 }, \ 884 /* AR_I_REGS. */ \ 885 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 886 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 887 0x00000000, 0x00000000, 0x3800 }, \ 888 /* ADDL_REGS. */ \ 889 { 0x0000000F, 0x00000000, 0x00000000, 0x00000000, \ 890 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 891 0x00000000, 0x00000000, 0x0000 }, \ 892 /* GR_REGS. */ \ 893 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 894 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 895 0x00000000, 0x00000000, 0x0100 }, \ 896 /* FR_REGS. */ \ 897 { 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 898 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 899 0x00000000, 0x00000000, 0x0000 }, \ 900 /* GR_AND_BR_REGS. */ \ 901 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 902 0x00000000, 0x00000000, 0x00000000, 0x00000000, \ 903 0x00000000, 0x00000000, 0x01FF }, \ 904 /* GR_AND_FR_REGS. */ \ 905 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 906 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 907 0x00000000, 0x00000000, 0x0100 }, \ 908 /* ALL_REGS. */ \ 909 { 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 910 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, \ 911 0xFFFFFFFF, 0xFFFFFFFF, 0x3FFF }, \ 912 } 913 914 /* A C expression whose value is a register class containing hard register 915 REGNO. In general there is more than one such class; choose a class which 916 is "minimal", meaning that no smaller class also contains the register. */ 917 /* The NO_REGS case is primarily for the benefit of rws_access_reg, which 918 may call here with private (invalid) register numbers, such as 919 REG_VOLATILE. */ 920 #define REGNO_REG_CLASS(REGNO) \ 921 (ADDL_REGNO_P (REGNO) ? ADDL_REGS \ 922 : GENERAL_REGNO_P (REGNO) ? GR_REGS \ 923 : FR_REGNO_P (REGNO) ? FR_REGS \ 924 : PR_REGNO_P (REGNO) ? PR_REGS \ 925 : BR_REGNO_P (REGNO) ? BR_REGS \ 926 : AR_M_REGNO_P (REGNO) ? AR_M_REGS \ 927 : AR_I_REGNO_P (REGNO) ? AR_I_REGS \ 928 : NO_REGS) 929 930 /* A macro whose definition is the name of the class to which a valid base 931 register must belong. A base register is one used in an address which is 932 the register value plus a displacement. */ 933 #define BASE_REG_CLASS GENERAL_REGS 934 935 /* A macro whose definition is the name of the class to which a valid index 936 register must belong. An index register is one used in an address where its 937 value is either multiplied by a scale factor or added to another register 938 (as well as added to a displacement). This is needed for POST_MODIFY. */ 939 #define INDEX_REG_CLASS GENERAL_REGS 940 941 /* A C expression which defines the machine-dependent operand constraint 942 letters for register classes. If CHAR is such a letter, the value should be 943 the register class corresponding to it. Otherwise, the value should be 944 `NO_REGS'. The register letter `r', corresponding to class `GENERAL_REGS', 945 will not be passed to this macro; you do not need to handle it. */ 946 947 #define REG_CLASS_FROM_LETTER(CHAR) \ 948 ((CHAR) == 'f' ? FR_REGS \ 949 : (CHAR) == 'a' ? ADDL_REGS \ 950 : (CHAR) == 'b' ? BR_REGS \ 951 : (CHAR) == 'c' ? PR_REGS \ 952 : (CHAR) == 'd' ? AR_M_REGS \ 953 : (CHAR) == 'e' ? AR_I_REGS \ 954 : NO_REGS) 955 956 /* A C expression which is nonzero if register number NUM is suitable for use 957 as a base register in operand addresses. It may be either a suitable hard 958 register or a pseudo register that has been allocated such a hard reg. */ 959 #define REGNO_OK_FOR_BASE_P(REGNO) \ 960 (GENERAL_REGNO_P (REGNO) || GENERAL_REGNO_P (reg_renumber[REGNO])) 961 962 /* A C expression which is nonzero if register number NUM is suitable for use 963 as an index register in operand addresses. It may be either a suitable hard 964 register or a pseudo register that has been allocated such a hard reg. 965 This is needed for POST_MODIFY. */ 966 #define REGNO_OK_FOR_INDEX_P(NUM) REGNO_OK_FOR_BASE_P (NUM) 967 968 /* A C expression that places additional restrictions on the register class to 969 use when it is necessary to copy value X into a register in class CLASS. 970 The value is a register class; perhaps CLASS, or perhaps another, smaller 971 class. */ 972 973 /* Don't allow volatile mem reloads into floating point registers. This 974 is defined to force reload to choose the r/m case instead of the f/f case 975 when reloading (set (reg fX) (mem/v)). 976 977 Do not reload expressions into AR regs. */ 978 979 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 980 (CLASS == FR_REGS && GET_CODE (X) == MEM && MEM_VOLATILE_P (X) ? NO_REGS \ 981 : CLASS == FR_REGS && GET_CODE (X) == CONST_DOUBLE ? NO_REGS \ 982 : GET_RTX_CLASS (GET_CODE (X)) != 'o' \ 983 && (CLASS == AR_M_REGS || CLASS == AR_I_REGS) ? NO_REGS \ 984 : CLASS) 985 986 /* You should define this macro to indicate to the reload phase that it may 987 need to allocate at least one register for a reload in addition to the 988 register to contain the data. Specifically, if copying X to a register 989 CLASS in MODE requires an intermediate register, you should define this 990 to return the largest register class all of whose registers can be used 991 as intermediate registers or scratch registers. */ 992 993 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ 994 ia64_secondary_reload_class (CLASS, MODE, X) 995 996 /* Certain machines have the property that some registers cannot be copied to 997 some other registers without using memory. Define this macro on those 998 machines to be a C expression that is nonzero if objects of mode M in 999 registers of CLASS1 can only be copied to registers of class CLASS2 by 1000 storing a register of CLASS1 into memory and loading that memory location 1001 into a register of CLASS2. */ 1002 1003 #if 0 1004 /* ??? May need this, but since we've disallowed TFmode in GR_REGS, 1005 I'm not quite sure how it could be invoked. The normal problems 1006 with unions should be solved with the addressof fiddling done by 1007 movtf and friends. */ 1008 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 1009 ((MODE) == TFmode && (((CLASS1) == GR_REGS && (CLASS2) == FR_REGS) \ 1010 || ((CLASS1) == FR_REGS && (CLASS2) == GR_REGS))) 1011 #endif 1012 1013 /* A C expression for the maximum number of consecutive registers of 1014 class CLASS needed to hold a value of mode MODE. 1015 This is closely related to the macro `HARD_REGNO_NREGS'. */ 1016 1017 #define CLASS_MAX_NREGS(CLASS, MODE) \ 1018 ((MODE) == BImode && (CLASS) == PR_REGS ? 2 \ 1019 : ((CLASS) == FR_REGS && (MODE) == TFmode) ? 1 \ 1020 : (GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1021 1022 /* In FP regs, we can't change FP values to integer values and vice 1023 versa, but we can change e.g. DImode to SImode. */ 1024 1025 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1026 (GET_MODE_CLASS (FROM) != GET_MODE_CLASS (TO) \ 1027 ? reg_classes_intersect_p (CLASS, FR_REGS) : 0) 1028 1029 /* A C expression that defines the machine-dependent operand constraint 1030 letters (`I', `J', `K', .. 'P') that specify particular ranges of 1031 integer values. */ 1032 1033 /* 14 bit signed immediate for arithmetic instructions. */ 1034 #define CONST_OK_FOR_I(VALUE) \ 1035 ((unsigned HOST_WIDE_INT)(VALUE) + 0x2000 < 0x4000) 1036 /* 22 bit signed immediate for arith instructions with r0/r1/r2/r3 source. */ 1037 #define CONST_OK_FOR_J(VALUE) \ 1038 ((unsigned HOST_WIDE_INT)(VALUE) + 0x200000 < 0x400000) 1039 /* 8 bit signed immediate for logical instructions. */ 1040 #define CONST_OK_FOR_K(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x80 < 0x100) 1041 /* 8 bit adjusted signed immediate for compare pseudo-ops. */ 1042 #define CONST_OK_FOR_L(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x7F < 0x100) 1043 /* 6 bit unsigned immediate for shift counts. */ 1044 #define CONST_OK_FOR_M(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) < 0x40) 1045 /* 9 bit signed immediate for load/store post-increments. */ 1046 #define CONST_OK_FOR_N(VALUE) ((unsigned HOST_WIDE_INT)(VALUE) + 0x100 < 0x200) 1047 /* 0 for r0. Used by Linux kernel, do not change. */ 1048 #define CONST_OK_FOR_O(VALUE) ((VALUE) == 0) 1049 /* 0 or -1 for dep instruction. */ 1050 #define CONST_OK_FOR_P(VALUE) ((VALUE) == 0 || (VALUE) == -1) 1051 1052 #define CONST_OK_FOR_LETTER_P(VALUE, C) \ 1053 ((C) == 'I' ? CONST_OK_FOR_I (VALUE) \ 1054 : (C) == 'J' ? CONST_OK_FOR_J (VALUE) \ 1055 : (C) == 'K' ? CONST_OK_FOR_K (VALUE) \ 1056 : (C) == 'L' ? CONST_OK_FOR_L (VALUE) \ 1057 : (C) == 'M' ? CONST_OK_FOR_M (VALUE) \ 1058 : (C) == 'N' ? CONST_OK_FOR_N (VALUE) \ 1059 : (C) == 'O' ? CONST_OK_FOR_O (VALUE) \ 1060 : (C) == 'P' ? CONST_OK_FOR_P (VALUE) \ 1061 : 0) 1062 1063 /* A C expression that defines the machine-dependent operand constraint letters 1064 (`G', `H') that specify particular ranges of `const_double' values. */ 1065 1066 /* 0.0 and 1.0 for fr0 and fr1. */ 1067 #define CONST_DOUBLE_OK_FOR_G(VALUE) \ 1068 ((VALUE) == CONST0_RTX (GET_MODE (VALUE)) \ 1069 || (VALUE) == CONST1_RTX (GET_MODE (VALUE))) 1070 1071 #define CONST_DOUBLE_OK_FOR_LETTER_P(VALUE, C) \ 1072 ((C) == 'G' ? CONST_DOUBLE_OK_FOR_G (VALUE) : 0) 1073 1074 /* A C expression that defines the optional machine-dependent constraint 1075 letters (`Q', `R', `S', `T', `U') that can be used to segregate specific 1076 types of operands, usually memory references, for the target machine. */ 1077 1078 /* Non-volatile memory for FP_REG loads/stores. */ 1079 #define CONSTRAINT_OK_FOR_Q(VALUE) \ 1080 (memory_operand((VALUE), VOIDmode) && ! MEM_VOLATILE_P (VALUE)) 1081 /* 1..4 for shladd arguments. */ 1082 #define CONSTRAINT_OK_FOR_R(VALUE) \ 1083 (GET_CODE (VALUE) == CONST_INT && INTVAL (VALUE) >= 1 && INTVAL (VALUE) <= 4) 1084 /* Non-post-inc memory for asms and other unsavory creatures. */ 1085 #define CONSTRAINT_OK_FOR_S(VALUE) \ 1086 (GET_CODE (VALUE) == MEM \ 1087 && GET_RTX_CLASS (GET_CODE (XEXP ((VALUE), 0))) != 'a' \ 1088 && (reload_in_progress || memory_operand ((VALUE), VOIDmode))) 1089 1090 #define EXTRA_CONSTRAINT(VALUE, C) \ 1091 ((C) == 'Q' ? CONSTRAINT_OK_FOR_Q (VALUE) \ 1092 : (C) == 'R' ? CONSTRAINT_OK_FOR_R (VALUE) \ 1093 : (C) == 'S' ? CONSTRAINT_OK_FOR_S (VALUE) \ 1094 : 0) 1095 1096 /* Basic Stack Layout */ 1097 1098 /* Define this macro if pushing a word onto the stack moves the stack pointer 1099 to a smaller address. */ 1100 #define STACK_GROWS_DOWNWARD 1 1101 1102 /* Define this macro if the addresses of local variable slots are at negative 1103 offsets from the frame pointer. */ 1104 /* #define FRAME_GROWS_DOWNWARD */ 1105 1106 /* Offset from the frame pointer to the first local variable slot to 1107 be allocated. */ 1108 #define STARTING_FRAME_OFFSET 0 1109 1110 /* Offset from the stack pointer register to the first location at which 1111 outgoing arguments are placed. If not specified, the default value of zero 1112 is used. This is the proper value for most machines. */ 1113 /* IA64 has a 16 byte scratch area that is at the bottom of the stack. */ 1114 #define STACK_POINTER_OFFSET 16 1115 1116 /* Offset from the argument pointer register to the first argument's address. 1117 On some machines it may depend on the data type of the function. */ 1118 #define FIRST_PARM_OFFSET(FUNDECL) 0 1119 1120 /* A C expression whose value is RTL representing the value of the return 1121 address for the frame COUNT steps up from the current frame, after the 1122 prologue. */ 1123 1124 /* ??? Frames other than zero would likely require interpreting the frame 1125 unwind info, so we don't try to support them. We would also need to define 1126 DYNAMIC_CHAIN_ADDRESS and SETUP_FRAME_ADDRESS (for the reg stack flush). */ 1127 1128 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 1129 ia64_return_addr_rtx (COUNT, FRAME) 1130 1131 /* A C expression whose value is RTL representing the location of the incoming 1132 return address at the beginning of any function, before the prologue. This 1133 RTL is either a `REG', indicating that the return value is saved in `REG', 1134 or a `MEM' representing a location in the stack. This enables DWARF2 1135 unwind info for C++ EH. */ 1136 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (VOIDmode, BR_REG (0)) 1137 1138 /* ??? This is not defined because of three problems. 1139 1) dwarf2out.c assumes that DWARF_FRAME_RETURN_COLUMN fits in one byte. 1140 The default value is FIRST_PSEUDO_REGISTER which doesn't. This can be 1141 worked around by setting PC_REGNUM to FR_REG (0) which is an otherwise 1142 unused register number. 1143 2) dwarf2out_frame_debug core dumps while processing prologue insns. We 1144 need to refine which insns have RTX_FRAME_RELATED_P set and which don't. 1145 3) It isn't possible to turn off EH frame info by defining DWARF2_UNIND_INFO 1146 to zero, despite what the documentation implies, because it is tested in 1147 a few places with #ifdef instead of #if. */ 1148 #undef INCOMING_RETURN_ADDR_RTX 1149 1150 /* A C expression whose value is an integer giving the offset, in bytes, from 1151 the value of the stack pointer register to the top of the stack frame at the 1152 beginning of any function, before the prologue. The top of the frame is 1153 defined to be the value of the stack pointer in the previous frame, just 1154 before the call instruction. */ 1155 #define INCOMING_FRAME_SP_OFFSET 0 1156 1157 1158 /* Register That Address the Stack Frame. */ 1159 1160 /* The register number of the stack pointer register, which must also be a 1161 fixed register according to `FIXED_REGISTERS'. On most machines, the 1162 hardware determines which register this is. */ 1163 1164 #define STACK_POINTER_REGNUM 12 1165 1166 /* The register number of the frame pointer register, which is used to access 1167 automatic variables in the stack frame. On some machines, the hardware 1168 determines which register this is. On other machines, you can choose any 1169 register you wish for this purpose. */ 1170 1171 #define FRAME_POINTER_REGNUM 328 1172 1173 /* Base register for access to local variables of the function. */ 1174 #define HARD_FRAME_POINTER_REGNUM LOC_REG (79) 1175 1176 /* The register number of the arg pointer register, which is used to access the 1177 function's argument list. */ 1178 /* r0 won't otherwise be used, so put the always eliminated argument pointer 1179 in it. */ 1180 #define ARG_POINTER_REGNUM R_GR(0) 1181 1182 /* Due to the way varargs and argument spilling happens, the argument 1183 pointer is not 16-byte aligned like the stack pointer. */ 1184 #define INIT_EXPANDERS \ 1185 do { \ 1186 if (cfun && cfun->emit->regno_pointer_align) \ 1187 REGNO_POINTER_ALIGN (ARG_POINTER_REGNUM) = 64; \ 1188 } while (0) 1189 1190 /* Register numbers used for passing a function's static chain pointer. */ 1191 /* ??? The ABI sez the static chain should be passed as a normal parameter. */ 1192 #define STATIC_CHAIN_REGNUM 15 1193 1194 /* Eliminating the Frame Pointer and the Arg Pointer */ 1195 1196 /* A C expression which is nonzero if a function must have and use a frame 1197 pointer. This expression is evaluated in the reload pass. If its value is 1198 nonzero the function will have a frame pointer. */ 1199 #define FRAME_POINTER_REQUIRED 0 1200 1201 /* Show we can debug even without a frame pointer. */ 1202 #define CAN_DEBUG_WITHOUT_FP 1203 1204 /* If defined, this macro specifies a table of register pairs used to eliminate 1205 unneeded registers that point into the stack frame. */ 1206 1207 #define ELIMINABLE_REGS \ 1208 { \ 1209 {ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1210 {ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1211 {FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1212 {FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1213 } 1214 1215 /* A C expression that returns nonzero if the compiler is allowed to try to 1216 replace register number FROM with register number TO. The frame pointer 1217 is automatically handled. */ 1218 1219 #define CAN_ELIMINATE(FROM, TO) \ 1220 (TO == BR_REG (0) ? current_function_is_leaf : 1) 1221 1222 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It 1223 specifies the initial difference between the specified pair of 1224 registers. This macro must be defined if `ELIMINABLE_REGS' is 1225 defined. */ 1226 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1227 ((OFFSET) = ia64_initial_elimination_offset ((FROM), (TO))) 1228 1229 /* Passing Function Arguments on the Stack */ 1230 1231 /* Define this macro if an argument declared in a prototype as an integral type 1232 smaller than `int' should actually be passed as an `int'. In addition to 1233 avoiding errors in certain cases of mismatch, it also makes for better code 1234 on certain machines. */ 1235 /* ??? Investigate. */ 1236 /* #define PROMOTE_PROTOTYPES */ 1237 1238 /* If defined, the maximum amount of space required for outgoing arguments will 1239 be computed and placed into the variable 1240 `current_function_outgoing_args_size'. */ 1241 1242 #define ACCUMULATE_OUTGOING_ARGS 1 1243 1244 /* A C expression that should indicate the number of bytes of its own arguments 1245 that a function pops on returning, or 0 if the function pops no arguments 1246 and the caller must therefore pop them all after the function returns. */ 1247 1248 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, STACK_SIZE) 0 1249 1250 1251 /* Function Arguments in Registers */ 1252 1253 #define MAX_ARGUMENT_SLOTS 8 1254 #define MAX_INT_RETURN_SLOTS 4 1255 #define GR_ARG_FIRST IN_REG (0) 1256 #define GR_RET_FIRST GR_REG (8) 1257 #define GR_RET_LAST GR_REG (11) 1258 #define FR_ARG_FIRST FR_REG (8) 1259 #define FR_RET_FIRST FR_REG (8) 1260 #define FR_RET_LAST FR_REG (15) 1261 #define AR_ARG_FIRST OUT_REG (0) 1262 1263 /* A C expression that controls whether a function argument is passed in a 1264 register, and which register. */ 1265 1266 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1267 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 0) 1268 1269 /* Define this macro if the target machine has "register windows", so that the 1270 register in which a function sees an arguments is not necessarily the same 1271 as the one in which the caller passed the argument. */ 1272 1273 #define FUNCTION_INCOMING_ARG(CUM, MODE, TYPE, NAMED) \ 1274 ia64_function_arg (&CUM, MODE, TYPE, NAMED, 1) 1275 1276 /* A C expression for the number of words, at the beginning of an argument, 1277 must be put in registers. The value must be zero for arguments that are 1278 passed entirely in registers or that are entirely pushed on the stack. */ 1279 1280 #define FUNCTION_ARG_PARTIAL_NREGS(CUM, MODE, TYPE, NAMED) \ 1281 ia64_function_arg_partial_nregs (&CUM, MODE, TYPE, NAMED) 1282 1283 /* A C expression that indicates when an argument must be passed by reference. 1284 If nonzero for an argument, a copy of that argument is made in memory and a 1285 pointer to the argument is passed instead of the argument itself. The 1286 pointer is passed in whatever way is appropriate for passing a pointer to 1287 that type. */ 1288 1289 #define FUNCTION_ARG_PASS_BY_REFERENCE(CUM, MODE, TYPE, NAMED) \ 1290 ia64_function_arg_pass_by_reference (&CUM, MODE, TYPE, NAMED) 1291 1292 /* Nonzero if we do not know how to pass TYPE solely in registers. */ 1293 1294 #define MUST_PASS_IN_STACK(MODE, TYPE) \ 1295 ((TYPE) != 0 \ 1296 && (TREE_CODE (TYPE_SIZE (TYPE)) != INTEGER_CST \ 1297 || TREE_ADDRESSABLE (TYPE))) 1298 1299 /* A C type for declaring a variable that is used as the first argument of 1300 `FUNCTION_ARG' and other related values. For some target machines, the type 1301 `int' suffices and can hold the number of bytes of argument so far. */ 1302 1303 typedef struct ia64_args 1304 { 1305 int words; /* # words of arguments so far */ 1306 int int_regs; /* # GR registers used so far */ 1307 int fp_regs; /* # FR registers used so far */ 1308 int prototype; /* whether function prototyped */ 1309 } CUMULATIVE_ARGS; 1310 1311 /* A C statement (sans semicolon) for initializing the variable CUM for the 1312 state at the beginning of the argument list. */ 1313 1314 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT) \ 1315 do { \ 1316 (CUM).words = 0; \ 1317 (CUM).int_regs = 0; \ 1318 (CUM).fp_regs = 0; \ 1319 (CUM).prototype = ((FNTYPE) && TYPE_ARG_TYPES (FNTYPE)) || (LIBNAME); \ 1320 } while (0) 1321 1322 /* Like `INIT_CUMULATIVE_ARGS' but overrides it for the purposes of finding the 1323 arguments for the function being compiled. If this macro is undefined, 1324 `INIT_CUMULATIVE_ARGS' is used instead. */ 1325 1326 /* We set prototype to true so that we never try to return a PARALLEL from 1327 function_arg. */ 1328 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1329 do { \ 1330 (CUM).words = 0; \ 1331 (CUM).int_regs = 0; \ 1332 (CUM).fp_regs = 0; \ 1333 (CUM).prototype = 1; \ 1334 } while (0) 1335 1336 /* A C statement (sans semicolon) to update the summarizer variable CUM to 1337 advance past an argument in the argument list. The values MODE, TYPE and 1338 NAMED describe that argument. Once this is done, the variable CUM is 1339 suitable for analyzing the *following* argument with `FUNCTION_ARG'. */ 1340 1341 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1342 ia64_function_arg_advance (&CUM, MODE, TYPE, NAMED) 1343 1344 /* If defined, a C expression that gives the alignment boundary, in bits, of an 1345 argument with the specified mode and type. */ 1346 1347 /* Arguments with alignment larger than 8 bytes start at the next even 1348 boundary. See ia64_function_arg. */ 1349 1350 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 1351 (((TYPE) ? (TYPE_ALIGN (TYPE) > 8 * BITS_PER_UNIT) \ 1352 : (((((MODE) == BLKmode \ 1353 ? int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) \ 1354 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) > 1)) \ 1355 ? 128 : PARM_BOUNDARY) 1356 1357 /* A C expression that is nonzero if REGNO is the number of a hard register in 1358 which function arguments are sometimes passed. This does *not* include 1359 implicit arguments such as the static chain and the structure-value address. 1360 On many machines, no registers can be used for this purpose since all 1361 function arguments are pushed on the stack. */ 1362 #define FUNCTION_ARG_REGNO_P(REGNO) \ 1363 (((REGNO) >= AR_ARG_FIRST && (REGNO) < (AR_ARG_FIRST + MAX_ARGUMENT_SLOTS)) \ 1364 || ((REGNO) >= FR_ARG_FIRST && (REGNO) < (FR_ARG_FIRST + MAX_ARGUMENT_SLOTS))) 1365 1366 /* Implement `va_arg'. */ 1367 #define EXPAND_BUILTIN_VA_ARG(valist, type) \ 1368 ia64_va_arg (valist, type) 1369 1370 /* How Scalar Function Values are Returned */ 1371 1372 /* A C expression to create an RTX representing the place where a function 1373 returns a value of data type VALTYPE. */ 1374 1375 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 1376 ia64_function_value (VALTYPE, FUNC) 1377 1378 /* A C expression to create an RTX representing the place where a library 1379 function returns a value of mode MODE. */ 1380 1381 #define LIBCALL_VALUE(MODE) \ 1382 gen_rtx_REG (MODE, \ 1383 (((GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1384 || GET_MODE_CLASS (MODE) == MODE_COMPLEX_FLOAT) && \ 1385 ((MODE) != TFmode || INTEL_EXTENDED_IEEE_FORMAT)) \ 1386 ? FR_RET_FIRST : GR_RET_FIRST)) 1387 1388 /* A C expression that is nonzero if REGNO is the number of a hard register in 1389 which the values of called function may come back. */ 1390 1391 #define FUNCTION_VALUE_REGNO_P(REGNO) \ 1392 (((REGNO) >= GR_RET_FIRST && (REGNO) <= GR_RET_LAST) \ 1393 || ((REGNO) >= FR_RET_FIRST && (REGNO) <= FR_RET_LAST)) 1394 1395 1396 /* How Large Values are Returned */ 1397 1398 /* A nonzero value says to return the function value in memory, just as large 1399 structures are always returned. */ 1400 1401 #define RETURN_IN_MEMORY(TYPE) \ 1402 ia64_return_in_memory (TYPE) 1403 1404 /* If you define this macro to be 0, then the conventions used for structure 1405 and union return values are decided by the `RETURN_IN_MEMORY' macro. */ 1406 1407 #define DEFAULT_PCC_STRUCT_RETURN 0 1408 1409 /* If the structure value address is passed in a register, then 1410 `STRUCT_VALUE_REGNUM' should be the number of that register. */ 1411 1412 #define STRUCT_VALUE_REGNUM GR_REG (8) 1413 1414 1415 /* Caller-Saves Register Allocation */ 1416 1417 /* A C expression to determine whether it is worthwhile to consider placing a 1418 pseudo-register in a call-clobbered hard register and saving and restoring 1419 it around each function call. The expression should be 1 when this is worth 1420 doing, and 0 otherwise. 1421 1422 If you don't define this macro, a default is used which is good on most 1423 machines: `4 * CALLS < REFS'. */ 1424 /* ??? Investigate. */ 1425 /* #define CALLER_SAVE_PROFITABLE(REFS, CALLS) */ 1426 1427 1428 /* Function Entry and Exit */ 1429 1430 /* Define this macro as a C expression that is nonzero if the return 1431 instruction or the function epilogue ignores the value of the stack pointer; 1432 in other words, if it is safe to delete an instruction to adjust the stack 1433 pointer before a return from the function. */ 1434 1435 #define EXIT_IGNORE_STACK 1 1436 1437 /* Define this macro as a C expression that is nonzero for registers 1438 used by the epilogue or the `return' pattern. */ 1439 1440 #define EPILOGUE_USES(REGNO) ia64_epilogue_uses (REGNO) 1441 1442 /* Nonzero for registers used by the exception handling mechanism. */ 1443 1444 #define EH_USES(REGNO) ia64_eh_uses (REGNO) 1445 1446 /* Output at beginning of assembler file. */ 1447 1448 #define ASM_FILE_START(FILE) \ 1449 emit_safe_across_calls (FILE) 1450 1451 /* Output part N of a function descriptor for DECL. For ia64, both 1452 words are emitted with a single relocation, so ignore N > 0. */ 1453 #define ASM_OUTPUT_FDESC(FILE, DECL, PART) \ 1454 do { \ 1455 if ((PART) == 0) \ 1456 { \ 1457 if (TARGET_ILP32) \ 1458 fputs ("\tdata8.ua @iplt(", FILE); \ 1459 else \ 1460 fputs ("\tdata16.ua @iplt(", FILE); \ 1461 assemble_name (FILE, XSTR (XEXP (DECL_RTL (DECL), 0), 0)); \ 1462 fputs (")\n", FILE); \ 1463 if (TARGET_ILP32) \ 1464 fputs ("\tdata8.ua 0\n", FILE); \ 1465 } \ 1466 } while (0) 1467 1468 /* Generating Code for Profiling. */ 1469 1470 /* A C statement or compound statement to output to FILE some assembler code to 1471 call the profiling subroutine `mcount'. */ 1472 1473 #undef FUNCTION_PROFILER 1474 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1475 do { \ 1476 char buf[20]; \ 1477 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", LABELNO); \ 1478 fputs ("\talloc out0 = ar.pfs, 8, 0, 4, 0\n", FILE); \ 1479 if (TARGET_AUTO_PIC) \ 1480 fputs ("\tmovl out3 = @gprel(", FILE); \ 1481 else \ 1482 fputs ("\taddl out3 = @ltoff(", FILE); \ 1483 assemble_name (FILE, buf); \ 1484 if (TARGET_AUTO_PIC) \ 1485 fputs (");;\n", FILE); \ 1486 else \ 1487 fputs ("), r1;;\n", FILE); \ 1488 fputs ("\tmov out1 = r1\n", FILE); \ 1489 fputs ("\tmov out2 = b0\n", FILE); \ 1490 fputs ("\tbr.call.sptk.many b0 = _mcount;;\n", FILE); \ 1491 } while (0) 1492 1493 /* Implementing the Varargs Macros. */ 1494 1495 /* Define this macro to store the anonymous register arguments into the stack 1496 so that all the arguments appear to have been passed consecutively on the 1497 stack. */ 1498 1499 #define SETUP_INCOMING_VARARGS(ARGS_SO_FAR, MODE, TYPE, PRETEND_ARGS_SIZE, SECOND_TIME) \ 1500 ia64_setup_incoming_varargs (ARGS_SO_FAR, MODE, TYPE, & PRETEND_ARGS_SIZE, SECOND_TIME) 1501 1502 /* Define this macro if the location where a function argument is passed 1503 depends on whether or not it is a named argument. */ 1504 1505 #define STRICT_ARGUMENT_NAMING 1 1506 1507 1508 /* Trampolines for Nested Functions. */ 1509 1510 /* We need 32 bytes, so we can save the sp, ar.rnat, ar.bsp, and ar.pfs of 1511 the function containing a non-local goto target. */ 1512 1513 #define STACK_SAVEAREA_MODE(LEVEL) \ 1514 ((LEVEL) == SAVE_NONLOCAL ? OImode : Pmode) 1515 1516 /* Output assembler code for a block containing the constant parts of 1517 a trampoline, leaving space for the variable parts. 1518 1519 The trampoline should set the static chain pointer to value placed 1520 into the trampoline and should branch to the specified routine. 1521 To make the normal indirect-subroutine calling convention work, 1522 the trampoline must look like a function descriptor; the first 1523 word being the target address and the second being the target's 1524 global pointer. 1525 1526 We abuse the concept of a global pointer by arranging for it 1527 to point to the data we need to load. The complete trampoline 1528 has the following form: 1529 1530 +-------------------+ \ 1531 TRAMP: | __ia64_trampoline | | 1532 +-------------------+ > fake function descriptor 1533 | TRAMP+16 | | 1534 +-------------------+ / 1535 | target descriptor | 1536 +-------------------+ 1537 | static link | 1538 +-------------------+ 1539 */ 1540 1541 /* A C expression for the size in bytes of the trampoline, as an integer. */ 1542 1543 #define TRAMPOLINE_SIZE 32 1544 1545 /* Alignment required for trampolines, in bits. */ 1546 1547 #define TRAMPOLINE_ALIGNMENT 64 1548 1549 /* A C statement to initialize the variable parts of a trampoline. */ 1550 1551 #define INITIALIZE_TRAMPOLINE(ADDR, FNADDR, STATIC_CHAIN) \ 1552 ia64_initialize_trampoline((ADDR), (FNADDR), (STATIC_CHAIN)) 1553 1554 /* Implicit Calls to Library Routines */ 1555 1556 /* Define this macro if GNU CC should generate calls to the System V (and ANSI 1557 C) library functions `memcpy' and `memset' rather than the BSD functions 1558 `bcopy' and `bzero'. */ 1559 1560 #define TARGET_MEM_FUNCTIONS 1561 1562 1563 /* Addressing Modes */ 1564 1565 /* Define this macro if the machine supports post-increment addressing. */ 1566 1567 #define HAVE_POST_INCREMENT 1 1568 #define HAVE_POST_DECREMENT 1 1569 #define HAVE_POST_MODIFY_DISP 1 1570 #define HAVE_POST_MODIFY_REG 1 1571 1572 /* A C expression that is 1 if the RTX X is a constant which is a valid 1573 address. */ 1574 1575 #define CONSTANT_ADDRESS_P(X) 0 1576 1577 /* The max number of registers that can appear in a valid memory address. */ 1578 1579 #define MAX_REGS_PER_ADDRESS 2 1580 1581 /* A C compound statement with a conditional `goto LABEL;' executed if X (an 1582 RTX) is a legitimate memory address on the target machine for a memory 1583 operand of mode MODE. */ 1584 1585 #define LEGITIMATE_ADDRESS_REG(X) \ 1586 ((GET_CODE (X) == REG && REG_OK_FOR_BASE_P (X)) \ 1587 || (GET_CODE (X) == SUBREG && GET_CODE (XEXP (X, 0)) == REG \ 1588 && REG_OK_FOR_BASE_P (XEXP (X, 0)))) 1589 1590 #define LEGITIMATE_ADDRESS_DISP(R, X) \ 1591 (GET_CODE (X) == PLUS \ 1592 && rtx_equal_p (R, XEXP (X, 0)) \ 1593 && (LEGITIMATE_ADDRESS_REG (XEXP (X, 1)) \ 1594 || (GET_CODE (XEXP (X, 1)) == CONST_INT \ 1595 && INTVAL (XEXP (X, 1)) >= -256 \ 1596 && INTVAL (XEXP (X, 1)) < 256))) 1597 1598 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, LABEL) \ 1599 do { \ 1600 if (LEGITIMATE_ADDRESS_REG (X)) \ 1601 goto LABEL; \ 1602 else if ((GET_CODE (X) == POST_INC || GET_CODE (X) == POST_DEC) \ 1603 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \ 1604 && XEXP (X, 0) != arg_pointer_rtx) \ 1605 goto LABEL; \ 1606 else if (GET_CODE (X) == POST_MODIFY \ 1607 && LEGITIMATE_ADDRESS_REG (XEXP (X, 0)) \ 1608 && XEXP (X, 0) != arg_pointer_rtx \ 1609 && LEGITIMATE_ADDRESS_DISP (XEXP (X, 0), XEXP (X, 1))) \ 1610 goto LABEL; \ 1611 } while (0) 1612 1613 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for 1614 use as a base register. */ 1615 1616 #ifdef REG_OK_STRICT 1617 #define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X)) 1618 #else 1619 #define REG_OK_FOR_BASE_P(X) \ 1620 (GENERAL_REGNO_P (REGNO (X)) || (REGNO (X) >= FIRST_PSEUDO_REGISTER)) 1621 #endif 1622 1623 /* A C expression that is nonzero if X (assumed to be a `reg' RTX) is valid for 1624 use as an index register. This is needed for POST_MODIFY. */ 1625 1626 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) 1627 1628 /* A C compound statement that attempts to replace X with a valid memory 1629 address for an operand of mode MODE. 1630 1631 This must be present, but there is nothing useful to be done here. */ 1632 1633 #define LEGITIMIZE_ADDRESS(X, OLDX, MODE, WIN) 1634 1635 /* A C statement or compound statement with a conditional `goto LABEL;' 1636 executed if memory address X (an RTX) can have different meanings depending 1637 on the machine mode of the memory reference it is used for or if the address 1638 is valid for some modes but not others. */ 1639 1640 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 1641 if (GET_CODE (ADDR) == POST_DEC || GET_CODE (ADDR) == POST_INC) \ 1642 goto LABEL; 1643 1644 /* A C expression that is nonzero if X is a legitimate constant for an 1645 immediate operand on the target machine. */ 1646 1647 #define LEGITIMATE_CONSTANT_P(X) \ 1648 (GET_CODE (X) != CONST_DOUBLE || GET_MODE (X) == VOIDmode \ 1649 || GET_MODE (X) == DImode || CONST_DOUBLE_OK_FOR_G (X)) \ 1650 1651 1652 /* Condition Code Status */ 1653 1654 /* One some machines not all possible comparisons are defined, but you can 1655 convert an invalid comparison into a valid one. */ 1656 /* ??? Investigate. See the alpha definition. */ 1657 /* #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) */ 1658 1659 1660 /* Describing Relative Costs of Operations */ 1661 1662 /* A part of a C `switch' statement that describes the relative costs of 1663 constant RTL expressions. */ 1664 1665 /* ??? This is incomplete. */ 1666 1667 #define CONST_COSTS(X, CODE, OUTER_CODE) \ 1668 case CONST_INT: \ 1669 if ((X) == const0_rtx) \ 1670 return 0; \ 1671 switch (OUTER_CODE) \ 1672 { \ 1673 case SET: \ 1674 return CONST_OK_FOR_J (INTVAL (X)) ? 0 : COSTS_N_INSNS (1); \ 1675 case PLUS: \ 1676 if (CONST_OK_FOR_I (INTVAL (X))) \ 1677 return 0; \ 1678 if (CONST_OK_FOR_J (INTVAL (X))) \ 1679 return 1; \ 1680 return COSTS_N_INSNS (1); \ 1681 default: \ 1682 if (CONST_OK_FOR_K (INTVAL (X)) || CONST_OK_FOR_L (INTVAL (X))) \ 1683 return 0; \ 1684 return COSTS_N_INSNS (1); \ 1685 } \ 1686 case CONST_DOUBLE: \ 1687 return COSTS_N_INSNS (1); \ 1688 case CONST: \ 1689 case SYMBOL_REF: \ 1690 case LABEL_REF: \ 1691 return COSTS_N_INSNS (3); 1692 1693 /* Like `CONST_COSTS' but applies to nonconstant RTL expressions. */ 1694 1695 #define RTX_COSTS(X, CODE, OUTER_CODE) \ 1696 case MULT: \ 1697 /* For multiplies wider than HImode, we have to go to the FPU, \ 1698 which normally involves copies. Plus there's the latency \ 1699 of the multiply itself, and the latency of the instructions to \ 1700 transfer integer regs to FP regs. */ \ 1701 if (GET_MODE_SIZE (GET_MODE (X)) > 2) \ 1702 return COSTS_N_INSNS (10); \ 1703 return COSTS_N_INSNS (2); \ 1704 case PLUS: \ 1705 case MINUS: \ 1706 case ASHIFT: \ 1707 case ASHIFTRT: \ 1708 case LSHIFTRT: \ 1709 return COSTS_N_INSNS (1); \ 1710 case DIV: \ 1711 case UDIV: \ 1712 case MOD: \ 1713 case UMOD: \ 1714 /* We make divide expensive, so that divide-by-constant will be \ 1715 optimized to a multiply. */ \ 1716 return COSTS_N_INSNS (60); 1717 1718 /* An expression giving the cost of an addressing mode that contains ADDRESS. 1719 If not defined, the cost is computed from the ADDRESS expression and the 1720 `CONST_COSTS' values. */ 1721 1722 #define ADDRESS_COST(ADDRESS) 0 1723 1724 /* A C expression for the cost of moving data from a register in class FROM to 1725 one in class TO, using MODE. */ 1726 1727 #define REGISTER_MOVE_COST ia64_register_move_cost 1728 1729 /* A C expression for the cost of moving data of mode M between a 1730 register and memory. */ 1731 #define MEMORY_MOVE_COST(MODE,CLASS,IN) \ 1732 ((CLASS) == GENERAL_REGS || (CLASS) == FR_REGS \ 1733 || (CLASS) == GR_AND_FR_REGS ? 4 : 10) 1734 1735 /* A C expression for the cost of a branch instruction. A value of 1 is the 1736 default; other values are interpreted relative to that. Used by the 1737 if-conversion code as max instruction count. */ 1738 /* ??? This requires investigation. The primary effect might be how 1739 many additional insn groups we run into, vs how good the dynamic 1740 branch predictor is. */ 1741 1742 #define BRANCH_COST 6 1743 1744 /* Define this macro as a C expression which is nonzero if accessing less than 1745 a word of memory (i.e. a `char' or a `short') is no faster than accessing a 1746 word of memory. */ 1747 1748 #define SLOW_BYTE_ACCESS 1 1749 1750 /* Define this macro if it is as good or better to call a constant function 1751 address than to call an address kept in a register. 1752 1753 Indirect function calls are more expensive that direct function calls, so 1754 don't cse function addresses. */ 1755 1756 #define NO_FUNCTION_CSE 1757 1758 1759 /* Dividing the output into sections. */ 1760 1761 /* A C expression whose value is a string containing the assembler operation 1762 that should precede instructions and read-only data. */ 1763 1764 #define TEXT_SECTION_ASM_OP "\t.text" 1765 1766 /* A C expression whose value is a string containing the assembler operation to 1767 identify the following data as writable initialized data. */ 1768 1769 #define DATA_SECTION_ASM_OP "\t.data" 1770 1771 /* If defined, a C expression whose value is a string containing the assembler 1772 operation to identify the following data as uninitialized global data. */ 1773 1774 #define BSS_SECTION_ASM_OP "\t.bss" 1775 1776 #define ENCODE_SECTION_INFO_CHAR '@' 1777 1778 #define IA64_DEFAULT_GVALUE 8 1779 1780 /* Position Independent Code. */ 1781 1782 /* The register number of the register used to address a table of static data 1783 addresses in memory. */ 1784 1785 /* ??? Should modify ia64.md to use pic_offset_table_rtx instead of 1786 gen_rtx_REG (DImode, 1). */ 1787 1788 /* ??? Should we set flag_pic? Probably need to define 1789 LEGITIMIZE_PIC_OPERAND_P to make that work. */ 1790 1791 #define PIC_OFFSET_TABLE_REGNUM GR_REG (1) 1792 1793 /* Define this macro if the register defined by `PIC_OFFSET_TABLE_REGNUM' is 1794 clobbered by calls. */ 1795 1796 #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED 1797 1798 1799 /* The Overall Framework of an Assembler File. */ 1800 1801 /* A C string constant describing how to begin a comment in the target 1802 assembler language. The compiler assumes that the comment will end at the 1803 end of the line. */ 1804 1805 #define ASM_COMMENT_START "//" 1806 1807 /* A C string constant for text to be output before each `asm' statement or 1808 group of consecutive ones. */ 1809 1810 /* ??? This won't work with the Intel assembler, because it does not accept 1811 # as a comment start character. However, //APP does not work in gas, so we 1812 can't use that either. Same problem for ASM_APP_OFF below. */ 1813 1814 #define ASM_APP_ON "#APP\n" 1815 1816 /* A C string constant for text to be output after each `asm' statement or 1817 group of consecutive ones. */ 1818 1819 #define ASM_APP_OFF "#NO_APP\n" 1820 1821 1822 /* Output of Uninitialized Variables. */ 1823 1824 /* This is all handled by svr4.h. */ 1825 1826 1827 /* Output and Generation of Labels. */ 1828 1829 /* A C statement (sans semicolon) to output to the stdio stream STREAM the 1830 assembler definition of a label named NAME. */ 1831 1832 /* See the ASM_OUTPUT_LABELREF definition in sysv4.h for an explanation of 1833 why ia64_asm_output_label exists. */ 1834 1835 extern int ia64_asm_output_label; 1836 #define ASM_OUTPUT_LABEL(STREAM, NAME) \ 1837 do { \ 1838 ia64_asm_output_label = 1; \ 1839 assemble_name (STREAM, NAME); \ 1840 fputs (":\n", STREAM); \ 1841 ia64_asm_output_label = 0; \ 1842 } while (0) 1843 1844 /* Globalizing directive for a label. */ 1845 #define GLOBAL_ASM_OP "\t.global " 1846 1847 /* A C statement (sans semicolon) to output to the stdio stream STREAM any text 1848 necessary for declaring the name of an external symbol named NAME which is 1849 referenced in this compilation but not defined. */ 1850 1851 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ 1852 ia64_asm_output_external (FILE, DECL, NAME) 1853 1854 /* A C statement to store into the string STRING a label whose name is made 1855 from the string PREFIX and the number NUM. */ 1856 1857 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ 1858 do { \ 1859 sprintf (LABEL, "*.%s%d", PREFIX, NUM); \ 1860 } while (0) 1861 1862 /* A C expression to assign to OUTVAR (which is a variable of type `char *') a 1863 newly allocated string made from the string NAME and the number NUMBER, with 1864 some suitable punctuation added. */ 1865 1866 /* ??? Not sure if using a ? in the name for Intel as is safe. */ 1867 1868 #define ASM_FORMAT_PRIVATE_NAME(OUTVAR, NAME, NUMBER) \ 1869 do { \ 1870 (OUTVAR) = (char *) alloca (strlen (NAME) + 12); \ 1871 sprintf (OUTVAR, "%s%c%ld", (NAME), (TARGET_GNU_AS ? '.' : '?'), \ 1872 (long)(NUMBER)); \ 1873 } while (0) 1874 1875 /* A C statement to output to the stdio stream STREAM assembler code which 1876 defines (equates) the symbol NAME to have the value VALUE. */ 1877 1878 #define ASM_OUTPUT_DEF(STREAM, NAME, VALUE) \ 1879 do { \ 1880 assemble_name (STREAM, NAME); \ 1881 fputs (" = ", STREAM); \ 1882 assemble_name (STREAM, VALUE); \ 1883 fputc ('\n', STREAM); \ 1884 } while (0) 1885 1886 1887 /* Macros Controlling Initialization Routines. */ 1888 1889 /* This is handled by svr4.h and sysv4.h. */ 1890 1891 1892 /* Output of Assembler Instructions. */ 1893 1894 /* A C initializer containing the assembler's names for the machine registers, 1895 each one as a C string constant. */ 1896 1897 #define REGISTER_NAMES \ 1898 { \ 1899 /* General registers. */ \ 1900 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", \ 1901 "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17", "r18", "r19", \ 1902 "r20", "r21", "r22", "r23", "r24", "r25", "r26", "r27", "r28", "r29", \ 1903 "r30", "r31", \ 1904 /* Local registers. */ \ 1905 "loc0", "loc1", "loc2", "loc3", "loc4", "loc5", "loc6", "loc7", \ 1906 "loc8", "loc9", "loc10","loc11","loc12","loc13","loc14","loc15", \ 1907 "loc16","loc17","loc18","loc19","loc20","loc21","loc22","loc23", \ 1908 "loc24","loc25","loc26","loc27","loc28","loc29","loc30","loc31", \ 1909 "loc32","loc33","loc34","loc35","loc36","loc37","loc38","loc39", \ 1910 "loc40","loc41","loc42","loc43","loc44","loc45","loc46","loc47", \ 1911 "loc48","loc49","loc50","loc51","loc52","loc53","loc54","loc55", \ 1912 "loc56","loc57","loc58","loc59","loc60","loc61","loc62","loc63", \ 1913 "loc64","loc65","loc66","loc67","loc68","loc69","loc70","loc71", \ 1914 "loc72","loc73","loc74","loc75","loc76","loc77","loc78","loc79", \ 1915 /* Input registers. */ \ 1916 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", \ 1917 /* Output registers. */ \ 1918 "out0", "out1", "out2", "out3", "out4", "out5", "out6", "out7", \ 1919 /* Floating-point registers. */ \ 1920 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", "f8", "f9", \ 1921 "f10", "f11", "f12", "f13", "f14", "f15", "f16", "f17", "f18", "f19", \ 1922 "f20", "f21", "f22", "f23", "f24", "f25", "f26", "f27", "f28", "f29", \ 1923 "f30", "f31", "f32", "f33", "f34", "f35", "f36", "f37", "f38", "f39", \ 1924 "f40", "f41", "f42", "f43", "f44", "f45", "f46", "f47", "f48", "f49", \ 1925 "f50", "f51", "f52", "f53", "f54", "f55", "f56", "f57", "f58", "f59", \ 1926 "f60", "f61", "f62", "f63", "f64", "f65", "f66", "f67", "f68", "f69", \ 1927 "f70", "f71", "f72", "f73", "f74", "f75", "f76", "f77", "f78", "f79", \ 1928 "f80", "f81", "f82", "f83", "f84", "f85", "f86", "f87", "f88", "f89", \ 1929 "f90", "f91", "f92", "f93", "f94", "f95", "f96", "f97", "f98", "f99", \ 1930 "f100","f101","f102","f103","f104","f105","f106","f107","f108","f109",\ 1931 "f110","f111","f112","f113","f114","f115","f116","f117","f118","f119",\ 1932 "f120","f121","f122","f123","f124","f125","f126","f127", \ 1933 /* Predicate registers. */ \ 1934 "p0", "p1", "p2", "p3", "p4", "p5", "p6", "p7", "p8", "p9", \ 1935 "p10", "p11", "p12", "p13", "p14", "p15", "p16", "p17", "p18", "p19", \ 1936 "p20", "p21", "p22", "p23", "p24", "p25", "p26", "p27", "p28", "p29", \ 1937 "p30", "p31", "p32", "p33", "p34", "p35", "p36", "p37", "p38", "p39", \ 1938 "p40", "p41", "p42", "p43", "p44", "p45", "p46", "p47", "p48", "p49", \ 1939 "p50", "p51", "p52", "p53", "p54", "p55", "p56", "p57", "p58", "p59", \ 1940 "p60", "p61", "p62", "p63", \ 1941 /* Branch registers. */ \ 1942 "b0", "b1", "b2", "b3", "b4", "b5", "b6", "b7", \ 1943 /* Frame pointer. Application registers. */ \ 1944 "sfp", "ar.ccv", "ar.unat", "ar.pfs", "ar.lc", "ar.ec", \ 1945 } 1946 1947 /* If defined, a C initializer for an array of structures containing a name and 1948 a register number. This macro defines additional names for hard registers, 1949 thus allowing the `asm' option in declarations to refer to registers using 1950 alternate names. */ 1951 1952 #define ADDITIONAL_REGISTER_NAMES \ 1953 { \ 1954 { "gp", R_GR (1) }, \ 1955 { "sp", R_GR (12) }, \ 1956 { "in0", IN_REG (0) }, \ 1957 { "in1", IN_REG (1) }, \ 1958 { "in2", IN_REG (2) }, \ 1959 { "in3", IN_REG (3) }, \ 1960 { "in4", IN_REG (4) }, \ 1961 { "in5", IN_REG (5) }, \ 1962 { "in6", IN_REG (6) }, \ 1963 { "in7", IN_REG (7) }, \ 1964 { "out0", OUT_REG (0) }, \ 1965 { "out1", OUT_REG (1) }, \ 1966 { "out2", OUT_REG (2) }, \ 1967 { "out3", OUT_REG (3) }, \ 1968 { "out4", OUT_REG (4) }, \ 1969 { "out5", OUT_REG (5) }, \ 1970 { "out6", OUT_REG (6) }, \ 1971 { "out7", OUT_REG (7) }, \ 1972 { "loc0", LOC_REG (0) }, \ 1973 { "loc1", LOC_REG (1) }, \ 1974 { "loc2", LOC_REG (2) }, \ 1975 { "loc3", LOC_REG (3) }, \ 1976 { "loc4", LOC_REG (4) }, \ 1977 { "loc5", LOC_REG (5) }, \ 1978 { "loc6", LOC_REG (6) }, \ 1979 { "loc7", LOC_REG (7) }, \ 1980 { "loc8", LOC_REG (8) }, \ 1981 { "loc9", LOC_REG (9) }, \ 1982 { "loc10", LOC_REG (10) }, \ 1983 { "loc11", LOC_REG (11) }, \ 1984 { "loc12", LOC_REG (12) }, \ 1985 { "loc13", LOC_REG (13) }, \ 1986 { "loc14", LOC_REG (14) }, \ 1987 { "loc15", LOC_REG (15) }, \ 1988 { "loc16", LOC_REG (16) }, \ 1989 { "loc17", LOC_REG (17) }, \ 1990 { "loc18", LOC_REG (18) }, \ 1991 { "loc19", LOC_REG (19) }, \ 1992 { "loc20", LOC_REG (20) }, \ 1993 { "loc21", LOC_REG (21) }, \ 1994 { "loc22", LOC_REG (22) }, \ 1995 { "loc23", LOC_REG (23) }, \ 1996 { "loc24", LOC_REG (24) }, \ 1997 { "loc25", LOC_REG (25) }, \ 1998 { "loc26", LOC_REG (26) }, \ 1999 { "loc27", LOC_REG (27) }, \ 2000 { "loc28", LOC_REG (28) }, \ 2001 { "loc29", LOC_REG (29) }, \ 2002 { "loc30", LOC_REG (30) }, \ 2003 { "loc31", LOC_REG (31) }, \ 2004 { "loc32", LOC_REG (32) }, \ 2005 { "loc33", LOC_REG (33) }, \ 2006 { "loc34", LOC_REG (34) }, \ 2007 { "loc35", LOC_REG (35) }, \ 2008 { "loc36", LOC_REG (36) }, \ 2009 { "loc37", LOC_REG (37) }, \ 2010 { "loc38", LOC_REG (38) }, \ 2011 { "loc39", LOC_REG (39) }, \ 2012 { "loc40", LOC_REG (40) }, \ 2013 { "loc41", LOC_REG (41) }, \ 2014 { "loc42", LOC_REG (42) }, \ 2015 { "loc43", LOC_REG (43) }, \ 2016 { "loc44", LOC_REG (44) }, \ 2017 { "loc45", LOC_REG (45) }, \ 2018 { "loc46", LOC_REG (46) }, \ 2019 { "loc47", LOC_REG (47) }, \ 2020 { "loc48", LOC_REG (48) }, \ 2021 { "loc49", LOC_REG (49) }, \ 2022 { "loc50", LOC_REG (50) }, \ 2023 { "loc51", LOC_REG (51) }, \ 2024 { "loc52", LOC_REG (52) }, \ 2025 { "loc53", LOC_REG (53) }, \ 2026 { "loc54", LOC_REG (54) }, \ 2027 { "loc55", LOC_REG (55) }, \ 2028 { "loc56", LOC_REG (56) }, \ 2029 { "loc57", LOC_REG (57) }, \ 2030 { "loc58", LOC_REG (58) }, \ 2031 { "loc59", LOC_REG (59) }, \ 2032 { "loc60", LOC_REG (60) }, \ 2033 { "loc61", LOC_REG (61) }, \ 2034 { "loc62", LOC_REG (62) }, \ 2035 { "loc63", LOC_REG (63) }, \ 2036 { "loc64", LOC_REG (64) }, \ 2037 { "loc65", LOC_REG (65) }, \ 2038 { "loc66", LOC_REG (66) }, \ 2039 { "loc67", LOC_REG (67) }, \ 2040 { "loc68", LOC_REG (68) }, \ 2041 { "loc69", LOC_REG (69) }, \ 2042 { "loc70", LOC_REG (70) }, \ 2043 { "loc71", LOC_REG (71) }, \ 2044 { "loc72", LOC_REG (72) }, \ 2045 { "loc73", LOC_REG (73) }, \ 2046 { "loc74", LOC_REG (74) }, \ 2047 { "loc75", LOC_REG (75) }, \ 2048 { "loc76", LOC_REG (76) }, \ 2049 { "loc77", LOC_REG (77) }, \ 2050 { "loc78", LOC_REG (78) }, \ 2051 { "loc79", LOC_REG (79) }, \ 2052 } 2053 2054 /* A C compound statement to output to stdio stream STREAM the assembler syntax 2055 for an instruction operand X. X is an RTL expression. */ 2056 2057 #define PRINT_OPERAND(STREAM, X, CODE) \ 2058 ia64_print_operand (STREAM, X, CODE) 2059 2060 /* A C expression which evaluates to true if CODE is a valid punctuation 2061 character for use in the `PRINT_OPERAND' macro. */ 2062 2063 /* ??? Keep this around for now, as we might need it later. */ 2064 2065 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2066 ((CODE) == '+' || (CODE) == ',') 2067 2068 /* A C compound statement to output to stdio stream STREAM the assembler syntax 2069 for an instruction operand that is a memory reference whose address is X. X 2070 is an RTL expression. */ 2071 2072 #define PRINT_OPERAND_ADDRESS(STREAM, X) \ 2073 ia64_print_operand_address (STREAM, X) 2074 2075 /* If defined, C string expressions to be used for the `%R', `%L', `%U', and 2076 `%I' options of `asm_fprintf' (see `final.c'). */ 2077 2078 #define REGISTER_PREFIX "" 2079 #define LOCAL_LABEL_PREFIX "." 2080 #define USER_LABEL_PREFIX "" 2081 #define IMMEDIATE_PREFIX "" 2082 2083 2084 /* Output of dispatch tables. */ 2085 2086 /* This macro should be provided on machines where the addresses in a dispatch 2087 table are relative to the table's own address. */ 2088 2089 /* ??? Depends on the pointer size. */ 2090 2091 #define ASM_OUTPUT_ADDR_DIFF_ELT(STREAM, BODY, VALUE, REL) \ 2092 do { \ 2093 if (TARGET_ILP32) \ 2094 fprintf (STREAM, "\tdata4 @pcrel(.L%d)\n", VALUE); \ 2095 else \ 2096 fprintf (STREAM, "\tdata8 @pcrel(.L%d)\n", VALUE); \ 2097 } while (0) 2098 2099 /* This is how to output an element of a case-vector that is absolute. 2100 (Ia64 does not use such vectors, but we must define this macro anyway.) */ 2101 2102 #define ASM_OUTPUT_ADDR_VEC_ELT(STREAM, VALUE) abort () 2103 2104 /* Jump tables only need 8 byte alignment. */ 2105 2106 #define ADDR_VEC_ALIGN(ADDR_VEC) 3 2107 2108 2109 /* Assembler Commands for Exception Regions. */ 2110 2111 /* Select a format to encode pointers in exception handling data. CODE 2112 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 2113 true if the symbol may be affected by dynamic relocations. */ 2114 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 2115 (((CODE) == 1 ? DW_EH_PE_textrel : DW_EH_PE_datarel) \ 2116 | ((GLOBAL) ? DW_EH_PE_indirect : 0) \ 2117 | (TARGET_ILP32 ? DW_EH_PE_udata4 : DW_EH_PE_udata8)) 2118 2119 /* Handle special EH pointer encodings. Absolute, pc-relative, and 2120 indirect are handled automatically. */ 2121 #define ASM_MAYBE_OUTPUT_ENCODED_ADDR_RTX(FILE, ENCODING, SIZE, ADDR, DONE) \ 2122 do { \ 2123 const char *reltag = NULL; \ 2124 if (((ENCODING) & 0xF0) == DW_EH_PE_textrel) \ 2125 reltag = "@segrel("; \ 2126 else if (((ENCODING) & 0xF0) == DW_EH_PE_datarel) \ 2127 reltag = "@gprel("; \ 2128 if (reltag) \ 2129 { \ 2130 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 2131 fputs (reltag, FILE); \ 2132 assemble_name (FILE, XSTR (ADDR, 0)); \ 2133 fputc (')', FILE); \ 2134 goto DONE; \ 2135 } \ 2136 } while (0) 2137 2138 2139 /* Assembler Commands for Alignment. */ 2140 2141 /* ??? Investigate. */ 2142 2143 /* The alignment (log base 2) to put in front of LABEL, which follows 2144 a BARRIER. */ 2145 2146 /* #define LABEL_ALIGN_AFTER_BARRIER(LABEL) */ 2147 2148 /* The desired alignment for the location counter at the beginning 2149 of a loop. */ 2150 2151 /* #define LOOP_ALIGN(LABEL) */ 2152 2153 /* Define this macro if `ASM_OUTPUT_SKIP' should not be used in the text 2154 section because it fails put zeros in the bytes that are skipped. */ 2155 2156 #define ASM_NO_SKIP_IN_TEXT 1 2157 2158 /* A C statement to output to the stdio stream STREAM an assembler command to 2159 advance the location counter to a multiple of 2 to the POWER bytes. */ 2160 2161 #define ASM_OUTPUT_ALIGN(STREAM, POWER) \ 2162 fprintf (STREAM, "\t.align %d\n", 1<<(POWER)) 2163 2164 2165 /* Macros Affecting all Debug Formats. */ 2166 2167 /* This is handled in svr4.h and sysv4.h. */ 2168 2169 2170 /* Specific Options for DBX Output. */ 2171 2172 /* This is handled by dbxelf.h which is included by svr4.h. */ 2173 2174 2175 /* Open ended Hooks for DBX Output. */ 2176 2177 /* Likewise. */ 2178 2179 2180 /* File names in DBX format. */ 2181 2182 /* Likewise. */ 2183 2184 2185 /* Macros for SDB and Dwarf Output. */ 2186 2187 /* Define this macro if GNU CC should produce dwarf version 2 format debugging 2188 output in response to the `-g' option. */ 2189 2190 #define DWARF2_DEBUGGING_INFO 1 2191 2192 #define DWARF2_ASM_LINE_DEBUG_INFO (TARGET_DWARF2_ASM) 2193 2194 /* Use tags for debug info labels, so that they don't break instruction 2195 bundles. This also avoids getting spurious DV warnings from the 2196 assembler. This is similar to ASM_OUTPUT_INTERNAL_LABEL, except that we 2197 add brackets around the label. */ 2198 2199 #define ASM_OUTPUT_DEBUG_LABEL(FILE, PREFIX, NUM) \ 2200 fprintf (FILE, "[.%s%d:]\n", PREFIX, NUM) 2201 2202 /* Use section-relative relocations for debugging offsets. Unlike other 2203 targets that fake this by putting the section VMA at 0, IA-64 has 2204 proper relocations for them. */ 2205 #define ASM_OUTPUT_DWARF_OFFSET(FILE, SIZE, LABEL) \ 2206 do { \ 2207 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 2208 fputs ("@secrel(", FILE); \ 2209 assemble_name (FILE, LABEL); \ 2210 fputc (')', FILE); \ 2211 } while (0) 2212 2213 /* Emit a PC-relative relocation. */ 2214 #define ASM_OUTPUT_DWARF_PCREL(FILE, SIZE, LABEL) \ 2215 do { \ 2216 fputs (integer_asm_op (SIZE, FALSE), FILE); \ 2217 fputs ("@pcrel(", FILE); \ 2218 assemble_name (FILE, LABEL); \ 2219 fputc (')', FILE); \ 2220 } while (0) 2221 2222 /* Register Renaming Parameters. */ 2223 2224 /* A C expression that is nonzero if hard register number REGNO2 can be 2225 considered for use as a rename register for REGNO1 */ 2226 2227 #define HARD_REGNO_RENAME_OK(REGNO1,REGNO2) \ 2228 ia64_hard_regno_rename_ok((REGNO1), (REGNO2)) 2229 2230 2231 /* Miscellaneous Parameters. */ 2232 2233 /* Define this if you have defined special-purpose predicates in the file 2234 `MACHINE.c'. For each predicate, list all rtl codes that can be in 2235 expressions matched by the predicate. */ 2236 2237 #define PREDICATE_CODES \ 2238 { "call_operand", {SUBREG, REG, SYMBOL_REF}}, \ 2239 { "got_symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ 2240 { "sdata_symbolic_operand", {SYMBOL_REF, CONST}}, \ 2241 { "symbolic_operand", {SYMBOL_REF, CONST, LABEL_REF}}, \ 2242 { "function_operand", {SYMBOL_REF}}, \ 2243 { "setjmp_operand", {SYMBOL_REF}}, \ 2244 { "destination_operand", {SUBREG, REG, MEM}}, \ 2245 { "not_postinc_memory_operand", {MEM}}, \ 2246 { "move_operand", {SUBREG, REG, MEM, CONST_INT, CONST_DOUBLE, \ 2247 CONSTANT_P_RTX, SYMBOL_REF, CONST, LABEL_REF}}, \ 2248 { "gr_register_operand", {SUBREG, REG}}, \ 2249 { "fr_register_operand", {SUBREG, REG}}, \ 2250 { "grfr_register_operand", {SUBREG, REG}}, \ 2251 { "gr_nonimmediate_operand", {SUBREG, REG, MEM}}, \ 2252 { "fr_nonimmediate_operand", {SUBREG, REG, MEM}}, \ 2253 { "grfr_nonimmediate_operand", {SUBREG, REG, MEM}}, \ 2254 { "gr_reg_or_0_operand", {SUBREG, REG, CONST_INT}}, \ 2255 { "gr_reg_or_5bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ 2256 { "gr_reg_or_6bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ 2257 { "gr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ 2258 { "grfr_reg_or_8bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ 2259 { "gr_reg_or_8bit_adjusted_operand", {SUBREG, REG, CONST_INT, \ 2260 CONSTANT_P_RTX}}, \ 2261 { "gr_reg_or_8bit_and_adjusted_operand", {SUBREG, REG, CONST_INT, \ 2262 CONSTANT_P_RTX}}, \ 2263 { "gr_reg_or_14bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ 2264 { "gr_reg_or_22bit_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ 2265 { "shift_count_operand", {SUBREG, REG, CONST_INT, CONSTANT_P_RTX}}, \ 2266 { "shift_32bit_count_operand", {SUBREG, REG, CONST_INT, \ 2267 CONSTANT_P_RTX}}, \ 2268 { "shladd_operand", {CONST_INT}}, \ 2269 { "fetchadd_operand", {CONST_INT}}, \ 2270 { "fr_reg_or_fp01_operand", {SUBREG, REG, CONST_DOUBLE}}, \ 2271 { "normal_comparison_operator", {EQ, NE, GT, LE, GTU, LEU}}, \ 2272 { "adjusted_comparison_operator", {LT, GE, LTU, GEU}}, \ 2273 { "signed_inequality_operator", {GE, GT, LE, LT}}, \ 2274 { "predicate_operator", {NE, EQ}}, \ 2275 { "condop_operator", {PLUS, MINUS, IOR, XOR, AND}}, \ 2276 { "ar_lc_reg_operand", {REG}}, \ 2277 { "ar_ccv_reg_operand", {REG}}, \ 2278 { "ar_pfs_reg_operand", {REG}}, \ 2279 { "general_tfmode_operand", {SUBREG, REG, CONST_DOUBLE, MEM}}, \ 2280 { "destination_tfmode_operand", {SUBREG, REG, MEM}}, \ 2281 { "tfreg_or_fp01_operand", {REG, CONST_DOUBLE}}, \ 2282 { "basereg_operand", {SUBREG, REG}}, 2283 2284 /* An alias for a machine mode name. This is the machine mode that elements of 2285 a jump-table should have. */ 2286 2287 #define CASE_VECTOR_MODE ptr_mode 2288 2289 /* Define as C expression which evaluates to nonzero if the tablejump 2290 instruction expects the table to contain offsets from the address of the 2291 table. */ 2292 2293 #define CASE_VECTOR_PC_RELATIVE 1 2294 2295 /* Define this macro if operations between registers with integral mode smaller 2296 than a word are always performed on the entire register. */ 2297 2298 #define WORD_REGISTER_OPERATIONS 2299 2300 /* Define this macro to be a C expression indicating when insns that read 2301 memory in MODE, an integral mode narrower than a word, set the bits outside 2302 of MODE to be either the sign-extension or the zero-extension of the data 2303 read. */ 2304 2305 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 2306 2307 /* The maximum number of bytes that a single instruction can move quickly from 2308 memory to memory. */ 2309 #define MOVE_MAX 8 2310 2311 /* A C expression which is nonzero if on this machine it is safe to "convert" 2312 an integer of INPREC bits to one of OUTPREC bits (where OUTPREC is smaller 2313 than INPREC) by merely operating on it as if it had only OUTPREC bits. */ 2314 2315 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2316 2317 /* A C expression describing the value returned by a comparison operator with 2318 an integral mode and stored by a store-flag instruction (`sCOND') when the 2319 condition is true. */ 2320 2321 /* ??? Investigate using -1 instead of 1. */ 2322 2323 #define STORE_FLAG_VALUE 1 2324 2325 /* An alias for the machine mode for pointers. */ 2326 2327 /* ??? This would change if we had ILP32 support. */ 2328 2329 #define Pmode DImode 2330 2331 /* An alias for the machine mode used for memory references to functions being 2332 called, in `call' RTL expressions. */ 2333 2334 #define FUNCTION_MODE Pmode 2335 2336 /* Define this macro to handle System V style pragmas: #pragma pack and 2337 #pragma weak. Note, #pragma weak will only be supported if SUPPORT_WEAK is 2338 defined. */ 2339 2340 /* If this architecture supports prefetch, define this to be the number of 2341 prefetch commands that can be executed in parallel. 2342 2343 ??? This number is bogus and needs to be replaced before the value is 2344 actually used in optimizations. */ 2345 2346 #define SIMULTANEOUS_PREFETCHES 6 2347 2348 /* If this architecture supports prefetch, define this to be the size of 2349 the cache line that is prefetched. */ 2350 2351 #define PREFETCH_BLOCK 32 2352 2353 #define HANDLE_SYSV_PRAGMA 1 2354 2355 /* In rare cases, correct code generation requires extra machine dependent 2356 processing between the second jump optimization pass and delayed branch 2357 scheduling. On those machines, define this macro as a C statement to act on 2358 the code starting at INSN. */ 2359 2360 #define MACHINE_DEPENDENT_REORG(INSN) ia64_reorg (INSN) 2361 2362 /* A C expression for the maximum number of instructions to execute via 2363 conditional execution instructions instead of a branch. A value of 2364 BRANCH_COST+1 is the default if the machine does not use 2365 cc0, and 1 if it does use cc0. */ 2366 /* ??? Investigate. */ 2367 #define MAX_CONDITIONAL_EXECUTE 12 2368 2369 extern int ia64_final_schedule; 2370 2371 #define IA64_UNWIND_INFO 1 2372 #define IA64_UNWIND_EMIT(f,i) process_for_unwind_directive (f,i) 2373 2374 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 15 : INVALID_REGNUM) 2375 2376 /* This function contains machine specific function data. */ 2377 struct machine_function GTY(()) 2378 { 2379 /* The new stack pointer when unwinding from EH. */ 2380 rtx ia64_eh_epilogue_sp; 2381 2382 /* The new bsp value when unwinding from EH. */ 2383 rtx ia64_eh_epilogue_bsp; 2384 2385 /* The GP value save register. */ 2386 rtx ia64_gp_save; 2387 2388 /* The number of varargs registers to save. */ 2389 int n_varargs; 2390 }; 2391 2392 2393 enum ia64_builtins 2394 { 2395 IA64_BUILTIN_SYNCHRONIZE, 2396 2397 IA64_BUILTIN_FETCH_AND_ADD_SI, 2398 IA64_BUILTIN_FETCH_AND_SUB_SI, 2399 IA64_BUILTIN_FETCH_AND_OR_SI, 2400 IA64_BUILTIN_FETCH_AND_AND_SI, 2401 IA64_BUILTIN_FETCH_AND_XOR_SI, 2402 IA64_BUILTIN_FETCH_AND_NAND_SI, 2403 2404 IA64_BUILTIN_ADD_AND_FETCH_SI, 2405 IA64_BUILTIN_SUB_AND_FETCH_SI, 2406 IA64_BUILTIN_OR_AND_FETCH_SI, 2407 IA64_BUILTIN_AND_AND_FETCH_SI, 2408 IA64_BUILTIN_XOR_AND_FETCH_SI, 2409 IA64_BUILTIN_NAND_AND_FETCH_SI, 2410 2411 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_SI, 2412 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_SI, 2413 2414 IA64_BUILTIN_SYNCHRONIZE_SI, 2415 2416 IA64_BUILTIN_LOCK_TEST_AND_SET_SI, 2417 2418 IA64_BUILTIN_LOCK_RELEASE_SI, 2419 2420 IA64_BUILTIN_FETCH_AND_ADD_DI, 2421 IA64_BUILTIN_FETCH_AND_SUB_DI, 2422 IA64_BUILTIN_FETCH_AND_OR_DI, 2423 IA64_BUILTIN_FETCH_AND_AND_DI, 2424 IA64_BUILTIN_FETCH_AND_XOR_DI, 2425 IA64_BUILTIN_FETCH_AND_NAND_DI, 2426 2427 IA64_BUILTIN_ADD_AND_FETCH_DI, 2428 IA64_BUILTIN_SUB_AND_FETCH_DI, 2429 IA64_BUILTIN_OR_AND_FETCH_DI, 2430 IA64_BUILTIN_AND_AND_FETCH_DI, 2431 IA64_BUILTIN_XOR_AND_FETCH_DI, 2432 IA64_BUILTIN_NAND_AND_FETCH_DI, 2433 2434 IA64_BUILTIN_BOOL_COMPARE_AND_SWAP_DI, 2435 IA64_BUILTIN_VAL_COMPARE_AND_SWAP_DI, 2436 2437 IA64_BUILTIN_SYNCHRONIZE_DI, 2438 2439 IA64_BUILTIN_LOCK_TEST_AND_SET_DI, 2440 2441 IA64_BUILTIN_LOCK_RELEASE_DI, 2442 2443 IA64_BUILTIN_BSP, 2444 IA64_BUILTIN_FLUSHRS 2445 }; 2446 2447 /* Codes for expand_compare_and_swap and expand_swap_and_compare. */ 2448 enum fetchop_code { 2449 IA64_ADD_OP, IA64_SUB_OP, IA64_OR_OP, IA64_AND_OP, IA64_XOR_OP, IA64_NAND_OP 2450 }; 2451 2452 #define DONT_USE_BUILTIN_SETJMP 2453 2454 /* Output any profiling code before the prologue. */ 2455 2456 #undef PROFILE_BEFORE_PROLOGUE 2457 #define PROFILE_BEFORE_PROLOGUE 1 2458 2459 #define FUNCTION_OK_FOR_SIBCALL(DECL) ia64_function_ok_for_sibcall (DECL) 2460 /* End of ia64.h */ 2461