1 /* hp2100_defs.h: HP 2100 simulator definitions 2 3 Copyright (c) 1993-2012, Robert M. Supnik 4 5 Permission is hereby granted, free of charge, to any person obtaining a 6 copy of this software and associated documentation files (the "Software"), 7 to deal in the Software without restriction, including without limitation 8 the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 and/or sell copies of the Software, and to permit persons to whom the 10 Software is furnished to do so, subject to the following conditions: 11 12 The above copyright notice and this permission notice shall be included in 13 all copies or substantial portions of the Software. 14 15 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 ROBERT M SUPNIK BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER 19 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 20 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 21 22 Except as contained in this notice, the name of Robert M Supnik shall not 23 be used in advertising or otherwise to promote the sale, use or other dealings 24 in this Software without prior written authorization from Robert M Supnik. 25 26 10-Feb-12 JDB Added hp_setsc, hp_showsc functions to support SC modifier 27 28-Mar-11 JDB Tidied up signal handling 28 29-Oct-10 JDB DMA channels renamed from 0,1 to 1,2 to match documentation 29 27-Oct-10 JDB Revised I/O signal enum values for concurrent signals 30 Revised I/O macros for new signal handling 31 09-Oct-10 JDB Added DA and DC device select code assignments 32 07-Sep-08 JDB Added POLL_FIRST to indicate immediate connection attempt 33 15-Jul-08 JDB Rearranged declarations with hp2100_cpu.h 34 26-Jun-08 JDB Rewrote device I/O to model backplane signals 35 25-Jun-08 JDB Added PIF device 36 17-Jun-08 JDB Declared fmt_char() function 37 26-May-08 JDB Added MPX device 38 24-Apr-08 JDB Added I_MRG_I, I_JSB, I_JSB_I, and I_JMP instruction masks 39 14-Apr-08 JDB Changed TMR_MUX to TMR_POLL for idle support 40 Added POLLMODE, sync_poll() declaration 41 Added I_MRG, I_ISZ, I_IOG, I_STF, and I_SFS instruction masks 42 07-Dec-07 JDB Added BACI device 43 10-Nov-07 JDB Added 16/32-bit unsigned-to-signed conversions 44 11-Jan-07 JDB Added 12578A DMA byte packing to DMA structure 45 28-Dec-06 JDB Added CRS backplane signal as I/O pseudo-opcode 46 Added DMASK32 32-bit mask value 47 21-Dec-06 JDB Changed MEM_ADDR_OK for 21xx loader support 48 12-Sep-06 JDB Define NOTE_IOG to recalc interrupts after instr exec 49 Rename STOP_INDINT to NOTE_INDINT (not a stop condition) 50 30-Dec-04 JDB Added IBL_DS_HEAD head number mask 51 19-Nov-04 JDB Added STOP_OFFLINE, STOP_PWROFF stop codes 52 25-Apr-04 RMS Added additional IBL definitions 53 Added DMA EDT I/O pseudo-opcode 54 25-Apr-03 RMS Revised for extended file support 55 24-Oct-02 RMS Added indirect address interrupt 56 08-Feb-02 RMS Added DMS definitions 57 01-Feb-02 RMS Added terminal multiplexor support 58 16-Jan-02 RMS Added additional device support 59 30-Nov-01 RMS Added extended SET/SHOW support 60 15-Oct-00 RMS Added dynamic device numbers 61 14-Apr-99 RMS Changed t_addr to unsigned 62 63 The author gratefully acknowledges the help of Jeff Moffat in answering 64 questions about the HP2100; and of Dave Bryan in adding features and 65 correcting errors throughout the simulator. 66 */ 67 68 69 #ifndef _HP2100_DEFS_H_ 70 #define _HP2100_DEFS_H_ 0 71 72 #include "sim_defs.h" /* simulator defns */ 73 74 75 /* Simulator stop and notification codes */ 76 77 #define STOP_RSRV 1 /* must be 1 */ 78 #define STOP_IODV 2 /* must be 2 */ 79 #define STOP_HALT 3 /* HALT */ 80 #define STOP_IBKPT 4 /* breakpoint */ 81 #define STOP_IND 5 /* indirect loop */ 82 #define NOTE_INDINT 6 /* indirect intr */ 83 #define STOP_NOCONN 7 /* no connection */ 84 #define STOP_OFFLINE 8 /* device offline */ 85 #define STOP_PWROFF 9 /* device powered off */ 86 #define NOTE_IOG 10 /* I/O instr executed */ 87 88 /* Memory */ 89 90 #define MEMSIZE (cpu_unit.capac) /* actual memory size */ 91 #define VA_N_SIZE 15 /* virtual addr size */ 92 #define VASIZE (1 << VA_N_SIZE) 93 #define VAMASK 077777 /* virt addr mask */ 94 #define PA_N_SIZE 20 /* phys addr size */ 95 #define PASIZE (1 << PA_N_SIZE) 96 #define PAMASK (PASIZE - 1) /* phys addr mask */ 97 98 /* Architectural constants */ 99 100 #define SIGN32 020000000000 /* 32b sign */ 101 #define DMASK32 037777777777 /* 32b data mask/maximum value */ 102 #define DMAX32 017777777777 /* 32b maximum signed value */ 103 #define SIGN 0100000 /* 16b sign */ 104 #define DMASK 0177777 /* 16b data mask/maximum value */ 105 #define DMAX 0077777 /* 16b maximum signed value */ 106 #define DMASK8 0377 /* 8b data mask/maximum value */ 107 108 /* Portable conversions (sign-extension, unsigned-to-signed) */ 109 110 #define SEXT(x) ((int32) (((x) & SIGN)? ((x) | ~DMASK): ((x) & DMASK))) 111 112 #define INT16(u) ((u) > DMAX ? (-(int16) (DMASK - (u)) - 1) : (int16) (u)) 113 #define INT32(u) ((u) > DMAX32 ? (-(int32) (DMASK32 - (u)) - 1) : (int32) (u)) 114 115 /* Timers */ 116 117 #define TMR_CLK 0 /* clock */ 118 #define TMR_POLL 1 /* input polling */ 119 120 #define POLL_RATE 100 /* poll 100 times per second */ 121 #define POLL_FIRST 1 /* first poll is "immediate" */ 122 #define POLL_WAIT 15800 /* initial poll ~ 10 msec. */ 123 124 typedef enum { INITIAL, SERVICE } POLLMODE; /* poll synchronization modes */ 125 126 /* I/O instruction sub-opcodes */ 127 128 #define soHLT 0 /* halt */ 129 #define soFLG 1 /* set/clear flag */ 130 #define soSFC 2 /* skip on flag clear */ 131 #define soSFS 3 /* skip on flag set */ 132 #define soMIX 4 /* merge into A/B */ 133 #define soLIX 5 /* load into A/B */ 134 #define soOTX 6 /* output from A/B */ 135 #define soCTL 7 /* set/clear control */ 136 137 /* I/O devices - fixed select code assignments */ 138 139 #define CPU 000 /* interrupt control */ 140 #define OVF 001 /* overflow */ 141 #define DMALT1 002 /* DMA 1 alternate */ 142 #define DMALT2 003 /* DMA 2 alternate */ 143 #define PWR 004 /* power fail */ 144 #define PRO 005 /* parity/mem protect */ 145 #define DMA1 006 /* DMA channel 1 */ 146 #define DMA2 007 /* DMA channel 2 */ 147 148 /* I/O devices - variable select code assignment defaults */ 149 150 #define PTR 010 /* 12597A-002 paper tape reader */ 151 #define TTY 011 /* 12531C teleprinter */ 152 #define PTP 012 /* 12597A-005 paper tape punch */ 153 #define CLK 013 /* 12539C time-base generator */ 154 #define LPS 014 /* 12653A line printer */ 155 #define LPT 015 /* 12845A line printer */ 156 #define MTD 020 /* 12559A data */ 157 #define MTC 021 /* 12559A control */ 158 #define DPD 022 /* 12557A data */ 159 #define DPC 023 /* 12557A control */ 160 #define DQD 024 /* 12565A data */ 161 #define DQC 025 /* 12565A control */ 162 #define DRD 026 /* 12610A data */ 163 #define DRC 027 /* 12610A control */ 164 #define MSD 030 /* 13181A data */ 165 #define MSC 031 /* 13181A control */ 166 #define IPLI 032 /* 12566B link in */ 167 #define IPLO 033 /* 12566B link out */ 168 #define DS 034 /* 13037A control */ 169 #define BACI 035 /* 12966A Buffered Async Comm Interface */ 170 #define MPX 036 /* 12792A/B/C 8-channel multiplexer */ 171 #define PIF 037 /* 12620A/12936A Privileged Interrupt Fence */ 172 #define MUXL 040 /* 12920A lower data */ 173 #define MUXU 041 /* 12920A upper data */ 174 #define MUXC 042 /* 12920A control */ 175 #define DI_DA 043 /* 12821A Disc Interface with Amigo disc devices */ 176 #define DI_DC 044 /* 12821A Disc Interface with CS/80 disc and tape devices */ 177 178 #define OPTDEV 002 /* start of optional devices */ 179 #define CRSDEV 006 /* start of devices that receive CRS */ 180 #define VARDEV 010 /* start of variable assignments */ 181 #define MAXDEV 077 /* end of select code range */ 182 183 /* IBL assignments */ 184 185 #define IBL_V_SEL 14 /* ROM select <15:14> */ 186 #define IBL_M_SEL 03 187 #define IBL_PTR 0000000 /* ROM 0: 12992K paper tape reader (PTR) */ 188 #define IBL_DP 0040000 /* ROM 1: 12992A 7900 disc (DP) */ 189 #define IBL_DQ 0060000 /* ROM 1: 12992A 2883 disc (DQ) */ 190 #define IBL_MS 0100000 /* ROM 2: 12992D 7970 tape (MS) */ 191 #define IBL_DS 0140000 /* ROM 3: 12992B 7905/06/20/25 disc (DS) */ 192 #define IBL_MAN 0010000 /* RPL/manual boot <13:12> */ 193 #define IBL_V_DEV 6 /* select code <11:6> */ 194 #define IBL_OPT 0000070 /* options in <5:3> */ 195 #define IBL_DP_REM 0000001 /* DP removable <0:0> */ 196 #define IBL_DS_HEAD 0000003 /* DS head number <1:0> */ 197 #define IBL_LNT 64 /* boot ROM length in words */ 198 #define IBL_MASK (IBL_LNT - 1) /* boot length mask */ 199 #define IBL_DPC (IBL_LNT - 2) /* DMA ctrl word */ 200 #define IBL_END (IBL_LNT - 1) /* last location */ 201 202 typedef uint16 BOOT_ROM [IBL_LNT]; /* boot ROM data */ 203 204 205 /* I/O backplane signals. 206 207 The IOSIGNAL declarations mirror the hardware I/O backplane signals. A set 208 of one or more signals forms an IOCYCLE that is sent to a device IOHANDLER 209 for action. The CPU and DMA dispatch one signal set to the target device 210 handler per I/O cycle. A CPU cycle consists of either one or two signals; if 211 present, the second signal will be CLF. A DMA cycle consists of from two to 212 five signals. In addition, a front-panel PRESET or power-on reset dispatches 213 two or three signals, respectively. 214 215 In hardware, signals are assigned to one or more specific I/O T-periods, and 216 some signals are asserted concurrently. For example, a programmed STC sc,C 217 instruction asserts the STC and CLF signals together in period T4. Under 218 simulation, signals are ORed to form an I/O cycle; in this example, the 219 signal handler would receive an IOCYCLE value of "ioSTC | ioCLF". 220 221 Hardware allows parallel action for concurrent signals. Under simulation, a 222 "concurrent" set of signals is processed sequentially by the signal handler 223 in order of ascending numerical value. Although assigned T-periods differ 224 between programmed I/O and DMA I/O cycles, a single processing order is used. 225 The order of execution generally follows the order of T-period assertion, 226 except that ioSIR is processed after all other signals that may affect the 227 interrupt request chain. 228 229 Implementation notes: 230 231 1. The ioCLF signal must be processed after ioSFS/ioSFC to ensure that a 232 true skip test generates ioSKF before the flag is cleared, and after 233 ioIOI/ioIOO/ioSTC/ioCLC to meet the requirement that executing an 234 instruction having the H/C bit set is equivalent to executing the same 235 instruction with the H/C bit clear and then a CLF instruction. 236 237 2. The ioSKF signal is never sent to an I/O handler. Rather, it is returned 238 from the handler if the SFC or SFS condition is true. If the condition 239 is false, ioNONE is returned instead. As these two values are returned 240 in the 16-bit data portion of the returned value, their assigned values 241 must be <= 100000 octal. 242 243 3. An I/O handler will receive ioCRS as a result of a CLC 0 instruction, 244 ioPOPIO and ioCRS as a result of a RESET command, and ioPON, ioPOPIO, and 245 ioCRS as a result of a RESET -P command. 246 247 4. An I/O handler will receive ioNONE when a HLT instruction is executed 248 that has the H/C bit clear (i.e., no CLF generated). 249 250 5. In hardware, the SIR signal is generated unconditionally every T5 period 251 to time the setting of the IRQ flip-flop. Under simulation, ioSIR 252 indicates that the I/O handler must set the PRL, IRQ, and SRQ signals as 253 required by the interface logic. ioSIR must be included in the I/O cycle 254 if any of the flip-flops affecting these signals are changed and the 255 interface supports interrupts or DMA transfers. 256 257 6. In hardware, the ENF signal is unconditionally generated every T2 period 258 to time the setting of the flag flip-flop and to reset the IRQ flip-flop. 259 If the flag buffer flip-flip is set, then flag will be set by ENF. If 260 the flag buffer is clear, ENF will not affect flag. Under simulation, 261 ioENF is sent to set the flag buffer and flag flip-flops. For those 262 interfaces where this action is identical to that provided by STF, the 263 ioENF handler may simply fall into the ioSTF handler. 264 265 7. In hardware, the PON signal is asserted continuously while the CPU is 266 operating. Under simulation, ioPON is asserted only at simulator 267 initialization or when processing a RESET -P command. 268 */ 269 270 typedef enum { ioNONE = 0000000, /* -- -- -- -- -- no signal asserted */ 271 ioPON = 0000001, /* T2 T3 T4 T5 T6 power on normal */ 272 ioENF = 0000002, /* T2 -- -- -- -- enable flag */ 273 ioIOI = 0000004, /* -- -- T4 T5 -- I/O data input (CPU) 274 T2 T3 -- -- -- I/O data input (DMA) */ 275 ioIOO = 0000010, /* -- T3 T4 -- -- I/O data output */ 276 ioSKF = 0000020, /* -- T3 T4 T5 -- skip on flag */ 277 ioSFS = 0000040, /* -- T3 T4 T5 -- skip if flag is set */ 278 ioSFC = 0000100, /* -- T3 T4 T5 -- skip if flag is clear */ 279 ioSTC = 0000200, /* -- -- T4 -- -- set control flip-flop (CPU) 280 -- T3 -- -- -- set control flip-flop (DMA) */ 281 ioCLC = 0000400, /* -- -- T4 -- -- clear control flip-flop (CPU) 282 -- T3 T4 -- -- clear control flip-flop (DMA) */ 283 ioSTF = 0001000, /* -- T3 -- -- -- set flag flip-flop */ 284 ioCLF = 0002000, /* -- -- T4 -- -- clear flag flip-flop (CPU) 285 -- T3 -- -- -- clear flag flip-flop (DMA) */ 286 ioEDT = 0004000, /* -- -- T4 -- -- end data transfer */ 287 ioCRS = 0010000, /* -- -- -- T5 -- control reset */ 288 ioPOPIO = 0020000, /* -- -- -- T5 -- power-on preset to I/O */ 289 ioIAK = 0040000, /* -- -- -- -- T6 interrupt acknowledge */ 290 ioSIR = 0100000 } IOSIGNAL; /* -- -- -- T5 -- set interrupt request */ 291 292 293 typedef uint32 IOCYCLE; /* a set of signals forming one I/O cycle */ 294 295 #define IOIRQSET (ioSTC | ioCLC | ioENF | \ 296 ioSTF | ioCLF | ioIAK | \ 297 ioCRS | ioPOPIO | ioPON) /* signals that may affect interrupt state */ 298 299 300 /* I/O structures */ 301 302 typedef enum { CLEAR, SET } FLIP_FLOP; /* flip-flop type and values */ 303 304 typedef struct dib DIB; /* incomplete definition */ 305 306 typedef uint32 IOHANDLER (DIB *dibptr, /* I/O signal handler prototype */ 307 IOCYCLE signal_set, 308 uint32 stat_data); 309 310 struct dib { /* Device information block */ 311 IOHANDLER *io_handler; /* pointer to device's I/O signal handler */ 312 uint32 select_code; /* device's select code */ 313 uint32 card_index; /* device's card index for state variables */ 314 }; 315 316 317 /* I/O signal and status macros. 318 319 The following macros are useful in I/O signal handlers and unit service 320 routines. The parameter definition symbols employed are: 321 322 I = an IOCYCLE value 323 E = a t_stat error status value 324 D = a uint16 data value 325 C = a uint32 combined status and data value 326 P = a pointer to a DIB structure 327 B = a Boolean test value 328 329 Implementation notes: 330 331 1. The IONEXT macro isolates the next signal in sequence to process from the 332 I/O cycle I. 333 334 2. The IOADDSIR macro adds an ioSIR signal to the I/O cycle I if it 335 contains signals that might change the interrupt state. 336 337 3. The IORETURN macro forms the combined status and data value to be 338 returned by a handler from the t_stat error code E and the 16-bit data 339 value D. 340 341 4. The IOSTATUS macro isolates the t_stat error code from a combined status 342 and data value value C. 343 344 5. The IODATA macro isolates the 16-bit data value from a combined status 345 and data value value C. 346 347 6. The IOPOWERON macro calls signal handler P->H with DIB pointer P to 348 process a power-on reset action. 349 350 7. The IOPRESET macro calls signal handler P->H with DIB pointer P to 351 process a front-panel PRESET action. 352 353 8. The IOERROR macro returns t_stat error code E from a unit service routine 354 if the Boolean test B is true. 355 */ 356 357 #define IONEXT(I) (IOSIGNAL) ((I) & (IOCYCLE) (- (int32) (I))) /* extract next I/O signal to handle */ 358 #define IOADDSIR(I) ((I) & IOIRQSET ? (I) | ioSIR : (I)) /* add SIR if IRQ state might change */ 359 360 #define IORETURN(E,D) ((uint32) ((E) << 16 | (D) & DMASK)) /* form I/O handler return value */ 361 #define IOSTATUS(C) ((t_stat) ((C) >> 16) & DMASK) /* extract I/O status from combined value */ 362 #define IODATA(C) ((uint16) ((C) & DMASK)) /* extract data from combined value */ 363 364 #define IOPOWERON(P) (P)->io_handler ((P), ioPON | ioPOPIO | ioCRS, 0) /* send power-on signals to handler */ 365 #define IOPRESET(P) (P)->io_handler ((P), ioPOPIO | ioCRS, 0) /* send PRESET signals to handler */ 366 #define IOERROR(B,E) ((B) ? (E) : SCPE_OK) /* stop on I/O error if enabled */ 367 368 369 /* I/O signal logic macros. 370 371 The following macros implement the logic for the SKF, PRL, IRQ, and SRQ 372 signals. Both standard and general logic macros are provided. The parameter 373 definition symbols employed are: 374 375 S = a uint32 select code value 376 B = a Boolean test value 377 N = a name of a structure containing the standard flip-flops 378 379 Implementation notes: 380 381 1. The setSKF macro sets the Skip on Flag signal in the return data value if 382 the Boolean value B is true. 383 384 2. The setPRL macro sets the Priority Low signal for select code S to the 385 Boolean value B. 386 387 3. The setIRQ macro sets the Interrupt Request signal for select code S to 388 the Boolean value B. 389 390 4. The setSRQ macro sets the Service Request signal for select code S to the 391 Boolean value B. 392 393 5. The PRL macro returns the Priority Low signal for select code S as a 394 Boolean value. 395 396 6. The IRQ macro returns the Interrupt Request signal for select code S as a 397 Boolean value. 398 399 7. The SRQ macro returns the Service Request signal for select code S as a 400 Boolean value. 401 402 8. The setstdSKF macro sets Skip on Flag signal in the return data value if 403 the flag state in structure N matches the current skip test condition. 404 405 9. The setstdPRL macro sets the Priority Low signal for the select code 406 referenced by "dibptr" using the standard logic and the control and flag 407 states in structure N. 408 409 10. The setstdIRQ macro sets the Interrupt Request signal for the select code 410 referenced by "dibptr" using the standard logic and the control, flag, 411 and flag buffer states in structure N. 412 413 11. The setstdSRQ macro sets the Service Request signal for the select code 414 referenced by "dibptr" using the standard logic and the flag state in 415 structure N. 416 */ 417 418 #define BIT_V(S) ((S) & 037) /* convert select code to bit position */ 419 #define BIT_M(S) (1u << BIT_V (S)) /* convert select code to bit mask */ 420 421 #define setSKF(B) stat_data = IORETURN (SCPE_OK, (uint16) ((B) ? ioSKF : ioNONE)) 422 423 #define setPRL(S,B) dev_prl[(S)/32] = dev_prl[(S)/32] & ~BIT_M (S) | (((B) & 1) << BIT_V (S)) 424 #define setIRQ(S,B) dev_irq[(S)/32] = dev_irq[(S)/32] & ~BIT_M (S) | (((B) & 1) << BIT_V (S)) 425 #define setSRQ(S,B) dev_srq[(S)/32] = dev_srq[(S)/32] & ~BIT_M (S) | (((B) & 1) << BIT_V (S)) 426 427 #define PRL(S) ((dev_prl[(S)/32] >> BIT_V (S)) & 1) 428 #define IRQ(S) ((dev_irq[(S)/32] >> BIT_V (S)) & 1) 429 #define SRQ(S) ((dev_srq[(S)/32] >> BIT_V (S)) & 1) 430 431 #define setstdSKF(N) setSKF ((signal == ioSFC) && !N.flag || \ 432 (signal == ioSFS) && N.flag) 433 434 #define setstdPRL(N) setPRL (dibptr->select_code, !(N.control & N.flag)); 435 #define setstdIRQ(N) setIRQ (dibptr->select_code, N.control & N.flag & N.flagbuf); 436 #define setstdSRQ(N) setSRQ (dibptr->select_code, N.flag); 437 438 439 /* CPU state */ 440 441 extern uint32 SR; /* S register (for IBL) */ 442 extern uint32 dev_prl [2], dev_irq [2], dev_srq [2]; /* I/O signal vectors */ 443 444 /* Simulator state */ 445 446 extern FILE *sim_deb; 447 extern FILE *sim_log; 448 extern int32 sim_step; 449 extern int32 sim_switches; 450 451 /* CPU functions */ 452 453 extern t_stat ibl_copy (const BOOT_ROM rom, int32 dev); 454 extern void hp_enbdis_pair (DEVICE *ccp, DEVICE *dcp); 455 456 /* System functions */ 457 458 extern t_stat fprint_sym (FILE *ofile, t_addr addr, t_value *val, UNIT *uptr, int32 sw); 459 extern const char *fmt_char (uint8 ch); 460 extern t_stat hp_setsc (UNIT *uptr, int32 val, char *cptr, void *desc); 461 extern t_stat hp_showsc (FILE *st, UNIT *uptr, int32 val, void *desc); 462 extern t_stat hp_setdev (UNIT *uptr, int32 val, char *cptr, void *desc); 463 extern t_stat hp_showdev (FILE *st, UNIT *uptr, int32 val, void *desc); 464 465 /* Device-specific functions */ 466 467 extern int32 sync_poll (POLLMODE poll_mode); 468 469 #endif 470