1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2023, Intel Corporation. */
3
4 #ifndef _ICE_TYPE_H_
5 #define _ICE_TYPE_H_
6
7 #define ICE_BYTES_PER_WORD 2
8 #define ICE_BYTES_PER_DWORD 4
9 #define ICE_CHNL_MAX_TC 16
10
11 #include "ice_hw_autogen.h"
12 #include "ice_devids.h"
13 #include "ice_osdep.h"
14 #include "ice_controlq.h"
15 #include "ice_lan_tx_rx.h"
16 #include "ice_flex_type.h"
17 #include "ice_protocol_type.h"
18 #include "ice_sbq_cmd.h"
19 #include "ice_vlan_mode.h"
20 #include "ice_fwlog.h"
21
ice_is_tc_ena(unsigned long bitmap,u8 tc)22 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
23 {
24 return test_bit(tc, &bitmap);
25 }
26
round_up_64bit(u64 a,u32 b)27 static inline u64 round_up_64bit(u64 a, u32 b)
28 {
29 return div64_long(((a) + (b) / 2), (b));
30 }
31
ice_round_to_num(u32 N,u32 R)32 static inline u32 ice_round_to_num(u32 N, u32 R)
33 {
34 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
35 ((((N) + (R) - 1) / (R)) * (R)));
36 }
37
38 /* Driver always calls main vsi_handle first */
39 #define ICE_MAIN_VSI_HANDLE 0
40
41 /* debug masks - set these bits in hw->debug_mask to control output */
42 #define ICE_DBG_INIT BIT_ULL(1)
43 #define ICE_DBG_FW_LOG BIT_ULL(3)
44 #define ICE_DBG_LINK BIT_ULL(4)
45 #define ICE_DBG_PHY BIT_ULL(5)
46 #define ICE_DBG_QCTX BIT_ULL(6)
47 #define ICE_DBG_NVM BIT_ULL(7)
48 #define ICE_DBG_LAN BIT_ULL(8)
49 #define ICE_DBG_FLOW BIT_ULL(9)
50 #define ICE_DBG_SW BIT_ULL(13)
51 #define ICE_DBG_SCHED BIT_ULL(14)
52 #define ICE_DBG_RDMA BIT_ULL(15)
53 #define ICE_DBG_PKG BIT_ULL(16)
54 #define ICE_DBG_RES BIT_ULL(17)
55 #define ICE_DBG_PTP BIT_ULL(19)
56 #define ICE_DBG_AQ_MSG BIT_ULL(24)
57 #define ICE_DBG_AQ_DESC BIT_ULL(25)
58 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
59 #define ICE_DBG_AQ_CMD BIT_ULL(27)
60 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
61 ICE_DBG_AQ_DESC | \
62 ICE_DBG_AQ_DESC_BUF | \
63 ICE_DBG_AQ_CMD)
64
65 #define ICE_DBG_USER BIT_ULL(31)
66
67 enum ice_aq_res_ids {
68 ICE_NVM_RES_ID = 1,
69 ICE_SPD_RES_ID,
70 ICE_CHANGE_LOCK_RES_ID,
71 ICE_GLOBAL_CFG_LOCK_RES_ID
72 };
73
74 enum ice_fec_stats_types {
75 ICE_FEC_CORR_LOW,
76 ICE_FEC_CORR_HIGH,
77 ICE_FEC_UNCORR_LOW,
78 ICE_FEC_UNCORR_HIGH,
79 ICE_FEC_MAX
80 };
81
82 /* FW update timeout definitions are in milliseconds */
83 #define ICE_NVM_TIMEOUT 180000
84 #define ICE_CHANGE_LOCK_TIMEOUT 1000
85 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000
86
87 enum ice_aq_res_access_type {
88 ICE_RES_READ = 1,
89 ICE_RES_WRITE
90 };
91
92 struct ice_driver_ver {
93 u8 major_ver;
94 u8 minor_ver;
95 u8 build_ver;
96 u8 subbuild_ver;
97 u8 driver_string[32];
98 };
99
100 enum ice_fc_mode {
101 ICE_FC_NONE = 0,
102 ICE_FC_RX_PAUSE,
103 ICE_FC_TX_PAUSE,
104 ICE_FC_FULL,
105 ICE_FC_PFC,
106 ICE_FC_DFLT
107 };
108
109 enum ice_phy_cache_mode {
110 ICE_FC_MODE = 0,
111 ICE_SPEED_MODE,
112 ICE_FEC_MODE
113 };
114
115 enum ice_fec_mode {
116 ICE_FEC_NONE = 0,
117 ICE_FEC_RS,
118 ICE_FEC_BASER,
119 ICE_FEC_AUTO
120 };
121
122 struct ice_phy_cache_mode_data {
123 union {
124 enum ice_fec_mode curr_user_fec_req;
125 enum ice_fc_mode curr_user_fc_req;
126 u16 curr_user_speed_req;
127 } data;
128 };
129
130 enum ice_set_fc_aq_failures {
131 ICE_SET_FC_AQ_FAIL_NONE = 0,
132 ICE_SET_FC_AQ_FAIL_GET,
133 ICE_SET_FC_AQ_FAIL_SET,
134 ICE_SET_FC_AQ_FAIL_UPDATE
135 };
136
137 /* Various MAC types */
138 enum ice_mac_type {
139 ICE_MAC_UNKNOWN = 0,
140 ICE_MAC_E810,
141 ICE_MAC_E830,
142 ICE_MAC_GENERIC,
143 ICE_MAC_GENERIC_3K_E825,
144 };
145
146 /* Media Types */
147 enum ice_media_type {
148 ICE_MEDIA_UNKNOWN = 0,
149 ICE_MEDIA_FIBER,
150 ICE_MEDIA_BASET,
151 ICE_MEDIA_BACKPLANE,
152 ICE_MEDIA_DA,
153 };
154
155 enum ice_vsi_type {
156 ICE_VSI_PF = 0,
157 ICE_VSI_VF = 1,
158 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
159 ICE_VSI_CHNL = 4,
160 ICE_VSI_LB = 6,
161 };
162
163 struct ice_link_status {
164 /* Refer to ice_aq_phy_type for bits definition */
165 u64 phy_type_low;
166 u64 phy_type_high;
167 u8 topo_media_conflict;
168 u16 max_frame_size;
169 u16 link_speed;
170 u16 req_speeds;
171 u8 link_cfg_err;
172 u8 lse_ena; /* Link Status Event notification */
173 u8 link_info;
174 u8 an_info;
175 u8 ext_info;
176 u8 fec_info;
177 u8 pacing;
178 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
179 * ice_aqc_get_phy_caps structure
180 */
181 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
182 };
183
184 /* Different reset sources for which a disable queue AQ call has to be made in
185 * order to clean the Tx scheduler as a part of the reset
186 */
187 enum ice_disq_rst_src {
188 ICE_NO_RESET = 0,
189 ICE_VM_RESET,
190 ICE_VF_RESET,
191 };
192
193 /* PHY info such as phy_type, etc... */
194 struct ice_phy_info {
195 struct ice_link_status link_info;
196 struct ice_link_status link_info_old;
197 u64 phy_type_low;
198 u64 phy_type_high;
199 enum ice_media_type media_type;
200 u8 get_link_info;
201 /* Please refer to struct ice_aqc_get_link_status_data to get
202 * detail of enable bit in curr_user_speed_req
203 */
204 u16 curr_user_speed_req;
205 enum ice_fec_mode curr_user_fec_req;
206 enum ice_fc_mode curr_user_fc_req;
207 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
208 };
209
210 /* protocol enumeration for filters */
211 enum ice_fltr_ptype {
212 /* NONE - used for undef/error */
213 ICE_FLTR_PTYPE_NONF_NONE = 0,
214 ICE_FLTR_PTYPE_NONF_ETH,
215 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
216 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
217 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
218 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
219 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
220 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
221 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
222 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
223 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
224 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
225 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
226 ICE_FLTR_PTYPE_NONF_IPV4_ESP,
227 ICE_FLTR_PTYPE_NONF_IPV6_ESP,
228 ICE_FLTR_PTYPE_NONF_IPV4_AH,
229 ICE_FLTR_PTYPE_NONF_IPV6_AH,
230 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
231 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
232 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
233 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
234 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
235 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
236 ICE_FLTR_PTYPE_NON_IP_L2,
237 ICE_FLTR_PTYPE_FRAG_IPV4,
238 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
239 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
240 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
241 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
242 ICE_FLTR_PTYPE_MAX,
243 };
244
245 enum ice_fd_hw_seg {
246 ICE_FD_HW_SEG_NON_TUN = 0,
247 ICE_FD_HW_SEG_TUN,
248 ICE_FD_HW_SEG_MAX,
249 };
250
251 /* 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + ICE_CHNL_MAX_TC */
252 #define ICE_MAX_FDIR_VSI_PER_FILTER (2 + ICE_CHNL_MAX_TC)
253
254 struct ice_fd_hw_prof {
255 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
256 int cnt;
257 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
258 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
259 u64 prof_id[ICE_FD_HW_SEG_MAX];
260 };
261
262 /* Common HW capabilities for SW use */
263 struct ice_hw_common_caps {
264 u32 valid_functions;
265 /* DCB capabilities */
266 u32 active_tc_bitmap;
267 u32 maxtc;
268
269 /* Tx/Rx queues */
270 u16 num_rxq; /* Number/Total Rx queues */
271 u16 rxq_first_id; /* First queue ID for Rx queues */
272 u16 num_txq; /* Number/Total Tx queues */
273 u16 txq_first_id; /* First queue ID for Tx queues */
274
275 /* MSI-X vectors */
276 u16 num_msix_vectors;
277 u16 msix_vector_first_id;
278
279 /* Max MTU for function or device */
280 u16 max_mtu;
281
282 /* Virtualization support */
283 u8 sr_iov_1_1; /* SR-IOV enabled */
284
285 /* RSS related capabilities */
286 u16 rss_table_size; /* 512 for PFs and 64 for VFs */
287 u8 rss_table_entry_width; /* RSS Entry width in bits */
288
289 u8 dcb;
290 u8 ieee_1588;
291 u8 rdma;
292 u8 roce_lag;
293 u8 sriov_lag;
294
295 bool nvm_update_pending_nvm;
296 bool nvm_update_pending_orom;
297 bool nvm_update_pending_netlist;
298 #define ICE_NVM_PENDING_NVM_IMAGE BIT(0)
299 #define ICE_NVM_PENDING_OROM BIT(1)
300 #define ICE_NVM_PENDING_NETLIST BIT(2)
301 bool nvm_unified_update;
302 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
303 /* PCIe reset avoidance */
304 bool pcie_reset_avoidance;
305 /* Post update reset restriction */
306 bool reset_restrict_support;
307 bool tx_sched_topo_comp_mode_en;
308 };
309
310 /* IEEE 1588 TIME_SYNC specific info */
311 /* Function specific definitions */
312 #define ICE_TS_FUNC_ENA_M BIT(0)
313 #define ICE_TS_SRC_TMR_OWND_M BIT(1)
314 #define ICE_TS_TMR_ENA_M BIT(2)
315 #define ICE_TS_TMR_IDX_OWND_S 4
316 #define ICE_TS_TMR_IDX_OWND_M BIT(4)
317 #define ICE_TS_CLK_FREQ_S 16
318 #define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S)
319 #define ICE_TS_CLK_SRC_S 20
320 #define ICE_TS_CLK_SRC_M BIT(20)
321 #define ICE_TS_TMR_IDX_ASSOC_S 24
322 #define ICE_TS_TMR_IDX_ASSOC_M BIT(24)
323
324 /* TIME_REF clock rate specification */
325 enum ice_time_ref_freq {
326 ICE_TIME_REF_FREQ_25_000 = 0,
327 ICE_TIME_REF_FREQ_122_880 = 1,
328 ICE_TIME_REF_FREQ_125_000 = 2,
329 ICE_TIME_REF_FREQ_153_600 = 3,
330 ICE_TIME_REF_FREQ_156_250 = 4,
331 ICE_TIME_REF_FREQ_245_760 = 5,
332
333 NUM_ICE_TIME_REF_FREQ,
334
335 ICE_TIME_REF_FREQ_INVALID = -1,
336 };
337
338 /* Clock source specification */
339 enum ice_clk_src {
340 ICE_CLK_SRC_TCXO = 0, /* Temperature compensated oscillator */
341 ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */
342
343 NUM_ICE_CLK_SRC
344 };
345
346 struct ice_ts_func_info {
347 /* Function specific info */
348 enum ice_time_ref_freq time_ref;
349 u8 clk_freq;
350 u8 clk_src;
351 u8 tmr_index_assoc;
352 u8 ena;
353 u8 tmr_index_owned;
354 u8 src_tmr_owned;
355 u8 tmr_ena;
356 };
357
358 /* Device specific definitions */
359 #define ICE_TS_TMR0_OWNR_M 0x7
360 #define ICE_TS_TMR0_OWND_M BIT(3)
361 #define ICE_TS_TMR1_OWNR_S 4
362 #define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S)
363 #define ICE_TS_TMR1_OWND_M BIT(7)
364 #define ICE_TS_DEV_ENA_M BIT(24)
365 #define ICE_TS_TMR0_ENA_M BIT(25)
366 #define ICE_TS_TMR1_ENA_M BIT(26)
367 #define ICE_TS_LL_TX_TS_READ_M BIT(28)
368 #define ICE_TS_LL_TX_TS_INT_READ_M BIT(29)
369
370 struct ice_ts_dev_info {
371 /* Device specific info */
372 u32 ena_ports;
373 u32 tmr_own_map;
374 u32 tmr0_owner;
375 u32 tmr1_owner;
376 u8 tmr0_owned;
377 u8 tmr1_owned;
378 u8 ena;
379 u8 tmr0_ena;
380 u8 tmr1_ena;
381 u8 ts_ll_read;
382 u8 ts_ll_int_read;
383 };
384
385 #define ICE_NAC_TOPO_PRIMARY_M BIT(0)
386 #define ICE_NAC_TOPO_DUAL_M BIT(1)
387 #define ICE_NAC_TOPO_ID_M GENMASK(0xF, 0)
388
389 struct ice_nac_topology {
390 u32 mode;
391 u8 id;
392 };
393
394 /* Function specific capabilities */
395 struct ice_hw_func_caps {
396 struct ice_hw_common_caps common_cap;
397 u32 num_allocd_vfs; /* Number of allocated VFs */
398 u32 vf_base_id; /* Logical ID of the first VF */
399 u32 guar_num_vsi;
400 u32 fd_fltr_guar; /* Number of filters guaranteed */
401 u32 fd_fltr_best_effort; /* Number of best effort filters */
402 struct ice_ts_func_info ts_func_info;
403 };
404
405 #define ICE_SENSOR_SUPPORT_E810_INT_TEMP_BIT 0
406
407 /* Device wide capabilities */
408 struct ice_hw_dev_caps {
409 struct ice_hw_common_caps common_cap;
410 u32 num_vfs_exposed; /* Total number of VFs exposed */
411 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
412 u32 num_flow_director_fltr; /* Number of FD filters available */
413 struct ice_ts_dev_info ts_dev_info;
414 u32 num_funcs;
415 struct ice_nac_topology nac_topo;
416 /* bitmap of supported sensors
417 * bit 0 - internal temperature sensor
418 * bit 31:1 - Reserved
419 */
420 u32 supported_sensors;
421 };
422
423 /* MAC info */
424 struct ice_mac_info {
425 u8 lan_addr[ETH_ALEN];
426 u8 perm_addr[ETH_ALEN];
427 };
428
429 /* Reset types used to determine which kind of reset was requested. These
430 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
431 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
432 * because its reset source is different than the other types listed.
433 */
434 enum ice_reset_req {
435 ICE_RESET_POR = 0,
436 ICE_RESET_INVAL = 0,
437 ICE_RESET_CORER = 1,
438 ICE_RESET_GLOBR = 2,
439 ICE_RESET_EMPR = 3,
440 ICE_RESET_PFR = 4,
441 };
442
443 /* Bus parameters */
444 struct ice_bus_info {
445 u16 device;
446 u8 func;
447 };
448
449 /* Flow control (FC) parameters */
450 struct ice_fc_info {
451 enum ice_fc_mode current_mode; /* FC mode in effect */
452 enum ice_fc_mode req_mode; /* FC mode requested by caller */
453 };
454
455 /* Option ROM version information */
456 struct ice_orom_info {
457 u8 major; /* Major version of OROM */
458 u8 patch; /* Patch version of OROM */
459 u16 build; /* Build version of OROM */
460 };
461
462 /* NVM version information */
463 struct ice_nvm_info {
464 u32 eetrack;
465 u8 major;
466 u8 minor;
467 };
468
469 /* netlist version information */
470 struct ice_netlist_info {
471 u32 major; /* major high/low */
472 u32 minor; /* minor high/low */
473 u32 type; /* type high/low */
474 u32 rev; /* revision high/low */
475 u32 hash; /* SHA-1 hash word */
476 u16 cust_ver; /* customer version */
477 };
478
479 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
480 * of the flash image.
481 */
482 enum ice_flash_bank {
483 ICE_INVALID_FLASH_BANK,
484 ICE_1ST_FLASH_BANK,
485 ICE_2ND_FLASH_BANK,
486 };
487
488 /* Enumeration of which flash bank is desired to read from, either the active
489 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
490 * code which just wants to read the active or inactive flash bank.
491 */
492 enum ice_bank_select {
493 ICE_ACTIVE_FLASH_BANK,
494 ICE_INACTIVE_FLASH_BANK,
495 };
496
497 /* information for accessing NVM, OROM, and Netlist flash banks */
498 struct ice_bank_info {
499 u32 nvm_ptr; /* Pointer to 1st NVM bank */
500 u32 nvm_size; /* Size of NVM bank */
501 u32 orom_ptr; /* Pointer to 1st OROM bank */
502 u32 orom_size; /* Size of OROM bank */
503 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
504 u32 netlist_size; /* Size of Netlist bank */
505 u32 active_css_hdr_len; /* Active CSS header length */
506 u32 inactive_css_hdr_len; /* Inactive CSS header length */
507 enum ice_flash_bank nvm_bank; /* Active NVM bank */
508 enum ice_flash_bank orom_bank; /* Active OROM bank */
509 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
510 };
511
512 /* Flash Chip Information */
513 struct ice_flash_info {
514 struct ice_orom_info orom; /* Option ROM version info */
515 struct ice_nvm_info nvm; /* NVM version information */
516 struct ice_netlist_info netlist;/* Netlist version info */
517 struct ice_bank_info banks; /* Flash Bank information */
518 u16 sr_words; /* Shadow RAM size in words */
519 u32 flash_size; /* Size of available flash in bytes */
520 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
521 };
522
523 struct ice_link_default_override_tlv {
524 u8 options;
525 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
526 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
527 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
528 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
529 #define ICE_LINK_OVERRIDE_EN BIT(3)
530 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
531 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
532 u8 phy_config;
533 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
534 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
535 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
536 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
537 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
538 u8 fec_options;
539 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
540 u8 rsvd1;
541 u64 phy_type_low;
542 u64 phy_type_high;
543 };
544
545 #define ICE_NVM_VER_LEN 32
546
547 /* Max number of port to queue branches w.r.t topology */
548 #define ICE_MAX_TRAFFIC_CLASS 8
549 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
550
551 #define ice_for_each_traffic_class(_i) \
552 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
553
554 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
555 * to driver defined policy for default aggregator
556 */
557 #define ICE_INVAL_TEID 0xFFFFFFFF
558 #define ICE_DFLT_AGG_ID 0
559
560 struct ice_sched_node {
561 struct ice_sched_node *parent;
562 struct ice_sched_node *sibling; /* next sibling in the same layer */
563 struct ice_sched_node **children;
564 struct ice_aqc_txsched_elem_data info;
565 char *name;
566 struct devlink_rate *rate_node;
567 u64 tx_max;
568 u64 tx_share;
569 u32 agg_id; /* aggregator group ID */
570 u32 id;
571 u32 tx_priority;
572 u32 tx_weight;
573 u16 vsi_handle;
574 u8 in_use; /* suspended or in use */
575 u8 tx_sched_layer; /* Logical Layer (1-9) */
576 u8 num_children;
577 u8 tc_num;
578 u8 owner;
579 #define ICE_SCHED_NODE_OWNER_LAN 0
580 #define ICE_SCHED_NODE_OWNER_RDMA 2
581 };
582
583 /* Access Macros for Tx Sched Elements data */
584 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
585
586 /* The aggregator type determines if identifier is for a VSI group,
587 * aggregator group, aggregator of queues, or queue group.
588 */
589 enum ice_agg_type {
590 ICE_AGG_TYPE_UNKNOWN = 0,
591 ICE_AGG_TYPE_VSI,
592 ICE_AGG_TYPE_AGG, /* aggregator */
593 ICE_AGG_TYPE_Q,
594 ICE_AGG_TYPE_QG
595 };
596
597 /* Rate limit types */
598 enum ice_rl_type {
599 ICE_UNKNOWN_BW = 0,
600 ICE_MIN_BW, /* for CIR profile */
601 ICE_MAX_BW, /* for EIR profile */
602 ICE_SHARED_BW /* for shared profile */
603 };
604
605 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
606 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
607 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
608 #define ICE_SCHED_DFLT_RL_PROF_ID 0
609 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
610 #define ICE_SCHED_DFLT_BW_WT 4
611 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
612 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
613
614 #define ICE_MAX_PORT_PER_PCI_DEV 8
615
616 /* Data structure for saving BW information */
617 enum ice_bw_type {
618 ICE_BW_TYPE_PRIO,
619 ICE_BW_TYPE_CIR,
620 ICE_BW_TYPE_CIR_WT,
621 ICE_BW_TYPE_EIR,
622 ICE_BW_TYPE_EIR_WT,
623 ICE_BW_TYPE_SHARED,
624 ICE_BW_TYPE_CNT /* This must be last */
625 };
626
627 struct ice_bw {
628 u32 bw;
629 u16 bw_alloc;
630 };
631
632 struct ice_bw_type_info {
633 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT);
634 u8 generic;
635 struct ice_bw cir_bw;
636 struct ice_bw eir_bw;
637 u32 shared_bw;
638 };
639
640 /* VSI queue context structure for given TC */
641 struct ice_q_ctx {
642 u16 q_handle;
643 u32 q_teid;
644 /* bw_t_info saves queue BW information */
645 struct ice_bw_type_info bw_t_info;
646 };
647
648 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
649 struct ice_sched_vsi_info {
650 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
651 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
652 struct list_head list_entry;
653 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
654 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS];
655 /* bw_t_info saves VSI BW information */
656 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
657 };
658
659 /* driver defines the policy */
660 struct ice_sched_tx_policy {
661 u16 max_num_vsis;
662 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
663 u8 rdma_ena;
664 };
665
666 /* CEE or IEEE 802.1Qaz ETS Configuration data */
667 struct ice_dcb_ets_cfg {
668 u8 willing;
669 u8 cbs;
670 u8 maxtcs;
671 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
672 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
673 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
674 };
675
676 /* CEE or IEEE 802.1Qaz PFC Configuration data */
677 struct ice_dcb_pfc_cfg {
678 u8 willing;
679 u8 mbc;
680 u8 pfccap;
681 u8 pfcena;
682 };
683
684 /* CEE or IEEE 802.1Qaz Application Priority data */
685 struct ice_dcb_app_priority_table {
686 u16 prot_id;
687 u8 priority;
688 u8 selector;
689 };
690
691 #define ICE_MAX_USER_PRIORITY 8
692 #define ICE_DCBX_MAX_APPS 64
693 #define ICE_DSCP_NUM_VAL 64
694 #define ICE_LLDPDU_SIZE 1500
695 #define ICE_TLV_STATUS_OPER 0x1
696 #define ICE_TLV_STATUS_SYNC 0x2
697 #define ICE_TLV_STATUS_ERR 0x4
698 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
699 #define ICE_APP_SEL_ETHTYPE 0x1
700 #define ICE_APP_SEL_TCPIP 0x2
701 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
702 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
703 #define ICE_CEE_APP_SEL_TCPIP 0x1
704
705 struct ice_dcbx_cfg {
706 u32 numapps;
707 u32 tlv_status; /* CEE mode TLV status */
708 struct ice_dcb_ets_cfg etscfg;
709 struct ice_dcb_ets_cfg etsrec;
710 struct ice_dcb_pfc_cfg pfc;
711 #define ICE_QOS_MODE_VLAN 0x0
712 #define ICE_QOS_MODE_DSCP 0x1
713 u8 pfc_mode;
714 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
715 /* when DSCP mapping defined by user set its bit to 1 */
716 DECLARE_BITMAP(dscp_mapped, ICE_DSCP_NUM_VAL);
717 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
718 u8 dscp_map[ICE_DSCP_NUM_VAL];
719 u8 dcbx_mode;
720 #define ICE_DCBX_MODE_CEE 0x1
721 #define ICE_DCBX_MODE_IEEE 0x2
722 u8 app_mode;
723 #define ICE_DCBX_APPS_NON_WILLING 0x1
724 };
725
726 struct ice_qos_cfg {
727 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
728 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
729 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
730 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
731 u8 is_sw_lldp : 1;
732 };
733
734 struct ice_port_info {
735 struct ice_sched_node *root; /* Root Node per Port */
736 struct ice_hw *hw; /* back pointer to HW instance */
737 u32 last_node_teid; /* scheduler last node info */
738 u16 sw_id; /* Initial switch ID belongs to port */
739 u16 pf_vf_num;
740 u8 port_state;
741 u8 local_fwd_mode;
742 #define ICE_SCHED_PORT_STATE_INIT 0x0
743 #define ICE_SCHED_PORT_STATE_READY 0x1
744 u8 lport;
745 #define ICE_LPORT_MASK 0xff
746 struct ice_fc_info fc;
747 struct ice_mac_info mac;
748 struct ice_phy_info phy;
749 struct mutex sched_lock; /* protect access to TXSched tree */
750 struct ice_sched_node *
751 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
752 /* List contain profile ID(s) and other params per layer */
753 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
754 struct ice_qos_cfg qos_cfg;
755 struct xarray sched_node_ids;
756 u8 is_vf:1;
757 u8 is_custom_tx_enabled:1;
758 };
759
760 struct ice_switch_info {
761 struct list_head vsi_list_map_head;
762 struct ice_sw_recipe *recp_list;
763 u16 prof_res_bm_init;
764 u16 max_used_prof_index;
765 u16 rule_cnt;
766 u8 recp_cnt;
767
768 DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
769 };
770
771 /* Enum defining the different states of the mailbox snapshot in the
772 * PF-VF mailbox overflow detection algorithm. The snapshot can be in
773 * states:
774 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot
775 * within the mailbox buffer.
776 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot
777 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the
778 * mailbox and mark any VFs sending more messages than the threshold limit set.
779 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF.
780 */
781 enum ice_mbx_snapshot_state {
782 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0,
783 ICE_MAL_VF_DETECT_STATE_TRAVERSE,
784 ICE_MAL_VF_DETECT_STATE_DETECT,
785 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF,
786 };
787
788 /* Structure to hold information of the static snapshot and the mailbox
789 * buffer data used to generate and track the snapshot.
790 * 1. state: the state of the mailbox snapshot in the malicious VF
791 * detection state handler ice_mbx_vf_state_handler()
792 * 2. head: head of the mailbox snapshot in a circular mailbox buffer
793 * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer
794 * 4. num_iterations: number of messages traversed in circular mailbox buffer
795 * 5. num_msg_proc: number of messages processed in mailbox
796 * 6. num_pending_arq: number of pending asynchronous messages
797 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently
798 * serviced work item or interrupt.
799 */
800 struct ice_mbx_snap_buffer_data {
801 enum ice_mbx_snapshot_state state;
802 u32 head;
803 u32 tail;
804 u32 num_iterations;
805 u16 num_msg_proc;
806 u16 num_pending_arq;
807 u16 max_num_msgs_mbx;
808 };
809
810 /* Structure used to track a single VF's messages on the mailbox:
811 * 1. list_entry: linked list entry node
812 * 2. msg_count: the number of asynchronous messages sent by this VF
813 * 3. malicious: whether this VF has been detected as malicious before
814 */
815 struct ice_mbx_vf_info {
816 struct list_head list_entry;
817 u32 msg_count;
818 u8 malicious : 1;
819 };
820
821 /* Structure to hold data relevant to the captured static snapshot
822 * of the PF-VF mailbox.
823 */
824 struct ice_mbx_snapshot {
825 struct ice_mbx_snap_buffer_data mbx_buf;
826 struct list_head mbx_vf;
827 };
828
829 /* Structure to hold data to be used for capturing or updating a
830 * static snapshot.
831 * 1. num_msg_proc: number of messages processed in mailbox
832 * 2. num_pending_arq: number of pending asynchronous messages
833 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently
834 * serviced work item or interrupt.
835 * 4. async_watermark_val: An upper threshold set by caller to determine
836 * if the pending arq count is large enough to assume that there is
837 * the possibility of a mailicious VF.
838 */
839 struct ice_mbx_data {
840 u16 num_msg_proc;
841 u16 num_pending_arq;
842 u16 max_num_msgs_mbx;
843 u16 async_watermark_val;
844 };
845
846 #define ICE_PORTS_PER_QUAD 4
847 #define ICE_GET_QUAD_NUM(port) ((port) / ICE_PORTS_PER_QUAD)
848
849 struct ice_eth56g_params {
850 u8 num_phys;
851 u8 phy_addr[2];
852 bool onestep_ena;
853 bool sfd_ena;
854 u32 peer_delay;
855 };
856
857 union ice_phy_params {
858 struct ice_eth56g_params eth56g;
859 };
860
861 /* PHY model */
862 enum ice_phy_model {
863 ICE_PHY_UNSUP = -1,
864 ICE_PHY_E810 = 1,
865 ICE_PHY_E82X,
866 ICE_PHY_ETH56G,
867 };
868
869 /* Global Link Topology */
870 enum ice_global_link_topo {
871 ICE_LINK_TOPO_UP_TO_2_LINKS,
872 ICE_LINK_TOPO_UP_TO_4_LINKS,
873 ICE_LINK_TOPO_UP_TO_8_LINKS,
874 ICE_LINK_TOPO_RESERVED,
875 };
876
877 struct ice_ptp_hw {
878 enum ice_phy_model phy_model;
879 union ice_phy_params phy;
880 u8 num_lports;
881 u8 ports_per_phy;
882 bool is_2x50g_muxed_topo;
883 };
884
885 /* Port hardware description */
886 struct ice_hw {
887 u8 __iomem *hw_addr;
888 void *back;
889 struct ice_aqc_layer_props *layer_info;
890 struct ice_port_info *port_info;
891 /* PSM clock frequency for calculating RL profile params */
892 u32 psm_clk_freq;
893 u64 debug_mask; /* bitmap for debug mask */
894 enum ice_mac_type mac_type;
895
896 u16 fd_ctr_base; /* FD counter base index */
897
898 /* pci info */
899 u16 device_id;
900 u16 vendor_id;
901 u16 subsystem_device_id;
902 u16 subsystem_vendor_id;
903 u8 revision_id;
904
905 u8 pf_id; /* device profile info */
906
907 u16 max_burst_size; /* driver sets this value */
908
909 u8 recp_reuse:1; /* indicates whether FW supports recipe reuse */
910
911 /* Tx Scheduler values */
912 u8 num_tx_sched_layers;
913 u8 num_tx_sched_phys_layers;
914 u8 flattened_layers;
915 u8 max_cgds;
916 u8 sw_entry_point_layer;
917 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
918 struct list_head agg_list; /* lists all aggregator */
919
920 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
921 u8 evb_veb; /* true for VEB, false for VEPA */
922 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
923 struct ice_bus_info bus;
924 struct ice_flash_info flash;
925 struct ice_hw_dev_caps dev_caps; /* device capabilities */
926 struct ice_hw_func_caps func_caps; /* function capabilities */
927
928 struct ice_switch_info *switch_info; /* switch filter lists */
929
930 /* Control Queue info */
931 struct ice_ctl_q_info adminq;
932 struct ice_ctl_q_info sbq;
933 struct ice_ctl_q_info mailboxq;
934
935 u8 api_branch; /* API branch version */
936 u8 api_maj_ver; /* API major version */
937 u8 api_min_ver; /* API minor version */
938 u8 api_patch; /* API patch version */
939 u8 fw_branch; /* firmware branch version */
940 u8 fw_maj_ver; /* firmware major version */
941 u8 fw_min_ver; /* firmware minor version */
942 u8 fw_patch; /* firmware patch version */
943 u32 fw_build; /* firmware build number */
944
945 struct ice_fwlog_cfg fwlog_cfg;
946 bool fwlog_supported; /* does hardware support FW logging? */
947 struct ice_fwlog_ring fwlog_ring;
948
949 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
950 * register. Used for determining the ITR/INTRL granularity during
951 * initialization.
952 */
953 #define ICE_MAX_AGG_BW_200G 0x0
954 #define ICE_MAX_AGG_BW_100G 0X1
955 #define ICE_MAX_AGG_BW_50G 0x2
956 #define ICE_MAX_AGG_BW_25G 0x3
957 /* ITR granularity for different speeds */
958 #define ICE_ITR_GRAN_ABOVE_25 2
959 #define ICE_ITR_GRAN_MAX_25 4
960 /* ITR granularity in 1 us */
961 u8 itr_gran;
962 /* INTRL granularity for different speeds */
963 #define ICE_INTRL_GRAN_ABOVE_25 4
964 #define ICE_INTRL_GRAN_MAX_25 8
965 /* INTRL granularity in 1 us */
966 u8 intrl_gran;
967
968 struct ice_ptp_hw ptp;
969
970 /* Active package version (currently active) */
971 struct ice_pkg_ver active_pkg_ver;
972 u32 pkg_seg_id;
973 u32 pkg_sign_type;
974 u32 active_track_id;
975 u8 pkg_has_signing_seg:1;
976 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
977 u8 active_pkg_in_nvm;
978
979 /* Driver's package ver - (from the Ice Metadata section) */
980 struct ice_pkg_ver pkg_ver;
981 u8 pkg_name[ICE_PKG_NAME_SIZE];
982
983 /* Driver's Ice segment format version and ID (from the Ice seg) */
984 struct ice_pkg_ver ice_seg_fmt_ver;
985 u8 ice_seg_id[ICE_SEG_ID_SIZE];
986
987 /* Pointer to the ice segment */
988 struct ice_seg *seg;
989
990 /* Pointer to allocated copy of pkg memory */
991 u8 *pkg_copy;
992 u32 pkg_size;
993
994 /* tunneling info */
995 struct mutex tnl_lock;
996 struct ice_tunnel_table tnl;
997
998 struct udp_tunnel_nic_shared udp_tunnel_shared;
999 struct udp_tunnel_nic_info udp_tunnel_nic;
1000
1001 /* dvm boost update information */
1002 struct ice_dvm_table dvm_upd;
1003
1004 /* HW block tables */
1005 struct ice_blk_info blk[ICE_BLK_COUNT];
1006 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
1007 struct list_head fl_profs[ICE_BLK_COUNT];
1008
1009 /* Flow Director filter info */
1010 int fdir_active_fltr;
1011
1012 struct mutex fdir_fltr_lock; /* protect Flow Director */
1013 struct list_head fdir_list_head;
1014
1015 /* Book-keeping of side-band filter count per flow-type.
1016 * This is used to detect and handle input set changes for
1017 * respective flow-type.
1018 */
1019 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
1020
1021 struct ice_fd_hw_prof **fdir_prof;
1022 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
1023 struct mutex rss_locks; /* protect RSS configuration */
1024 struct list_head rss_list_head;
1025 struct ice_mbx_snapshot mbx_snapshot;
1026 DECLARE_BITMAP(hw_ptype, ICE_FLOW_PTYPE_MAX);
1027 u8 dvm_ena;
1028 u16 io_expander_handle;
1029 u8 cgu_part_number;
1030 };
1031
1032 /* Statistics collected by each port, VSI, VEB, and S-channel */
1033 struct ice_eth_stats {
1034 u64 rx_bytes; /* gorc */
1035 u64 rx_unicast; /* uprc */
1036 u64 rx_multicast; /* mprc */
1037 u64 rx_broadcast; /* bprc */
1038 u64 rx_discards; /* rdpc */
1039 u64 rx_unknown_protocol; /* rupp */
1040 u64 tx_bytes; /* gotc */
1041 u64 tx_unicast; /* uptc */
1042 u64 tx_multicast; /* mptc */
1043 u64 tx_broadcast; /* bptc */
1044 u64 tx_discards; /* tdpc */
1045 u64 tx_errors; /* tepc */
1046 };
1047
1048 #define ICE_MAX_UP 8
1049
1050 /* Statistics collected by the MAC */
1051 struct ice_hw_port_stats {
1052 /* eth stats collected by the port */
1053 struct ice_eth_stats eth;
1054 /* additional port specific stats */
1055 u64 tx_dropped_link_down; /* tdold */
1056 u64 crc_errors; /* crcerrs */
1057 u64 illegal_bytes; /* illerrc */
1058 u64 error_bytes; /* errbc */
1059 u64 mac_local_faults; /* mlfc */
1060 u64 mac_remote_faults; /* mrfc */
1061 u64 link_xon_rx; /* lxonrxc */
1062 u64 link_xoff_rx; /* lxoffrxc */
1063 u64 link_xon_tx; /* lxontxc */
1064 u64 link_xoff_tx; /* lxofftxc */
1065 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1066 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1067 u64 priority_xon_tx[8]; /* pxontxc[8] */
1068 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1069 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1070 u64 rx_size_64; /* prc64 */
1071 u64 rx_size_127; /* prc127 */
1072 u64 rx_size_255; /* prc255 */
1073 u64 rx_size_511; /* prc511 */
1074 u64 rx_size_1023; /* prc1023 */
1075 u64 rx_size_1522; /* prc1522 */
1076 u64 rx_size_big; /* prc9522 */
1077 u64 rx_undersize; /* ruc */
1078 u64 rx_fragments; /* rfc */
1079 u64 rx_oversize; /* roc */
1080 u64 rx_jabber; /* rjc */
1081 u64 tx_size_64; /* ptc64 */
1082 u64 tx_size_127; /* ptc127 */
1083 u64 tx_size_255; /* ptc255 */
1084 u64 tx_size_511; /* ptc511 */
1085 u64 tx_size_1023; /* ptc1023 */
1086 u64 tx_size_1522; /* ptc1522 */
1087 u64 tx_size_big; /* ptc9522 */
1088 /* flow director stats */
1089 u32 fd_sb_status;
1090 u64 fd_sb_match;
1091 };
1092
1093 enum ice_sw_fwd_act_type {
1094 ICE_FWD_TO_VSI = 0,
1095 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1096 ICE_FWD_TO_Q,
1097 ICE_FWD_TO_QGRP,
1098 ICE_DROP_PACKET,
1099 ICE_MIRROR_PACKET,
1100 ICE_NOP,
1101 ICE_INVAL_ACT
1102 };
1103
1104 struct ice_aq_get_set_rss_lut_params {
1105 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
1106 enum ice_lut_size lut_size; /* size of the LUT buffer */
1107 enum ice_lut_type lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1108 u16 vsi_handle; /* software VSI handle */
1109 u8 global_lut_id; /* only valid when lut_type is global */
1110 };
1111
1112 /* Checksum and Shadow RAM pointers */
1113 #define ICE_SR_NVM_CTRL_WORD 0x00
1114 #define ICE_SR_BOOT_CFG_PTR 0x132
1115 #define ICE_SR_NVM_WOL_CFG 0x19
1116 #define ICE_NVM_OROM_VER_OFF 0x02
1117 #define ICE_SR_PBA_BLOCK_PTR 0x16
1118 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1119 #define ICE_SR_NVM_EETRACK_LO 0x2D
1120 #define ICE_SR_NVM_EETRACK_HI 0x2E
1121 #define ICE_NVM_VER_LO_SHIFT 0
1122 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1123 #define ICE_NVM_VER_HI_SHIFT 12
1124 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1125 #define ICE_OROM_VER_PATCH_SHIFT 0
1126 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1127 #define ICE_OROM_VER_BUILD_SHIFT 8
1128 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1129 #define ICE_OROM_VER_SHIFT 24
1130 #define ICE_OROM_VER_MASK (0xffU << ICE_OROM_VER_SHIFT)
1131 #define ICE_SR_PFA_PTR 0x40
1132 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1133 #define ICE_SR_NVM_BANK_SIZE 0x43
1134 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1135 #define ICE_SR_OROM_BANK_SIZE 0x45
1136 #define ICE_SR_NETLIST_BANK_PTR 0x46
1137 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1138 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1139
1140 /* CSS Header words */
1141 #define ICE_NVM_CSS_HDR_LEN_L 0x02
1142 #define ICE_NVM_CSS_HDR_LEN_H 0x03
1143 #define ICE_NVM_CSS_SREV_L 0x14
1144 #define ICE_NVM_CSS_SREV_H 0x15
1145
1146 /* Length of Authentication header section in words */
1147 #define ICE_NVM_AUTH_HEADER_LEN 0x08
1148
1149 /* The Link Topology Netlist section is stored as a series of words. It is
1150 * stored in the NVM as a TLV, with the first two words containing the type
1151 * and length.
1152 */
1153 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B
1154 #define ICE_NETLIST_TYPE_OFFSET 0x0000
1155 #define ICE_NETLIST_LEN_OFFSET 0x0001
1156
1157 /* The Link Topology section follows the TLV header. When reading the netlist
1158 * using ice_read_netlist_module, we need to account for the 2-word TLV
1159 * header.
1160 */
1161 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2)
1162
1163 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1164 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1165
1166 #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0)
1167
1168 /* The Netlist ID Block is located after all of the Link Topology nodes. */
1169 #define ICE_NETLIST_ID_BLK_SIZE 0x30
1170 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1171
1172 /* netlist ID block field offsets (word offsets) */
1173 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02
1174 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03
1175 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04
1176 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05
1177 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06
1178 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07
1179 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08
1180 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09
1181 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n))
1182 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F
1183
1184 /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */
1185 #define ICE_SR_CTRL_WORD_1_S 0x06
1186 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1187 #define ICE_SR_CTRL_WORD_VALID 0x1
1188 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
1189 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
1190 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
1191
1192 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
1193
1194 /* Link override related */
1195 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1196 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1197 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1198 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1199 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1200 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1201 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1202 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1203
1204 #define ICE_SR_WORDS_IN_1KB 512
1205
1206 /* AQ API version for LLDP_FILTER_CONTROL */
1207 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1208 #define ICE_FW_API_LLDP_FLTR_MIN 7
1209 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1210
1211 /* AQ API version for report default configuration */
1212 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
1213 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
1214 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
1215
1216 #endif /* _ICE_TYPE_H_ */
1217