1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2023, Intel Corporation. */
3
4 #ifndef _ICE_TYPE_H_
5 #define _ICE_TYPE_H_
6
7 #define ICE_BYTES_PER_WORD 2
8 #define ICE_BYTES_PER_DWORD 4
9 #define ICE_CHNL_MAX_TC 16
10
11 #include "ice_hw_autogen.h"
12 #include "ice_devids.h"
13 #include "ice_osdep.h"
14 #include "ice_controlq.h"
15 #include "ice_lan_tx_rx.h"
16 #include "ice_flex_type.h"
17 #include "ice_protocol_type.h"
18 #include "ice_sbq_cmd.h"
19 #include "ice_vlan_mode.h"
20 #include "ice_fwlog.h"
21
ice_is_tc_ena(unsigned long bitmap,u8 tc)22 static inline bool ice_is_tc_ena(unsigned long bitmap, u8 tc)
23 {
24 return test_bit(tc, &bitmap);
25 }
26
round_up_64bit(u64 a,u32 b)27 static inline u64 round_up_64bit(u64 a, u32 b)
28 {
29 return div64_long(((a) + (b) / 2), (b));
30 }
31
ice_round_to_num(u32 N,u32 R)32 static inline u32 ice_round_to_num(u32 N, u32 R)
33 {
34 return ((((N) % (R)) < ((R) / 2)) ? (((N) / (R)) * (R)) :
35 ((((N) + (R) - 1) / (R)) * (R)));
36 }
37
38 /* Driver always calls main vsi_handle first */
39 #define ICE_MAIN_VSI_HANDLE 0
40
41 /* debug masks - set these bits in hw->debug_mask to control output */
42 #define ICE_DBG_INIT BIT_ULL(1)
43 #define ICE_DBG_FW_LOG BIT_ULL(3)
44 #define ICE_DBG_LINK BIT_ULL(4)
45 #define ICE_DBG_PHY BIT_ULL(5)
46 #define ICE_DBG_QCTX BIT_ULL(6)
47 #define ICE_DBG_NVM BIT_ULL(7)
48 #define ICE_DBG_LAN BIT_ULL(8)
49 #define ICE_DBG_FLOW BIT_ULL(9)
50 #define ICE_DBG_SW BIT_ULL(13)
51 #define ICE_DBG_SCHED BIT_ULL(14)
52 #define ICE_DBG_RDMA BIT_ULL(15)
53 #define ICE_DBG_PKG BIT_ULL(16)
54 #define ICE_DBG_RES BIT_ULL(17)
55 #define ICE_DBG_PTP BIT_ULL(19)
56 #define ICE_DBG_AQ_MSG BIT_ULL(24)
57 #define ICE_DBG_AQ_DESC BIT_ULL(25)
58 #define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
59 #define ICE_DBG_AQ_CMD BIT_ULL(27)
60 #define ICE_DBG_AQ (ICE_DBG_AQ_MSG | \
61 ICE_DBG_AQ_DESC | \
62 ICE_DBG_AQ_DESC_BUF | \
63 ICE_DBG_AQ_CMD)
64
65 #define ICE_DBG_USER BIT_ULL(31)
66
67 enum ice_aq_res_ids {
68 ICE_NVM_RES_ID = 1,
69 ICE_SPD_RES_ID,
70 ICE_CHANGE_LOCK_RES_ID,
71 ICE_GLOBAL_CFG_LOCK_RES_ID
72 };
73
74 /* FW update timeout definitions are in milliseconds */
75 #define ICE_NVM_TIMEOUT 180000
76 #define ICE_CHANGE_LOCK_TIMEOUT 1000
77 #define ICE_GLOBAL_CFG_LOCK_TIMEOUT 5000
78
79 enum ice_aq_res_access_type {
80 ICE_RES_READ = 1,
81 ICE_RES_WRITE
82 };
83
84 struct ice_driver_ver {
85 u8 major_ver;
86 u8 minor_ver;
87 u8 build_ver;
88 u8 subbuild_ver;
89 u8 driver_string[32];
90 };
91
92 enum ice_fc_mode {
93 ICE_FC_NONE = 0,
94 ICE_FC_RX_PAUSE,
95 ICE_FC_TX_PAUSE,
96 ICE_FC_FULL,
97 ICE_FC_PFC,
98 ICE_FC_DFLT
99 };
100
101 enum ice_phy_cache_mode {
102 ICE_FC_MODE = 0,
103 ICE_SPEED_MODE,
104 ICE_FEC_MODE
105 };
106
107 enum ice_fec_mode {
108 ICE_FEC_NONE = 0,
109 ICE_FEC_RS,
110 ICE_FEC_BASER,
111 ICE_FEC_AUTO
112 };
113
114 struct ice_phy_cache_mode_data {
115 union {
116 enum ice_fec_mode curr_user_fec_req;
117 enum ice_fc_mode curr_user_fc_req;
118 u16 curr_user_speed_req;
119 } data;
120 };
121
122 enum ice_set_fc_aq_failures {
123 ICE_SET_FC_AQ_FAIL_NONE = 0,
124 ICE_SET_FC_AQ_FAIL_GET,
125 ICE_SET_FC_AQ_FAIL_SET,
126 ICE_SET_FC_AQ_FAIL_UPDATE
127 };
128
129 /* Various MAC types */
130 enum ice_mac_type {
131 ICE_MAC_UNKNOWN = 0,
132 ICE_MAC_E810,
133 ICE_MAC_E830,
134 ICE_MAC_GENERIC,
135 ICE_MAC_GENERIC_3K_E825,
136 };
137
138 /* Media Types */
139 enum ice_media_type {
140 ICE_MEDIA_UNKNOWN = 0,
141 ICE_MEDIA_FIBER,
142 ICE_MEDIA_BASET,
143 ICE_MEDIA_BACKPLANE,
144 ICE_MEDIA_DA,
145 };
146
147 enum ice_vsi_type {
148 ICE_VSI_PF = 0,
149 ICE_VSI_VF = 1,
150 ICE_VSI_CTRL = 3, /* equates to ICE_VSI_PF with 1 queue pair */
151 ICE_VSI_CHNL = 4,
152 ICE_VSI_LB = 6,
153 };
154
155 struct ice_link_status {
156 /* Refer to ice_aq_phy_type for bits definition */
157 u64 phy_type_low;
158 u64 phy_type_high;
159 u8 topo_media_conflict;
160 u16 max_frame_size;
161 u16 link_speed;
162 u16 req_speeds;
163 u8 link_cfg_err;
164 u8 lse_ena; /* Link Status Event notification */
165 u8 link_info;
166 u8 an_info;
167 u8 ext_info;
168 u8 fec_info;
169 u8 pacing;
170 /* Refer to #define from module_type[ICE_MODULE_TYPE_TOTAL_BYTE] of
171 * ice_aqc_get_phy_caps structure
172 */
173 u8 module_type[ICE_MODULE_TYPE_TOTAL_BYTE];
174 };
175
176 /* Different reset sources for which a disable queue AQ call has to be made in
177 * order to clean the Tx scheduler as a part of the reset
178 */
179 enum ice_disq_rst_src {
180 ICE_NO_RESET = 0,
181 ICE_VM_RESET,
182 ICE_VF_RESET,
183 };
184
185 /* PHY info such as phy_type, etc... */
186 struct ice_phy_info {
187 struct ice_link_status link_info;
188 struct ice_link_status link_info_old;
189 u64 phy_type_low;
190 u64 phy_type_high;
191 enum ice_media_type media_type;
192 u8 get_link_info;
193 /* Please refer to struct ice_aqc_get_link_status_data to get
194 * detail of enable bit in curr_user_speed_req
195 */
196 u16 curr_user_speed_req;
197 enum ice_fec_mode curr_user_fec_req;
198 enum ice_fc_mode curr_user_fc_req;
199 struct ice_aqc_set_phy_cfg_data curr_user_phy_cfg;
200 };
201
202 /* protocol enumeration for filters */
203 enum ice_fltr_ptype {
204 /* NONE - used for undef/error */
205 ICE_FLTR_PTYPE_NONF_NONE = 0,
206 ICE_FLTR_PTYPE_NONF_ETH,
207 ICE_FLTR_PTYPE_NONF_IPV4_UDP,
208 ICE_FLTR_PTYPE_NONF_IPV4_TCP,
209 ICE_FLTR_PTYPE_NONF_IPV4_SCTP,
210 ICE_FLTR_PTYPE_NONF_IPV4_OTHER,
211 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_UDP,
212 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_TCP,
213 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_ICMP,
214 ICE_FLTR_PTYPE_NONF_IPV4_GTPU_IPV4_OTHER,
215 ICE_FLTR_PTYPE_NONF_IPV6_GTPU_IPV6_OTHER,
216 ICE_FLTR_PTYPE_NONF_IPV4_L2TPV3,
217 ICE_FLTR_PTYPE_NONF_IPV6_L2TPV3,
218 ICE_FLTR_PTYPE_NONF_IPV4_ESP,
219 ICE_FLTR_PTYPE_NONF_IPV6_ESP,
220 ICE_FLTR_PTYPE_NONF_IPV4_AH,
221 ICE_FLTR_PTYPE_NONF_IPV6_AH,
222 ICE_FLTR_PTYPE_NONF_IPV4_NAT_T_ESP,
223 ICE_FLTR_PTYPE_NONF_IPV6_NAT_T_ESP,
224 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_NODE,
225 ICE_FLTR_PTYPE_NONF_IPV4_PFCP_SESSION,
226 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_NODE,
227 ICE_FLTR_PTYPE_NONF_IPV6_PFCP_SESSION,
228 ICE_FLTR_PTYPE_NON_IP_L2,
229 ICE_FLTR_PTYPE_FRAG_IPV4,
230 ICE_FLTR_PTYPE_NONF_IPV6_UDP,
231 ICE_FLTR_PTYPE_NONF_IPV6_TCP,
232 ICE_FLTR_PTYPE_NONF_IPV6_SCTP,
233 ICE_FLTR_PTYPE_NONF_IPV6_OTHER,
234 ICE_FLTR_PTYPE_MAX,
235 };
236
237 enum ice_fd_hw_seg {
238 ICE_FD_HW_SEG_NON_TUN = 0,
239 ICE_FD_HW_SEG_TUN,
240 ICE_FD_HW_SEG_MAX,
241 };
242
243 /* 1 ICE_VSI_PF + 1 ICE_VSI_CTRL + ICE_CHNL_MAX_TC */
244 #define ICE_MAX_FDIR_VSI_PER_FILTER (2 + ICE_CHNL_MAX_TC)
245
246 struct ice_fd_hw_prof {
247 struct ice_flow_seg_info *fdir_seg[ICE_FD_HW_SEG_MAX];
248 int cnt;
249 u64 entry_h[ICE_MAX_FDIR_VSI_PER_FILTER][ICE_FD_HW_SEG_MAX];
250 u16 vsi_h[ICE_MAX_FDIR_VSI_PER_FILTER];
251 u64 prof_id[ICE_FD_HW_SEG_MAX];
252 };
253
254 /* Common HW capabilities for SW use */
255 struct ice_hw_common_caps {
256 u32 valid_functions;
257 /* DCB capabilities */
258 u32 active_tc_bitmap;
259 u32 maxtc;
260
261 /* Tx/Rx queues */
262 u16 num_rxq; /* Number/Total Rx queues */
263 u16 rxq_first_id; /* First queue ID for Rx queues */
264 u16 num_txq; /* Number/Total Tx queues */
265 u16 txq_first_id; /* First queue ID for Tx queues */
266
267 /* MSI-X vectors */
268 u16 num_msix_vectors;
269 u16 msix_vector_first_id;
270
271 /* Max MTU for function or device */
272 u16 max_mtu;
273
274 /* Virtualization support */
275 u8 sr_iov_1_1; /* SR-IOV enabled */
276
277 /* RSS related capabilities */
278 u16 rss_table_size; /* 512 for PFs and 64 for VFs */
279 u8 rss_table_entry_width; /* RSS Entry width in bits */
280
281 u8 dcb;
282 u8 ieee_1588;
283 u8 rdma;
284 u8 roce_lag;
285 u8 sriov_lag;
286
287 bool nvm_update_pending_nvm;
288 bool nvm_update_pending_orom;
289 bool nvm_update_pending_netlist;
290 #define ICE_NVM_PENDING_NVM_IMAGE BIT(0)
291 #define ICE_NVM_PENDING_OROM BIT(1)
292 #define ICE_NVM_PENDING_NETLIST BIT(2)
293 bool nvm_unified_update;
294 #define ICE_NVM_MGMT_UNIFIED_UPD_SUPPORT BIT(3)
295 /* PCIe reset avoidance */
296 bool pcie_reset_avoidance;
297 /* Post update reset restriction */
298 bool reset_restrict_support;
299 bool tx_sched_topo_comp_mode_en;
300 };
301
302 /* IEEE 1588 TIME_SYNC specific info */
303 /* Function specific definitions */
304 #define ICE_TS_FUNC_ENA_M BIT(0)
305 #define ICE_TS_SRC_TMR_OWND_M BIT(1)
306 #define ICE_TS_TMR_ENA_M BIT(2)
307 #define ICE_TS_TMR_IDX_OWND_S 4
308 #define ICE_TS_TMR_IDX_OWND_M BIT(4)
309 #define ICE_TS_CLK_FREQ_S 16
310 #define ICE_TS_CLK_FREQ_M ICE_M(0x7, ICE_TS_CLK_FREQ_S)
311 #define ICE_TS_CLK_SRC_S 20
312 #define ICE_TS_CLK_SRC_M BIT(20)
313 #define ICE_TS_TMR_IDX_ASSOC_S 24
314 #define ICE_TS_TMR_IDX_ASSOC_M BIT(24)
315
316 /* TIME_REF clock rate specification */
317 enum ice_time_ref_freq {
318 ICE_TIME_REF_FREQ_25_000 = 0,
319 ICE_TIME_REF_FREQ_122_880 = 1,
320 ICE_TIME_REF_FREQ_125_000 = 2,
321 ICE_TIME_REF_FREQ_153_600 = 3,
322 ICE_TIME_REF_FREQ_156_250 = 4,
323 ICE_TIME_REF_FREQ_245_760 = 5,
324
325 NUM_ICE_TIME_REF_FREQ
326 };
327
328 /* Clock source specification */
329 enum ice_clk_src {
330 ICE_CLK_SRC_TCX0 = 0, /* Temperature compensated oscillator */
331 ICE_CLK_SRC_TIME_REF = 1, /* Use TIME_REF reference clock */
332
333 NUM_ICE_CLK_SRC
334 };
335
336 struct ice_ts_func_info {
337 /* Function specific info */
338 enum ice_time_ref_freq time_ref;
339 u8 clk_freq;
340 u8 clk_src;
341 u8 tmr_index_assoc;
342 u8 ena;
343 u8 tmr_index_owned;
344 u8 src_tmr_owned;
345 u8 tmr_ena;
346 };
347
348 /* Device specific definitions */
349 #define ICE_TS_TMR0_OWNR_M 0x7
350 #define ICE_TS_TMR0_OWND_M BIT(3)
351 #define ICE_TS_TMR1_OWNR_S 4
352 #define ICE_TS_TMR1_OWNR_M ICE_M(0x7, ICE_TS_TMR1_OWNR_S)
353 #define ICE_TS_TMR1_OWND_M BIT(7)
354 #define ICE_TS_DEV_ENA_M BIT(24)
355 #define ICE_TS_TMR0_ENA_M BIT(25)
356 #define ICE_TS_TMR1_ENA_M BIT(26)
357 #define ICE_TS_LL_TX_TS_READ_M BIT(28)
358 #define ICE_TS_LL_TX_TS_INT_READ_M BIT(29)
359
360 struct ice_ts_dev_info {
361 /* Device specific info */
362 u32 ena_ports;
363 u32 tmr_own_map;
364 u32 tmr0_owner;
365 u32 tmr1_owner;
366 u8 tmr0_owned;
367 u8 tmr1_owned;
368 u8 ena;
369 u8 tmr0_ena;
370 u8 tmr1_ena;
371 u8 ts_ll_read;
372 u8 ts_ll_int_read;
373 };
374
375 /* Function specific capabilities */
376 struct ice_hw_func_caps {
377 struct ice_hw_common_caps common_cap;
378 u32 num_allocd_vfs; /* Number of allocated VFs */
379 u32 vf_base_id; /* Logical ID of the first VF */
380 u32 guar_num_vsi;
381 u32 fd_fltr_guar; /* Number of filters guaranteed */
382 u32 fd_fltr_best_effort; /* Number of best effort filters */
383 struct ice_ts_func_info ts_func_info;
384 };
385
386 #define ICE_SENSOR_SUPPORT_E810_INT_TEMP_BIT 0
387
388 /* Device wide capabilities */
389 struct ice_hw_dev_caps {
390 struct ice_hw_common_caps common_cap;
391 u32 num_vfs_exposed; /* Total number of VFs exposed */
392 u32 num_vsi_allocd_to_host; /* Excluding EMP VSI */
393 u32 num_flow_director_fltr; /* Number of FD filters available */
394 struct ice_ts_dev_info ts_dev_info;
395 u32 num_funcs;
396 /* bitmap of supported sensors
397 * bit 0 - internal temperature sensor
398 * bit 31:1 - Reserved
399 */
400 u32 supported_sensors;
401 };
402
403 /* MAC info */
404 struct ice_mac_info {
405 u8 lan_addr[ETH_ALEN];
406 u8 perm_addr[ETH_ALEN];
407 };
408
409 /* Reset types used to determine which kind of reset was requested. These
410 * defines match what the RESET_TYPE field of the GLGEN_RSTAT register.
411 * ICE_RESET_PFR does not match any RESET_TYPE field in the GLGEN_RSTAT register
412 * because its reset source is different than the other types listed.
413 */
414 enum ice_reset_req {
415 ICE_RESET_POR = 0,
416 ICE_RESET_INVAL = 0,
417 ICE_RESET_CORER = 1,
418 ICE_RESET_GLOBR = 2,
419 ICE_RESET_EMPR = 3,
420 ICE_RESET_PFR = 4,
421 };
422
423 /* Bus parameters */
424 struct ice_bus_info {
425 u16 device;
426 u8 func;
427 };
428
429 /* Flow control (FC) parameters */
430 struct ice_fc_info {
431 enum ice_fc_mode current_mode; /* FC mode in effect */
432 enum ice_fc_mode req_mode; /* FC mode requested by caller */
433 };
434
435 /* Option ROM version information */
436 struct ice_orom_info {
437 u8 major; /* Major version of OROM */
438 u8 patch; /* Patch version of OROM */
439 u16 build; /* Build version of OROM */
440 };
441
442 /* NVM version information */
443 struct ice_nvm_info {
444 u32 eetrack;
445 u8 major;
446 u8 minor;
447 };
448
449 /* netlist version information */
450 struct ice_netlist_info {
451 u32 major; /* major high/low */
452 u32 minor; /* minor high/low */
453 u32 type; /* type high/low */
454 u32 rev; /* revision high/low */
455 u32 hash; /* SHA-1 hash word */
456 u16 cust_ver; /* customer version */
457 };
458
459 /* Enumeration of possible flash banks for the NVM, OROM, and Netlist modules
460 * of the flash image.
461 */
462 enum ice_flash_bank {
463 ICE_INVALID_FLASH_BANK,
464 ICE_1ST_FLASH_BANK,
465 ICE_2ND_FLASH_BANK,
466 };
467
468 /* Enumeration of which flash bank is desired to read from, either the active
469 * bank or the inactive bank. Used to abstract 1st and 2nd bank notion from
470 * code which just wants to read the active or inactive flash bank.
471 */
472 enum ice_bank_select {
473 ICE_ACTIVE_FLASH_BANK,
474 ICE_INACTIVE_FLASH_BANK,
475 };
476
477 /* information for accessing NVM, OROM, and Netlist flash banks */
478 struct ice_bank_info {
479 u32 nvm_ptr; /* Pointer to 1st NVM bank */
480 u32 nvm_size; /* Size of NVM bank */
481 u32 orom_ptr; /* Pointer to 1st OROM bank */
482 u32 orom_size; /* Size of OROM bank */
483 u32 netlist_ptr; /* Pointer to 1st Netlist bank */
484 u32 netlist_size; /* Size of Netlist bank */
485 u32 active_css_hdr_len; /* Active CSS header length */
486 u32 inactive_css_hdr_len; /* Inactive CSS header length */
487 enum ice_flash_bank nvm_bank; /* Active NVM bank */
488 enum ice_flash_bank orom_bank; /* Active OROM bank */
489 enum ice_flash_bank netlist_bank; /* Active Netlist bank */
490 };
491
492 /* Flash Chip Information */
493 struct ice_flash_info {
494 struct ice_orom_info orom; /* Option ROM version info */
495 struct ice_nvm_info nvm; /* NVM version information */
496 struct ice_netlist_info netlist;/* Netlist version info */
497 struct ice_bank_info banks; /* Flash Bank information */
498 u16 sr_words; /* Shadow RAM size in words */
499 u32 flash_size; /* Size of available flash in bytes */
500 u8 blank_nvm_mode; /* is NVM empty (no FW present) */
501 };
502
503 struct ice_link_default_override_tlv {
504 u8 options;
505 #define ICE_LINK_OVERRIDE_OPT_M 0x3F
506 #define ICE_LINK_OVERRIDE_STRICT_MODE BIT(0)
507 #define ICE_LINK_OVERRIDE_EPCT_DIS BIT(1)
508 #define ICE_LINK_OVERRIDE_PORT_DIS BIT(2)
509 #define ICE_LINK_OVERRIDE_EN BIT(3)
510 #define ICE_LINK_OVERRIDE_AUTO_LINK_DIS BIT(4)
511 #define ICE_LINK_OVERRIDE_EEE_EN BIT(5)
512 u8 phy_config;
513 #define ICE_LINK_OVERRIDE_PHY_CFG_S 8
514 #define ICE_LINK_OVERRIDE_PHY_CFG_M (0xC3 << ICE_LINK_OVERRIDE_PHY_CFG_S)
515 #define ICE_LINK_OVERRIDE_PAUSE_M 0x3
516 #define ICE_LINK_OVERRIDE_LESM_EN BIT(6)
517 #define ICE_LINK_OVERRIDE_AUTO_FEC_EN BIT(7)
518 u8 fec_options;
519 #define ICE_LINK_OVERRIDE_FEC_OPT_M 0xFF
520 u8 rsvd1;
521 u64 phy_type_low;
522 u64 phy_type_high;
523 };
524
525 #define ICE_NVM_VER_LEN 32
526
527 /* Max number of port to queue branches w.r.t topology */
528 #define ICE_MAX_TRAFFIC_CLASS 8
529 #define ICE_TXSCHED_MAX_BRANCHES ICE_MAX_TRAFFIC_CLASS
530
531 #define ice_for_each_traffic_class(_i) \
532 for ((_i) = 0; (_i) < ICE_MAX_TRAFFIC_CLASS; (_i)++)
533
534 /* ICE_DFLT_AGG_ID means that all new VM(s)/VSI node connects
535 * to driver defined policy for default aggregator
536 */
537 #define ICE_INVAL_TEID 0xFFFFFFFF
538 #define ICE_DFLT_AGG_ID 0
539
540 struct ice_sched_node {
541 struct ice_sched_node *parent;
542 struct ice_sched_node *sibling; /* next sibling in the same layer */
543 struct ice_sched_node **children;
544 struct ice_aqc_txsched_elem_data info;
545 char *name;
546 struct devlink_rate *rate_node;
547 u64 tx_max;
548 u64 tx_share;
549 u32 agg_id; /* aggregator group ID */
550 u32 id;
551 u32 tx_priority;
552 u32 tx_weight;
553 u16 vsi_handle;
554 u8 in_use; /* suspended or in use */
555 u8 tx_sched_layer; /* Logical Layer (1-9) */
556 u8 num_children;
557 u8 tc_num;
558 u8 owner;
559 #define ICE_SCHED_NODE_OWNER_LAN 0
560 #define ICE_SCHED_NODE_OWNER_RDMA 2
561 };
562
563 /* Access Macros for Tx Sched Elements data */
564 #define ICE_TXSCHED_GET_NODE_TEID(x) le32_to_cpu((x)->info.node_teid)
565
566 /* The aggregator type determines if identifier is for a VSI group,
567 * aggregator group, aggregator of queues, or queue group.
568 */
569 enum ice_agg_type {
570 ICE_AGG_TYPE_UNKNOWN = 0,
571 ICE_AGG_TYPE_VSI,
572 ICE_AGG_TYPE_AGG, /* aggregator */
573 ICE_AGG_TYPE_Q,
574 ICE_AGG_TYPE_QG
575 };
576
577 /* Rate limit types */
578 enum ice_rl_type {
579 ICE_UNKNOWN_BW = 0,
580 ICE_MIN_BW, /* for CIR profile */
581 ICE_MAX_BW, /* for EIR profile */
582 ICE_SHARED_BW /* for shared profile */
583 };
584
585 #define ICE_SCHED_MIN_BW 500 /* in Kbps */
586 #define ICE_SCHED_MAX_BW 100000000 /* in Kbps */
587 #define ICE_SCHED_DFLT_BW 0xFFFFFFFF /* unlimited */
588 #define ICE_SCHED_DFLT_RL_PROF_ID 0
589 #define ICE_SCHED_NO_SHARED_RL_PROF_ID 0xFFFF
590 #define ICE_SCHED_DFLT_BW_WT 4
591 #define ICE_SCHED_INVAL_PROF_ID 0xFFFF
592 #define ICE_SCHED_DFLT_BURST_SIZE (15 * 1024) /* in bytes (15k) */
593
594 #define ICE_MAX_PORT_PER_PCI_DEV 8
595
596 /* Data structure for saving BW information */
597 enum ice_bw_type {
598 ICE_BW_TYPE_PRIO,
599 ICE_BW_TYPE_CIR,
600 ICE_BW_TYPE_CIR_WT,
601 ICE_BW_TYPE_EIR,
602 ICE_BW_TYPE_EIR_WT,
603 ICE_BW_TYPE_SHARED,
604 ICE_BW_TYPE_CNT /* This must be last */
605 };
606
607 struct ice_bw {
608 u32 bw;
609 u16 bw_alloc;
610 };
611
612 struct ice_bw_type_info {
613 DECLARE_BITMAP(bw_t_bitmap, ICE_BW_TYPE_CNT);
614 u8 generic;
615 struct ice_bw cir_bw;
616 struct ice_bw eir_bw;
617 u32 shared_bw;
618 };
619
620 /* VSI queue context structure for given TC */
621 struct ice_q_ctx {
622 u16 q_handle;
623 u32 q_teid;
624 /* bw_t_info saves queue BW information */
625 struct ice_bw_type_info bw_t_info;
626 };
627
628 /* VSI type list entry to locate corresponding VSI/aggregator nodes */
629 struct ice_sched_vsi_info {
630 struct ice_sched_node *vsi_node[ICE_MAX_TRAFFIC_CLASS];
631 struct ice_sched_node *ag_node[ICE_MAX_TRAFFIC_CLASS];
632 struct list_head list_entry;
633 u16 max_lanq[ICE_MAX_TRAFFIC_CLASS];
634 u16 max_rdmaq[ICE_MAX_TRAFFIC_CLASS];
635 /* bw_t_info saves VSI BW information */
636 struct ice_bw_type_info bw_t_info[ICE_MAX_TRAFFIC_CLASS];
637 };
638
639 /* driver defines the policy */
640 struct ice_sched_tx_policy {
641 u16 max_num_vsis;
642 u8 max_num_lan_qs_per_tc[ICE_MAX_TRAFFIC_CLASS];
643 u8 rdma_ena;
644 };
645
646 /* CEE or IEEE 802.1Qaz ETS Configuration data */
647 struct ice_dcb_ets_cfg {
648 u8 willing;
649 u8 cbs;
650 u8 maxtcs;
651 u8 prio_table[ICE_MAX_TRAFFIC_CLASS];
652 u8 tcbwtable[ICE_MAX_TRAFFIC_CLASS];
653 u8 tsatable[ICE_MAX_TRAFFIC_CLASS];
654 };
655
656 /* CEE or IEEE 802.1Qaz PFC Configuration data */
657 struct ice_dcb_pfc_cfg {
658 u8 willing;
659 u8 mbc;
660 u8 pfccap;
661 u8 pfcena;
662 };
663
664 /* CEE or IEEE 802.1Qaz Application Priority data */
665 struct ice_dcb_app_priority_table {
666 u16 prot_id;
667 u8 priority;
668 u8 selector;
669 };
670
671 #define ICE_MAX_USER_PRIORITY 8
672 #define ICE_DCBX_MAX_APPS 64
673 #define ICE_DSCP_NUM_VAL 64
674 #define ICE_LLDPDU_SIZE 1500
675 #define ICE_TLV_STATUS_OPER 0x1
676 #define ICE_TLV_STATUS_SYNC 0x2
677 #define ICE_TLV_STATUS_ERR 0x4
678 #define ICE_APP_PROT_ID_ISCSI_860 0x035c
679 #define ICE_APP_SEL_ETHTYPE 0x1
680 #define ICE_APP_SEL_TCPIP 0x2
681 #define ICE_CEE_APP_SEL_ETHTYPE 0x0
682 #define ICE_SR_LINK_DEFAULT_OVERRIDE_PTR 0x134
683 #define ICE_CEE_APP_SEL_TCPIP 0x1
684
685 struct ice_dcbx_cfg {
686 u32 numapps;
687 u32 tlv_status; /* CEE mode TLV status */
688 struct ice_dcb_ets_cfg etscfg;
689 struct ice_dcb_ets_cfg etsrec;
690 struct ice_dcb_pfc_cfg pfc;
691 #define ICE_QOS_MODE_VLAN 0x0
692 #define ICE_QOS_MODE_DSCP 0x1
693 u8 pfc_mode;
694 struct ice_dcb_app_priority_table app[ICE_DCBX_MAX_APPS];
695 /* when DSCP mapping defined by user set its bit to 1 */
696 DECLARE_BITMAP(dscp_mapped, ICE_DSCP_NUM_VAL);
697 /* array holding DSCP -> UP/TC values for DSCP L3 QoS mode */
698 u8 dscp_map[ICE_DSCP_NUM_VAL];
699 u8 dcbx_mode;
700 #define ICE_DCBX_MODE_CEE 0x1
701 #define ICE_DCBX_MODE_IEEE 0x2
702 u8 app_mode;
703 #define ICE_DCBX_APPS_NON_WILLING 0x1
704 };
705
706 struct ice_qos_cfg {
707 struct ice_dcbx_cfg local_dcbx_cfg; /* Oper/Local Cfg */
708 struct ice_dcbx_cfg desired_dcbx_cfg; /* CEE Desired Cfg */
709 struct ice_dcbx_cfg remote_dcbx_cfg; /* Peer Cfg */
710 u8 dcbx_status : 3; /* see ICE_DCBX_STATUS_DIS */
711 u8 is_sw_lldp : 1;
712 };
713
714 struct ice_port_info {
715 struct ice_sched_node *root; /* Root Node per Port */
716 struct ice_hw *hw; /* back pointer to HW instance */
717 u32 last_node_teid; /* scheduler last node info */
718 u16 sw_id; /* Initial switch ID belongs to port */
719 u16 pf_vf_num;
720 u8 port_state;
721 #define ICE_SCHED_PORT_STATE_INIT 0x0
722 #define ICE_SCHED_PORT_STATE_READY 0x1
723 u8 lport;
724 #define ICE_LPORT_MASK 0xff
725 struct ice_fc_info fc;
726 struct ice_mac_info mac;
727 struct ice_phy_info phy;
728 struct mutex sched_lock; /* protect access to TXSched tree */
729 struct ice_sched_node *
730 sib_head[ICE_MAX_TRAFFIC_CLASS][ICE_AQC_TOPO_MAX_LEVEL_NUM];
731 /* List contain profile ID(s) and other params per layer */
732 struct list_head rl_prof_list[ICE_AQC_TOPO_MAX_LEVEL_NUM];
733 struct ice_qos_cfg qos_cfg;
734 struct xarray sched_node_ids;
735 u8 is_vf:1;
736 u8 is_custom_tx_enabled:1;
737 };
738
739 struct ice_switch_info {
740 struct list_head vsi_list_map_head;
741 struct ice_sw_recipe *recp_list;
742 u16 prof_res_bm_init;
743 u16 max_used_prof_index;
744
745 DECLARE_BITMAP(prof_res_bm[ICE_MAX_NUM_PROFILES], ICE_MAX_FV_WORDS);
746 };
747
748 /* Enum defining the different states of the mailbox snapshot in the
749 * PF-VF mailbox overflow detection algorithm. The snapshot can be in
750 * states:
751 * 1. ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT - generate a new static snapshot
752 * within the mailbox buffer.
753 * 2. ICE_MAL_VF_DETECT_STATE_TRAVERSE - iterate through the mailbox snaphot
754 * 3. ICE_MAL_VF_DETECT_STATE_DETECT - track the messages sent per VF via the
755 * mailbox and mark any VFs sending more messages than the threshold limit set.
756 * 4. ICE_MAL_VF_DETECT_STATE_INVALID - Invalid mailbox state set to 0xFFFFFFFF.
757 */
758 enum ice_mbx_snapshot_state {
759 ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT = 0,
760 ICE_MAL_VF_DETECT_STATE_TRAVERSE,
761 ICE_MAL_VF_DETECT_STATE_DETECT,
762 ICE_MAL_VF_DETECT_STATE_INVALID = 0xFFFFFFFF,
763 };
764
765 /* Structure to hold information of the static snapshot and the mailbox
766 * buffer data used to generate and track the snapshot.
767 * 1. state: the state of the mailbox snapshot in the malicious VF
768 * detection state handler ice_mbx_vf_state_handler()
769 * 2. head: head of the mailbox snapshot in a circular mailbox buffer
770 * 3. tail: tail of the mailbox snapshot in a circular mailbox buffer
771 * 4. num_iterations: number of messages traversed in circular mailbox buffer
772 * 5. num_msg_proc: number of messages processed in mailbox
773 * 6. num_pending_arq: number of pending asynchronous messages
774 * 7. max_num_msgs_mbx: maximum messages in mailbox for currently
775 * serviced work item or interrupt.
776 */
777 struct ice_mbx_snap_buffer_data {
778 enum ice_mbx_snapshot_state state;
779 u32 head;
780 u32 tail;
781 u32 num_iterations;
782 u16 num_msg_proc;
783 u16 num_pending_arq;
784 u16 max_num_msgs_mbx;
785 };
786
787 /* Structure used to track a single VF's messages on the mailbox:
788 * 1. list_entry: linked list entry node
789 * 2. msg_count: the number of asynchronous messages sent by this VF
790 * 3. malicious: whether this VF has been detected as malicious before
791 */
792 struct ice_mbx_vf_info {
793 struct list_head list_entry;
794 u32 msg_count;
795 u8 malicious : 1;
796 };
797
798 /* Structure to hold data relevant to the captured static snapshot
799 * of the PF-VF mailbox.
800 */
801 struct ice_mbx_snapshot {
802 struct ice_mbx_snap_buffer_data mbx_buf;
803 struct list_head mbx_vf;
804 };
805
806 /* Structure to hold data to be used for capturing or updating a
807 * static snapshot.
808 * 1. num_msg_proc: number of messages processed in mailbox
809 * 2. num_pending_arq: number of pending asynchronous messages
810 * 3. max_num_msgs_mbx: maximum messages in mailbox for currently
811 * serviced work item or interrupt.
812 * 4. async_watermark_val: An upper threshold set by caller to determine
813 * if the pending arq count is large enough to assume that there is
814 * the possibility of a mailicious VF.
815 */
816 struct ice_mbx_data {
817 u16 num_msg_proc;
818 u16 num_pending_arq;
819 u16 max_num_msgs_mbx;
820 u16 async_watermark_val;
821 };
822
823 /* PHY model */
824 enum ice_phy_model {
825 ICE_PHY_UNSUP = -1,
826 ICE_PHY_E810 = 1,
827 ICE_PHY_E82X,
828 };
829
830 /* Port hardware description */
831 struct ice_hw {
832 u8 __iomem *hw_addr;
833 void *back;
834 struct ice_aqc_layer_props *layer_info;
835 struct ice_port_info *port_info;
836 /* PSM clock frequency for calculating RL profile params */
837 u32 psm_clk_freq;
838 u64 debug_mask; /* bitmap for debug mask */
839 enum ice_mac_type mac_type;
840
841 u16 fd_ctr_base; /* FD counter base index */
842
843 /* pci info */
844 u16 device_id;
845 u16 vendor_id;
846 u16 subsystem_device_id;
847 u16 subsystem_vendor_id;
848 u8 revision_id;
849
850 u8 pf_id; /* device profile info */
851 enum ice_phy_model phy_model;
852
853 u16 max_burst_size; /* driver sets this value */
854
855 u8 recp_reuse:1; /* indicates whether FW supports recipe reuse */
856
857 /* Tx Scheduler values */
858 u8 num_tx_sched_layers;
859 u8 num_tx_sched_phys_layers;
860 u8 flattened_layers;
861 u8 max_cgds;
862 u8 sw_entry_point_layer;
863 u16 max_children[ICE_AQC_TOPO_MAX_LEVEL_NUM];
864 struct list_head agg_list; /* lists all aggregator */
865
866 struct ice_vsi_ctx *vsi_ctx[ICE_MAX_VSI];
867 u8 evb_veb; /* true for VEB, false for VEPA */
868 u8 reset_ongoing; /* true if HW is in reset, false otherwise */
869 struct ice_bus_info bus;
870 struct ice_flash_info flash;
871 struct ice_hw_dev_caps dev_caps; /* device capabilities */
872 struct ice_hw_func_caps func_caps; /* function capabilities */
873
874 struct ice_switch_info *switch_info; /* switch filter lists */
875
876 /* Control Queue info */
877 struct ice_ctl_q_info adminq;
878 struct ice_ctl_q_info sbq;
879 struct ice_ctl_q_info mailboxq;
880
881 u8 api_branch; /* API branch version */
882 u8 api_maj_ver; /* API major version */
883 u8 api_min_ver; /* API minor version */
884 u8 api_patch; /* API patch version */
885 u8 fw_branch; /* firmware branch version */
886 u8 fw_maj_ver; /* firmware major version */
887 u8 fw_min_ver; /* firmware minor version */
888 u8 fw_patch; /* firmware patch version */
889 u32 fw_build; /* firmware build number */
890
891 struct ice_fwlog_cfg fwlog_cfg;
892 bool fwlog_supported; /* does hardware support FW logging? */
893 struct ice_fwlog_ring fwlog_ring;
894
895 /* Device max aggregate bandwidths corresponding to the GL_PWR_MODE_CTL
896 * register. Used for determining the ITR/INTRL granularity during
897 * initialization.
898 */
899 #define ICE_MAX_AGG_BW_200G 0x0
900 #define ICE_MAX_AGG_BW_100G 0X1
901 #define ICE_MAX_AGG_BW_50G 0x2
902 #define ICE_MAX_AGG_BW_25G 0x3
903 /* ITR granularity for different speeds */
904 #define ICE_ITR_GRAN_ABOVE_25 2
905 #define ICE_ITR_GRAN_MAX_25 4
906 /* ITR granularity in 1 us */
907 u8 itr_gran;
908 /* INTRL granularity for different speeds */
909 #define ICE_INTRL_GRAN_ABOVE_25 4
910 #define ICE_INTRL_GRAN_MAX_25 8
911 /* INTRL granularity in 1 us */
912 u8 intrl_gran;
913
914 #define ICE_MAX_QUAD 2
915 #define ICE_QUADS_PER_PHY_E82X 2
916 #define ICE_PORTS_PER_PHY_E82X 8
917 #define ICE_PORTS_PER_QUAD 4
918 #define ICE_PORTS_PER_PHY_E810 4
919 #define ICE_NUM_EXTERNAL_PORTS (ICE_MAX_QUAD * ICE_PORTS_PER_QUAD)
920
921 /* Active package version (currently active) */
922 struct ice_pkg_ver active_pkg_ver;
923 u32 pkg_seg_id;
924 u32 pkg_sign_type;
925 u32 active_track_id;
926 u8 pkg_has_signing_seg:1;
927 u8 active_pkg_name[ICE_PKG_NAME_SIZE];
928 u8 active_pkg_in_nvm;
929
930 /* Driver's package ver - (from the Ice Metadata section) */
931 struct ice_pkg_ver pkg_ver;
932 u8 pkg_name[ICE_PKG_NAME_SIZE];
933
934 /* Driver's Ice segment format version and ID (from the Ice seg) */
935 struct ice_pkg_ver ice_seg_fmt_ver;
936 u8 ice_seg_id[ICE_SEG_ID_SIZE];
937
938 /* Pointer to the ice segment */
939 struct ice_seg *seg;
940
941 /* Pointer to allocated copy of pkg memory */
942 u8 *pkg_copy;
943 u32 pkg_size;
944
945 /* tunneling info */
946 struct mutex tnl_lock;
947 struct ice_tunnel_table tnl;
948
949 struct udp_tunnel_nic_shared udp_tunnel_shared;
950 struct udp_tunnel_nic_info udp_tunnel_nic;
951
952 /* dvm boost update information */
953 struct ice_dvm_table dvm_upd;
954
955 /* HW block tables */
956 struct ice_blk_info blk[ICE_BLK_COUNT];
957 struct mutex fl_profs_locks[ICE_BLK_COUNT]; /* lock fltr profiles */
958 struct list_head fl_profs[ICE_BLK_COUNT];
959
960 /* Flow Director filter info */
961 int fdir_active_fltr;
962
963 struct mutex fdir_fltr_lock; /* protect Flow Director */
964 struct list_head fdir_list_head;
965
966 /* Book-keeping of side-band filter count per flow-type.
967 * This is used to detect and handle input set changes for
968 * respective flow-type.
969 */
970 u16 fdir_fltr_cnt[ICE_FLTR_PTYPE_MAX];
971
972 struct ice_fd_hw_prof **fdir_prof;
973 DECLARE_BITMAP(fdir_perfect_fltr, ICE_FLTR_PTYPE_MAX);
974 struct mutex rss_locks; /* protect RSS configuration */
975 struct list_head rss_list_head;
976 struct ice_mbx_snapshot mbx_snapshot;
977 DECLARE_BITMAP(hw_ptype, ICE_FLOW_PTYPE_MAX);
978 u8 dvm_ena;
979 u16 io_expander_handle;
980 u8 cgu_part_number;
981 };
982
983 /* Statistics collected by each port, VSI, VEB, and S-channel */
984 struct ice_eth_stats {
985 u64 rx_bytes; /* gorc */
986 u64 rx_unicast; /* uprc */
987 u64 rx_multicast; /* mprc */
988 u64 rx_broadcast; /* bprc */
989 u64 rx_discards; /* rdpc */
990 u64 rx_unknown_protocol; /* rupp */
991 u64 tx_bytes; /* gotc */
992 u64 tx_unicast; /* uptc */
993 u64 tx_multicast; /* mptc */
994 u64 tx_broadcast; /* bptc */
995 u64 tx_discards; /* tdpc */
996 u64 tx_errors; /* tepc */
997 };
998
999 #define ICE_MAX_UP 8
1000
1001 /* Statistics collected by the MAC */
1002 struct ice_hw_port_stats {
1003 /* eth stats collected by the port */
1004 struct ice_eth_stats eth;
1005 /* additional port specific stats */
1006 u64 tx_dropped_link_down; /* tdold */
1007 u64 crc_errors; /* crcerrs */
1008 u64 illegal_bytes; /* illerrc */
1009 u64 error_bytes; /* errbc */
1010 u64 mac_local_faults; /* mlfc */
1011 u64 mac_remote_faults; /* mrfc */
1012 u64 link_xon_rx; /* lxonrxc */
1013 u64 link_xoff_rx; /* lxoffrxc */
1014 u64 link_xon_tx; /* lxontxc */
1015 u64 link_xoff_tx; /* lxofftxc */
1016 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1017 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1018 u64 priority_xon_tx[8]; /* pxontxc[8] */
1019 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1020 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1021 u64 rx_size_64; /* prc64 */
1022 u64 rx_size_127; /* prc127 */
1023 u64 rx_size_255; /* prc255 */
1024 u64 rx_size_511; /* prc511 */
1025 u64 rx_size_1023; /* prc1023 */
1026 u64 rx_size_1522; /* prc1522 */
1027 u64 rx_size_big; /* prc9522 */
1028 u64 rx_undersize; /* ruc */
1029 u64 rx_fragments; /* rfc */
1030 u64 rx_oversize; /* roc */
1031 u64 rx_jabber; /* rjc */
1032 u64 tx_size_64; /* ptc64 */
1033 u64 tx_size_127; /* ptc127 */
1034 u64 tx_size_255; /* ptc255 */
1035 u64 tx_size_511; /* ptc511 */
1036 u64 tx_size_1023; /* ptc1023 */
1037 u64 tx_size_1522; /* ptc1522 */
1038 u64 tx_size_big; /* ptc9522 */
1039 /* flow director stats */
1040 u32 fd_sb_status;
1041 u64 fd_sb_match;
1042 };
1043
1044 enum ice_sw_fwd_act_type {
1045 ICE_FWD_TO_VSI = 0,
1046 ICE_FWD_TO_VSI_LIST, /* Do not use this when adding filter */
1047 ICE_FWD_TO_Q,
1048 ICE_FWD_TO_QGRP,
1049 ICE_DROP_PACKET,
1050 ICE_MIRROR_PACKET,
1051 ICE_NOP,
1052 ICE_INVAL_ACT
1053 };
1054
1055 struct ice_aq_get_set_rss_lut_params {
1056 u8 *lut; /* input RSS LUT for set and output RSS LUT for get */
1057 enum ice_lut_size lut_size; /* size of the LUT buffer */
1058 enum ice_lut_type lut_type; /* type of the LUT (i.e. VSI, PF, Global) */
1059 u16 vsi_handle; /* software VSI handle */
1060 u8 global_lut_id; /* only valid when lut_type is global */
1061 };
1062
1063 /* Checksum and Shadow RAM pointers */
1064 #define ICE_SR_NVM_CTRL_WORD 0x00
1065 #define ICE_SR_BOOT_CFG_PTR 0x132
1066 #define ICE_SR_NVM_WOL_CFG 0x19
1067 #define ICE_NVM_OROM_VER_OFF 0x02
1068 #define ICE_SR_PBA_BLOCK_PTR 0x16
1069 #define ICE_SR_NVM_DEV_STARTER_VER 0x18
1070 #define ICE_SR_NVM_EETRACK_LO 0x2D
1071 #define ICE_SR_NVM_EETRACK_HI 0x2E
1072 #define ICE_NVM_VER_LO_SHIFT 0
1073 #define ICE_NVM_VER_LO_MASK (0xff << ICE_NVM_VER_LO_SHIFT)
1074 #define ICE_NVM_VER_HI_SHIFT 12
1075 #define ICE_NVM_VER_HI_MASK (0xf << ICE_NVM_VER_HI_SHIFT)
1076 #define ICE_OROM_VER_PATCH_SHIFT 0
1077 #define ICE_OROM_VER_PATCH_MASK (0xff << ICE_OROM_VER_PATCH_SHIFT)
1078 #define ICE_OROM_VER_BUILD_SHIFT 8
1079 #define ICE_OROM_VER_BUILD_MASK (0xffff << ICE_OROM_VER_BUILD_SHIFT)
1080 #define ICE_OROM_VER_SHIFT 24
1081 #define ICE_OROM_VER_MASK (0xffU << ICE_OROM_VER_SHIFT)
1082 #define ICE_SR_PFA_PTR 0x40
1083 #define ICE_SR_1ST_NVM_BANK_PTR 0x42
1084 #define ICE_SR_NVM_BANK_SIZE 0x43
1085 #define ICE_SR_1ST_OROM_BANK_PTR 0x44
1086 #define ICE_SR_OROM_BANK_SIZE 0x45
1087 #define ICE_SR_NETLIST_BANK_PTR 0x46
1088 #define ICE_SR_NETLIST_BANK_SIZE 0x47
1089 #define ICE_SR_SECTOR_SIZE_IN_WORDS 0x800
1090
1091 /* CSS Header words */
1092 #define ICE_NVM_CSS_HDR_LEN_L 0x02
1093 #define ICE_NVM_CSS_HDR_LEN_H 0x03
1094 #define ICE_NVM_CSS_SREV_L 0x14
1095 #define ICE_NVM_CSS_SREV_H 0x15
1096
1097 /* Length of Authentication header section in words */
1098 #define ICE_NVM_AUTH_HEADER_LEN 0x08
1099
1100 /* The Link Topology Netlist section is stored as a series of words. It is
1101 * stored in the NVM as a TLV, with the first two words containing the type
1102 * and length.
1103 */
1104 #define ICE_NETLIST_LINK_TOPO_MOD_ID 0x011B
1105 #define ICE_NETLIST_TYPE_OFFSET 0x0000
1106 #define ICE_NETLIST_LEN_OFFSET 0x0001
1107
1108 /* The Link Topology section follows the TLV header. When reading the netlist
1109 * using ice_read_netlist_module, we need to account for the 2-word TLV
1110 * header.
1111 */
1112 #define ICE_NETLIST_LINK_TOPO_OFFSET(n) ((n) + 2)
1113
1114 #define ICE_LINK_TOPO_MODULE_LEN ICE_NETLIST_LINK_TOPO_OFFSET(0x0000)
1115 #define ICE_LINK_TOPO_NODE_COUNT ICE_NETLIST_LINK_TOPO_OFFSET(0x0001)
1116
1117 #define ICE_LINK_TOPO_NODE_COUNT_M ICE_M(0x3FF, 0)
1118
1119 /* The Netlist ID Block is located after all of the Link Topology nodes. */
1120 #define ICE_NETLIST_ID_BLK_SIZE 0x30
1121 #define ICE_NETLIST_ID_BLK_OFFSET(n) ICE_NETLIST_LINK_TOPO_OFFSET(0x0004 + 2 * (n))
1122
1123 /* netlist ID block field offsets (word offsets) */
1124 #define ICE_NETLIST_ID_BLK_MAJOR_VER_LOW 0x02
1125 #define ICE_NETLIST_ID_BLK_MAJOR_VER_HIGH 0x03
1126 #define ICE_NETLIST_ID_BLK_MINOR_VER_LOW 0x04
1127 #define ICE_NETLIST_ID_BLK_MINOR_VER_HIGH 0x05
1128 #define ICE_NETLIST_ID_BLK_TYPE_LOW 0x06
1129 #define ICE_NETLIST_ID_BLK_TYPE_HIGH 0x07
1130 #define ICE_NETLIST_ID_BLK_REV_LOW 0x08
1131 #define ICE_NETLIST_ID_BLK_REV_HIGH 0x09
1132 #define ICE_NETLIST_ID_BLK_SHA_HASH_WORD(n) (0x0A + (n))
1133 #define ICE_NETLIST_ID_BLK_CUST_VER 0x2F
1134
1135 /* Auxiliary field, mask, and shift definition for Shadow RAM and NVM Flash */
1136 #define ICE_SR_CTRL_WORD_1_S 0x06
1137 #define ICE_SR_CTRL_WORD_1_M (0x03 << ICE_SR_CTRL_WORD_1_S)
1138 #define ICE_SR_CTRL_WORD_VALID 0x1
1139 #define ICE_SR_CTRL_WORD_OROM_BANK BIT(3)
1140 #define ICE_SR_CTRL_WORD_NETLIST_BANK BIT(4)
1141 #define ICE_SR_CTRL_WORD_NVM_BANK BIT(5)
1142
1143 #define ICE_SR_NVM_PTR_4KB_UNITS BIT(15)
1144
1145 /* Link override related */
1146 #define ICE_SR_PFA_LINK_OVERRIDE_WORDS 10
1147 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_WORDS 4
1148 #define ICE_SR_PFA_LINK_OVERRIDE_OFFSET 2
1149 #define ICE_SR_PFA_LINK_OVERRIDE_FEC_OFFSET 1
1150 #define ICE_SR_PFA_LINK_OVERRIDE_PHY_OFFSET 2
1151 #define ICE_FW_API_LINK_OVERRIDE_MAJ 1
1152 #define ICE_FW_API_LINK_OVERRIDE_MIN 5
1153 #define ICE_FW_API_LINK_OVERRIDE_PATCH 2
1154
1155 #define ICE_SR_WORDS_IN_1KB 512
1156
1157 /* AQ API version for LLDP_FILTER_CONTROL */
1158 #define ICE_FW_API_LLDP_FLTR_MAJ 1
1159 #define ICE_FW_API_LLDP_FLTR_MIN 7
1160 #define ICE_FW_API_LLDP_FLTR_PATCH 1
1161
1162 /* AQ API version for report default configuration */
1163 #define ICE_FW_API_REPORT_DFLT_CFG_MAJ 1
1164 #define ICE_FW_API_REPORT_DFLT_CFG_MIN 7
1165 #define ICE_FW_API_REPORT_DFLT_CFG_PATCH 3
1166
1167 #endif /* _ICE_TYPE_H_ */
1168