1 /* $OpenBSD: ichreg.h,v 1.8 2022/01/09 05:42:46 jsg Exp $ */ 2 3 /* 4 * Copyright (c) 2004, 2005 Alexander Yurchenko <grange@openbsd.org> 5 * 6 * Permission to use, copy, modify, and distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 */ 18 19 #ifndef _DEV_PCI_ICHREG_H_ 20 #define _DEV_PCI_ICHREG_H_ 21 22 /* 23 * Intel I/O Controller Hub (ICH) register definitions. 24 */ 25 26 /* 27 * LPC interface bridge registers. 28 */ 29 30 /* PCI configuration registers */ 31 #define ICH_PMBASE 0x40 /* ACPI base address */ 32 #define ICH_ACPI_CNTL 0x44 /* ACPI control */ 33 #define ICH_ACPI_CNTL_ACPI_EN (1 << 4) /* ACPI enable */ 34 #define ICH_GEN_PMCON1 0xa0 /* general PM configuration */ 35 /* ICHx-M only */ 36 #define ICH_GEN_PMCON1_SS_EN 0x08 /* enable SpeedStep */ 37 38 /* Power management I/O registers */ 39 #define ICH_PM_TMR 0x08 /* PM timer */ 40 /* ICHx-M only */ 41 #define ICH_PM_CNTL 0x20 /* power management control */ 42 #define ICH_PM_ARB_DIS 0x01 /* disable arbiter */ 43 #define ICH_PM_SS_CNTL 0x50 /* SpeedStep control */ 44 #define ICH_PM_SS_STATE_LOW 0x01 /* low power state */ 45 46 #define ICH_PMSIZE 128 /* ACPI I/O space size */ 47 48 /* 49 * SMBus controller registers. 50 */ 51 52 /* PCI configuration registers */ 53 #define ICH_SMB_BASE 0x20 /* SMBus base address */ 54 #define ICH_SMB_HOSTC 0x40 /* host configuration */ 55 #define ICH_SMB_HOSTC_HSTEN (1 << 0) /* enable host controller */ 56 #define ICH_SMB_HOSTC_SMIEN (1 << 1) /* generate SMI */ 57 #define ICH_SMB_HOSTC_I2CEN (1 << 2) /* enable I2C commands */ 58 59 /* SMBus I/O registers */ 60 #define ICH_SMB_HS 0x00 /* host status */ 61 #define ICH_SMB_HS_BUSY (1 << 0) /* running a command */ 62 #define ICH_SMB_HS_INTR (1 << 1) /* command completed */ 63 #define ICH_SMB_HS_DEVERR (1 << 2) /* command error */ 64 #define ICH_SMB_HS_BUSERR (1 << 3) /* transaction collision */ 65 #define ICH_SMB_HS_FAILED (1 << 4) /* failed bus transaction */ 66 #define ICH_SMB_HS_SMBAL (1 << 5) /* SMBALERT# asserted */ 67 #define ICH_SMB_HS_INUSE (1 << 6) /* bus semaphore */ 68 #define ICH_SMB_HS_BDONE (1 << 7) /* byte received/transmitted */ 69 #define ICH_SMB_HS_BITS "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED\006SMBAL\007INUSE\010BDONE" 70 #define ICH_SMB_HC 0x02 /* host control */ 71 #define ICH_SMB_HC_INTREN (1 << 0) /* enable interrupts */ 72 #define ICH_SMB_HC_KILL (1 << 1) /* kill current transaction */ 73 #define ICH_SMB_HC_CMD_QUICK (0 << 2) /* QUICK command */ 74 #define ICH_SMB_HC_CMD_BYTE (1 << 2) /* BYTE command */ 75 #define ICH_SMB_HC_CMD_BDATA (2 << 2) /* BYTE DATA command */ 76 #define ICH_SMB_HC_CMD_WDATA (3 << 2) /* WORD DATA command */ 77 #define ICH_SMB_HC_CMD_PCALL (4 << 2) /* PROCESS CALL command */ 78 #define ICH_SMB_HC_CMD_BLOCK (5 << 2) /* BLOCK command */ 79 #define ICH_SMB_HC_CMD_I2CREAD (6 << 2) /* I2C READ command */ 80 #define ICH_SMB_HC_CMD_BLOCKP (7 << 2) /* BLOCK PROCESS command */ 81 #define ICH_SMB_HC_LASTB (1 << 5) /* last byte in block */ 82 #define ICH_SMB_HC_START (1 << 6) /* start transaction */ 83 #define ICH_SMB_HC_PECEN (1 << 7) /* enable PEC */ 84 #define ICH_SMB_HCMD 0x03 /* host command */ 85 #define ICH_SMB_TXSLVA 0x04 /* transmit slave address */ 86 #define ICH_SMB_TXSLVA_READ (1 << 0) /* read direction */ 87 #define ICH_SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */ 88 #define ICH_SMB_HD0 0x05 /* host data 0 */ 89 #define ICH_SMB_HD1 0x06 /* host data 1 */ 90 #define ICH_SMB_HBDB 0x07 /* host block data byte */ 91 #define ICH_SMB_PEC 0x08 /* PEC data */ 92 #define ICH_SMB_RXSLVA 0x09 /* receive slave address */ 93 #define ICH_SMB_SD 0x0a /* receive slave data */ 94 #define ICH_SMB_SD_MSG0(x) ((x) & 0xff) /* data message byte 0 */ 95 #define ICH_SMB_SD_MSG1(x) ((x) >> 8) /* data message byte 1 */ 96 #define ICH_SMB_AS 0x0c /* auxiliary status */ 97 #define ICH_SMB_AS_CRCE (1 << 0) /* CRC error */ 98 #define ICH_SMB_AS_TCO (1 << 1) /* advanced TCO mode */ 99 #define ICH_SMB_AC 0x0d /* auxiliary control */ 100 #define ICH_SMB_AC_AAC (1 << 0) /* automatically append CRC */ 101 #define ICH_SMB_AC_E32B (1 << 1) /* enable 32-byte buffer */ 102 #define ICH_SMB_SMLPC 0x0e /* SMLink pin control */ 103 #define ICH_SMB_SMLPC_LINK0 (1 << 0) /* SMLINK0 pin state */ 104 #define ICH_SMB_SMLPC_LINK1 (1 << 1) /* SMLINK1 pin state */ 105 #define ICH_SMB_SMLPC_CLKC (1 << 2) /* SMLINK0 pin is untouched */ 106 #define ICH_SMB_SMBPC 0x0f /* SMBus pin control */ 107 #define ICH_SMB_SMBPC_CLK (1 << 0) /* SMBCLK pin state */ 108 #define ICH_SMB_SMBPC_DATA (1 << 1) /* SMBDATA pin state */ 109 #define ICH_SMB_SMBPC_CLKC (1 << 2) /* SMBCLK pin is untouched */ 110 #define ICH_SMB_SS 0x10 /* slave status */ 111 #define ICH_SMB_SS_HN (1 << 0) /* Host Notify command */ 112 #define ICH_SMB_SCMD 0x11 /* slave command */ 113 #define ICH_SMB_SCMD_INTREN (1 << 0) /* enable interrupts on HN */ 114 #define ICH_SMB_SCMD_WKEN (1 << 1) /* wake on HN */ 115 #define ICH_SMB_SCMD_SMBALDS (1 << 2) /* disable SMBALERT# intr */ 116 #define ICH_SMB_NDADDR 0x14 /* notify device address */ 117 #define ICH_SMB_NDADDR_ADDR(x) ((x) >> 1) /* 7-bit address */ 118 #define ICH_SMB_NDLOW 0x16 /* notify data low byte */ 119 #define ICH_SMB_NDHIGH 0x17 /* notify data high byte */ 120 121 /* 122 * 6300ESB watchdog timer registers. 123 */ 124 125 /* PCI configuration registers */ 126 #define ICH_WDT_BASE 0x10 /* memory space base address */ 127 #define ICH_WDT_CONF 0x60 /* configuration register */ 128 #define ICH_WDT_CONF_MASK 0xffff /* 16-bit register */ 129 #define ICH_WDT_CONF_INT_MASK 0x3 /* interrupt type */ 130 #define ICH_WDT_CONF_INT_IRQ 0x0 /* IRQ (APIC 1, INT 10) */ 131 #define ICH_WDT_CONF_INT_SMI 0x2 /* SMI */ 132 #define ICH_WDT_CONF_INT_DIS 0x3 /* disabled */ 133 #define ICH_WDT_CONF_PRE (1 << 2) /* 2^5 clock divisor */ 134 #define ICH_WDT_CONF_OUTDIS (1 << 5) /* WDT_TOUT# output disabled */ 135 #define ICH_WDT_LOCK 0x68 /* lock register */ 136 #define ICH_WDT_LOCK_LOCKED (1 << 0) /* register locked */ 137 #define ICH_WDT_LOCK_ENABLED (1 << 1) /* WDT enabled */ 138 #define ICH_WDT_LOCK_FREERUN (1 << 2) /* free running mode */ 139 140 /* Memory mapped registers */ 141 #define ICH_WDT_PRE1 0x00 /* preload value 1 */ 142 #define ICH_WDT_PRE2 0x04 /* preload value 2 */ 143 #define ICH_WDT_GIS 0x08 /* general interrupt status */ 144 #define ICH_WDT_GIS_ACTIVE (1 << 0) /* interrupt active */ 145 #define ICH_WDT_RELOAD 0x0c /* reload register */ 146 #define ICH_WDT_RELOAD_RLD (1 << 8) /* safe reload */ 147 #define ICH_WDT_RELOAD_TIMEOUT (1 << 9) /* timeout occurred */ 148 149 #endif /* !_DEV_PCI_ICHREG_H_ */ 150