1 /* SPDX-License-Identifier: BSD-3-Clause */ 2 /* Copyright(c) 2007-2022 Intel Corporation */ 3 /* 4 **************************************************************************** 5 * @file icp_qat_hw_20_comp_defs.h, (autogenerated at 04-19-18 16:06) 6 * @defgroup icp_qat_hw_comp_20 7 * @ingroup icp_qat_hw_comp_20 8 * @description 9 * This file represents the HW configuration CSR definitions 10 **************************************************************************** 11 */ 12 13 #ifndef _ICP_QAT_HW_20_COMP_DEFS_H 14 #define _ICP_QAT_HW_20_COMP_DEFS_H 15 16 /*****************************************************************************/ 17 /* SCB Disabled - Set by FW, located in upper 32bit */ 18 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_BITPOS 31 19 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_MASK 0x1 20 /* 21 **************************************************************************** 22 * @ingroup icp_qat_hw_defs 23 * @description 24 * Enumeration of possible SCB_CONTROL field values 25 *****************************************************************************/ 26 typedef enum { 27 ICP_QAT_HW_COMP_20_SCB_CONTROL_ENABLE = 0x0, 28 /* Normal Mode using SCB (Default) */ 29 ICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE = 0x1, 30 /* Legacy CPM1.x Mode with SCB disabled. */ 31 } icp_qat_hw_comp_20_scb_control_t; 32 33 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_CONTROL_DEFAULT_VAL \ 34 ICP_QAT_HW_COMP_20_SCB_CONTROL_DISABLE 35 36 /*****************************************************************************/ 37 /* Reset Bit Mask Disabled - Set by FW , located in upper 32bit */ 38 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_BITPOS 30 39 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_MASK 0x1 40 /* 41 **************************************************************************** 42 * @ingroup icp_qat_hw_defs 43 * @description 44 * Enumeration of possible RMB_CONTROL field values 45 *****************************************************************************/ 46 typedef enum { 47 ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_ALL = 0x0, 48 /* Reset all data structures with a set_config command. (Set by FW) */ 49 ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_FC_ONLY = 0x1, 50 /* Reset only the Frequency Counters (LFCT) with a set_config command. 51 */ 52 } icp_qat_hw_comp_20_rmb_control_t; 53 54 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_RMB_CONTROL_DEFAULT_VAL \ 55 ICP_QAT_HW_COMP_20_RMB_CONTROL_RESET_ALL 56 57 /*****************************************************************************/ 58 /* Slice Operation Mode (SOM) - Set By FW, located in upper 32bit */ 59 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_BITPOS 28 60 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_MASK 0x3 61 /* 62 **************************************************************************** 63 * @ingroup icp_qat_hw_defs 64 * @description 65 * Enumeration of possible SOM_CONTROL field values 66 *****************************************************************************/ 67 typedef enum { 68 ICP_QAT_HW_COMP_20_SOM_CONTROL_NORMAL_MODE = 0x0, 69 /* Normal mode. */ 70 ICP_QAT_HW_COMP_20_SOM_CONTROL_REPLAY_MODE = 0x1, 71 /* Replay mode */ 72 ICP_QAT_HW_COMP_20_SOM_CONTROL_INPUT_CRC = 0x2, 73 /* Input CRC Mode */ 74 ICP_QAT_HW_COMP_20_SOM_CONTROL_RESERVED_MODE = 0x3, 75 /* Reserved. */ 76 } icp_qat_hw_comp_20_som_control_t; 77 78 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SOM_CONTROL_DEFAULT_VAL \ 79 ICP_QAT_HW_COMP_20_SOM_CONTROL_NORMAL_MODE 80 81 /*****************************************************************************/ 82 /* Skip Hash Read (Set By FW) , located in upper 32bit */ 83 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_BITPOS 27 84 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_MASK 0x1 85 /* 86 **************************************************************************** 87 * @ingroup icp_qat_hw_defs 88 * @description 89 * Enumeration of possible SKIP_HASH_RD_CONTROL field values 90 *****************************************************************************/ 91 typedef enum { 92 ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_NO_SKIP = 0x0, 93 /* When set to 0, hash reads are not skipped. */ 94 ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_SKIP_HASH_READS = 0x1, 95 /* Hash reads are skipped. */ 96 } icp_qat_hw_comp_20_skip_hash_rd_control_t; 97 98 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_RD_CONTROL_DEFAULT_VAL \ 99 ICP_QAT_HW_COMP_20_SKIP_HASH_RD_CONTROL_NO_SKIP 100 101 /*****************************************************************************/ 102 /* SCB Unload Disable, located in upper 32bit */ 103 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_BITPOS 26 104 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_MASK 0x1 105 /* 106 **************************************************************************** 107 * @ingroup icp_qat_hw_defs 108 * @description 109 * Enumeration of possible SCB_UNLOAD_CONTROL field values 110 *****************************************************************************/ 111 typedef enum { 112 ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_UNLOAD = 0x0, 113 /* Unloads the LFCT and flushes the State Registers. */ 114 ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_NO_UNLOAD = 0x1, 115 /* Does not unload the LFCT, but flushes the State Registers. */ 116 } icp_qat_hw_comp_20_scb_unload_control_t; 117 118 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_UNLOAD_CONTROL_DEFAULT_VAL \ 119 ICP_QAT_HW_COMP_20_SCB_UNLOAD_CONTROL_UNLOAD 120 121 /*****************************************************************************/ 122 /* Disable token fusion, located in upper 32bit */ 123 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_BITPOS 21 124 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_MASK 0x1 125 /* 126 **************************************************************************** 127 * @ingroup icp_qat_hw_defs 128 * @description 129 * Enumeration of possible DISABLE_TOKEN_FUSION_CONTROL field values 130 *****************************************************************************/ 131 typedef enum { 132 ICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_ENABLE = 0x0, 133 /* Enables token fusion. */ 134 ICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_DISABLE = 0x1, 135 /* Disables token fusion. */ 136 } icp_qat_hw_comp_20_disable_token_fusion_control_t; 137 138 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_DISABLE_TOKEN_FUSION_CONTROL_DEFAULT_VAL \ 139 ICP_QAT_HW_COMP_20_DISABLE_TOKEN_FUSION_CONTROL_ENABLE 140 141 /*****************************************************************************/ 142 /* LZ4 Block Maximum Size (LBMS). Set by FW , located in upper 32bit */ 143 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_BITPOS 19 144 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_MASK 0x3 145 /* 146 **************************************************************************** 147 * @ingroup icp_qat_hw_defs 148 * @description 149 * Enumeration of possible LBMS field values 150 *****************************************************************************/ 151 typedef enum { 152 ICP_QAT_HW_COMP_20_LBMS_LBMS_64KB = 0x0, 153 /* LZ4 Block Maximum Size (LBMS) == 64 KB */ 154 ICP_QAT_HW_COMP_20_LBMS_LBMS_256KB = 0x1, 155 /* LZ4 Block Maximum Size (LBMS) == 256 KB */ 156 ICP_QAT_HW_COMP_20_LBMS_LBMS_1MB = 0x2, 157 /* LZ4 Block Maximum Size (LBMS) == 1 MB */ 158 ICP_QAT_HW_COMP_20_LBMS_LBMS_4MB = 0x3, 159 /* LZ4 Block Maximum Size (LBMS) == 4 MB */ 160 } icp_qat_hw_comp_20_lbms_t; 161 162 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LBMS_DEFAULT_VAL \ 163 ICP_QAT_HW_COMP_20_LBMS_LBMS_64KB 164 165 /*****************************************************************************/ 166 /* SCB Mode Reset Mask (Set By FW) , located in upper 32bit */ 167 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_BITPOS 18 168 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_MASK 0x1 169 /* 170 **************************************************************************** 171 * @ingroup icp_qat_hw_defs 172 * @description 173 * Enumeration of possible SCB_MODE_RESET_MASK field values 174 *****************************************************************************/ 175 typedef enum { 176 ICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS = 0x0, 177 /* LZ4 mode: Reset LIBC, LOBC, In iLZ77 mode: Reset LFCT, OBC */ 178 ICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS_AND_HISTORY = 0x1, 179 /* LZ4 mode: Reset LIBC, LOBC, HB, HT, In iLZ77 mode: Reset LFCT, OBC, 180 HB, HT */ 181 } icp_qat_hw_comp_20_scb_mode_reset_mask_t; 182 183 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SCB_MODE_RESET_MASK_DEFAULT_VAL \ 184 ICP_QAT_HW_COMP_20_SCB_MODE_RESET_MASK_RESET_COUNTERS 185 186 /*****************************************************************************/ 187 /* Lazy - For iLZ77, LZ4, and Static DEFLATE, Lazy = 102h , located in upper 188 * 32bit */ 189 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_BITPOS 9 190 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_MASK 0x1ff 191 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LAZY_PARAM_DEFAULT_VAL 258 192 193 /*****************************************************************************/ 194 /* Nice - For iLZ77, LZ4, and Static DEFLATE, Nice = 103h , located in upper 195 * 32bit */ 196 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_BITPOS 0 197 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_MASK 0x1ff 198 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_NICE_PARAM_DEFAULT_VAL 259 199 200 /*****************************************************************************/ 201 /* History Buffer Size (Set By the Driver/ Application), located in lower 32bit 202 */ 203 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS 14 204 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_MASK 0x7 205 /* 206 **************************************************************************** 207 * @ingroup icp_qat_hw_defs 208 * @description 209 * Enumeration of possible HBS_CONTROL field values 210 *****************************************************************************/ 211 typedef enum { 212 ICP_QAT_HW_COMP_20_HBS_CONTROL_HBS_IS_32KB = 0x0, 213 /* 000b - 32KB */ 214 } icp_qat_hw_comp_20_hbs_control_t; 215 216 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HBS_CONTROL_DEFAULT_VAL \ 217 ICP_QAT_HW_COMP_20_HBS_CONTROL_HBS_IS_32KB 218 219 /*****************************************************************************/ 220 /* Adaptive Block Drop (Set By FW if Dynamic), located in lower 32bit */ 221 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_BITPOS 13 222 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_MASK 0x1 223 /* 224 **************************************************************************** 225 * @ingroup icp_qat_hw_defs 226 * @description 227 * Enumeration of possible ABD field values 228 *****************************************************************************/ 229 typedef enum { 230 ICP_QAT_HW_COMP_20_ABD_ABD_ENABLED = 0x0, 231 /* 0b - Feature enabled. */ 232 ICP_QAT_HW_COMP_20_ABD_ABD_DISABLED = 0x1, 233 /* 1b - Feature disabled. */ 234 } icp_qat_hw_comp_20_abd_t; 235 236 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_ABD_DEFAULT_VAL \ 237 ICP_QAT_HW_COMP_20_ABD_ABD_ENABLED 238 239 /*****************************************************************************/ 240 /* Literal+Length Limit Block Drop Block Drop, (Set By FW if Dynamic) , located 241 * in lower 32bit */ 242 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_BITPOS 12 243 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_MASK 0x1 244 /* 245 **************************************************************************** 246 * @ingroup icp_qat_hw_defs 247 * @description 248 * Enumeration of possible LLLBD_CTRL field values 249 *****************************************************************************/ 250 typedef enum { 251 ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED = 0x0, 252 /* 0b - Feature enabled. */ 253 ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_DISABLED = 0x1, 254 /* 1b - Feature disabled. */ 255 } icp_qat_hw_comp_20_lllbd_ctrl_t; 256 257 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_LLLBD_CTRL_DEFAULT_VAL \ 258 ICP_QAT_HW_COMP_20_LLLBD_CTRL_LLLBD_ENABLED 259 260 /*****************************************************************************/ 261 /* Search Depth (SD) (Set By Driver/Application), located in lower 32bit */ 262 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_BITPOS 8 263 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_MASK 0xf 264 /* 265 **************************************************************************** 266 * @ingroup icp_qat_hw_defs 267 * @description 268 * Enumeration of possible SEARCH_DEPTH field values 269 *****************************************************************************/ 270 typedef enum { 271 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1 = 0x1, 272 /* 0001b - Level 1 (search depth = 2^1 = 2) */ 273 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_6 = 0x3, 274 /* 0001b - Level 6 (search depth = 2^3 = 8) */ 275 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_9 = 0x4, 276 /* 0001b - Level 9 (search depth = 2^4 = 16) */ 277 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_9P = 0x12, 278 /* 0001b - Level 9P (search depth = 2^12 = 4096) */ 279 } icp_qat_hw_comp_20_search_depth_t; 280 281 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SEARCH_DEPTH_DEFAULT_VAL \ 282 ICP_QAT_HW_COMP_20_SEARCH_DEPTH_LEVEL_1 283 284 /*****************************************************************************/ 285 /* Compression Format (Set By Driver/Application. Also See CMD ID), located in 286 * lower 32bit */ 287 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_BITPOS 5 288 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_MASK 0x7 289 /* 290 **************************************************************************** 291 * @ingroup icp_qat_hw_defs 292 * @description 293 * Enumeration of possible HW_COMP_FORMAT field values 294 *****************************************************************************/ 295 typedef enum { 296 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_ILZ77 = 0x0, 297 /* 000 - iLZ77. (Must set Min_Match = 3 bytes and HB size = 32KB.) */ 298 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_DEFLATE = 0x1, 299 /* 001 - Static DEFLATE. (Must set Min_Match = 3 bytes and HB size = 300 * 32KB.) 301 */ 302 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_LZ4 = 0x2, 303 /* 010 - LZ4. (Must set Min Match = 4 bytes and HB size = 64KB.) */ 304 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_LZ4S = 0x3, 305 /* 011 - LZ4s. (Min_Match and HBSize must be set accordingly.) */ 306 } icp_qat_hw_comp_20_hw_comp_format_t; 307 308 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_HW_COMP_FORMAT_DEFAULT_VAL \ 309 ICP_QAT_HW_COMP_20_HW_COMP_FORMAT_DEFLATE 310 311 /*****************************************************************************/ 312 /* Min Match (Set By FW to default value), located in lower 32bit */ 313 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS 4 314 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK 0x1 315 /* 316 **************************************************************************** 317 * @ingroup icp_qat_hw_defs 318 * @description 319 * Enumeration of possible MIN_MATCH_CONTROL field values 320 *****************************************************************************/ 321 typedef enum { 322 ICP_QAT_HW_COMP_20_MIN_MATCH_CONTROL_MATCH_3B = 0x0, 323 /* 0 - Match 3 B */ 324 ICP_QAT_HW_COMP_20_MIN_MATCH_CONTROL_MATCH_4B = 0x1, 325 /* 1 - Match 4 B */ 326 } icp_qat_hw_comp_20_min_match_control_t; 327 328 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_DEFAULT_VAL \ 329 ICP_QAT_HW_COMP_20_MIN_MATCH_CONTROL_MATCH_3B 330 331 /*****************************************************************************/ 332 /* Skip Hash Collision (Set By FW to default value), located in lower 32bit */ 333 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_BITPOS 3 334 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_MASK 0x1 335 /* 336 **************************************************************************** 337 * @ingroup icp_qat_hw_defs 338 * @description 339 * Enumeration of possible SKIP_HASH_COLLISION field values 340 *****************************************************************************/ 341 typedef enum { 342 ICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_ALLOW = 0x0, 343 /* When set to 0, hash collisions are allowed. */ 344 ICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_DONT_ALLOW = 0x1, 345 /* When set to 0, hash collisions are allowed. */ 346 } icp_qat_hw_comp_20_skip_hash_collision_t; 347 348 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_COLLISION_DEFAULT_VAL \ 349 ICP_QAT_HW_COMP_20_SKIP_HASH_COLLISION_ALLOW 350 351 /*****************************************************************************/ 352 /* Skip Hash Update (Set By FW to default value) , located in lower 32bit */ 353 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_BITPOS 2 354 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_MASK 0x1 355 /* 356 **************************************************************************** 357 * @ingroup icp_qat_hw_defs 358 * @description 359 * Enumeration of possible SKIP_HASH_UPDATE field values 360 *****************************************************************************/ 361 typedef enum { 362 ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_ALLOW = 0x0, 363 /* 0 - hash updates are not skipped. */ 364 ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_DONT_ALLOW = 0x1, 365 /* 1 - hash updates are skipped. */ 366 } icp_qat_hw_comp_20_skip_hash_update_t; 367 368 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_SKIP_HASH_UPDATE_DEFAULT_VAL \ 369 ICP_QAT_HW_COMP_20_SKIP_HASH_UPDATE_ALLOW 370 371 /*****************************************************************************/ 372 /* 3-Byte Match Skip (Set By FW to default value), located in lower 32bit */ 373 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_BITPOS 1 374 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_MASK 0x1 375 /* 376 **************************************************************************** 377 * @ingroup icp_qat_hw_defs 378 * @description 379 * Enumeration of possible BYTE_SKIP field values 380 *****************************************************************************/ 381 typedef enum { 382 ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_TOKEN = 0x0, 383 /* 0 - Use 3-byte token */ 384 ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_LITERAL = 0x1, 385 /* 0 - Use 3-byte literal */ 386 } icp_qat_hw_comp_20_byte_skip_t; 387 388 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_BYTE_SKIP_DEFAULT_VAL \ 389 ICP_QAT_HW_COMP_20_BYTE_SKIP_3BYTE_TOKEN 390 391 /*****************************************************************************/ 392 /* Extended Delayed Match Mode enabled (Set By the Driver), located in lower 393 * 32bit */ 394 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_BITPOS 0 395 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_MASK 0x1 396 /* 397 **************************************************************************** 398 * @ingroup icp_qat_hw_defs 399 * @description 400 * Enumeration of possible EXTENDED_DELAY_MATCH_MODE field values 401 *****************************************************************************/ 402 typedef enum { 403 ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_DISABLED = 0x0, 404 /* 0 - EXTENDED_DELAY_MATCH_MODE disabled */ 405 ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_ENABLED = 0x1, 406 /* 1 - EXTENDED_DELAY_MATCH_MODE enabled */ 407 } icp_qat_hw_comp_20_extended_delay_match_mode_t; 408 409 #define ICP_QAT_HW_COMP_20_CONFIG_CSR_EXTENDED_DELAY_MATCH_MODE_DEFAULT_VAL \ 410 ICP_QAT_HW_COMP_20_EXTENDED_DELAY_MATCH_MODE_EDMM_DISABLED 411 412 /*****************************************************************************/ 413 /* Speculative Decoder Disable (Set By the Driver/ Application), located in 414 * upper 32bit */ 415 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_BITPOS 31 416 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_MASK 0x1 417 /* 418 **************************************************************************** 419 * @ingroup icp_qat_hw_defs 420 * @description 421 * Enumeration of possible SPECULATIVE_DECODER_CONTROL field values 422 *****************************************************************************/ 423 typedef enum { 424 ICP_QAT_HW_DECOMP_20_SPECULATIVE_DECODER_CONTROL_ENABLE = 0x0, 425 /* 0b - Enabled */ 426 ICP_QAT_HW_DECOMP_20_SPECULATIVE_DECODER_CONTROL_DISABLE = 0x1, 427 /* 1b - Disabled */ 428 } icp_qat_hw_decomp_20_speculative_decoder_control_t; 429 430 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_SPECULATIVE_DECODER_CONTROL_DEFAULT_VAL \ 431 ICP_QAT_HW_DECOMP_20_SPECULATIVE_DECODER_CONTROL_ENABLE 432 433 /*****************************************************************************/ 434 /* Mini CAM Disable (Set By the Driver/ Application), located in upper 32bit */ 435 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_RESERVED4_CONTROL_BITPOS 30 436 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_RESERVED4_CONTROL_MASK 0x1 437 /* 438 **************************************************************************** 439 * @ingroup icp_qat_hw_defs 440 * @description 441 * Enumeration of possible RESERVED4 field values 442 *****************************************************************************/ 443 typedef enum { 444 ICP_QAT_HW_DECOMP_20_RESERVED4_CONTROL_ENABLE = 0x0, 445 /* 0b - Enabled */ 446 ICP_QAT_HW_DECOMP_20_RESERVED4_CONTROL_DISABLE = 0x1, 447 /* 1b - Disabled */ 448 } icp_qat_hw_decomp_20_reserved4_control_t; 449 450 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_RESERVED4_CONTROL_DEFAULT_VAL \ 451 ICP_QAT_HW_DECOMP_20_RESERVED4_CONTROL_ENABLE 452 453 /*****************************************************************************/ 454 /* History Buffer Size (Set By the Driver/ Application), located in lower 32bit 455 */ 456 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_BITPOS 14 457 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_MASK 0x7 458 /* 459 **************************************************************************** 460 * @ingroup icp_qat_hw_defs 461 * @description 462 * Enumeration of possible HBS_CONTROL field values 463 *****************************************************************************/ 464 typedef enum { 465 ICP_QAT_HW_DECOMP_20_HBS_CONTROL_HBS_IS_32KB = 0x0, 466 /* 000b - 32KB */ 467 } icp_qat_hw_decomp_20_hbs_control_t; 468 469 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HBS_CONTROL_DEFAULT_VAL \ 470 ICP_QAT_HW_DECOMP_20_HBS_CONTROL_HBS_IS_32KB 471 472 /*****************************************************************************/ 473 /* LZ4 Block Maximum Size (LBMS). Set by FW , located in lower 32bit */ 474 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_BITPOS 8 475 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_MASK 0x3 476 /* 477 **************************************************************************** 478 * @ingroup icp_qat_hw_defs 479 * @description 480 * Enumeration of possible LBMS field values 481 *****************************************************************************/ 482 typedef enum { 483 ICP_QAT_HW_DECOMP_20_LBMS_LBMS_64KB = 0x0, 484 /* LZ4 Block Maximum Size (LBMS) == 64 KB */ 485 ICP_QAT_HW_DECOMP_20_LBMS_LBMS_256KB = 0x1, 486 /* LZ4 Block Maximum Size (LBMS) == 256 KB */ 487 ICP_QAT_HW_DECOMP_20_LBMS_LBMS_1MB = 0x2, 488 /* LZ4 Block Maximum Size (LBMS) == 1 MB */ 489 ICP_QAT_HW_DECOMP_20_LBMS_LBMS_4MB = 0x3, 490 /* LZ4 Block Maximum Size (LBMS) == 4 MB */ 491 } icp_qat_hw_decomp_20_lbms_t; 492 493 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LBMS_DEFAULT_VAL \ 494 ICP_QAT_HW_DECOMP_20_LBMS_LBMS_64KB 495 496 /*****************************************************************************/ 497 /* Decompression Format (Set By Driver/Application. Also See CMD ID), located in 498 * lower 32bit */ 499 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_BITPOS 5 500 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_MASK 0x7 501 /* 502 **************************************************************************** 503 * @ingroup icp_qat_hw_defs 504 * @description 505 * Enumeration of possible HW_DECOMP_FORMAT field values 506 *****************************************************************************/ 507 typedef enum { 508 ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE = 0x1, 509 /* 001 - Static DEFLATE. (Must set Min_Match = 3 bytes and HB size = 510 * 32KB.) 511 */ 512 ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_LZ4 = 0x2, 513 /* 010 - LZ4. (Must set Min Match = 4 bytes and HB size = 32KB.) */ 514 ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_LZ4S = 0x3, 515 /* 011 - LZ4s. (Min_Match and HBSize must be set accordingly.) */ 516 } icp_qat_hw_decomp_20_hw_comp_format_t; 517 518 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_HW_DECOMP_FORMAT_DEFAULT_VAL \ 519 ICP_QAT_HW_DECOMP_20_HW_DECOMP_FORMAT_DEFLATE 520 521 /*****************************************************************************/ 522 /* Decompression Format (Set By Driver/Application. Also See CMD ID), located in 523 * lower 32bit */ 524 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_BITPOS 4 525 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_MASK 0x1 526 527 /* 528 **************************************************************************** 529 * @ingroup icp_qat_hw_defs 530 * @description 531 * Enumeration of possible MIN_MATCH_CONTROL field values 532 *****************************************************************************/ 533 typedef enum { 534 ICP_QAT_HW_DECOMP_20_MIN_MATCH_CONTROL_MATCH_3B = 0x0, 535 /* 0 - Match 3 B */ 536 ICP_QAT_HW_DECOMP_20_MIN_MATCH_CONTROL_MATCH_4B = 0x1, 537 /* 1 - Match 4 B */ 538 } icp_qat_hw_decomp_20_min_match_control_t; 539 540 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_MIN_MATCH_CONTROL_DEFAULT_VAL \ 541 ICP_QAT_HW_DECOMP_20_MIN_MATCH_CONTROL_MATCH_3B 542 543 /*****************************************************************************/ 544 /* LZ4 Block Checksum Present, located in lower 32bit */ 545 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_BITPOS 3 546 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_MASK 0x1 547 /* 548 **************************************************************************** 549 * @ingroup icp_qat_hw_defs 550 * @description 551 * Enumeration of possible LZ4_CHECKSUM_PRESENT field values 552 *****************************************************************************/ 553 typedef enum { 554 ICP_QAT_HW_DECOMP_20_LZ4_BLOCK_CHKSUM_ABSENT = 0x0, 555 /* the LZ4 Block does not contain the 4-byte checksum */ 556 ICP_QAT_HW_DECOMP_20_LZ4_BLOCK_CHKSUM_PRESENT = 0x1, 557 /* LZ4 Block contains a 4-byte checksum. */ 558 } icp_qat_hw_decomp_20_lz4_block_checksum_present_t; 559 560 #define ICP_QAT_HW_DECOMP_20_CONFIG_CSR_LZ4_BLOCK_CHECKSUM_PRESENT_DEFAULT_VAL \ 561 ICP_QAT_HW_DECOMP_20_LZ4_BLOCK_CHKSUM_ABSENT 562 563 #endif /* _ICP_QAT_HW_20_COMP_DEFS_H */ 564