1 /* $OpenBSD: ahc_pci.c,v 1.64 2024/05/24 06:02:53 jsg Exp $ */
2 /* $NetBSD: ahc_pci.c,v 1.43 2003/08/18 09:16:22 taca Exp $ */
3
4 /*
5 * Product specific probe and attach routines for:
6 * 3940, 2940, aic7895, aic7890, aic7880,
7 * aic7870, aic7860 and aic7850 SCSI controllers
8 *
9 * Copyright (c) 1994-2001 Justin T. Gibbs.
10 * Copyright (c) 2000-2001 Adaptec Inc.
11 * All rights reserved.
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions, and the following disclaimer,
18 * without modification.
19 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
20 * substantially similar to the "NO WARRANTY" disclaimer below
21 * ("Disclaimer") and any redistribution must be conditioned upon
22 * including a substantially similar Disclaimer requirement for further
23 * binary redistribution.
24 * 3. Neither the names of the above-listed copyright holders nor the names
25 * of any contributors may be used to endorse or promote products derived
26 * from this software without specific prior written permission.
27 *
28 * Alternatively, this software may be distributed under the terms of the
29 * GNU General Public License ("GPL") version 2 as published by the Free
30 * Software Foundation.
31 *
32 * NO WARRANTY
33 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
34 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
35 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
36 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
37 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
42 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
43 * POSSIBILITY OF SUCH DAMAGES.
44 *
45 * $Id: ahc_pci.c,v 1.64 2024/05/24 06:02:53 jsg Exp $
46 *
47 * //depot/aic7xxx/aic7xxx/aic7xxx_pci.c#57 $
48 *
49 * $FreeBSD: /repoman/r/ncvs/src/sys/dev/aic7xxx/aic7xxx_pci.c,v 1.22 2003/01/20 20:44:55 gibbs Exp $
50 */
51 /*
52 * Ported from FreeBSD by Pascal Renauld, Network Storage Solutions, Inc. - April 2003
53 */
54
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/malloc.h>
58 #include <sys/queue.h>
59 #include <sys/device.h>
60
61 #include <machine/bus.h>
62 #include <machine/intr.h>
63
64 #include <dev/pci/pcireg.h>
65 #include <dev/pci/pcivar.h>
66
67 #define AHC_PCI_IOADDR PCI_MAPREG_START /* I/O Address */
68 #define AHC_PCI_MEMADDR (PCI_MAPREG_START + 4) /* Mem I/O Address */
69
70 #include <dev/ic/aic7xxx_openbsd.h>
71 #include <dev/ic/aic7xxx_inline.h>
72
73 #ifndef __i386__
74 #define AHC_ALLOW_MEMIO
75 #endif
76
77 static __inline uint64_t
ahc_compose_id(u_int device,u_int vendor,u_int subdevice,u_int subvendor)78 ahc_compose_id(u_int device, u_int vendor, u_int subdevice, u_int subvendor)
79 {
80 uint64_t id;
81
82 id = subvendor
83 | (subdevice << 16)
84 | ((uint64_t)vendor << 32)
85 | ((uint64_t)device << 48);
86
87 return (id);
88 }
89
90 #define ID_ALL_MASK 0xFFFFFFFFFFFFFFFFull
91 #define ID_DEV_VENDOR_MASK 0xFFFFFFFF00000000ull
92 #define ID_9005_GENERIC_MASK 0xFFF0FFFF00000000ull
93 #define ID_9005_SISL_MASK 0x000FFFFF00000000ull
94 #define ID_9005_SISL_ID 0x0005900500000000ull
95 #define ID_AIC7850 0x5078900400000000ull
96 #define ID_AHA_2902_04_10_15_20_30C 0x5078900478509004ull
97 #define ID_AIC7855 0x5578900400000000ull
98 #define ID_AIC7859 0x3860900400000000ull
99 #define ID_AHA_2930CU 0x3860900438699004ull
100 #define ID_AIC7860 0x6078900400000000ull
101 #define ID_AIC7860C 0x6078900478609004ull
102 #define ID_AHA_1480A 0x6075900400000000ull
103 #define ID_AHA_2940AU_0 0x6178900400000000ull
104 #define ID_AHA_2940AU_1 0x6178900478619004ull
105 #define ID_AHA_2940AU_CN 0x2178900478219004ull
106 #define ID_AHA_2930C_VAR 0x6038900438689004ull
107
108 #define ID_AIC7870 0x7078900400000000ull
109 #define ID_AHA_2940 0x7178900400000000ull
110 #define ID_AHA_3940 0x7278900400000000ull
111 #define ID_AHA_398X 0x7378900400000000ull
112 #define ID_AHA_2944 0x7478900400000000ull
113 #define ID_AHA_3944 0x7578900400000000ull
114 #define ID_AHA_4944 0x7678900400000000ull
115
116 #define ID_AIC7880 0x8078900400000000ull
117 #define ID_AIC7880_B 0x8078900478809004ull
118 #define ID_AHA_2940U 0x8178900400000000ull
119 #define ID_AHA_3940U 0x8278900400000000ull
120 #define ID_AHA_2944U 0x8478900400000000ull
121 #define ID_AHA_3944U 0x8578900400000000ull
122 #define ID_AHA_398XU 0x8378900400000000ull
123 #define ID_AHA_4944U 0x8678900400000000ull
124 #define ID_AHA_2940UB 0x8178900478819004ull
125 #define ID_AHA_2930U 0x8878900478889004ull
126 #define ID_AHA_2940U_PRO 0x8778900478879004ull
127 #define ID_AHA_2940U_CN 0x0078900478009004ull
128
129 #define ID_AIC7895 0x7895900478959004ull
130 #define ID_AIC7895_ARO 0x7890900478939004ull
131 #define ID_AIC7895_ARO_MASK 0xFFF0FFFFFFFFFFFFull
132 #define ID_AHA_2940U_DUAL 0x7895900478919004ull
133 #define ID_AHA_3940AU 0x7895900478929004ull
134 #define ID_AHA_3944AU 0x7895900478949004ull
135
136 #define ID_AIC7890 0x001F9005000F9005ull
137 #define ID_AIC7890_ARO 0x00139005000F9005ull
138 #define ID_AAA_131U2 0x0013900500039005ull
139 #define ID_AHA_2930U2 0x0011900501819005ull
140 #define ID_AHA_2940U2B 0x00109005A1009005ull
141 #define ID_AHA_2940U2_OEM 0x0010900521809005ull
142 #define ID_AHA_2940U2 0x00109005A1809005ull
143 #define ID_AHA_2950U2B 0x00109005E1009005ull
144
145 #define ID_AIC7892 0x008F9005FFFF9005ull
146 #define ID_AIC7892_ARO 0x00839005FFFF9005ull
147 #define ID_AHA_2915LP 0x0082900502109005ull
148 #define ID_AHA_29160 0x00809005E2A09005ull
149 #define ID_AHA_29160_CPQ 0x00809005E2A00E11ull
150 #define ID_AHA_29160N 0x0080900562A09005ull
151 #define ID_AHA_29160C 0x0080900562209005ull
152 #define ID_AHA_29160B 0x00809005E2209005ull
153 #define ID_AHA_19160B 0x0081900562A19005ull
154
155 #define ID_AIC7896 0x005F9005FFFF9005ull
156 #define ID_AIC7896_ARO 0x00539005FFFF9005ull
157 #define ID_AHA_3950U2B_0 0x00509005FFFF9005ull
158 #define ID_AHA_3950U2B_1 0x00509005F5009005ull
159 #define ID_AHA_3950U2D_0 0x00519005FFFF9005ull
160 #define ID_AHA_3950U2D_1 0x00519005B5009005ull
161
162 #define ID_AIC7899 0x00CF9005FFFF9005ull
163 #define ID_AIC7899_ARO 0x00C39005FFFF9005ull
164 #define ID_AHA_3960D 0x00C09005F6209005ull
165 #define ID_AHA_3960D_CPQ 0x00C09005F6200E11ull
166
167 #define ID_AIC7810 0x1078900400000000ull
168 #define ID_AIC7815 0x7815900400000000ull
169
170 #define DEVID_9005_TYPE(id) ((id) & 0xF)
171 #define DEVID_9005_TYPE_HBA 0x0 /* Standard Card */
172 #define DEVID_9005_TYPE_AAA 0x3 /* RAID Card */
173 #define DEVID_9005_TYPE_SISL 0x5 /* Container ROMB */
174 #define DEVID_9005_TYPE_MB 0xF /* On Motherboard */
175
176 #define DEVID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
177 #define DEVID_9005_MAXRATE_U160 0x0
178 #define DEVID_9005_MAXRATE_ULTRA2 0x1
179 #define DEVID_9005_MAXRATE_ULTRA 0x2
180 #define DEVID_9005_MAXRATE_FAST 0x3
181
182 #define DEVID_9005_MFUNC(id) (((id) & 0x40) >> 6)
183
184 #define DEVID_9005_CLASS(id) (((id) & 0xFF00) >> 8)
185 #define DEVID_9005_CLASS_SPI 0x0 /* Parallel SCSI */
186
187 #define SUBID_9005_TYPE(id) ((id) & 0xF)
188 #define SUBID_9005_TYPE_MB 0xF /* On Motherboard */
189 #define SUBID_9005_TYPE_CARD 0x0 /* Standard Card */
190 #define SUBID_9005_TYPE_LCCARD 0x1 /* Low Cost Card */
191 #define SUBID_9005_TYPE_RAID 0x3 /* Combined with Raid */
192
193 #define SUBID_9005_TYPE_KNOWN(id) \
194 ((((id) & 0xF) == SUBID_9005_TYPE_MB) \
195 || (((id) & 0xF) == SUBID_9005_TYPE_CARD) \
196 || (((id) & 0xF) == SUBID_9005_TYPE_LCCARD) \
197 || (((id) & 0xF) == SUBID_9005_TYPE_RAID))
198
199 #define SUBID_9005_MAXRATE(id) (((id) & 0x30) >> 4)
200 #define SUBID_9005_MAXRATE_ULTRA2 0x0
201 #define SUBID_9005_MAXRATE_ULTRA 0x1
202 #define SUBID_9005_MAXRATE_U160 0x2
203 #define SUBID_9005_MAXRATE_RESERVED 0x3
204
205 #define SUBID_9005_SEEPTYPE(id) \
206 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
207 ? ((id) & 0xC0) >> 6 \
208 : ((id) & 0x300) >> 8)
209 #define SUBID_9005_SEEPTYPE_NONE 0x0
210 #define SUBID_9005_SEEPTYPE_1K 0x1
211 #define SUBID_9005_SEEPTYPE_2K_4K 0x2
212 #define SUBID_9005_SEEPTYPE_RESERVED 0x3
213 #define SUBID_9005_AUTOTERM(id) \
214 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
215 ? (((id) & 0x400) >> 10) == 0 \
216 : (((id) & 0x40) >> 6) == 0)
217
218 #define SUBID_9005_NUMCHAN(id) \
219 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
220 ? ((id) & 0x300) >> 8 \
221 : ((id) & 0xC00) >> 10)
222
223 #define SUBID_9005_LEGACYCONN(id) \
224 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
225 ? 0 \
226 : ((id) & 0x80) >> 7)
227
228 #define SUBID_9005_MFUNCENB(id) \
229 ((SUBID_9005_TYPE(id) == SUBID_9005_TYPE_MB) \
230 ? ((id) & 0x800) >> 11 \
231 : ((id) & 0x1000) >> 12)
232 /*
233 * Informational only. Should use chip register to be
234 * certain, but may be use in identification strings.
235 */
236 #define SUBID_9005_CARD_SCSIWIDTH_MASK 0x2000
237 #define SUBID_9005_CARD_PCIWIDTH_MASK 0x4000
238 #define SUBID_9005_CARD_SEDIFF_MASK 0x8000
239
240 static ahc_device_setup_t ahc_aic785X_setup;
241 static ahc_device_setup_t ahc_aic7860_setup;
242 static ahc_device_setup_t ahc_apa1480_setup;
243 static ahc_device_setup_t ahc_aic7870_setup;
244 static ahc_device_setup_t ahc_aha394X_setup;
245 static ahc_device_setup_t ahc_aha494X_setup;
246 static ahc_device_setup_t ahc_aha398X_setup;
247 static ahc_device_setup_t ahc_aic7880_setup;
248 static ahc_device_setup_t ahc_aha2940Pro_setup;
249 static ahc_device_setup_t ahc_aha394XU_setup;
250 static ahc_device_setup_t ahc_aha398XU_setup;
251 static ahc_device_setup_t ahc_aic7890_setup;
252 static ahc_device_setup_t ahc_aic7892_setup;
253 static ahc_device_setup_t ahc_aic7895_setup;
254 static ahc_device_setup_t ahc_aic7896_setup;
255 static ahc_device_setup_t ahc_aic7899_setup;
256 static ahc_device_setup_t ahc_aha29160C_setup;
257 static ahc_device_setup_t ahc_raid_setup;
258 static ahc_device_setup_t ahc_aha394XX_setup;
259 static ahc_device_setup_t ahc_aha494XX_setup;
260 static ahc_device_setup_t ahc_aha398XX_setup;
261
262 const struct ahc_pci_identity ahc_pci_ident_table [] =
263 {
264 /* aic7850 based controllers */
265 {
266 ID_AHA_2902_04_10_15_20_30C,
267 ID_ALL_MASK,
268 ahc_aic785X_setup
269 },
270 /* aic7860 based controllers */
271 {
272 ID_AHA_2930CU,
273 ID_ALL_MASK,
274 ahc_aic7860_setup
275 },
276 {
277 ID_AHA_1480A & ID_DEV_VENDOR_MASK,
278 ID_DEV_VENDOR_MASK,
279 ahc_apa1480_setup
280 },
281 {
282 ID_AHA_2940AU_0 & ID_DEV_VENDOR_MASK,
283 ID_DEV_VENDOR_MASK,
284 ahc_aic7860_setup
285 },
286 {
287 ID_AHA_2940AU_CN & ID_DEV_VENDOR_MASK,
288 ID_DEV_VENDOR_MASK,
289 ahc_aic7860_setup
290 },
291 {
292 ID_AHA_2930C_VAR & ID_DEV_VENDOR_MASK,
293 ID_DEV_VENDOR_MASK,
294 ahc_aic7860_setup
295 },
296 /* aic7870 based controllers */
297 {
298 ID_AHA_2940,
299 ID_ALL_MASK,
300 ahc_aic7870_setup
301 },
302 {
303 ID_AHA_3940,
304 ID_ALL_MASK,
305 ahc_aha394X_setup
306 },
307 {
308 ID_AHA_398X,
309 ID_ALL_MASK,
310 ahc_aha398X_setup
311 },
312 {
313 ID_AHA_2944,
314 ID_ALL_MASK,
315 ahc_aic7870_setup
316 },
317 {
318 ID_AHA_3944,
319 ID_ALL_MASK,
320 ahc_aha394X_setup
321 },
322 {
323 ID_AHA_4944,
324 ID_ALL_MASK,
325 ahc_aha494X_setup
326 },
327 /* aic7880 based controllers */
328 {
329 ID_AHA_2940U & ID_DEV_VENDOR_MASK,
330 ID_DEV_VENDOR_MASK,
331 ahc_aic7880_setup
332 },
333 {
334 ID_AHA_3940U & ID_DEV_VENDOR_MASK,
335 ID_DEV_VENDOR_MASK,
336 ahc_aha394XU_setup
337 },
338 {
339 ID_AHA_2944U & ID_DEV_VENDOR_MASK,
340 ID_DEV_VENDOR_MASK,
341 ahc_aic7880_setup
342 },
343 {
344 ID_AHA_3944U & ID_DEV_VENDOR_MASK,
345 ID_DEV_VENDOR_MASK,
346 ahc_aha394XU_setup
347 },
348 {
349 ID_AHA_398XU & ID_DEV_VENDOR_MASK,
350 ID_DEV_VENDOR_MASK,
351 ahc_aha398XU_setup
352 },
353 {
354 /*
355 * XXX Don't know the slot numbers
356 * so we can't identify channels
357 */
358 ID_AHA_4944U & ID_DEV_VENDOR_MASK,
359 ID_DEV_VENDOR_MASK,
360 ahc_aic7880_setup
361 },
362 {
363 ID_AHA_2930U & ID_DEV_VENDOR_MASK,
364 ID_DEV_VENDOR_MASK,
365 ahc_aic7880_setup
366 },
367 {
368 ID_AHA_2940U_PRO & ID_DEV_VENDOR_MASK,
369 ID_DEV_VENDOR_MASK,
370 ahc_aha2940Pro_setup
371 },
372 {
373 ID_AHA_2940U_CN & ID_DEV_VENDOR_MASK,
374 ID_DEV_VENDOR_MASK,
375 ahc_aic7880_setup
376 },
377 /* Ignore all SISL (AAC on MB) based controllers. */
378 {
379 ID_9005_SISL_ID,
380 ID_9005_SISL_MASK,
381 NULL
382 },
383 /* aic7890 based controllers */
384 {
385 ID_AHA_2930U2,
386 ID_ALL_MASK,
387 ahc_aic7890_setup
388 },
389 {
390 ID_AHA_2940U2B,
391 ID_ALL_MASK,
392 ahc_aic7890_setup
393 },
394 {
395 ID_AHA_2940U2_OEM,
396 ID_ALL_MASK,
397 ahc_aic7890_setup
398 },
399 {
400 ID_AHA_2940U2,
401 ID_ALL_MASK,
402 ahc_aic7890_setup
403 },
404 {
405 ID_AHA_2950U2B,
406 ID_ALL_MASK,
407 ahc_aic7890_setup
408 },
409 {
410 ID_AIC7890_ARO,
411 ID_ALL_MASK,
412 ahc_aic7890_setup
413 },
414 {
415 ID_AAA_131U2,
416 ID_ALL_MASK,
417 ahc_aic7890_setup
418 },
419 /* aic7892 based controllers */
420 {
421 ID_AHA_29160,
422 ID_ALL_MASK,
423 ahc_aic7892_setup
424 },
425 {
426 ID_AHA_29160_CPQ,
427 ID_ALL_MASK,
428 ahc_aic7892_setup
429 },
430 {
431 ID_AHA_29160N,
432 ID_ALL_MASK,
433 ahc_aic7892_setup
434 },
435 {
436 ID_AHA_29160C,
437 ID_ALL_MASK,
438 ahc_aha29160C_setup
439 },
440 {
441 ID_AHA_29160B,
442 ID_ALL_MASK,
443 ahc_aic7892_setup
444 },
445 {
446 ID_AHA_19160B,
447 ID_ALL_MASK,
448 ahc_aic7892_setup
449 },
450 {
451 ID_AIC7892_ARO,
452 ID_ALL_MASK,
453 ahc_aic7892_setup
454 },
455 {
456 ID_AHA_2915LP,
457 ID_ALL_MASK,
458 ahc_aic7892_setup
459 },
460 /* aic7895 based controllers */
461 {
462 ID_AHA_2940U_DUAL,
463 ID_ALL_MASK,
464 ahc_aic7895_setup
465 },
466 {
467 ID_AHA_3940AU,
468 ID_ALL_MASK,
469 ahc_aic7895_setup
470 },
471 {
472 ID_AHA_3944AU,
473 ID_ALL_MASK,
474 ahc_aic7895_setup
475 },
476 {
477 ID_AIC7895_ARO,
478 ID_AIC7895_ARO_MASK,
479 ahc_aic7895_setup
480 },
481 /* aic7896/97 based controllers */
482 {
483 ID_AHA_3950U2B_0,
484 ID_ALL_MASK,
485 ahc_aic7896_setup
486 },
487 {
488 ID_AHA_3950U2B_1,
489 ID_ALL_MASK,
490 ahc_aic7896_setup
491 },
492 {
493 ID_AHA_3950U2D_0,
494 ID_ALL_MASK,
495 ahc_aic7896_setup
496 },
497 {
498 ID_AHA_3950U2D_1,
499 ID_ALL_MASK,
500 ahc_aic7896_setup
501 },
502 {
503 ID_AIC7896_ARO,
504 ID_ALL_MASK,
505 ahc_aic7896_setup
506 },
507 /* aic7899 based controllers */
508 {
509 ID_AHA_3960D,
510 ID_ALL_MASK,
511 ahc_aic7899_setup
512 },
513 {
514 ID_AHA_3960D_CPQ,
515 ID_ALL_MASK,
516 ahc_aic7899_setup
517 },
518 {
519 ID_AIC7899_ARO,
520 ID_ALL_MASK,
521 ahc_aic7899_setup
522 },
523 /* Generic chip probes for devices we don't know 'exactly' */
524 {
525 ID_AIC7850 & ID_DEV_VENDOR_MASK,
526 ID_DEV_VENDOR_MASK,
527 ahc_aic785X_setup
528 },
529 {
530 ID_AIC7855 & ID_DEV_VENDOR_MASK,
531 ID_DEV_VENDOR_MASK,
532 ahc_aic785X_setup
533 },
534 {
535 ID_AIC7859 & ID_DEV_VENDOR_MASK,
536 ID_DEV_VENDOR_MASK,
537 ahc_aic7860_setup
538 },
539 {
540 ID_AIC7860 & ID_DEV_VENDOR_MASK,
541 ID_DEV_VENDOR_MASK,
542 ahc_aic7860_setup
543 },
544 {
545 ID_AIC7870 & ID_DEV_VENDOR_MASK,
546 ID_DEV_VENDOR_MASK,
547 ahc_aic7870_setup
548 },
549 {
550 ID_AIC7880 & ID_DEV_VENDOR_MASK,
551 ID_DEV_VENDOR_MASK,
552 ahc_aic7880_setup
553 },
554 {
555 ID_AIC7890 & ID_9005_GENERIC_MASK,
556 ID_9005_GENERIC_MASK,
557 ahc_aic7890_setup
558 },
559 {
560 ID_AIC7892 & ID_9005_GENERIC_MASK,
561 ID_9005_GENERIC_MASK,
562 ahc_aic7892_setup
563 },
564 {
565 ID_AIC7895 & ID_DEV_VENDOR_MASK,
566 ID_DEV_VENDOR_MASK,
567 ahc_aic7895_setup
568 },
569 {
570 ID_AIC7896 & ID_9005_GENERIC_MASK,
571 ID_9005_GENERIC_MASK,
572 ahc_aic7896_setup
573 },
574 {
575 ID_AIC7899 & ID_9005_GENERIC_MASK,
576 ID_9005_GENERIC_MASK,
577 ahc_aic7899_setup
578 },
579 {
580 ID_AIC7810 & ID_DEV_VENDOR_MASK,
581 ID_DEV_VENDOR_MASK,
582 ahc_raid_setup
583 },
584 {
585 ID_AIC7815 & ID_DEV_VENDOR_MASK,
586 ID_DEV_VENDOR_MASK,
587 ahc_raid_setup
588 }
589 };
590
591 #define AHC_394X_SLOT_CHANNEL_A 4
592 #define AHC_394X_SLOT_CHANNEL_B 5
593
594 #define AHC_398X_SLOT_CHANNEL_A 4
595 #define AHC_398X_SLOT_CHANNEL_B 8
596 #define AHC_398X_SLOT_CHANNEL_C 12
597
598 #define AHC_494X_SLOT_CHANNEL_A 4
599 #define AHC_494X_SLOT_CHANNEL_B 5
600 #define AHC_494X_SLOT_CHANNEL_C 6
601 #define AHC_494X_SLOT_CHANNEL_D 7
602
603 #define DEVCONFIG 0x40
604 #define PCIERRGENDIS 0x80000000ul
605 #define SCBSIZE32 0x00010000ul /* aic789X only */
606 #define REXTVALID 0x00001000ul /* ultra cards only */
607 #define MPORTMODE 0x00000400ul /* aic7870+ only */
608 #define RAMPSM 0x00000200ul /* aic7870+ only */
609 #define VOLSENSE 0x00000100ul
610 #define PCI64BIT 0x00000080ul /* 64Bit PCI bus (Ultra2 Only)*/
611 #define SCBRAMSEL 0x00000080ul
612 #define MRDCEN 0x00000040ul
613 #define EXTSCBTIME 0x00000020ul /* aic7870 only */
614 #define EXTSCBPEN 0x00000010ul /* aic7870 only */
615 #define BERREN 0x00000008ul
616 #define DACEN 0x00000004ul
617 #define STPWLEVEL 0x00000002ul
618 #define DIFACTNEGEN 0x00000001ul /* aic7870 only */
619
620 #define CSIZE_LATTIME 0x0c
621 #define CACHESIZE 0x0000003ful /* only 5 bits */
622 #define LATTIME 0x0000ff00ul
623
624 /* PCI STATUS definitions */
625 #define DPE 0x80
626 #define SSE 0x40
627 #define RMA 0x20
628 #define RTA 0x10
629 #define STA 0x08
630 #define DPR 0x01
631
632 static int ahc_9005_subdevinfo_valid(uint16_t vendor, uint16_t device,
633 uint16_t subvendor, uint16_t subdevice);
634 static int ahc_ext_scbram_present(struct ahc_softc *ahc);
635 static void ahc_scbram_config(struct ahc_softc *ahc, int enable,
636 int pcheck, int fast, int large);
637 static void ahc_probe_ext_scbram(struct ahc_softc *ahc);
638 static int ahc_pci_chip_init(struct ahc_softc *ahc);
639
640 int ahc_pci_probe(struct device *, void *, void *);
641 void ahc_pci_attach(struct device *, struct device *, void *);
642
643
644 const struct cfattach ahc_pci_ca = {
645 sizeof(struct ahc_softc), ahc_pci_probe, ahc_pci_attach
646 };
647
648 const struct ahc_pci_identity *
ahc_find_pci_device(pcireg_t id,pcireg_t subid,u_int func)649 ahc_find_pci_device(pcireg_t id, pcireg_t subid, u_int func)
650 {
651 u_int64_t full_id;
652 const struct ahc_pci_identity *entry;
653 u_int i;
654
655 full_id = ahc_compose_id(PCI_PRODUCT(id), PCI_VENDOR(id),
656 PCI_PRODUCT(subid), PCI_VENDOR(subid));
657
658 /*
659 * If the second function is not hooked up, ignore it.
660 * Unfortunately, not all MB vendors implement the
661 * subdevice ID as per the Adaptec spec, so do our best
662 * to sanity check it prior to accepting the subdevice
663 * ID as valid.
664 */
665 if (func > 0
666 && ahc_9005_subdevinfo_valid(PCI_VENDOR(id), PCI_PRODUCT(id),
667 PCI_VENDOR(subid), PCI_PRODUCT(subid))
668 && SUBID_9005_MFUNCENB(PCI_PRODUCT(subid)) == 0)
669 return (NULL);
670
671 for (i = 0; i < NUM_ELEMENTS(ahc_pci_ident_table); i++) {
672 entry = &ahc_pci_ident_table[i];
673 if (entry->full_id == (full_id & entry->id_mask))
674 return (entry);
675 }
676 return (NULL);
677 }
678
679 int
ahc_pci_probe(struct device * parent,void * match,void * aux)680 ahc_pci_probe(struct device *parent, void *match, void *aux)
681 {
682 struct pci_attach_args *pa = aux;
683 const struct ahc_pci_identity *entry;
684 pcireg_t subid;
685
686 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
687 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function);
688 return (entry != NULL && entry->setup != NULL) ? 1 : 0;
689 }
690
691 void
ahc_pci_attach(struct device * parent,struct device * self,void * aux)692 ahc_pci_attach(struct device *parent, struct device *self, void *aux)
693 {
694 struct pci_attach_args *pa = aux;
695 const struct ahc_pci_identity *entry;
696 struct ahc_softc *ahc = (void *)self;
697 pcireg_t command;
698 u_int our_id = 0;
699 u_int sxfrctl1;
700 u_int scsiseq;
701 u_int sblkctl;
702 uint8_t dscommand0;
703 uint32_t devconfig;
704 int error;
705 pcireg_t subid;
706 int ioh_valid;
707 bus_space_tag_t st, iot;
708 bus_space_handle_t sh, ioh;
709 #ifdef AHC_ALLOW_MEMIO
710 int memh_valid;
711 bus_space_tag_t memt;
712 bus_space_handle_t memh;
713 pcireg_t memtype;
714 #endif
715 pci_intr_handle_t ih;
716 const char *intrstr;
717 struct ahc_pci_busdata *bd;
718 int i;
719
720 /*
721 * Instead of ahc_alloc() as in FreeBSD, do the few relevant
722 * initializations manually.
723 */
724 LIST_INIT(&ahc->pending_scbs);
725 ahc->channel = 'A';
726 ahc->seqctl = FASTMODE;
727 for (i = 0; i < AHC_NUM_TARGETS; i++)
728 TAILQ_INIT(&ahc->untagged_queues[i]);
729
730 /*
731 * SCSI_IS_SCSIBUS_B() must returns false until sc_channel_b
732 * has been properly initialized.
733 */
734 ahc->sc_child_b = NULL;
735
736 ahc->dev_softc = pa;
737
738 ahc_set_name(ahc, ahc->sc_dev.dv_xname);
739 ahc->parent_dmat = pa->pa_dmat;
740
741 subid = pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_SUBSYS_ID_REG);
742 entry = ahc_find_pci_device(pa->pa_id, subid, pa->pa_function);
743 if (entry == NULL)
744 return;
745
746 /* Keep information about the PCI bus */
747 bd = malloc(sizeof (struct ahc_pci_busdata), M_DEVBUF,
748 M_NOWAIT | M_ZERO);
749 if (bd == NULL) {
750 printf("%s: unable to allocate bus-specific data\n",
751 ahc_name(ahc));
752 return;
753 }
754
755 bd->pc = pa->pa_pc;
756 bd->tag = pa->pa_tag;
757 bd->func = pa->pa_function;
758 bd->dev = pa->pa_device;
759 bd->class = pa->pa_class;
760
761 ahc->bd = bd;
762
763 error = entry->setup(ahc);
764 if (error != 0)
765 return;
766
767 ioh_valid = 0;
768
769 #ifdef AHC_ALLOW_MEMIO
770 memh_valid = 0;
771 memtype = pci_mapreg_type(pa->pa_pc, pa->pa_tag, AHC_PCI_MEMADDR);
772 switch (memtype) {
773 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_32BIT:
774 case PCI_MAPREG_TYPE_MEM | PCI_MAPREG_MEM_TYPE_64BIT:
775 memh_valid = (pci_mapreg_map(pa, AHC_PCI_MEMADDR,
776 memtype, 0, &memt, &memh, NULL, NULL, 0) == 0);
777 break;
778 default:
779 memh_valid = 0;
780 }
781 if (memh_valid == 0)
782 #endif
783 ioh_valid = (pci_mapreg_map(pa, AHC_PCI_IOADDR,
784 PCI_MAPREG_TYPE_IO, 0, &iot, &ioh, NULL, NULL, 0) == 0);
785 #if 0
786 printf("%s: mem mapping: memt 0x%lx, memh 0x%lx, iot 0x%lx, ioh 0x%lx\n",
787 ahc_name(ahc), (u_long)memt, memh, (u_long)iot, ioh);
788 #endif
789
790 if (ioh_valid) {
791 st = iot;
792 sh = ioh;
793 #ifdef AHC_ALLOW_MEMIO
794 } else if (memh_valid) {
795 st = memt;
796 sh = memh;
797 #endif
798 } else {
799 printf(": unable to map registers\n");
800 return;
801 }
802 ahc->tag = st;
803 ahc->bsh = sh;
804
805 ahc->chip |= AHC_PCI;
806 /*
807 * Before we continue probing the card, ensure that
808 * its interrupts are *disabled*. We don't want
809 * a misstep to hang the machine in an interrupt
810 * storm.
811 */
812 ahc_intr_enable(ahc, FALSE);
813
814 /*
815 * XXX somehow reading this once fails on some sparc64 systems.
816 * This may be a problem in the sparc64 PCI code. Doing it
817 * twice works around it.
818 */
819 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
820 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
821
822 /*
823 * If we need to support high memory, enable dual
824 * address cycles. This bit must be set to enable
825 * high address bit generation even if we are on a
826 * 64bit bus (PCI64BIT set in devconfig).
827 */
828 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
829
830 if (1/*bootverbose*/)
831 printf("%s: Enabling 39Bit Addressing\n",
832 ahc_name(ahc));
833 devconfig |= DACEN;
834 }
835
836 /* Ensure that pci error generation, a test feature, is disabled. */
837 devconfig |= PCIERRGENDIS;
838
839 pci_conf_write(pa->pa_pc, pa->pa_tag, DEVCONFIG, devconfig);
840
841 /*
842 * Disable PCI parity error reporting. Users typically
843 * do this to work around broken PCI chipsets that get
844 * the parity timing wrong and thus generate lots of spurious
845 * errors.
846 */
847 if ((ahc->flags & AHC_DISABLE_PCI_PERR) != 0) {
848 command = pci_conf_read(pa->pa_pc, pa->pa_tag,
849 PCI_COMMAND_STATUS_REG);
850 pci_conf_write(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG,
851 command & ~PCI_COMMAND_PARITY_ENABLE);
852 }
853
854 /* On all PCI adapters, we allow SCB paging */
855 ahc->flags |= AHC_PAGESCBS;
856 error = ahc_softc_init(ahc);
857 if (error != 0)
858 goto error_out;
859
860 ahc->bus_intr = ahc_pci_intr;
861 ahc->bus_chip_init = ahc_pci_chip_init;
862
863 /* Remember how the card was setup in case there is no SEEPROM */
864 if ((ahc_inb(ahc, HCNTRL) & POWRDN) == 0) {
865 ahc_pause(ahc);
866 if ((ahc->features & AHC_ULTRA2) != 0)
867 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
868 else
869 our_id = ahc_inb(ahc, SCSIID) & OID;
870 sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
871 scsiseq = ahc_inb(ahc, SCSISEQ);
872 } else {
873 sxfrctl1 = STPWEN;
874 our_id = 7;
875 scsiseq = 0;
876 }
877
878 error = ahc_reset(ahc, /*reinit*/FALSE);
879 if (error != 0)
880 goto error_out;
881
882 if ((ahc->features & AHC_DT) != 0) {
883 u_int sfunct;
884
885 /* Perform ALT-Mode Setup */
886 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
887 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
888 ahc_outb(ahc, OPTIONMODE,
889 OPTIONMODE_DEFAULTS|AUTOACKEN|BUSFREEREV|EXPPHASEDIS);
890 ahc_outb(ahc, SFUNCT, sfunct);
891
892 /* Normal mode setup */
893 ahc_outb(ahc, CRCCONTROL1, CRCVALCHKEN|CRCENDCHKEN|CRCREQCHKEN
894 |TARGCRCENDEN);
895 }
896
897 if (pci_intr_map(pa, &ih)) {
898 printf("%s: couldn't map interrupt\n", ahc_name(ahc));
899 ahc_free(ahc);
900 return;
901 }
902 intrstr = pci_intr_string(pa->pa_pc, ih);
903 ahc->ih = pci_intr_establish(pa->pa_pc, ih, IPL_BIO,
904 ahc_platform_intr, ahc, ahc->sc_dev.dv_xname);
905 if (ahc->ih == NULL) {
906 printf(": couldn't establish interrupt");
907 if (intrstr != NULL)
908 printf(" at %s", intrstr);
909 printf("\n");
910 ahc_free(ahc);
911 return;
912 } else
913 printf(": %s\n", intrstr ? intrstr : "?");
914
915 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
916 dscommand0 |= MPARCKEN|CACHETHEN;
917 if ((ahc->features & AHC_ULTRA2) != 0) {
918
919 /*
920 * DPARCKEN doesn't work correctly on
921 * some MBs so don't use it.
922 */
923 dscommand0 &= ~DPARCKEN;
924 }
925
926 /*
927 * Handle chips that must have cache line
928 * streaming (dis/en)abled.
929 */
930 if ((ahc->bugs & AHC_CACHETHEN_DIS_BUG) != 0)
931 dscommand0 |= CACHETHEN;
932
933 if ((ahc->bugs & AHC_CACHETHEN_BUG) != 0)
934 dscommand0 &= ~CACHETHEN;
935
936 ahc_outb(ahc, DSCOMMAND0, dscommand0);
937
938 ahc->pci_cachesize =
939 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME) & CACHESIZE;
940 ahc->pci_cachesize *= 4;
941
942 if ((ahc->bugs & AHC_PCI_2_1_RETRY_BUG) != 0
943 && ahc->pci_cachesize == 4) {
944 pci_conf_write(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME, 0);
945 ahc->pci_cachesize = 0;
946 }
947
948 /*
949 * We cannot perform ULTRA speeds without the presence
950 * of the external precision resistor.
951 */
952 if ((ahc->features & AHC_ULTRA) != 0) {
953 uint32_t devconfig;
954
955 devconfig = pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
956 if ((devconfig & REXTVALID) == 0)
957 ahc->features &= ~AHC_ULTRA;
958 }
959
960 ahc->seep_config = malloc(sizeof(*ahc->seep_config), M_DEVBUF,
961 M_NOWAIT | M_ZERO);
962 if (ahc->seep_config == NULL)
963 goto error_out;
964
965 /* See if we have a SEEPROM and perform auto-term */
966 ahc_check_extport(ahc, &sxfrctl1);
967
968 /*
969 * Take the LED out of diagnostic mode
970 */
971 sblkctl = ahc_inb(ahc, SBLKCTL);
972 ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
973
974 if ((ahc->features & AHC_ULTRA2) != 0) {
975 ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_MAX|WR_DFTHRSH_MAX);
976 } else {
977 ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
978 }
979
980 if (ahc->flags & AHC_USEDEFAULTS) {
981 /*
982 * PCI Adapter default setup
983 * Should only be used if the adapter does not have
984 * a SEEPROM.
985 */
986 /* See if someone else set us up already */
987 if ((ahc->flags & AHC_NO_BIOS_INIT) == 0
988 && scsiseq != 0) {
989 printf("%s: Using left over BIOS settings\n",
990 ahc_name(ahc));
991 ahc->flags &= ~AHC_USEDEFAULTS;
992 ahc->flags |= AHC_BIOS_ENABLED;
993 } else {
994 /*
995 * Assume only one connector and always turn
996 * on termination.
997 */
998 our_id = 0x07;
999 sxfrctl1 = STPWEN;
1000 }
1001 ahc_outb(ahc, SCSICONF, our_id|ENSPCHK|RESET_SCSI);
1002
1003 ahc->our_id = our_id;
1004 }
1005
1006 /*
1007 * Take a look to see if we have external SRAM.
1008 * We currently do not attempt to use SRAM that is
1009 * shared among multiple controllers.
1010 */
1011 ahc_probe_ext_scbram(ahc);
1012
1013 /*
1014 * Record our termination setting for the
1015 * generic initialization routine.
1016 */
1017 if ((sxfrctl1 & STPWEN) != 0)
1018 ahc->flags |= AHC_TERM_ENB_A;
1019
1020 /*
1021 * Save chip register configuration data for chip resets
1022 * that occur during runtime and resume events.
1023 */
1024 ahc->bus_softc.pci_softc.devconfig =
1025 pci_conf_read(pa->pa_pc, pa->pa_tag, DEVCONFIG);
1026 ahc->bus_softc.pci_softc.command =
1027 pci_conf_read(pa->pa_pc, pa->pa_tag, PCI_COMMAND_STATUS_REG);
1028 ahc->bus_softc.pci_softc.csize_lattime =
1029 pci_conf_read(pa->pa_pc, pa->pa_tag, CSIZE_LATTIME);
1030 ahc->bus_softc.pci_softc.dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1031 ahc->bus_softc.pci_softc.dspcistatus = ahc_inb(ahc, DSPCISTATUS);
1032 if ((ahc->features & AHC_DT) != 0) {
1033 u_int sfunct;
1034
1035 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1036 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1037 ahc->bus_softc.pci_softc.optionmode = ahc_inb(ahc, OPTIONMODE);
1038 ahc->bus_softc.pci_softc.targcrccnt = ahc_inw(ahc, TARGCRCCNT);
1039 ahc_outb(ahc, SFUNCT, sfunct);
1040 ahc->bus_softc.pci_softc.crccontrol1 =
1041 ahc_inb(ahc, CRCCONTROL1);
1042 }
1043 if ((ahc->features & AHC_MULTI_FUNC) != 0)
1044 ahc->bus_softc.pci_softc.scbbaddr = ahc_inb(ahc, SCBBADDR);
1045
1046 if ((ahc->features & AHC_ULTRA2) != 0)
1047 ahc->bus_softc.pci_softc.dff_thrsh = ahc_inb(ahc, DFF_THRSH);
1048
1049 /* Core initialization */
1050 if (ahc_init(ahc))
1051 goto error_out;
1052
1053 ahc_attach(ahc);
1054
1055 return;
1056
1057 error_out:
1058 ahc_free(ahc);
1059 return;
1060 }
1061
1062 static int
ahc_9005_subdevinfo_valid(uint16_t device,uint16_t vendor,uint16_t subdevice,uint16_t subvendor)1063 ahc_9005_subdevinfo_valid(uint16_t device, uint16_t vendor,
1064 uint16_t subdevice, uint16_t subvendor)
1065 {
1066 int result;
1067
1068 /* Default to invalid. */
1069 result = 0;
1070 if (vendor == 0x9005
1071 && subvendor == 0x9005
1072 && subdevice != device
1073 && SUBID_9005_TYPE_KNOWN(subdevice) != 0) {
1074
1075 switch (SUBID_9005_TYPE(subdevice)) {
1076 case SUBID_9005_TYPE_MB:
1077 break;
1078 case SUBID_9005_TYPE_CARD:
1079 case SUBID_9005_TYPE_LCCARD:
1080 /*
1081 * Currently only trust Adaptec cards to
1082 * get the sub device info correct.
1083 */
1084 if (DEVID_9005_TYPE(device) == DEVID_9005_TYPE_HBA)
1085 result = 1;
1086 break;
1087 case SUBID_9005_TYPE_RAID:
1088 break;
1089 default:
1090 break;
1091 }
1092 }
1093 return (result);
1094 }
1095
1096
1097 /*
1098 * Test for the presence of external sram in an
1099 * "unshared" configuration.
1100 */
1101 static int
ahc_ext_scbram_present(struct ahc_softc * ahc)1102 ahc_ext_scbram_present(struct ahc_softc *ahc)
1103 {
1104 u_int chip;
1105 int ramps;
1106 int single_user;
1107 uint32_t devconfig;
1108
1109 chip = ahc->chip & AHC_CHIPID_MASK;
1110 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG);
1111 single_user = (devconfig & MPORTMODE) != 0;
1112
1113 if ((ahc->features & AHC_ULTRA2) != 0)
1114 ramps = (ahc_inb(ahc, DSCOMMAND0) & RAMPS) != 0;
1115 else if (chip == AHC_AIC7895 || chip == AHC_AIC7895C)
1116 /*
1117 * External SCBRAM arbitration is flakey
1118 * on these chips. Unfortunately this means
1119 * we don't use the extra SCB ram space on the
1120 * 3940AUW.
1121 */
1122 ramps = 0;
1123 else if (chip >= AHC_AIC7870)
1124 ramps = (devconfig & RAMPSM) != 0;
1125 else
1126 ramps = 0;
1127
1128 if (ramps && single_user)
1129 return (1);
1130 return (0);
1131 }
1132
1133 /*
1134 * Enable external scbram.
1135 */
1136 static void
ahc_scbram_config(struct ahc_softc * ahc,int enable,int pcheck,int fast,int large)1137 ahc_scbram_config(struct ahc_softc *ahc, int enable, int pcheck,
1138 int fast, int large)
1139 {
1140 uint32_t devconfig;
1141
1142 if (ahc->features & AHC_MULTI_FUNC) {
1143 /*
1144 * Set the SCB Base addr (highest address bit)
1145 * depending on which channel we are.
1146 */
1147 ahc_outb(ahc, SCBBADDR, ahc->bd->func);
1148 }
1149
1150 ahc->flags &= ~AHC_LSCBS_ENABLED;
1151 if (large)
1152 ahc->flags |= AHC_LSCBS_ENABLED;
1153 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG);
1154 if ((ahc->features & AHC_ULTRA2) != 0) {
1155 u_int dscommand0;
1156
1157 dscommand0 = ahc_inb(ahc, DSCOMMAND0);
1158 if (enable)
1159 dscommand0 &= ~INTSCBRAMSEL;
1160 else
1161 dscommand0 |= INTSCBRAMSEL;
1162 if (large)
1163 dscommand0 &= ~USCBSIZE32;
1164 else
1165 dscommand0 |= USCBSIZE32;
1166 ahc_outb(ahc, DSCOMMAND0, dscommand0);
1167 } else {
1168 if (fast)
1169 devconfig &= ~EXTSCBTIME;
1170 else
1171 devconfig |= EXTSCBTIME;
1172 if (enable)
1173 devconfig &= ~SCBRAMSEL;
1174 else
1175 devconfig |= SCBRAMSEL;
1176 if (large)
1177 devconfig &= ~SCBSIZE32;
1178 else
1179 devconfig |= SCBSIZE32;
1180 }
1181 if (pcheck)
1182 devconfig |= EXTSCBPEN;
1183 else
1184 devconfig &= ~EXTSCBPEN;
1185
1186 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig);
1187 }
1188
1189 /*
1190 * Take a look to see if we have external SRAM.
1191 * We currently do not attempt to use SRAM that is
1192 * shared among multiple controllers.
1193 */
1194 static void
ahc_probe_ext_scbram(struct ahc_softc * ahc)1195 ahc_probe_ext_scbram(struct ahc_softc *ahc)
1196 {
1197 int num_scbs;
1198 int test_num_scbs;
1199 int enable;
1200 int pcheck;
1201 int fast;
1202 int large;
1203
1204 enable = FALSE;
1205 pcheck = FALSE;
1206 fast = FALSE;
1207 large = FALSE;
1208 num_scbs = 0;
1209
1210 if (ahc_ext_scbram_present(ahc) == 0)
1211 goto done;
1212
1213 /*
1214 * Probe for the best parameters to use.
1215 */
1216 ahc_scbram_config(ahc, /*enable*/TRUE, pcheck, fast, large);
1217 num_scbs = ahc_probe_scbs(ahc);
1218 if (num_scbs == 0) {
1219 /* The SRAM wasn't really present. */
1220 goto done;
1221 }
1222 enable = TRUE;
1223
1224 /*
1225 * Clear any outstanding parity error
1226 * and ensure that parity error reporting
1227 * is enabled.
1228 */
1229 ahc_outb(ahc, SEQCTL, 0);
1230 ahc_outb(ahc, CLRINT, CLRPARERR);
1231 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1232
1233 /* Now see if we can do parity */
1234 ahc_scbram_config(ahc, enable, /*pcheck*/TRUE, fast, large);
1235 num_scbs = ahc_probe_scbs(ahc);
1236 if ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1237 || (ahc_inb(ahc, ERROR) & MPARERR) == 0)
1238 pcheck = TRUE;
1239
1240 /* Clear any resulting parity error */
1241 ahc_outb(ahc, CLRINT, CLRPARERR);
1242 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1243
1244 /* Now see if we can do fast timing */
1245 ahc_scbram_config(ahc, enable, pcheck, /*fast*/TRUE, large);
1246 test_num_scbs = ahc_probe_scbs(ahc);
1247 if (test_num_scbs == num_scbs
1248 && ((ahc_inb(ahc, INTSTAT) & BRKADRINT) == 0
1249 || (ahc_inb(ahc, ERROR) & MPARERR) == 0))
1250 fast = TRUE;
1251
1252 /*
1253 * See if we can use large SCBs and still maintain
1254 * the same overall count of SCBs.
1255 */
1256 if ((ahc->features & AHC_LARGE_SCBS) != 0) {
1257 ahc_scbram_config(ahc, enable, pcheck, fast, /*large*/TRUE);
1258 test_num_scbs = ahc_probe_scbs(ahc);
1259 if (test_num_scbs >= num_scbs) {
1260 large = TRUE;
1261 num_scbs = test_num_scbs;
1262 if (num_scbs >= 64) {
1263 /*
1264 * We have enough space to move the
1265 * "busy targets table" into SCB space
1266 * and make it qualify all the way to the
1267 * lun level.
1268 */
1269 ahc->flags |= AHC_SCB_BTT;
1270 }
1271 }
1272 }
1273 done:
1274 /*
1275 * Disable parity error reporting until we
1276 * can load instruction ram.
1277 */
1278 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1279 /* Clear any latched parity error */
1280 ahc_outb(ahc, CLRINT, CLRPARERR);
1281 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
1282 if (1/*bootverbose*/ && enable) {
1283 printf("%s: External SRAM, %s access%s, %dbytes/SCB\n",
1284 ahc_name(ahc), fast ? "fast" : "slow",
1285 pcheck ? ", parity checking enabled" : "",
1286 large ? 64 : 32);
1287 }
1288 ahc_scbram_config(ahc, enable, pcheck, fast, large);
1289 }
1290
1291 #if 0
1292 /*
1293 * Perform some simple tests that should catch situations where
1294 * our registers are invalidly mapped.
1295 */
1296 int
1297 ahc_pci_test_register_access(struct ahc_softc *ahc)
1298 {
1299 int error;
1300 u_int status1;
1301 uint32_t cmd;
1302 uint8_t hcntrl;
1303
1304 error = EIO;
1305
1306 /*
1307 * Enable PCI error interrupt status, but suppress NMIs
1308 * generated by SERR raised due to target aborts.
1309 */
1310 cmd = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND);
1311 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCIR_COMMAND,
1312 cmd & ~PCIM_CMD_SERRESPEN);
1313
1314 /*
1315 * First a simple test to see if any
1316 * registers can be read. Reading
1317 * HCNTRL has no side effects and has
1318 * at least one bit that is guaranteed to
1319 * be zero so it is a good register to
1320 * use for this test.
1321 */
1322 hcntrl = ahc_inb(ahc, HCNTRL);
1323 if (hcntrl == 0xFF)
1324 goto fail;
1325
1326 /*
1327 * Next create a situation where write combining
1328 * or read prefetching could be initiated by the
1329 * CPU or host bridge. Our device does not support
1330 * either, so look for data corruption and/or flagged
1331 * PCI errors.
1332 */
1333 ahc_outb(ahc, HCNTRL, hcntrl|PAUSE);
1334 while (ahc_is_paused(ahc) == 0)
1335 ;
1336 ahc_outb(ahc, SEQCTL, PERRORDIS);
1337 ahc_outb(ahc, SCBPTR, 0);
1338 ahc_outl(ahc, SCB_BASE, 0x5aa555aa);
1339 if (ahc_inl(ahc, SCB_BASE) != 0x5aa555aa)
1340 goto fail;
1341
1342 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag,
1343 PCI_COMMAND_STATUS_REG + 1);
1344 if ((status1 & STA) != 0)
1345 goto fail;
1346
1347 error = 0;
1348
1349 fail:
1350 /* Silently clear any latched errors. */
1351 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG + 1);
1352 ahc_pci_write_config(ahc->dev_softc, PCIR_STATUS + 1,
1353 status1, /*bytes*/1);
1354 ahc_outb(ahc, CLRINT, CLRPARERR);
1355 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS);
1356 ahc_pci_write_config(ahc->dev_softc, PCIR_COMMAND, cmd, /*bytes*/2);
1357 return (error);
1358 }
1359 #endif
1360
1361 void
ahc_pci_intr(struct ahc_softc * ahc)1362 ahc_pci_intr(struct ahc_softc *ahc)
1363 {
1364 u_int error;
1365 u_int status1;
1366
1367 error = ahc_inb(ahc, ERROR);
1368 if ((error & PCIERRSTAT) == 0)
1369 return;
1370
1371 status1 = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG);
1372
1373 printf("%s: PCI error Interrupt at seqaddr = 0x%x\n",
1374 ahc_name(ahc),
1375 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
1376
1377 if (status1 & DPE) {
1378 printf("%s: Data Parity Error Detected during address "
1379 "or write data phase\n", ahc_name(ahc));
1380 }
1381 if (status1 & SSE) {
1382 printf("%s: Signal System Error Detected\n", ahc_name(ahc));
1383 }
1384 if (status1 & RMA) {
1385 printf("%s: Received a Master Abort\n", ahc_name(ahc));
1386 }
1387 if (status1 & RTA) {
1388 printf("%s: Received a Target Abort\n", ahc_name(ahc));
1389 }
1390 if (status1 & STA) {
1391 printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
1392 }
1393 if (status1 & DPR) {
1394 printf("%s: Data Parity Error has been reported via PERR#\n",
1395 ahc_name(ahc));
1396 }
1397
1398 /* Clear latched errors. */
1399 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, status1);
1400
1401 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
1402 printf("%s: Latched PCIERR interrupt with "
1403 "no status bits set\n", ahc_name(ahc));
1404 } else {
1405 ahc_outb(ahc, CLRINT, CLRPARERR);
1406 }
1407
1408 ahc_unpause(ahc);
1409 }
1410
1411 static int
ahc_pci_chip_init(struct ahc_softc * ahc)1412 ahc_pci_chip_init(struct ahc_softc *ahc)
1413 {
1414 ahc_outb(ahc, DSCOMMAND0, ahc->bus_softc.pci_softc.dscommand0);
1415 ahc_outb(ahc, DSPCISTATUS, ahc->bus_softc.pci_softc.dspcistatus);
1416 if ((ahc->features & AHC_DT) != 0) {
1417 u_int sfunct;
1418
1419 sfunct = ahc_inb(ahc, SFUNCT) & ~ALT_MODE;
1420 ahc_outb(ahc, SFUNCT, sfunct | ALT_MODE);
1421 ahc_outb(ahc, OPTIONMODE, ahc->bus_softc.pci_softc.optionmode);
1422 ahc_outw(ahc, TARGCRCCNT, ahc->bus_softc.pci_softc.targcrccnt);
1423 ahc_outb(ahc, SFUNCT, sfunct);
1424 ahc_outb(ahc, CRCCONTROL1,
1425 ahc->bus_softc.pci_softc.crccontrol1);
1426 }
1427 if ((ahc->features & AHC_MULTI_FUNC) != 0)
1428 ahc_outb(ahc, SCBBADDR, ahc->bus_softc.pci_softc.scbbaddr);
1429
1430 if ((ahc->features & AHC_ULTRA2) != 0)
1431 ahc_outb(ahc, DFF_THRSH, ahc->bus_softc.pci_softc.dff_thrsh);
1432
1433 return (ahc_chip_init(ahc));
1434 }
1435
1436 static int
ahc_aic785X_setup(struct ahc_softc * ahc)1437 ahc_aic785X_setup(struct ahc_softc *ahc)
1438 {
1439 uint8_t rev;
1440
1441 ahc->channel = 'A';
1442 ahc->chip = AHC_AIC7850;
1443 ahc->features = AHC_AIC7850_FE;
1444 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
1445 rev = PCI_REVISION(ahc->bd->class);
1446 if (rev >= 1)
1447 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
1448 ahc->instruction_ram_size = 512;
1449 return (0);
1450 }
1451
1452 static int
ahc_aic7860_setup(struct ahc_softc * ahc)1453 ahc_aic7860_setup(struct ahc_softc *ahc)
1454 {
1455 uint8_t rev;
1456
1457 ahc->channel = 'A';
1458 ahc->chip = AHC_AIC7860;
1459 ahc->features = AHC_AIC7860_FE;
1460 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
1461 rev = PCI_REVISION(ahc->bd->class);
1462 if (rev >= 1)
1463 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
1464 ahc->instruction_ram_size = 512;
1465 return (0);
1466 }
1467
1468 static int
ahc_apa1480_setup(struct ahc_softc * ahc)1469 ahc_apa1480_setup(struct ahc_softc *ahc)
1470 {
1471 int error;
1472
1473 error = ahc_aic7860_setup(ahc);
1474 if (error != 0)
1475 return (error);
1476 ahc->features |= AHC_REMOVABLE;
1477 return (0);
1478 }
1479
1480 static int
ahc_aic7870_setup(struct ahc_softc * ahc)1481 ahc_aic7870_setup(struct ahc_softc *ahc)
1482 {
1483
1484 ahc->channel = 'A';
1485 ahc->chip = AHC_AIC7870;
1486 ahc->features = AHC_AIC7870_FE;
1487 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
1488 ahc->instruction_ram_size = 512;
1489 return (0);
1490 }
1491
1492 static int
ahc_aha394X_setup(struct ahc_softc * ahc)1493 ahc_aha394X_setup(struct ahc_softc *ahc)
1494 {
1495 int error;
1496
1497 error = ahc_aic7870_setup(ahc);
1498 if (error == 0)
1499 error = ahc_aha394XX_setup(ahc);
1500 return (error);
1501 }
1502
1503 static int
ahc_aha398X_setup(struct ahc_softc * ahc)1504 ahc_aha398X_setup(struct ahc_softc *ahc)
1505 {
1506 int error;
1507
1508 error = ahc_aic7870_setup(ahc);
1509 if (error == 0)
1510 error = ahc_aha398XX_setup(ahc);
1511 return (error);
1512 }
1513
1514 static int
ahc_aha494X_setup(struct ahc_softc * ahc)1515 ahc_aha494X_setup(struct ahc_softc *ahc)
1516 {
1517 int error;
1518
1519 error = ahc_aic7870_setup(ahc);
1520 if (error == 0)
1521 error = ahc_aha494XX_setup(ahc);
1522 return (error);
1523 }
1524
1525 static int
ahc_aic7880_setup(struct ahc_softc * ahc)1526 ahc_aic7880_setup(struct ahc_softc *ahc)
1527 {
1528 uint8_t rev;
1529
1530 ahc->channel = 'A';
1531 ahc->chip = AHC_AIC7880;
1532 ahc->features = AHC_AIC7880_FE;
1533 ahc->bugs |= AHC_TMODE_WIDEODD_BUG;
1534 rev = PCI_REVISION(ahc->bd->class);
1535 if (rev >= 1) {
1536 ahc->bugs |= AHC_PCI_2_1_RETRY_BUG;
1537 } else {
1538 ahc->bugs |= AHC_CACHETHEN_BUG|AHC_PCI_MWI_BUG;
1539 }
1540 ahc->instruction_ram_size = 512;
1541 return (0);
1542 }
1543
1544 static int
ahc_aha2940Pro_setup(struct ahc_softc * ahc)1545 ahc_aha2940Pro_setup(struct ahc_softc *ahc)
1546 {
1547
1548 ahc->flags |= AHC_INT50_SPEEDFLEX;
1549 return (ahc_aic7880_setup(ahc));
1550 }
1551
1552 static int
ahc_aha394XU_setup(struct ahc_softc * ahc)1553 ahc_aha394XU_setup(struct ahc_softc *ahc)
1554 {
1555 int error;
1556
1557 error = ahc_aic7880_setup(ahc);
1558 if (error == 0)
1559 error = ahc_aha394XX_setup(ahc);
1560 return (error);
1561 }
1562
1563 static int
ahc_aha398XU_setup(struct ahc_softc * ahc)1564 ahc_aha398XU_setup(struct ahc_softc *ahc)
1565 {
1566 int error;
1567
1568 error = ahc_aic7880_setup(ahc);
1569 if (error == 0)
1570 error = ahc_aha398XX_setup(ahc);
1571 return (error);
1572 }
1573
1574 static int
ahc_aic7890_setup(struct ahc_softc * ahc)1575 ahc_aic7890_setup(struct ahc_softc *ahc)
1576 {
1577 uint8_t rev;
1578
1579 ahc->channel = 'A';
1580 ahc->chip = AHC_AIC7890;
1581 ahc->features = AHC_AIC7890_FE;
1582 ahc->flags |= AHC_NEWEEPROM_FMT;
1583 rev = PCI_REVISION(ahc->bd->class);
1584 if (rev == 0)
1585 ahc->bugs |= AHC_AUTOFLUSH_BUG|AHC_CACHETHEN_BUG;
1586 ahc->instruction_ram_size = 768;
1587 return (0);
1588 }
1589
1590 static int
ahc_aic7892_setup(struct ahc_softc * ahc)1591 ahc_aic7892_setup(struct ahc_softc *ahc)
1592 {
1593
1594 ahc->channel = 'A';
1595 ahc->chip = AHC_AIC7892;
1596 ahc->features = AHC_AIC7892_FE;
1597 ahc->flags |= AHC_NEWEEPROM_FMT;
1598 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
1599 ahc->instruction_ram_size = 1024;
1600 return (0);
1601 }
1602
1603 static int
ahc_aic7895_setup(struct ahc_softc * ahc)1604 ahc_aic7895_setup(struct ahc_softc *ahc)
1605 {
1606 uint8_t rev;
1607
1608 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A';
1609 /*
1610 * The 'C' revision of the aic7895 has a few additional features.
1611 */
1612 rev = PCI_REVISION(ahc->bd->class);
1613 if (rev >= 4) {
1614 ahc->chip = AHC_AIC7895C;
1615 ahc->features = AHC_AIC7895C_FE;
1616 } else {
1617 u_int command;
1618
1619 ahc->chip = AHC_AIC7895;
1620 ahc->features = AHC_AIC7895_FE;
1621
1622 /*
1623 * The BIOS disables the use of MWI transactions
1624 * since it does not have the MWI bug work around
1625 * we have. Disabling MWI reduces performance, so
1626 * turn it on again.
1627 */
1628 command = pci_conf_read(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG);
1629 command |= PCI_COMMAND_INVALIDATE_ENABLE;
1630 pci_conf_write(ahc->bd->pc, ahc->bd->tag, PCI_COMMAND_STATUS_REG, command);
1631 ahc->bugs |= AHC_PCI_MWI_BUG;
1632 }
1633 /*
1634 * XXX Does CACHETHEN really not work??? What about PCI retry?
1635 * on C level chips. Need to test, but for now, play it safe.
1636 */
1637 ahc->bugs |= AHC_TMODE_WIDEODD_BUG|AHC_PCI_2_1_RETRY_BUG
1638 | AHC_CACHETHEN_BUG;
1639
1640 #if 0
1641 uint32_t devconfig;
1642
1643 /*
1644 * Cachesize must also be zero due to stray DAC
1645 * problem when sitting behind some bridges.
1646 */
1647 pci_conf_write(ahc->bd->pc, ahc->bd->tag, CSIZE_LATTIME, 0);
1648 devconfig = pci_conf_read(ahc->bd->pc, ahc->bd->tag, DEVCONFIG);
1649 devconfig |= MRDCEN;
1650 pci_conf_write(ahc->bd->pc, ahc->bd->tag, DEVCONFIG, devconfig);
1651 #endif
1652 ahc->flags |= AHC_NEWEEPROM_FMT;
1653 ahc->instruction_ram_size = 512;
1654 return (0);
1655 }
1656
1657 static int
ahc_aic7896_setup(struct ahc_softc * ahc)1658 ahc_aic7896_setup(struct ahc_softc *ahc)
1659 {
1660 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A';
1661 ahc->chip = AHC_AIC7896;
1662 ahc->features = AHC_AIC7896_FE;
1663 ahc->flags |= AHC_NEWEEPROM_FMT;
1664 ahc->bugs |= AHC_CACHETHEN_DIS_BUG;
1665 ahc->instruction_ram_size = 768;
1666 return (0);
1667 }
1668
1669 static int
ahc_aic7899_setup(struct ahc_softc * ahc)1670 ahc_aic7899_setup(struct ahc_softc *ahc)
1671 {
1672 ahc->channel = (ahc->bd->func == 1) ? 'B' : 'A';
1673 ahc->chip = AHC_AIC7899;
1674 ahc->features = AHC_AIC7899_FE;
1675 ahc->flags |= AHC_NEWEEPROM_FMT;
1676 ahc->bugs |= AHC_SCBCHAN_UPLOAD_BUG;
1677 ahc->instruction_ram_size = 1024;
1678 return (0);
1679 }
1680
1681 static int
ahc_aha29160C_setup(struct ahc_softc * ahc)1682 ahc_aha29160C_setup(struct ahc_softc *ahc)
1683 {
1684 int error;
1685
1686 error = ahc_aic7899_setup(ahc);
1687 if (error != 0)
1688 return (error);
1689 ahc->features |= AHC_REMOVABLE;
1690 return (0);
1691 }
1692
1693 static int
ahc_raid_setup(struct ahc_softc * ahc)1694 ahc_raid_setup(struct ahc_softc *ahc)
1695 {
1696 printf("RAID functionality unsupported\n");
1697 return (ENXIO);
1698 }
1699
1700 static int
ahc_aha394XX_setup(struct ahc_softc * ahc)1701 ahc_aha394XX_setup(struct ahc_softc *ahc)
1702 {
1703
1704 switch (ahc->bd->dev) {
1705 case AHC_394X_SLOT_CHANNEL_A:
1706 ahc->channel = 'A';
1707 break;
1708 case AHC_394X_SLOT_CHANNEL_B:
1709 ahc->channel = 'B';
1710 break;
1711 default:
1712 printf("adapter at unexpected slot %d\n"
1713 "unable to map to a channel\n",
1714 ahc->bd->dev);
1715 ahc->channel = 'A';
1716 }
1717 return (0);
1718 }
1719
1720 static int
ahc_aha398XX_setup(struct ahc_softc * ahc)1721 ahc_aha398XX_setup(struct ahc_softc *ahc)
1722 {
1723
1724 switch (ahc->bd->dev) {
1725 case AHC_398X_SLOT_CHANNEL_A:
1726 ahc->channel = 'A';
1727 break;
1728 case AHC_398X_SLOT_CHANNEL_B:
1729 ahc->channel = 'B';
1730 break;
1731 case AHC_398X_SLOT_CHANNEL_C:
1732 ahc->channel = 'C';
1733 break;
1734 default:
1735 printf("adapter at unexpected slot %d\n"
1736 "unable to map to a channel\n",
1737 ahc->bd->dev);
1738 ahc->channel = 'A';
1739 break;
1740 }
1741 ahc->flags |= AHC_LARGE_SEEPROM;
1742 return (0);
1743 }
1744
1745 static int
ahc_aha494XX_setup(struct ahc_softc * ahc)1746 ahc_aha494XX_setup(struct ahc_softc *ahc)
1747 {
1748
1749 switch (ahc->bd->dev) {
1750 case AHC_494X_SLOT_CHANNEL_A:
1751 ahc->channel = 'A';
1752 break;
1753 case AHC_494X_SLOT_CHANNEL_B:
1754 ahc->channel = 'B';
1755 break;
1756 case AHC_494X_SLOT_CHANNEL_C:
1757 ahc->channel = 'C';
1758 break;
1759 case AHC_494X_SLOT_CHANNEL_D:
1760 ahc->channel = 'D';
1761 break;
1762 default:
1763 printf("adapter at unexpected slot %d\n"
1764 "unable to map to a channel\n",
1765 ahc->bd->dev);
1766 ahc->channel = 'A';
1767 }
1768 ahc->flags |= AHC_LARGE_SEEPROM;
1769 return (0);
1770 }
1771