1 /* 2 ** cpu.h Motorola M68k, CPU32 and ColdFire cpu-description header-file 3 ** (c) in 2002,2006-2017 by Frank Wille 4 */ 5 6 #define BIGENDIAN 1 7 #define LITTLEENDIAN 0 8 #define VASM_CPU_M68K 1 9 #define MNEMOHTABSIZE 0x4000 10 11 /* maximum number of operands for one mnemonic */ 12 #define MAX_OPERANDS 6 13 14 /* maximum number of mnemonic-qualifiers per mnemonic */ 15 #define MAX_QUALIFIERS 1 16 17 /* maximum number of additional command-line-flags for this cpu */ 18 19 /* data type to represent a target-address */ 20 typedef int32_t taddr; 21 typedef uint32_t utaddr; 22 23 /* instruction extension */ 24 #define HAVE_INSTRUCTION_EXTENSION 1 25 typedef struct { 26 union { 27 struct { 28 unsigned char flags; 29 signed char last_size; 30 signed char orig_ext; 31 char unused; 32 } real; 33 struct { 34 struct instruction *next; 35 } copy; 36 } un; 37 } instruction_ext; 38 #define IFL_RETAINLASTSIZE 1 /* retain current last_size value */ 39 #define IFL_UNSIZED 2 /* instruction had no size extension */ 40 41 /* we use OPTS atoms for cpu-specific options */ 42 #define HAVE_CPU_OPTS 1 43 typedef struct { 44 int cmd; 45 int arg; 46 } optcmd; 47 /* optcmd commands - warning: print_cpu_opts() depends on the order! */ 48 enum { 49 OCMD_NOP, 50 OCMD_CPU, 51 OCMD_FPU, 52 OCMD_SDREG, 53 OCMD_NOOPT, 54 OCMD_OPTGEN, 55 OCMD_OPTMOVEM, 56 OCMD_OPTPEA, 57 OCMD_OPTCLR, 58 OCMD_OPTST, 59 OCMD_OPTLSL, 60 OCMD_OPTMUL, 61 OCMD_OPTDIV, 62 OCMD_OPTFCONST, 63 OCMD_OPTBRAJMP, 64 OCMD_OPTJBRA, 65 OCMD_OPTPC, 66 OCMD_OPTBRA, 67 OCMD_OPTDISP, 68 OCMD_OPTABS, 69 OCMD_OPTMOVEQ, 70 OCMD_OPTQUICK, 71 OCMD_OPTBRANOP, 72 OCMD_OPTBDISP, 73 OCMD_OPTODISP, 74 OCMD_OPTLEA, 75 OCMD_OPTLQUICK, 76 OCMD_OPTIMMADDR, 77 OCMD_OPTSPEED, 78 OCMD_SMALLCODE, 79 OCMD_SMALLDATA, 80 OCMD_OPTWARN, 81 OCMD_CHKPIC, 82 OCMD_CHKTYPE, 83 OCMD_NOWARN 84 }; 85 86 /* minimum instruction alignment */ 87 #define INST_ALIGN 2 88 89 /* default alignment for n-bit data */ 90 #define DATA_ALIGN(n) ((n<=8)?1:2) 91 92 /* operand class for n-bit data definitions */ 93 #define DATA_OPERAND(n) m68k_data_operand(n) 94 95 /* returns true when instruction is valid for selected cpu */ 96 #define MNEMONIC_VALID(n) m68k_available(n) 97 98 /* parse cpu-specific directives with label */ 99 #define PARSE_CPU_LABEL(l,s) parse_cpu_label(l,s) 100 101 /* type to store each operand */ 102 typedef struct { 103 signed char mode; 104 signed char reg; 105 uint16_t format; /* used for (d8,An/PC,Rn) and ext.addr.modes */ 106 unsigned char bf_offset; /* bitfield offset, k-factor or MAC Upper Word */ 107 unsigned char bf_width; /* bitfield width or MAC-MASK '&' */ 108 int8_t basetype[2]; /* BASE_OK=normal, BASE=PCREL=pc-relative base */ 109 uint32_t flags; 110 expr *value[2]; /* immediate, abs. or displacem. expression */ 111 /* filled during instruction_size(): */ 112 taddr extval[2]; /* evaluated expression from value[0/1] */ 113 symbol *base[2]; /* symbol base for value[0/1], NULL otherwise */ 114 } operand; 115 116 /* flags */ 117 /* Note: FL_CheckMask bits are used together with optype.flags OTF-bits */ 118 #define FL_ExtVal0 1 /* extval[0] is set */ 119 #define FL_ExtVal1 2 /* extval[1] is set */ 120 #define FL_UsesFormat 4 /* operand uses format word */ 121 #define FL_020up 8 /* 020+ addressing mode */ 122 #define FL_noCPU32 0x10 /* addressing mode not available for CPU32 */ 123 #define FL_BFoffsetDyn 0x20 /* dynamic bitfield offset specified */ 124 #define FL_BFwidthDyn 0x40 /* dynamic bitfield width specified */ 125 #define FL_DoNotEval 0x80 /* do not evaluate, extval and base are ok */ 126 /*#define FL_PossRegList 0x80 parser is not sure if operand is RegList */ 127 #define FL_NoOptBase 0x100 /* never optimize base displacement */ 128 #define FL_NoOptOuter 0x200 /* never optimize outer displacement */ 129 #define FL_NoOpt 0x300 /* never optimize this whole operand */ 130 #define FL_ZBase 0x400 /* ZAn base register specified */ 131 #define FL_ZIndex 0x800 /* ZRn index register specified */ 132 #define FL_BaseReg 0x1000 /* BASEREG expression in exp.value[0] */ 133 #define FL_BnReg 0x4000 /* Apollo: Bn register instead of An */ 134 #define FL_MAC 0x8000 /* ColdFire MAC specific extensions */ 135 #define FL_Bitfield 0x10000 /* operand uses bf_offset/bf_width */ 136 #define FL_DoubleReg 0x20000 /* Dm:Dn or (Rm):(Rn), where both registers 137 are put into "reg": 0nnn0mmm */ 138 #define FL_KFactor 0x40000 /* k-factor <ea>{#n} or <ea>{Dn}, which 139 can be found in bf_offset */ 140 #define FL_FPSpec 0x80000 /* special FPU reg. FPIAR/FPCR/FPSR only */ 141 142 #define FL_CheckMask 0xfc000 /* bits to check, when comparing with 143 flags from struct optype */ 144 145 /* addressing modes */ 146 #define MODE_Dn 0 147 #define MODE_An 1 148 #define MODE_AnIndir 2 149 #define MODE_AnPostInc 3 150 #define MODE_AnPreDec 4 151 #define MODE_An16Disp 5 152 #define MODE_An8Format 6 /* uses format word */ 153 #define MODE_Extended 7 /* reg determines addressing mode */ 154 #define MODE_FPn 8 /* FPU register */ 155 #define MODE_SpecReg 9 /* reg determines index into SpecRegs */ 156 /* reg encodings for MODE_Extended: */ 157 #define REG_AbsShort 0 158 #define REG_AbsLong 1 159 #define REG_PC16Disp 2 160 #define REG_PC8Format 3 /* uses format word */ 161 #define REG_Immediate 4 162 #define REG_RnList 5 /* An/Dn register list in value[0] */ 163 #define REG_FPnList 6 /* FPn register list in value[0] */ 164 165 /* format word */ 166 #define FW_IndexAn 0x8000 167 #define FW_IndexReg_Shift 12 168 #define FW_IndexReg(n) ((n)<<FW_IndexReg_Shift) 169 #define FW_LongIndex 0x0800 170 #define FW_Scale_Shift 9 171 #define FW_Scale(n) ((n)<<FW_Scale_Shift) 172 #define FW_FullFormat 0x0100 173 #define FW_BaseSuppress 0x0080 174 #define FW_IndexSuppress 0x0040 175 #define FW_BDSize_Shift 4 176 #define FW_BDSize(n) ((n)<<FW_BDSize_Shift) 177 #define FW_getBDSize(n) (((n)>>FW_BDSize_Shift)&3) 178 #define FW_Postindexed 0x0004 179 #define FW_IndSize(n) (n) 180 #define FW_getIndSize(n) (n&3) 181 #define FW_None 0 182 #define FW_Null 1 183 #define FW_Word 2 184 #define FW_Long 3 185 #define FW_SizeMask 3 186 187 /* register macros */ 188 #define REGAn 8 189 #define REGPC 0x10 190 #define REGBn 0x20 /* Apollo only */ 191 #define REGZero 0x80 192 #define REGisAn(n) ((n)®An) 193 #define REGisDn(n) (!((n)®An)) 194 #define REGisPC(n) ((n)®PC) 195 #define REGisZero(n) ((n)®Zero) 196 #define REGisBn(n) ((n)®Bn) /* Apollo only */ 197 #define REGget(n) ((n)&(REGAn-1)) 198 #define REGgetA(n) ((n)&(REGPC-1)) 199 #define REGext_Shift 8 200 #define REGext(n) (((n)&0x700)>>REGext_Shift) 201 #define REGscale_Shift 12 202 #define REGscale(n) (((n)&0x3000)>>REGscale_Shift) 203 204 /* MAC scale-factor, stored as value[0] */ 205 #define MACSF_None 0 206 #define MACSF_ShiftLeft 1 207 #define MACSF_ShiftRight 3 208 209 /* special CPU registers */ 210 struct specreg { 211 char *name; 212 int code; /* -1 means no code, syntax-check only */ 213 uint32_t available; 214 }; 215 216 217 /* extension codes */ 218 #define EXT_BYTE 1 219 #define EXT_WORD 2 220 #define EXT_LONG 3 221 #define EXT_SINGLE 4 222 #define EXT_DOUBLE 5 223 #define EXT_EXTENDED 6 224 #define EXT_PACKED 7 225 #define EXT_UPPER 2 /* ColdFire MAC upper register word */ 226 #define EXT_LOWER 3 /* ColdFire MAC lower register word */ 227 #define EXT_MASK 7 228 229 230 struct addrmode { 231 signed char mode; 232 signed char reg; 233 }; 234 235 #define AM_Dn 0 236 #define AM_An 1 237 #define AM_AnIndir 2 238 #define AM_AnPostInc 3 239 #define AM_AnPreDec 4 240 #define AM_An16Disp 5 241 #define AM_An8Format 6 242 #define AM_AbsShort 7 243 #define AM_AbsLong 8 244 #define AM_PC16Disp 9 245 #define AM_PC8Format 10 246 #define AM_Immediate 11 247 #define AM_RnList 12 248 #define AM_FPnList 13 249 #define AM_FPn 14 250 #define AM_SpecReg 15 251 252 253 /* operand types */ 254 struct optype { 255 uint16_t modes; /* addressing modes allowed (0-15, see above) */ 256 uint32_t flags; 257 unsigned char first; 258 unsigned char last; 259 }; 260 261 /* flags */ 262 /* Note: Do not allocate bits from FL_CheckMask! */ 263 #define OTF_NOSIZE 1 /* this addr. mode requires no additional bytes */ 264 #define OTF_BRANCH 2 /* branch instruction */ 265 #define OTF_DATA 4 /* data definition */ 266 #define OTF_FLTIMM 8 /* base10 immediate values are floating point */ 267 #define OTF_QUADIMM 0x10 /* immediate values are 64 bits */ 268 #define OTF_SPECREG 0x20 /* check for special registers during parse */ 269 #define OTF_SRRANGE 0x40 /* check range between first/last only */ 270 #define OTF_REGLIST 0x80 /* register list required, even when single reg. */ 271 #define OTF_CHKVAL 0x100 /* compare op. value against first/last */ 272 #define OTF_CHKREG 0x200 /* compare op. register against first/last */ 273 #define OTF_VXRNG2 0x400 /* Apollo AMMX Rn:Rn+1 vector register range */ 274 #define OTF_VXRNG4 0x800 /* Apollo AMMX Rn-Rn+3 vector register range */ 275 276 277 /* additional mnemonic data */ 278 typedef struct { 279 uint16_t place[MAX_OPERANDS]; 280 uint16_t opcode[2]; 281 uint16_t size; 282 uint32_t available; 283 } mnemonic_extension; 284 285 /* size qualifiers, lowest two bits specify opcode size in words! */ 286 #define SIZE_UNSIZED 0 287 #define SIZE_BYTE 0x100 288 #define SIZE_WORD 0x200 289 #define SIZE_LONG 0x400 290 #define SIZE_SINGLE 0x800 291 #define SIZE_DOUBLE 0x1000 292 #define SIZE_EXTENDED 0x2000 293 #define SIZE_PACKED 0x4000 294 #define SIZE_MASK 0x7f00 295 #define SIZE_UNAMBIG 0x8000 /* only a single size allowed for this mnemonic */ 296 #define S_CFCHECK 0x80 /* SIZE_LONG only, when mcf (Coldfire) set */ 297 #define S_NONE 4 298 #define S_STD S_NONE+4 /* 1st word, bits 6-7 */ 299 #define S_STD1 S_STD+4 /* 1st word, bits 6-7, b=1,w=2,l=3 */ 300 #define S_HI S_STD1+4 /* 1st word, bits 9-10 */ 301 #define S_CAS S_HI+4 /* 1st word, bits 9-10, b=1,w=2,l=3 */ 302 #define S_MOVE S_CAS+4 /* move instruction, 1st word bits 12-13 */ 303 #define S_WL8 S_MOVE+4 /* w/l flag in 1st word bit 8 */ 304 #define S_LW7 S_WL8+4 /* l/w flag in 1st word bit 7 */ 305 #define S_WL6 S_LW7+4 /* w/l flag in 1st word bit 6 */ 306 #define S_TRAP S_WL6+4 /* 1st word, bits 1-0, w=2, l=3 */ 307 #define S_EXT S_TRAP+4 /* 2nd word, bits 6-7 */ 308 #define S_FP S_EXT+4 /* 2nd word, bits 12-10 (l=0,s,x,p,w,d,b) */ 309 #define S_MAC S_FP+4 /* w/l flag in 2nd word bit 11 */ 310 #define S_OPCODE_SIZE(n) (n&3) 311 #define S_SIZEMODE(n) (n&0x7c) 312 313 /* short cuts */ 314 #define UNS SIZE_UNSIZED 315 #define B SIZE_BYTE 316 #define W SIZE_WORD 317 #define L SIZE_LONG 318 #define Q SIZE_DOUBLE 319 #define SBW (SIZE_BYTE|SIZE_WORD|SIZE_SINGLE) /* .s = .b for branches */ 320 #define SBWL (SIZE_BYTE|SIZE_WORD|SIZE_LONG|SIZE_SINGLE) 321 #define BW (SIZE_BYTE|SIZE_WORD) 322 #define WL (SIZE_WORD|SIZE_LONG) 323 #define BWL (SIZE_BYTE|SIZE_WORD|SIZE_LONG) 324 #define CFWL (SIZE_WORD|SIZE_LONG|S_CFCHECK) 325 #define CFBWL (SIZE_BYTE|SIZE_WORD|SIZE_LONG|S_CFCHECK) 326 #define ANY (SIZE_BYTE|SIZE_WORD|SIZE_LONG|SIZE_SINGLE|SIZE_DOUBLE| \ 327 SIZE_EXTENDED|SIZE_PACKED) 328 #define CFANY (SIZE_BYTE|SIZE_WORD|SIZE_LONG|SIZE_SINGLE|SIZE_DOUBLE) 329 #define FX SIZE_EXTENDED 330 #define FD SIZE_DOUBLE 331 332 333 /* operand insertion info */ 334 struct oper_insert { 335 unsigned char mode; /* insert mode (see below) */ 336 unsigned char size; /* number of bits to insert */ 337 unsigned char pos; /* bit position for inserted value in stream */ 338 unsigned char flags; 339 void (*insert)(unsigned char *,struct oper_insert *,operand *); 340 }; 341 342 /* insert modes */ 343 #define M_nop 0 /* do nothing for this operand */ 344 #define M_noea 1 /* don't store ea, only extension words */ 345 #define M_ea 2 /* insert mode/reg in lowest 6 bits */ 346 #define M_high_ea 3 /* insert reg/mode in bits 11-6 (MOVE) */ 347 #define M_bfea 4 /* insert std. ea and bitfield offset/width */ 348 #define M_kfea 5 /* insert std. ea and k-factor/dest.format */ 349 #define M_func 6 /* use insert() function */ 350 #define M_branch 7 /* extval0 contains branch label */ 351 #define M_val0 8 /* extval0 at specified position */ 352 #define M_reg 9 /* insert reg at specified position */ 353 /* flags */ 354 #define IIF_MASK 1 /* value 2^size is represented by a 0 (M_val0) 355 recognize MASK-flag for MAC instr. (M_ea) */ 356 #define IIF_BCC 2 /* Bcc branch, opcode is modified */ 357 #define IIF_REVERSE 4 /* store bits in reverse order (M_val0) */ 358 #define IIF_NOMODE 8 /* don't store ea mode specifier in opcode */ 359 #define IIF_SIGNED 16 /* value is signed (M_val0) */ 360 #define IIF_3Q 64 /* MOV3Q: -1 is written as 0 (M_val0) */ 361 #define IIF_ABSVAL 128 /* make sure first expr. is absolute (M_func) */ 362 /* redefinition for AMMX special registers (M_func) */ 363 #define IIF_A 8 /* RegBit 4 to A-bit (bit-position 8) */ 364 #define IIF_B 7 /* RegBit 4 to B-bit (bit-position 7) */ 365 #define IIF_D 6 /* RegBit 4 to D-bit (bit-position 6) */ 366 367 368 /* CPU models and their type-flags */ 369 struct cpu_models { 370 char name[8]; 371 uint32_t type; 372 }; 373 374 /* cpu types for availability check - warning: order is important */ 375 #define CPUMASK 0x00ffffff 376 #define m68000 0x00000001 377 #define m68010 0x00000002 378 #define m68020 0x00000004 379 #define m68030 0x00000008 380 #define m68040 0x00000010 381 #define m68060 0x00000020 382 #define m68881 0x00000040 383 #define m68882 m68881 384 #define m68851 0x00000080 385 #define cpu32 0x00000100 386 #define mcfa 0x00000200 387 #define mcfaplus 0x00000400 388 #define mcfb 0x00000800 389 #define mcfc 0x00001000 390 #define mcfhwdiv 0x00002000 391 #define mcfmac 0x00004000 392 #define mcfemac 0x00008000 393 #define mcfusp 0x00010000 394 #define mcffpu 0x00020000 395 #define mcfmmu 0x00040000 396 #define ac68080 0x00100000 397 #define mgas 0x20000000 /* a GNU-as specific mnemonic */ 398 #define malias 0x40000000 /* a bad alias which we should warn about */ 399 #define mfpu 0x80000000 /* just to check if CP-ID needs to be inserted */ 400 401 /* handy aliases */ 402 #define m68k (m68000|m68010|m68020|m68030|m68040|m68060) 403 #define apollo (ac68080) 404 #define mcf (mcfa|mcfaplus|mcfb|mcfc) 405 #define mcf_all (mcfa|mcfaplus|mcfb|mcfc|mcfhwdiv|mcfmac|mcfemac|mcfusp|mcffpu|mcfmmu) 406 #define mfloat (mfpu|m68881|m68882|m68040|m68060) 407 #define mmmu (m68851|m68030|m68040|m68060) 408 #define m68040up (m68040|m68060|apollo) 409 #define m68030up (m68030|m68040up) 410 #define m68020up (m68020|m68030up) 411 #define m68010up (m68010|cpu32|m68020up) 412 #define m68000up (m68000|m68010up) 413 414 415 /* register symbols */ 416 #define HAVE_REGSYMS 417 #define REGSYMHTSIZE 256 418 419 #define RSTYPE_Dn 0 420 #define RSTYPE_An 1 421 #define RSTYPE_FPn 2 422 #define RSTYPE_Bn 3 /* Apollo only */ 423 424 425 /* MID for a.out format */ 426 extern int m68k_mid; 427 #define MID m68k_mid 428 429 /* exported functions */ 430 int m68k_available(int); 431 int m68k_data_operand(int); 432 int parse_cpu_label(char *,char **); 433