1 /* Public Domain */ 2 3 /* 4 * i.MX6Q clocks. 5 */ 6 7 #define IMX6_CLK_IPG 0x3e 8 #define IMX6_CLK_IPG_PER 0x3f 9 #define IMX6_CLK_ECSPI_ROOT 0x47 10 #define IMX6_CLK_ARM 0x68 11 #define IMX6_CLK_AHB 0x69 12 #define IMX6_CLK_ECSPI2 0x71 13 #define IMX6_CLK_ENET 0x75 14 #define IMX6_CLK_I2C1 0x7d 15 #define IMX6_CLK_I2C2 0x7e 16 #define IMX6_CLK_I2C3 0x7f 17 #define IMX6_CLK_SATA 0x9a 18 #define IMX6_CLK_UART_IPG 0xa0 19 #define IMX6_CLK_UART_SERIAL 0xa1 20 #define IMX6_CLK_USBOH3 0xa2 21 #define IMX6_CLK_USDHC1 0xa3 22 #define IMX6_CLK_USDHC2 0xa4 23 #define IMX6_CLK_USDHC3 0xa5 24 #define IMX6_CLK_USDHC4 0xa6 25 #define IMX6_CLK_PLL3_USB_OTG 0xac 26 #define IMX6_CLK_PLL7_USB_HOST 0xb0 27 #define IMX6_CLK_PLL6_ENET 0xb1 28 #define IMX6_CLK_USBPHY1 0xb6 29 #define IMX6_CLK_USBPHY2 0xb7 30 #define IMX6_CLK_SATA_REF 0xba 31 #define IMX6_CLK_SATA_REF_100 0xbb 32 #define IMX6_CLK_ENET_REF 0xbe 33 #define IMX6_CLK_PLL3 0xe1 34 #define IMX6_CLK_PLL6 0xe4 35 #define IMX6_CLK_PLL7 0xe5 36 37 const struct imxccm_gate imx6_gates[] = { 38 [IMX6_CLK_ECSPI2] = { CCM_CCGR1, 1, IMX6_CLK_ECSPI_ROOT }, 39 [IMX6_CLK_ENET] = { CCM_CCGR1, 5, IMX6_CLK_IPG }, 40 [IMX6_CLK_I2C1] = { CCM_CCGR2, 3, IMX6_CLK_IPG_PER }, 41 [IMX6_CLK_I2C2] = { CCM_CCGR2, 4, IMX6_CLK_IPG_PER }, 42 [IMX6_CLK_I2C3] = { CCM_CCGR2, 5, IMX6_CLK_IPG_PER }, 43 [IMX6_CLK_SATA] = { CCM_CCGR5, 2 }, 44 [IMX6_CLK_UART_IPG] = { CCM_CCGR5, 12, IMX6_CLK_IPG }, 45 [IMX6_CLK_UART_SERIAL] = { CCM_CCGR5, 13 }, 46 [IMX6_CLK_USBOH3] = { CCM_CCGR6, 0 }, 47 [IMX6_CLK_USDHC1] = { CCM_CCGR6, 1 }, 48 [IMX6_CLK_USDHC2] = { CCM_CCGR6, 2 }, 49 [IMX6_CLK_USDHC3] = { CCM_CCGR6, 3 }, 50 [IMX6_CLK_USDHC4] = { CCM_CCGR6, 4 }, 51 }; 52 53 /* 54 * i.MX6UL clocks. 55 */ 56 57 #define IMX6UL_CLK_ARM 0x5d 58 #define IMX6UL_CLK_PERCLK 0x63 59 #define IMX6UL_CLK_IPG 0x64 60 #define IMX6UL_CLK_GPT1_BUS 0x98 61 #define IMX6UL_CLK_GPT1_SERIAL 0x99 62 #define IMX6UL_CLK_I2C1 0x9c 63 #define IMX6UL_CLK_I2C2 0x9d 64 #define IMX6UL_CLK_I2C3 0x9e 65 #define IMX6UL_CLK_I2C4 0x9f 66 #define IMX6UL_CLK_UART1_IPG 0xbd 67 #define IMX6UL_CLK_UART1_SERIAL 0xbe 68 #define IMX6UL_CLK_USBOH3 0xcd 69 #define IMX6UL_CLK_USDHC1 0xce 70 #define IMX6UL_CLK_USDHC2 0xcf 71 72 const struct imxccm_gate imx6ul_gates[] = { 73 [IMX6UL_CLK_GPT1_BUS] = { CCM_CCGR1, 10, IMX6UL_CLK_PERCLK }, 74 [IMX6UL_CLK_GPT1_SERIAL] = { CCM_CCGR1, 11, IMX6UL_CLK_PERCLK }, 75 [IMX6UL_CLK_I2C1] = { CCM_CCGR2, 3, IMX6UL_CLK_PERCLK }, 76 [IMX6UL_CLK_I2C2] = { CCM_CCGR2, 4, IMX6UL_CLK_PERCLK }, 77 [IMX6UL_CLK_I2C3] = { CCM_CCGR2, 5, IMX6UL_CLK_PERCLK }, 78 [IMX6UL_CLK_I2C4] = { CCM_CCGR6, 12, IMX6UL_CLK_PERCLK }, 79 [IMX6UL_CLK_UART1_IPG] = { CCM_CCGR5, 12, IMX6UL_CLK_IPG }, 80 [IMX6UL_CLK_UART1_SERIAL] = { CCM_CCGR5, 12 }, 81 [IMX6UL_CLK_USBOH3] = { CCM_CCGR6, 0 }, 82 [IMX6UL_CLK_USDHC1] = { CCM_CCGR6, 1 }, 83 [IMX6UL_CLK_USDHC2] = { CCM_CCGR6, 2 }, 84 }; 85 86 /* 87 * i.MX7D clocks. 88 */ 89 90 #define IMX7D_PLL_ENET_MAIN_125M_CLK 0x2a 91 #define IMX7D_ENET_AXI_ROOT_CLK 0x52 92 #define IMX7D_ENET_AXI_ROOT_SRC 0x53 93 #define IMX7D_ENET_AXI_ROOT_CG 0x54 94 #define IMX7D_ENET_AXI_ROOT_DIV 0x55 95 #define IMX7D_ENET1_IPG_ROOT_CLK 0x9e 96 #define IMX7D_ENET1_TIME_ROOT_CLK 0xa2 97 #define IMX7D_ENET1_TIME_ROOT_SRC 0xa3 98 #define IMX7D_ENET1_TIME_ROOT_CG 0xa4 99 #define IMX7D_ENET1_TIME_ROOT_DIV 0xa5 100 #define IMX7D_ENET2_IPG_ROOT_CLK 0xa6 101 #define IMX7D_ENET2_TIME_ROOT_CLK 0xaa 102 #define IMX7D_ENET2_TIME_ROOT_SRC 0xab 103 #define IMX7D_ENET2_TIME_ROOT_CG 0xac 104 #define IMX7D_ENET2_TIME_ROOT_DIV 0xad 105 #define IMX7D_ENET_PHY_REF_ROOT_CLK 0xae 106 #define IMX7D_ENET_PHY_REF_ROOT_SRC 0xaf 107 #define IMX7D_ENET_PHY_REF_ROOT_CG 0xb0 108 #define IMX7D_ENET_PHY_REF_ROOT_DIV 0xb1 109 #define IMX7D_USDHC1_ROOT_CLK 0xbe 110 #define IMX7D_USDHC1_ROOT_SRC 0xbf 111 #define IMX7D_USDHC1_ROOT_CG 0xc0 112 #define IMX7D_USDHC1_ROOT_DIV 0xc1 113 #define IMX7D_USDHC2_ROOT_CLK 0xc2 114 #define IMX7D_USDHC2_ROOT_SRC 0xc3 115 #define IMX7D_USDHC2_ROOT_CG 0xc4 116 #define IMX7D_USDHC2_ROOT_DIV 0xc5 117 #define IMX7D_USDHC3_ROOT_CLK 0xc6 118 #define IMX7D_USDHC3_ROOT_SRC 0xc7 119 #define IMX7D_USDHC3_ROOT_CG 0xc8 120 #define IMX7D_USDHC3_ROOT_DIV 0xc9 121 #define IMX7D_I2C1_ROOT_CLK 0xd2 122 #define IMX7D_I2C1_ROOT_SRC 0xd3 123 #define IMX7D_I2C1_ROOT_CG 0xd4 124 #define IMX7D_I2C1_ROOT_DIV 0xd5 125 #define IMX7D_I2C2_ROOT_CLK 0xd6 126 #define IMX7D_I2C2_ROOT_SRC 0xd7 127 #define IMX7D_I2C2_ROOT_CG 0xd8 128 #define IMX7D_I2C2_ROOT_DIV 0xd9 129 #define IMX7D_I2C3_ROOT_CLK 0xda 130 #define IMX7D_I2C3_ROOT_SRC 0xdb 131 #define IMX7D_I2C3_ROOT_CG 0xdc 132 #define IMX7D_I2C3_ROOT_DIV 0xdd 133 #define IMX7D_I2C4_ROOT_CLK 0xde 134 #define IMX7D_I2C4_ROOT_SRC 0xdf 135 #define IMX7D_I2C4_ROOT_CG 0xe0 136 #define IMX7D_I2C4_ROOT_DIV 0xe1 137 #define IMX7D_UART1_ROOT_CLK 0xe2 138 #define IMX7D_UART1_ROOT_SRC 0xe3 139 #define IMX7D_UART1_ROOT_CG 0xe4 140 #define IMX7D_UART1_ROOT_DIV 0xe5 141 #define IMX7D_UART2_ROOT_CLK 0xe6 142 #define IMX7D_UART2_ROOT_SRC 0xe7 143 #define IMX7D_UART2_ROOT_CG 0xe8 144 #define IMX7D_UART2_ROOT_DIV 0xe9 145 #define IMX7D_UART3_ROOT_CLK 0xea 146 #define IMX7D_UART3_ROOT_SRC 0xeb 147 #define IMX7D_UART3_ROOT_CG 0xec 148 #define IMX7D_UART3_ROOT_DIV 0xed 149 #define IMX7D_UART4_ROOT_CLK 0xee 150 #define IMX7D_UART4_ROOT_SRC 0xef 151 #define IMX7D_UART4_ROOT_CG 0xf0 152 #define IMX7D_UART4_ROOT_DIV 0xf1 153 #define IMX7D_UART5_ROOT_CLK 0xf2 154 #define IMX7D_UART5_ROOT_SRC 0xf3 155 #define IMX7D_UART5_ROOT_CG 0xf4 156 #define IMX7D_UART5_ROOT_DIV 0xf5 157 #define IMX7D_UART6_ROOT_CLK 0xf6 158 #define IMX7D_UART6_ROOT_SRC 0xf7 159 #define IMX7D_UART6_ROOT_CG 0xf8 160 #define IMX7D_UART6_ROOT_DIV 0xf9 161 #define IMX7D_UART7_ROOT_CLK 0xfa 162 #define IMX7D_UART7_ROOT_SRC 0xfb 163 #define IMX7D_UART7_ROOT_CG 0xfc 164 #define IMX7D_UART7_ROOT_DIV 0xfd 165 #define IMX7D_ENET_AXI_ROOT_PRE_DIV 0x15a 166 #define IMX7D_ENET1_TIME_ROOT_PRE_DIV 0x16a 167 #define IMX7D_ENET2_TIME_ROOT_PRE_DIV 0x16c 168 #define IMX7D_ENET_PHY_REF_ROOT_PRE_DIV 0x16d 169 #define IMX7D_USDHC1_ROOT_PRE_DIV 0x171 170 #define IMX7D_USDHC2_ROOT_PRE_DIV 0x172 171 #define IMX7D_USDHC3_ROOT_PRE_DIV 0x173 172 #define IMX7D_I2C1_ROOT_PRE_DIV 0x176 173 #define IMX7D_I2C2_ROOT_PRE_DIV 0x177 174 #define IMX7D_I2C3_ROOT_PRE_DIV 0x178 175 #define IMX7D_I2C4_ROOT_PRE_DIV 0x179 176 #define IMX7D_UART1_ROOT_PRE_DIV 0x17a 177 #define IMX7D_UART2_ROOT_PRE_DIV 0x17b 178 #define IMX7D_UART3_ROOT_PRE_DIV 0x17c 179 #define IMX7D_UART4_ROOT_PRE_DIV 0x17d 180 #define IMX7D_UART5_ROOT_PRE_DIV 0x17e 181 #define IMX7D_UART6_ROOT_PRE_DIV 0x17f 182 #define IMX7D_UART7_ROOT_PRE_DIV 0x180 183 #define IMX7D_USB_CTRL_CLK 0x1a6 184 #define IMX7D_USB_PHY1_CLK 0x1a7 185 #define IMX7D_USB_PHY2_CLK 0x1a8 186 187 const struct imxccm_gate imx7d_gates[] = { 188 [IMX7D_ENET_AXI_ROOT_CG] = { 0x8900, 28, IMX7D_ENET_AXI_ROOT_SRC }, 189 [IMX7D_ENET1_TIME_ROOT_CG] = { 0xa780, 28, IMX7D_ENET1_TIME_ROOT_SRC }, 190 [IMX7D_ENET2_TIME_ROOT_CG] = { 0xa880, 28, IMX7D_ENET2_TIME_ROOT_SRC }, 191 [IMX7D_ENET_PHY_REF_ROOT_CG] = { 0xa900, 28, IMX7D_ENET_PHY_REF_ROOT_SRC }, 192 [IMX7D_USDHC1_ROOT_CG] = { 0xab00, 28, IMX7D_USDHC1_ROOT_SRC }, 193 [IMX7D_USDHC2_ROOT_CG] = { 0xab80, 28, IMX7D_USDHC2_ROOT_SRC }, 194 [IMX7D_USDHC3_ROOT_CG] = { 0xabc0, 28, IMX7D_USDHC3_ROOT_SRC }, 195 [IMX7D_I2C1_ROOT_CG] = { 0xad80, 28, IMX7D_I2C1_ROOT_SRC }, 196 [IMX7D_I2C2_ROOT_CG] = { 0xae00, 28, IMX7D_I2C2_ROOT_SRC }, 197 [IMX7D_I2C3_ROOT_CG] = { 0xae80, 28, IMX7D_I2C3_ROOT_SRC }, 198 [IMX7D_I2C4_ROOT_CG] = { 0xaf00, 28, IMX7D_I2C4_ROOT_SRC }, 199 [IMX7D_UART1_ROOT_CG] = { 0xaf80, 28, IMX7D_UART1_ROOT_SRC }, 200 [IMX7D_UART2_ROOT_CG] = { 0xb000, 28, IMX7D_UART2_ROOT_SRC }, 201 [IMX7D_UART3_ROOT_CG] = { 0xb080, 28, IMX7D_UART3_ROOT_SRC }, 202 [IMX7D_UART4_ROOT_CG] = { 0xb100, 28, IMX7D_UART4_ROOT_SRC }, 203 [IMX7D_UART5_ROOT_CG] = { 0xb180, 28, IMX7D_UART5_ROOT_SRC }, 204 [IMX7D_UART6_ROOT_CG] = { 0xb200, 28, IMX7D_UART6_ROOT_SRC }, 205 [IMX7D_UART7_ROOT_CG] = { 0xb280, 28, IMX7D_UART7_ROOT_SRC }, 206 [IMX7D_ENET_AXI_ROOT_CLK] = { 0x4060, 0, IMX7D_ENET_AXI_ROOT_DIV }, 207 [IMX7D_USB_CTRL_CLK] = { 0x4680, 0 }, 208 [IMX7D_USB_PHY1_CLK] = { 0x46a0, 0 }, 209 [IMX7D_USB_PHY2_CLK] = { 0x46b0, 0 }, 210 [IMX7D_USDHC1_ROOT_CLK] = { 0x46c0, 0, IMX7D_USDHC1_ROOT_DIV }, 211 [IMX7D_USDHC2_ROOT_CLK] = { 0x46d0, 0, IMX7D_USDHC2_ROOT_DIV }, 212 [IMX7D_USDHC3_ROOT_CLK] = { 0x46e0, 0, IMX7D_USDHC3_ROOT_DIV }, 213 [IMX7D_ENET1_IPG_ROOT_CLK] = { 0x4700, 0, IMX7D_ENET_AXI_ROOT_DIV }, 214 [IMX7D_ENET1_TIME_ROOT_CLK] = { 0x4700, 0, IMX7D_ENET1_TIME_ROOT_DIV }, 215 [IMX7D_ENET2_IPG_ROOT_CLK] = { 0x4710, 0, IMX7D_ENET_AXI_ROOT_DIV }, 216 [IMX7D_ENET2_TIME_ROOT_CLK] = { 0x4710, 0, IMX7D_ENET1_TIME_ROOT_DIV }, 217 [IMX7D_I2C1_ROOT_CLK] = { 0x4880, 0, IMX7D_I2C1_ROOT_DIV }, 218 [IMX7D_I2C2_ROOT_CLK] = { 0x4890, 0, IMX7D_I2C2_ROOT_DIV }, 219 [IMX7D_I2C3_ROOT_CLK] = { 0x48a0, 0, IMX7D_I2C3_ROOT_DIV }, 220 [IMX7D_I2C4_ROOT_CLK] = { 0x48b0, 0, IMX7D_I2C4_ROOT_DIV }, 221 [IMX7D_UART1_ROOT_CLK] = { 0x4940, 0, IMX7D_UART1_ROOT_DIV }, 222 [IMX7D_UART2_ROOT_CLK] = { 0x4950, 0, IMX7D_UART2_ROOT_DIV }, 223 [IMX7D_UART3_ROOT_CLK] = { 0x4960, 0, IMX7D_UART3_ROOT_DIV }, 224 [IMX7D_UART4_ROOT_CLK] = { 0x4970, 0, IMX7D_UART4_ROOT_DIV }, 225 [IMX7D_UART5_ROOT_CLK] = { 0x4980, 0, IMX7D_UART5_ROOT_DIV }, 226 [IMX7D_UART6_ROOT_CLK] = { 0x4990, 0, IMX7D_UART6_ROOT_DIV }, 227 [IMX7D_UART7_ROOT_CLK] = { 0x49a0, 0, IMX7D_UART7_ROOT_DIV }, 228 }; 229 230 const struct imxccm_divider imx7d_divs[] = { 231 [IMX7D_ENET_AXI_ROOT_PRE_DIV] = { 0x8900, 16, 0x7, IMX7D_ENET_AXI_ROOT_CG }, 232 [IMX7D_ENET1_TIME_ROOT_PRE_DIV] = { 0xa780, 16, 0x7, IMX7D_ENET1_TIME_ROOT_CG }, 233 [IMX7D_ENET2_TIME_ROOT_PRE_DIV] = { 0xa880, 16, 0x7, IMX7D_ENET2_TIME_ROOT_CG }, 234 [IMX7D_ENET_PHY_REF_ROOT_PRE_DIV] = { 0xa900, 16, 0x7, IMX7D_ENET_PHY_REF_ROOT_CG }, 235 [IMX7D_USDHC1_ROOT_PRE_DIV] = { 0xab00, 16, 0x7, IMX7D_USDHC1_ROOT_CG }, 236 [IMX7D_USDHC2_ROOT_PRE_DIV] = { 0xab80, 16, 0x7, IMX7D_USDHC2_ROOT_CG }, 237 [IMX7D_USDHC3_ROOT_PRE_DIV] = { 0xac00, 16, 0x7, IMX7D_USDHC3_ROOT_CG }, 238 [IMX7D_I2C1_ROOT_PRE_DIV] = { 0xad80, 16, 0x7, IMX7D_I2C1_ROOT_CG }, 239 [IMX7D_I2C2_ROOT_PRE_DIV] = { 0xae00, 16, 0x7, IMX7D_I2C2_ROOT_CG }, 240 [IMX7D_I2C3_ROOT_PRE_DIV] = { 0xae80, 16, 0x7, IMX7D_I2C3_ROOT_CG }, 241 [IMX7D_I2C4_ROOT_PRE_DIV] = { 0xaf00, 16, 0x7, IMX7D_I2C4_ROOT_CG }, 242 [IMX7D_UART1_ROOT_PRE_DIV] = { 0xaf80, 16, 0x7, IMX7D_UART1_ROOT_CG }, 243 [IMX7D_UART2_ROOT_PRE_DIV] = { 0xb000, 16, 0x7, IMX7D_UART2_ROOT_CG }, 244 [IMX7D_UART3_ROOT_PRE_DIV] = { 0xb080, 16, 0x7, IMX7D_UART3_ROOT_CG }, 245 [IMX7D_UART4_ROOT_PRE_DIV] = { 0xb100, 16, 0x7, IMX7D_UART4_ROOT_CG }, 246 [IMX7D_UART5_ROOT_PRE_DIV] = { 0xb180, 16, 0x7, IMX7D_UART5_ROOT_CG }, 247 [IMX7D_UART6_ROOT_PRE_DIV] = { 0xb200, 16, 0x7, IMX7D_UART6_ROOT_CG }, 248 [IMX7D_UART7_ROOT_PRE_DIV] = { 0xb280, 16, 0x7, IMX7D_UART7_ROOT_CG }, 249 [IMX7D_ENET_AXI_ROOT_DIV] = { 0x8900, 0, 0x3f, IMX7D_ENET_AXI_ROOT_PRE_DIV }, 250 [IMX7D_ENET1_TIME_ROOT_DIV] = { 0xa780, 0, 0x3f, IMX7D_ENET1_TIME_ROOT_PRE_DIV }, 251 [IMX7D_ENET2_TIME_ROOT_DIV] = { 0xa880, 0, 0x3f, IMX7D_ENET2_TIME_ROOT_PRE_DIV }, 252 [IMX7D_ENET_PHY_REF_ROOT_CLK] = { 0xa900, 0, 0x3f, IMX7D_ENET_PHY_REF_ROOT_PRE_DIV }, 253 [IMX7D_USDHC1_ROOT_DIV] = { 0xab00, 0, 0x3f, IMX7D_USDHC1_ROOT_PRE_DIV }, 254 [IMX7D_USDHC2_ROOT_DIV] = { 0xab80, 0, 0x3f, IMX7D_USDHC2_ROOT_PRE_DIV }, 255 [IMX7D_USDHC3_ROOT_DIV] = { 0xac00, 0, 0x3f, IMX7D_USDHC3_ROOT_PRE_DIV }, 256 [IMX7D_I2C1_ROOT_DIV] = { 0xad80, 0, 0x3f, IMX7D_I2C1_ROOT_PRE_DIV }, 257 [IMX7D_I2C2_ROOT_DIV] = { 0xae00, 0, 0x3f, IMX7D_I2C2_ROOT_PRE_DIV }, 258 [IMX7D_I2C3_ROOT_DIV] = { 0xae80, 0, 0x3f, IMX7D_I2C3_ROOT_PRE_DIV }, 259 [IMX7D_I2C4_ROOT_DIV] = { 0xaf00, 0, 0x3f, IMX7D_I2C4_ROOT_PRE_DIV }, 260 [IMX7D_UART1_ROOT_DIV] = { 0xaf80, 0, 0x3f, IMX7D_UART1_ROOT_PRE_DIV }, 261 [IMX7D_UART2_ROOT_DIV] = { 0xb000, 0, 0x3f, IMX7D_UART2_ROOT_PRE_DIV }, 262 [IMX7D_UART3_ROOT_DIV] = { 0xb080, 0, 0x3f, IMX7D_UART3_ROOT_PRE_DIV }, 263 [IMX7D_UART4_ROOT_DIV] = { 0xb100, 0, 0x3f, IMX7D_UART4_ROOT_PRE_DIV }, 264 [IMX7D_UART5_ROOT_DIV] = { 0xb180, 0, 0x3f, IMX7D_UART5_ROOT_PRE_DIV }, 265 [IMX7D_UART6_ROOT_DIV] = { 0xb200, 0, 0x3f, IMX7D_UART6_ROOT_PRE_DIV }, 266 [IMX7D_UART7_ROOT_DIV] = { 0xb280, 0, 0x3f, IMX7D_UART7_ROOT_PRE_DIV }, 267 }; 268 269 const struct imxccm_mux imx7d_muxs[] = { 270 [IMX7D_ENET_AXI_ROOT_SRC] = { 0x8900, 24, 0x7 }, 271 [IMX7D_ENET1_TIME_ROOT_SRC] = { 0xa780, 24, 0x7 }, 272 [IMX7D_ENET2_TIME_ROOT_SRC] = { 0xa880, 24, 0x7 }, 273 [IMX7D_ENET_PHY_REF_ROOT_SRC] = { 0xa900, 24, 0x7 }, 274 [IMX7D_USDHC1_ROOT_SRC] = { 0xab00, 24, 0x7 }, 275 [IMX7D_USDHC2_ROOT_SRC] = { 0xab80, 24, 0x7 }, 276 [IMX7D_USDHC3_ROOT_SRC] = { 0xac00, 24, 0x7 }, 277 [IMX7D_I2C1_ROOT_SRC] = { 0xad80, 24, 0x7 }, 278 [IMX7D_I2C2_ROOT_SRC] = { 0xae00, 24, 0x7 }, 279 [IMX7D_I2C3_ROOT_SRC] = { 0xae80, 24, 0x7 }, 280 [IMX7D_I2C4_ROOT_SRC] = { 0xaf00, 24, 0x7 }, 281 [IMX7D_UART1_ROOT_SRC] = { 0xaf80, 24, 0x7 }, 282 [IMX7D_UART2_ROOT_SRC] = { 0xb000, 24, 0x7 }, 283 [IMX7D_UART3_ROOT_SRC] = { 0xb080, 24, 0x7 }, 284 [IMX7D_UART4_ROOT_SRC] = { 0xb100, 24, 0x7 }, 285 [IMX7D_UART5_ROOT_SRC] = { 0xb180, 24, 0x7 }, 286 [IMX7D_UART6_ROOT_SRC] = { 0xb200, 24, 0x7 }, 287 [IMX7D_UART7_ROOT_SRC] = { 0xb280, 24, 0x7 }, 288 }; 289 290 /* 291 * i.MX8MM clocks. 292 */ 293 294 #define IMX8MM_ARM_PLL 0x18 295 #define IMX8MM_SYS_PLL1_100M 0x32 296 #define IMX8MM_SYS_PLL1_800M 0x38 297 #define IMX8MM_SYS_PLL2_100M 0x3a 298 #define IMX8MM_SYS_PLL2_250M 0x3e 299 #define IMX8MM_SYS_PLL2_500M 0x40 300 #define IMX8MM_CLK_A53_SRC 0x42 301 #define IMX8MM_ARM_PLL_OUT 0x2c 302 #define IMX8MM_CLK_A53_CG 0x47 303 #define IMX8MM_CLK_A53_DIV 0x4c 304 #define IMX8MM_CLK_ENET_AXI 0x52 305 #define IMX8MM_CLK_NAND_USDHC_BUS 0x53 306 #define IMX8MM_CLK_USB_BUS 0x58 307 #define IMX8MM_CLK_AHB 0x5d 308 #define IMX8MM_CLK_IPG_ROOT 0x5f 309 #define IMX8MM_CLK_PCIE1_CTRL 0x67 310 #define IMX8MM_CLK_PCIE1_PHY 0x68 311 #define IMX8MM_CLK_PCIE1_AUX 0x69 312 #define IMX8MM_CLK_ENET_REF 0x74 313 #define IMX8MM_CLK_ENET_TIMER 0x75 314 #define IMX8MM_CLK_ENET_PHY_REF 0x76 315 #define IMX8MM_CLK_USDHC1 0x79 316 #define IMX8MM_CLK_USDHC2 0x7a 317 #define IMX8MM_CLK_I2C1 0x7b 318 #define IMX8MM_CLK_I2C2 0x7c 319 #define IMX8MM_CLK_I2C3 0x7d 320 #define IMX8MM_CLK_I2C4 0x7e 321 #define IMX8MM_CLK_UART1 0x7f 322 #define IMX8MM_CLK_UART2 0x80 323 #define IMX8MM_CLK_UART3 0x81 324 #define IMX8MM_CLK_UART4 0x82 325 #define IMX8MM_CLK_USB_CORE_REF 0x83 326 #define IMX8MM_CLK_USB_PHY_REF 0x84 327 #define IMX8MM_CLK_USDHC3 0x91 328 #define IMX8MM_CLK_PCIE2_CTRL 0x98 329 #define IMX8MM_CLK_PCIE2_PHY 0x99 330 #define IMX8MM_CLK_PCIE2_AUX 0x9a 331 #define IMX8MM_CLK_ENET1_ROOT 0xa2 332 #define IMX8MM_CLK_I2C1_ROOT 0xa4 333 #define IMX8MM_CLK_I2C2_ROOT 0xa5 334 #define IMX8MM_CLK_I2C3_ROOT 0xa6 335 #define IMX8MM_CLK_I2C4_ROOT 0xa7 336 #define IMX8MM_CLK_OCOTP_ROOT 0xa8 337 #define IMX8MM_CLK_PCIE1_ROOT 0xa9 338 #define IMX8MM_CLK_UART1_ROOT 0xbc 339 #define IMX8MM_CLK_UART2_ROOT 0xbd 340 #define IMX8MM_CLK_UART3_ROOT 0xbe 341 #define IMX8MM_CLK_UART4_ROOT 0xbf 342 #define IMX8MM_CLK_USB1_CTRL_ROOT 0xc0 343 #define IMX8MM_CLK_USDHC1_ROOT 0xc2 344 #define IMX8MM_CLK_USDHC2_ROOT 0xc3 345 #define IMX8MM_CLK_USDHC3_ROOT 0xd0 346 #define IMX8MM_CLK_TMU_ROOT 0xd1 347 #define IMX8MM_CLK_ARM 0xd7 348 349 const struct imxccm_gate imx8mm_gates[] = { 350 [IMX8MM_CLK_A53_CG] = { 0x8000, 14 }, 351 [IMX8MM_CLK_ENET_AXI] = { 0x8880, 14 }, 352 [IMX8MM_CLK_NAND_USDHC_BUS] = { 0x8900, 14 }, 353 [IMX8MM_CLK_USB_BUS] = { 0x8b80, 14 }, 354 [IMX8MM_CLK_AHB] = { 0x9000, 14 }, 355 [IMX8MM_CLK_PCIE1_CTRL] = { 0xa300, 14 }, 356 [IMX8MM_CLK_PCIE1_PHY] = { 0xa380, 14 }, 357 [IMX8MM_CLK_PCIE1_AUX] = { 0xa400, 14 }, 358 [IMX8MM_CLK_ENET_REF] = { 0xa980, 14 }, 359 [IMX8MM_CLK_ENET_TIMER] = { 0xaa00, 14 }, 360 [IMX8MM_CLK_ENET_PHY_REF] = { 0xaa80, 14 }, 361 [IMX8MM_CLK_USDHC1] = { 0xac00, 14 }, 362 [IMX8MM_CLK_USDHC2] = { 0xac80, 14 }, 363 [IMX8MM_CLK_I2C1] = { 0xad00, 14 }, 364 [IMX8MM_CLK_I2C2] = { 0xad80, 14 }, 365 [IMX8MM_CLK_I2C3] = { 0xae00, 14 }, 366 [IMX8MM_CLK_I2C4] = { 0xae80, 14 }, 367 [IMX8MM_CLK_UART1] = { 0xaf00, 14 }, 368 [IMX8MM_CLK_UART2] = { 0xaf80, 14 }, 369 [IMX8MM_CLK_UART3] = { 0xb000, 14 }, 370 [IMX8MM_CLK_UART4] = { 0xb080, 14 }, 371 [IMX8MM_CLK_USB_CORE_REF] = { 0xb100, 14 }, 372 [IMX8MM_CLK_USB_PHY_REF] = { 0xb180, 14 }, 373 [IMX8MM_CLK_USDHC3] = { 0xbc80, 14 }, 374 [IMX8MM_CLK_PCIE2_CTRL] = { 0xc000, 24, 0x7 }, 375 [IMX8MM_CLK_PCIE2_PHY] = { 0xc080, 24, 0x7 }, 376 [IMX8MM_CLK_PCIE2_AUX] = { 0xc100, 24, 0x7 }, 377 [IMX8MM_CLK_ENET1_ROOT] = { 0x40a0, 0, IMX8MM_CLK_ENET_AXI }, 378 [IMX8MM_CLK_I2C1_ROOT] = { 0x4170, 0, IMX8MM_CLK_I2C1 }, 379 [IMX8MM_CLK_I2C2_ROOT] = { 0x4180, 0, IMX8MM_CLK_I2C2 }, 380 [IMX8MM_CLK_I2C3_ROOT] = { 0x4190, 0, IMX8MM_CLK_I2C3 }, 381 [IMX8MM_CLK_I2C4_ROOT] = { 0x41a0, 0, IMX8MM_CLK_I2C4 }, 382 [IMX8MM_CLK_OCOTP_ROOT] = { 0x4220, 0, IMX8MM_CLK_IPG_ROOT }, 383 [IMX8MM_CLK_PCIE1_ROOT] = { 0x4250, 0, IMX8MM_CLK_PCIE1_CTRL }, 384 [IMX8MM_CLK_UART1_ROOT] = { 0x4490, 0, IMX8MM_CLK_UART1 }, 385 [IMX8MM_CLK_UART2_ROOT] = { 0x44a0, 0, IMX8MM_CLK_UART2 }, 386 [IMX8MM_CLK_UART3_ROOT] = { 0x44b0, 0, IMX8MM_CLK_UART3 }, 387 [IMX8MM_CLK_UART4_ROOT] = { 0x44c0, 0, IMX8MM_CLK_UART4 }, 388 [IMX8MM_CLK_USB1_CTRL_ROOT] = { 0x44d0, 0, IMX8MM_CLK_USB_BUS }, 389 [IMX8MM_CLK_USDHC1_ROOT] = { 0x4510, 0, IMX8MM_CLK_USDHC1 }, 390 [IMX8MM_CLK_USDHC2_ROOT] = { 0x4520, 0, IMX8MM_CLK_USDHC2 }, 391 [IMX8MM_CLK_USDHC3_ROOT] = { 0x45e0, 0, IMX8MM_CLK_USDHC3 }, 392 [IMX8MM_CLK_TMU_ROOT] = { 0x4620, 0 }, 393 }; 394 395 const struct imxccm_divider imx8mm_divs[] = { 396 [IMX8MM_CLK_A53_DIV] = { 0x8000, 0, 0x7, IMX8MM_CLK_A53_CG }, 397 [IMX8MM_CLK_ENET_AXI] = { 0x8880, 0, 0x3f }, 398 [IMX8MM_CLK_NAND_USDHC_BUS] = { 0x8900, 0, 0x3f }, 399 [IMX8MM_CLK_USB_BUS] = { 0x8b80, 0, 0x3f }, 400 [IMX8MM_CLK_AHB] = { 0x9000, 0, 0x3f }, 401 [IMX8MM_CLK_IPG_ROOT] = { 0x9080, 0, 0x1, IMX8MM_CLK_AHB }, 402 [IMX8MM_CLK_PCIE1_CTRL] = { 0xa300, 0, 0x3f }, 403 [IMX8MM_CLK_PCIE1_PHY] = { 0xa380, 0, 0x3f }, 404 [IMX8MM_CLK_PCIE1_AUX] = { 0xa400, 0, 0x3f }, 405 [IMX8MM_CLK_USDHC1] = { 0xac00, 0, 0x3f }, 406 [IMX8MM_CLK_USDHC2] = { 0xac80, 0, 0x3f }, 407 [IMX8MM_CLK_I2C1] = { 0xad00, 0, 0x3f }, 408 [IMX8MM_CLK_I2C2] = { 0xad80, 0, 0x3f }, 409 [IMX8MM_CLK_I2C3] = { 0xae00, 0, 0x3f }, 410 [IMX8MM_CLK_I2C4] = { 0xae80, 0, 0x3f }, 411 [IMX8MM_CLK_UART1] = { 0xaf00, 0, 0x3f }, 412 [IMX8MM_CLK_UART2] = { 0xaf80, 0, 0x3f }, 413 [IMX8MM_CLK_UART3] = { 0xb000, 0, 0x3f }, 414 [IMX8MM_CLK_UART4] = { 0xb080, 0, 0x3f }, 415 [IMX8MM_CLK_USB_CORE_REF] = { 0xb100, 0, 0x3f }, 416 [IMX8MM_CLK_USB_PHY_REF] = { 0xb180, 0, 0x3f }, 417 [IMX8MM_CLK_USDHC3] = { 0xbc80, 0, 0x3f }, 418 [IMX8MM_CLK_PCIE2_CTRL] = { 0xc000, 0, 0x3f }, 419 [IMX8MM_CLK_PCIE2_PHY] = { 0xc080, 0, 0x3f }, 420 [IMX8MM_CLK_PCIE2_AUX] = { 0xc100, 0, 0x3f }, 421 }; 422 423 const struct imxccm_divider imx8mm_predivs[] = { 424 [IMX8MM_CLK_ENET_AXI] = { 0x8880, 16, 0x7 }, 425 [IMX8MM_CLK_NAND_USDHC_BUS] = { 0x8900, 16, 0x7 }, 426 [IMX8MM_CLK_USB_BUS] = { 0x8b80, 16, 0x7 }, 427 [IMX8MM_CLK_AHB] = { 0x9000, 16, 0x7 }, 428 [IMX8MM_CLK_PCIE1_CTRL] = { 0xa300, 16, 0x7 }, 429 [IMX8MM_CLK_PCIE1_PHY] = { 0xa380, 16, 0x7 }, 430 [IMX8MM_CLK_PCIE1_AUX] = { 0xa400, 16, 0x7 }, 431 [IMX8MM_CLK_USDHC1] = { 0xac00, 16, 0x7 }, 432 [IMX8MM_CLK_USDHC2] = { 0xac80, 16, 0x7 }, 433 [IMX8MM_CLK_I2C1] = { 0xad00, 16, 0x7 }, 434 [IMX8MM_CLK_I2C2] = { 0xad80, 16, 0x7 }, 435 [IMX8MM_CLK_I2C3] = { 0xae00, 16, 0x7 }, 436 [IMX8MM_CLK_I2C4] = { 0xae80, 16, 0x7 }, 437 [IMX8MM_CLK_UART1] = { 0xaf00, 16, 0x7 }, 438 [IMX8MM_CLK_UART2] = { 0xaf80, 16, 0x7 }, 439 [IMX8MM_CLK_UART3] = { 0xb000, 16, 0x7 }, 440 [IMX8MM_CLK_UART4] = { 0xb080, 16, 0x7 }, 441 [IMX8MM_CLK_USB_CORE_REF] = { 0xb100, 16, 0x7 }, 442 [IMX8MM_CLK_USB_PHY_REF] = { 0xb180, 16, 0x7 }, 443 [IMX8MM_CLK_USDHC3] = { 0xbc80, 16, 0x7 }, 444 [IMX8MM_CLK_PCIE2_CTRL] = { 0xc000, 16, 0x7 }, 445 [IMX8MM_CLK_PCIE2_PHY] = { 0xc080, 16, 0x7 }, 446 [IMX8MM_CLK_PCIE2_AUX] = { 0xc100, 16, 0x7 }, 447 }; 448 449 const struct imxccm_mux imx8mm_muxs[] = { 450 [IMX8MM_CLK_A53_SRC] = { 0x8000, 24, 0x7 }, 451 [IMX8MM_CLK_ENET_AXI] = { 0x8880, 24, 0x7 }, 452 [IMX8MM_CLK_NAND_USDHC_BUS] = { 0x8900, 24, 0x7 }, 453 [IMX8MM_CLK_USB_BUS] = { 0x8b80, 24, 0x7 }, 454 [IMX8MM_CLK_AHB] = { 0x9000, 24, 0x7 }, 455 [IMX8MM_CLK_PCIE1_CTRL] = { 0xa300, 24, 0x7 }, 456 [IMX8MM_CLK_PCIE1_PHY] = { 0xa380, 24, 0x7 }, 457 [IMX8MM_CLK_PCIE1_AUX] = { 0xa400, 24, 0x7 }, 458 [IMX8MM_CLK_USDHC1] = { 0xac00, 24, 0x7 }, 459 [IMX8MM_CLK_USDHC2] = { 0xac80, 24, 0x7 }, 460 [IMX8MM_CLK_I2C1] = { 0xad00, 24, 0x7 }, 461 [IMX8MM_CLK_I2C2] = { 0xad80, 24, 0x7 }, 462 [IMX8MM_CLK_I2C3] = { 0xae00, 24, 0x7 }, 463 [IMX8MM_CLK_I2C4] = { 0xae80, 24, 0x7 }, 464 [IMX8MM_CLK_UART1] = { 0xaf00, 24, 0x7 }, 465 [IMX8MM_CLK_UART2] = { 0xaf80, 24, 0x7 }, 466 [IMX8MM_CLK_UART3] = { 0xb000, 24, 0x7 }, 467 [IMX8MM_CLK_UART4] = { 0xb080, 24, 0x7 }, 468 [IMX8MM_CLK_USB_CORE_REF] = { 0xb100, 24, 0x7 }, 469 [IMX8MM_CLK_USB_PHY_REF] = { 0xb180, 24, 0x7 }, 470 [IMX8MM_CLK_USDHC3] = { 0xbc80, 24, 0x7 }, 471 [IMX8MM_CLK_PCIE2_CTRL] = { 0xc000, 24, 0x7 }, 472 [IMX8MM_CLK_PCIE2_PHY] = { 0xc080, 24, 0x7 }, 473 [IMX8MM_CLK_PCIE2_AUX] = { 0xc100, 24, 0x7 }, 474 }; 475 476 /* 477 * i.MX8MP clocks. 478 */ 479 480 #define IMX8MP_CLK_24M 0x02 481 #define IMX8MP_SYS_PLL1_266M 0x36 482 #define IMX8MP_SYS_PLL2_50M 0x39 483 #define IMX8MP_SYS_PLL2_100M 0x3a 484 #define IMX8MP_SYS_PLL2_125M 0x3b 485 #define IMX8MP_SYS_PLL2_500M 0x40 486 #define IMX8MP_CLK_ENET_AXI 0x5e 487 #define IMX8MP_CLK_NAND_USDHC_BUS 0x5f 488 #define IMX8MP_CLK_AHB 0x6b 489 #define IMX8MP_CLK_IPG_ROOT 0x6e 490 #define IMX8MP_CLK_PCIE_PHY 0x77 491 #define IMX8MP_CLK_PCIE_AUX 0x78 492 #define IMX8MP_CLK_I2C5 0x79 493 #define IMX8MP_CLK_I2C6 0x7a 494 #define IMX8MP_CLK_ENET_QOS 0x81 495 #define IMX8MP_CLK_ENET_QOS_TIMER 0x82 496 #define IMX8MP_CLK_ENET_REF 0x83 497 #define IMX8MP_CLK_ENET_TIMER 0x84 498 #define IMX8MP_CLK_ENET_PHY_REF 0x85 499 #define IMX8MP_CLK_USDHC1 0x88 500 #define IMX8MP_CLK_USDHC2 0x89 501 #define IMX8MP_CLK_I2C1 0x8a 502 #define IMX8MP_CLK_I2C2 0x8b 503 #define IMX8MP_CLK_I2C3 0x8c 504 #define IMX8MP_CLK_I2C4 0x8d 505 #define IMX8MP_CLK_UART1 0x8e 506 #define IMX8MP_CLK_UART2 0x8f 507 #define IMX8MP_CLK_UART3 0x90 508 #define IMX8MP_CLK_UART4 0x91 509 #define IMX8MP_CLK_USB_CORE_REF 0x92 510 #define IMX8MP_CLK_USB_PHY_REF 0x93 511 #define IMX8MP_CLK_USDHC3 0xa9 512 #define IMX8MP_CLK_PCIE2_CTRL 0xb0 513 #define IMX8MP_CLK_PCIE2_PHY 0xb1 514 #define IMX8MP_CLK_ENET1_ROOT 0xc0 515 #define IMX8MP_CLK_I2C1_ROOT 0xcd 516 #define IMX8MP_CLK_I2C2_ROOT 0xce 517 #define IMX8MP_CLK_I2C3_ROOT 0xcf 518 #define IMX8MP_CLK_I2C4_ROOT 0xd0 519 #define IMX8MP_CLK_PCIE_ROOT 0xd9 520 #define IMX8MP_CLK_QOS_ROOT 0xe0 521 #define IMX8MP_CLK_QOS_ENET_ROOT 0xe1 522 #define IMX8MP_CLK_I2C5_ROOT 0xe7 523 #define IMX8MP_CLK_I2C6_ROOT 0xe8 524 #define IMX8MP_CLK_ENET_QOS_ROOT 0xed 525 #define IMX8MP_CLK_SIM_ENET_ROOT 0xf2 526 #define IMX8MP_CLK_UART1_ROOT 0xfb 527 #define IMX8MP_CLK_UART2_ROOT 0xfc 528 #define IMX8MP_CLK_UART3_ROOT 0xfd 529 #define IMX8MP_CLK_UART4_ROOT 0xfe 530 #define IMX8MP_CLK_USB_ROOT 0xff 531 #define IMX8MP_CLK_USB_PHY_ROOT 0x100 532 #define IMX8MP_CLK_USDHC1_ROOT 0x101 533 #define IMX8MP_CLK_USDHC2_ROOT 0x102 534 #define IMX8MP_CLK_HSIO_ROOT 0x10c 535 #define IMX8MP_CLK_USDHC3_ROOT 0x115 536 #define IMX8MP_CLK_HSIO_AXI 0x137 537 538 const struct imxccm_gate imx8mp_gates[] = { 539 [IMX8MP_CLK_ENET_AXI] = { 0x8880, 14 }, 540 [IMX8MP_CLK_NAND_USDHC_BUS] = { 0x8900, 14 }, 541 [IMX8MP_CLK_AHB] = { 0x9000, 14 }, 542 [IMX8MP_CLK_PCIE_PHY] = { 0xa380, 14 }, 543 [IMX8MP_CLK_PCIE_AUX] = { 0xa400, 14 }, 544 [IMX8MP_CLK_I2C5] = { 0xa480, 14 }, 545 [IMX8MP_CLK_I2C6] = { 0xa500, 14 }, 546 [IMX8MP_CLK_ENET_QOS] = { 0xa880, 14 }, 547 [IMX8MP_CLK_ENET_QOS_TIMER] = { 0xa900, 14 }, 548 [IMX8MP_CLK_ENET_REF] = { 0xa980, 14 }, 549 [IMX8MP_CLK_ENET_TIMER] = { 0xaa00, 14 }, 550 [IMX8MP_CLK_ENET_PHY_REF] = { 0xaa80, 14 }, 551 [IMX8MP_CLK_USDHC1] = { 0xac00, 14 }, 552 [IMX8MP_CLK_USDHC2] = { 0xac80, 14 }, 553 [IMX8MP_CLK_I2C1] = { 0xad00, 14 }, 554 [IMX8MP_CLK_I2C2] = { 0xad80, 14 }, 555 [IMX8MP_CLK_I2C3] = { 0xae00, 14 }, 556 [IMX8MP_CLK_I2C4] = { 0xae80, 14 }, 557 [IMX8MP_CLK_UART1] = { 0xaf00, 14 }, 558 [IMX8MP_CLK_UART2] = { 0xaf80, 14 }, 559 [IMX8MP_CLK_UART3] = { 0xb000, 14 }, 560 [IMX8MP_CLK_UART4] = { 0xb080, 14 }, 561 [IMX8MP_CLK_USB_CORE_REF] = { 0xb100, 14 }, 562 [IMX8MP_CLK_USB_PHY_REF] = { 0xb180, 14 }, 563 [IMX8MP_CLK_USDHC3] = { 0xbc80, 14 }, 564 [IMX8MP_CLK_PCIE2_CTRL] = { 0xc000, 14 }, 565 [IMX8MP_CLK_PCIE2_PHY] = { 0xc080, 14 }, 566 [IMX8MP_CLK_ENET1_ROOT] = { 0x40a0, 0, IMX8MP_CLK_ENET_AXI }, 567 [IMX8MP_CLK_I2C1_ROOT] = { 0x4170, 0, IMX8MP_CLK_I2C1 }, 568 [IMX8MP_CLK_I2C2_ROOT] = { 0x4180, 0, IMX8MP_CLK_I2C2 }, 569 [IMX8MP_CLK_I2C3_ROOT] = { 0x4190, 0, IMX8MP_CLK_I2C3 }, 570 [IMX8MP_CLK_I2C4_ROOT] = { 0x41a0, 0, IMX8MP_CLK_I2C4 }, 571 [IMX8MP_CLK_PCIE_ROOT] = { 0x4250, 0, IMX8MP_CLK_PCIE_AUX }, 572 [IMX8MP_CLK_QOS_ROOT] = { 0x42c0, 0, IMX8MP_CLK_IPG_ROOT }, 573 [IMX8MP_CLK_QOS_ENET_ROOT] = { 0x42e0, 0, IMX8MP_CLK_IPG_ROOT }, 574 [IMX8MP_CLK_I2C5_ROOT] = { 0x4330, 0, IMX8MP_CLK_I2C5 }, 575 [IMX8MP_CLK_I2C6_ROOT] = { 0x4340, 0, IMX8MP_CLK_I2C6 }, 576 [IMX8MP_CLK_ENET_QOS_ROOT] = { 0x43b0, 0, IMX8MP_CLK_SIM_ENET_ROOT }, 577 [IMX8MP_CLK_SIM_ENET_ROOT] = { 0x4400, 0, IMX8MP_CLK_ENET_AXI }, 578 [IMX8MP_CLK_UART1_ROOT] = { 0x4490, 0, IMX8MP_CLK_UART1 }, 579 [IMX8MP_CLK_UART2_ROOT] = { 0x44a0, 0, IMX8MP_CLK_UART2 }, 580 [IMX8MP_CLK_UART3_ROOT] = { 0x44b0, 0, IMX8MP_CLK_UART3 }, 581 [IMX8MP_CLK_UART4_ROOT] = { 0x44c0, 0, IMX8MP_CLK_UART4 }, 582 [IMX8MP_CLK_USB_ROOT] = { 0x44d0, 0 }, 583 [IMX8MP_CLK_USB_PHY_ROOT] = { 0x44f0, 0, IMX8MP_CLK_USB_PHY_REF }, 584 [IMX8MP_CLK_USDHC1_ROOT] = { 0x4510, 0, IMX8MP_CLK_USDHC1 }, 585 [IMX8MP_CLK_USDHC2_ROOT] = { 0x4520, 0, IMX8MP_CLK_USDHC2 }, 586 [IMX8MP_CLK_HSIO_ROOT] = { 0x45c0, 0, IMX8MP_CLK_IPG_ROOT }, 587 [IMX8MP_CLK_USDHC3_ROOT] = { 0x45e0, 0, IMX8MP_CLK_USDHC3 }, 588 [IMX8MP_CLK_HSIO_AXI] = { 0x8400, 14 }, 589 }; 590 591 const struct imxccm_divider imx8mp_divs[] = { 592 [IMX8MP_CLK_ENET_AXI] = { 0x8880, 0, 0x3f }, 593 [IMX8MP_CLK_NAND_USDHC_BUS] = { 0x8900, 0, 0x3f }, 594 [IMX8MP_CLK_AHB] = { 0x9000, 0, 0x3f }, 595 [IMX8MP_CLK_IPG_ROOT] = { 0x9080, 0, 0x1, IMX8MP_CLK_AHB }, 596 [IMX8MP_CLK_PCIE_PHY] = { 0xa380, 0, 0x3f }, 597 [IMX8MP_CLK_PCIE_AUX] = { 0xa400, 0, 0x3f }, 598 [IMX8MP_CLK_I2C5] = { 0xa480, 0, 0x3f }, 599 [IMX8MP_CLK_I2C6] = { 0xa500, 0, 0x3f }, 600 [IMX8MP_CLK_ENET_QOS] = { 0xa880, 0, 0x3f }, 601 [IMX8MP_CLK_ENET_QOS_TIMER] = { 0xa900, 0, 0x3f }, 602 [IMX8MP_CLK_ENET_REF] = { 0xa980, 0, 0x3f }, 603 [IMX8MP_CLK_ENET_TIMER] = { 0xaa00, 0, 0x3f }, 604 [IMX8MP_CLK_ENET_PHY_REF] = { 0xaa80, 0, 0x3f}, 605 [IMX8MP_CLK_USDHC1] = { 0xac00, 0, 0x3f }, 606 [IMX8MP_CLK_USDHC2] = { 0xac80, 0, 0x3f }, 607 [IMX8MP_CLK_I2C1] = { 0xad00, 0, 0x3f }, 608 [IMX8MP_CLK_I2C2] = { 0xad80, 0, 0x3f }, 609 [IMX8MP_CLK_I2C3] = { 0xae00, 0, 0x3f }, 610 [IMX8MP_CLK_I2C4] = { 0xae80, 0, 0x3f }, 611 [IMX8MP_CLK_UART1] = { 0xaf00, 0, 0x3f }, 612 [IMX8MP_CLK_UART2] = { 0xaf80, 0, 0x3f }, 613 [IMX8MP_CLK_UART3] = { 0xb000, 0, 0x3f }, 614 [IMX8MP_CLK_UART4] = { 0xb080, 0, 0x3f }, 615 [IMX8MP_CLK_USB_CORE_REF] = { 0xb100, 0, 0x3f }, 616 [IMX8MP_CLK_USB_PHY_REF] = { 0xb180, 0, 0x3f }, 617 [IMX8MP_CLK_USDHC3] = { 0xbc80, 0, 0x3f }, 618 [IMX8MP_CLK_PCIE2_CTRL] = { 0xc000, 0, 0x3f }, 619 [IMX8MP_CLK_PCIE2_PHY] = { 0xc080, 0, 0x3f }, 620 [IMX8MP_CLK_HSIO_AXI] = { 0x8400, 0, 0x3f }, 621 }; 622 623 const struct imxccm_divider imx8mp_predivs[] = { 624 [IMX8MP_CLK_ENET_AXI] = { 0x8880, 16, 0x7 }, 625 [IMX8MP_CLK_NAND_USDHC_BUS] = { 0x8900, 16, 0x7 }, 626 [IMX8MP_CLK_AHB] = { 0x9000, 16, 0x7 }, 627 [IMX8MP_CLK_PCIE_PHY] = { 0xa380, 16, 0x7 }, 628 [IMX8MP_CLK_PCIE_AUX] = { 0xa400, 16, 0x7 }, 629 [IMX8MP_CLK_I2C5] = { 0xa480, 16, 0x7 }, 630 [IMX8MP_CLK_I2C6] = { 0xa500, 16, 0x7 }, 631 [IMX8MP_CLK_ENET_QOS] = { 0xa880, 16, 0x7 }, 632 [IMX8MP_CLK_ENET_QOS_TIMER] = { 0xa900, 16, 0x7 }, 633 [IMX8MP_CLK_ENET_REF] = { 0xa980, 16, 0x7 }, 634 [IMX8MP_CLK_ENET_TIMER] = { 0xaa00, 16, 0x7 }, 635 [IMX8MP_CLK_ENET_PHY_REF] = { 0xaa80, 16, 0x7 }, 636 [IMX8MP_CLK_USDHC1] = { 0xac00, 16, 0x7 }, 637 [IMX8MP_CLK_USDHC2] = { 0xac80, 16, 0x7 }, 638 [IMX8MP_CLK_I2C1] = { 0xad00, 16, 0x7 }, 639 [IMX8MP_CLK_I2C2] = { 0xad80, 16, 0x7 }, 640 [IMX8MP_CLK_I2C3] = { 0xae00, 16, 0x7 }, 641 [IMX8MP_CLK_I2C4] = { 0xae80, 16, 0x7 }, 642 [IMX8MP_CLK_UART1] = { 0xaf00, 16, 0x7 }, 643 [IMX8MP_CLK_UART2] = { 0xaf80, 16, 0x7 }, 644 [IMX8MP_CLK_UART3] = { 0xb000, 16, 0x7 }, 645 [IMX8MP_CLK_UART4] = { 0xb080, 16, 0x7 }, 646 [IMX8MP_CLK_USB_CORE_REF] = { 0xb100, 16, 0x7 }, 647 [IMX8MP_CLK_USB_PHY_REF] = { 0xb180, 16, 0x7 }, 648 [IMX8MP_CLK_USDHC3] = { 0xbc80, 16, 0x7 }, 649 [IMX8MP_CLK_PCIE2_CTRL] = { 0xc000, 16, 0x7 }, 650 [IMX8MP_CLK_PCIE2_PHY] = { 0xc080, 16, 0x7 }, 651 [IMX8MP_CLK_HSIO_AXI] = { 0x8400, 16, 0x7 }, 652 }; 653 654 const struct imxccm_mux imx8mp_muxs[] = { 655 [IMX8MP_CLK_ENET_AXI] = { 0x8880, 24, 0x7 }, 656 [IMX8MP_CLK_NAND_USDHC_BUS] = { 0x8900, 24, 0x7 }, 657 [IMX8MP_CLK_AHB] = { 0x9000, 24, 0x7 }, 658 [IMX8MP_CLK_PCIE_PHY] = { 0xa380, 24, 0x7 }, 659 [IMX8MP_CLK_PCIE_AUX] = { 0xa400, 24, 0x7 }, 660 [IMX8MP_CLK_I2C5] = { 0xa480, 24, 0x7 }, 661 [IMX8MP_CLK_I2C6] = { 0xa500, 24, 0x7 }, 662 [IMX8MP_CLK_ENET_QOS] = { 0xa880, 24, 0x7 }, 663 [IMX8MP_CLK_ENET_QOS_TIMER] = { 0xa900, 24, 0x7 }, 664 [IMX8MP_CLK_ENET_REF] = { 0xa980, 24, 0x7 }, 665 [IMX8MP_CLK_ENET_TIMER] = { 0xaa00, 24, 0x7 }, 666 [IMX8MP_CLK_ENET_PHY_REF] = { 0xaa80, 24, 0x7 }, 667 [IMX8MP_CLK_USDHC1] = { 0xac00, 24, 0x7 }, 668 [IMX8MP_CLK_USDHC2] = { 0xac80, 24, 0x7 }, 669 [IMX8MP_CLK_I2C1] = { 0xad00, 24, 0x7 }, 670 [IMX8MP_CLK_I2C2] = { 0xad80, 24, 0x7 }, 671 [IMX8MP_CLK_I2C3] = { 0xae00, 24, 0x7 }, 672 [IMX8MP_CLK_I2C4] = { 0xae80, 24, 0x7 }, 673 [IMX8MP_CLK_UART1] = { 0xaf00, 24, 0x7 }, 674 [IMX8MP_CLK_UART2] = { 0xaf80, 24, 0x7 }, 675 [IMX8MP_CLK_UART3] = { 0xb000, 24, 0x7 }, 676 [IMX8MP_CLK_UART4] = { 0xb080, 24, 0x7 }, 677 [IMX8MP_CLK_USB_CORE_REF] = { 0xb100, 24, 0x7 }, 678 [IMX8MP_CLK_USB_PHY_REF] = { 0xb180, 24, 0x7 }, 679 [IMX8MP_CLK_USDHC3] = { 0xbc80, 24, 0x7 }, 680 [IMX8MP_CLK_PCIE2_CTRL] = { 0xc000, 24, 0x7 }, 681 [IMX8MP_CLK_PCIE2_PHY] = { 0xc080, 24, 0x7 }, 682 [IMX8MP_CLK_HSIO_AXI] = { 0x8400, 24, 0x7 }, 683 }; 684 685 /* 686 * i.MX8MQ clocks. 687 */ 688 689 #define IMX8MQ_CLK_32K 0x01 690 #define IMX8MQ_ARM_PLL 0x0a 691 #define IMX8MQ_ARM_PLL_OUT 0x0c 692 #define IMX8MQ_SYS1_PLL_100M 0x48 693 #define IMX8MQ_SYS1_PLL_266M 0x4c 694 #define IMX8MQ_SYS1_PLL_400M 0x4d 695 #define IMX8MQ_SYS1_PLL_800M 0x4e 696 #define IMX8MQ_SYS2_PLL_100M 0x50 697 #define IMX8MQ_SYS2_PLL_250M 0x54 698 #define IMX8MQ_SYS2_PLL_500M 0x56 699 #define IMX8MQ_CLK_A53_SRC 0x58 700 #define IMX8MQ_CLK_A53_CG 0x59 701 #define IMX8MQ_CLK_A53_DIV 0x5a 702 #define IMX8MQ_CLK_ENET_AXI 0x68 703 #define IMX8MQ_CLK_NAND_USDHC_BUS 0x69 704 #define IMX8MQ_CLK_USB_BUS 0x6e 705 #define IMX8MQ_CLK_AHB 0x74 706 #define IMX8MQ_CLK_PCIE1_CTRL 0x7c 707 #define IMX8MQ_CLK_PCIE1_PHY 0x7d 708 #define IMX8MQ_CLK_PCIE1_AUX 0x7e 709 #define IMX8MQ_CLK_ENET_REF 0x89 710 #define IMX8MQ_CLK_ENET_TIMER 0x8a 711 #define IMX8MQ_CLK_ENET_PHY_REF 0x8b 712 #define IMX8MQ_CLK_USDHC1 0x8e 713 #define IMX8MQ_CLK_USDHC2 0x8f 714 #define IMX8MQ_CLK_I2C1 0x90 715 #define IMX8MQ_CLK_I2C2 0x91 716 #define IMX8MQ_CLK_I2C3 0x92 717 #define IMX8MQ_CLK_I2C4 0x93 718 #define IMX8MQ_CLK_UART1 0x94 719 #define IMX8MQ_CLK_UART2 0x95 720 #define IMX8MQ_CLK_UART3 0x96 721 #define IMX8MQ_CLK_UART4 0x97 722 #define IMX8MQ_CLK_USB_CORE_REF 0x98 723 #define IMX8MQ_CLK_USB_PHY_REF 0x99 724 #define IMX8MQ_CLK_ECSPI1 0x9a 725 #define IMX8MQ_CLK_ECSPI2 0x9b 726 #define IMX8MQ_CLK_PWM1 0x9c 727 #define IMX8MQ_CLK_PWM2 0x9d 728 #define IMX8MQ_CLK_PWM3 0x9e 729 #define IMX8MQ_CLK_PWM4 0x9f 730 #define IMX8MQ_CLK_PCIE2_CTRL 0xad 731 #define IMX8MQ_CLK_PCIE2_PHY 0xae 732 #define IMX8MQ_CLK_PCIE2_AUX 0xaf 733 #define IMX8MQ_CLK_ECSPI3 0xb0 734 #define IMX8MQ_CLK_ECSPI1_ROOT 0xb3 735 #define IMX8MQ_CLK_ECSPI2_ROOT 0xb4 736 #define IMX8MQ_CLK_ECSPI3_ROOT 0xb5 737 #define IMX8MQ_CLK_ENET1_ROOT 0xb6 738 #define IMX8MQ_CLK_I2C1_ROOT 0xb8 739 #define IMX8MQ_CLK_I2C2_ROOT 0xb9 740 #define IMX8MQ_CLK_I2C3_ROOT 0xba 741 #define IMX8MQ_CLK_I2C4_ROOT 0xbb 742 #define IMX8MQ_CLK_PCIE1_ROOT 0xbd 743 #define IMX8MQ_CLK_PCIE2_ROOT 0xbe 744 #define IMX8MQ_CLK_PWM1_ROOT 0xbf 745 #define IMX8MQ_CLK_PWM2_ROOT 0xc0 746 #define IMX8MQ_CLK_PWM3_ROOT 0xc1 747 #define IMX8MQ_CLK_PWM4_ROOT 0xc2 748 #define IMX8MQ_CLK_UART1_ROOT 0xca 749 #define IMX8MQ_CLK_UART2_ROOT 0xcb 750 #define IMX8MQ_CLK_UART3_ROOT 0xcc 751 #define IMX8MQ_CLK_UART4_ROOT 0xcd 752 #define IMX8MQ_CLK_USB1_CTRL_ROOT 0xce 753 #define IMX8MQ_CLK_USB2_CTRL_ROOT 0xcf 754 #define IMX8MQ_CLK_USB1_PHY_ROOT 0xd0 755 #define IMX8MQ_CLK_USB2_PHY_ROOT 0xd1 756 #define IMX8MQ_CLK_USDHC1_ROOT 0xd2 757 #define IMX8MQ_CLK_USDHC2_ROOT 0xd3 758 #define IMX8MQ_CLK_IPG_ROOT 0xec 759 #define IMX8MQ_CLK_TMU_ROOT 0xf6 760 #define IMX8MQ_CLK_OCOTP_ROOT 0xfa 761 #define IMX8MQ_CLK_ARM 0x102 762 763 const struct imxccm_gate imx8mq_gates[] = { 764 [IMX8MQ_CLK_A53_CG] = { 0x8000, 14 }, 765 [IMX8MQ_CLK_ENET_AXI] = { 0x8880, 14 }, 766 [IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 14 }, 767 [IMX8MQ_CLK_USB_BUS] = { 0x8b80, 14 }, 768 [IMX8MQ_CLK_AHB] = { 0x9000, 14 }, 769 [IMX8MQ_CLK_PCIE1_CTRL] = { 0xa300, 14 }, 770 [IMX8MQ_CLK_PCIE1_PHY] = { 0xa380, 14 }, 771 [IMX8MQ_CLK_PCIE1_AUX] = { 0xa400, 14 }, 772 [IMX8MQ_CLK_ENET_REF] = { 0xa980, 14 }, 773 [IMX8MQ_CLK_ENET_TIMER] = { 0xaa00, 14 }, 774 [IMX8MQ_CLK_ENET_PHY_REF] = { 0xaa80, 14 }, 775 [IMX8MQ_CLK_USDHC1] = { 0xac00, 14 }, 776 [IMX8MQ_CLK_USDHC2] = { 0xac80, 14 }, 777 [IMX8MQ_CLK_I2C1] = { 0xad00, 14 }, 778 [IMX8MQ_CLK_I2C2] = { 0xad80, 14 }, 779 [IMX8MQ_CLK_I2C3] = { 0xae00, 14 }, 780 [IMX8MQ_CLK_I2C4] = { 0xae80, 14 }, 781 [IMX8MQ_CLK_UART1] = { 0xaf00, 14 }, 782 [IMX8MQ_CLK_UART2] = { 0xaf80, 14 }, 783 [IMX8MQ_CLK_UART3] = { 0xb000, 14 }, 784 [IMX8MQ_CLK_UART4] = { 0xb080, 14 }, 785 [IMX8MQ_CLK_USB_CORE_REF] = { 0xb100, 14 }, 786 [IMX8MQ_CLK_USB_PHY_REF] = { 0xb180, 14 }, 787 [IMX8MQ_CLK_ECSPI1] = { 0xb280, 14 }, 788 [IMX8MQ_CLK_ECSPI2] = { 0xb300, 14 }, 789 [IMX8MQ_CLK_PWM1] = { 0xb380, 14 }, 790 [IMX8MQ_CLK_PWM2] = { 0xb400, 14 }, 791 [IMX8MQ_CLK_PWM3] = { 0xb480, 14 }, 792 [IMX8MQ_CLK_PWM4] = { 0xb500, 14 }, 793 [IMX8MQ_CLK_PCIE2_CTRL] = { 0xc000, 14 }, 794 [IMX8MQ_CLK_PCIE2_PHY] = { 0xc080, 14 }, 795 [IMX8MQ_CLK_PCIE2_AUX] = { 0xc100, 14 }, 796 [IMX8MQ_CLK_ECSPI3] = { 0xc180, 14 }, 797 [IMX8MQ_CLK_ECSPI1_ROOT] = { 0x4070, 0, IMX8MQ_CLK_ECSPI1 }, 798 [IMX8MQ_CLK_ECSPI2_ROOT] = { 0x4080, 0, IMX8MQ_CLK_ECSPI2 }, 799 [IMX8MQ_CLK_ECSPI3_ROOT] = { 0x4090, 0, IMX8MQ_CLK_ECSPI3 }, 800 [IMX8MQ_CLK_ENET1_ROOT] = { 0x40a0, 0, IMX8MQ_CLK_ENET_AXI }, 801 [IMX8MQ_CLK_I2C1_ROOT] = { 0x4170, 0, IMX8MQ_CLK_I2C1 }, 802 [IMX8MQ_CLK_I2C2_ROOT] = { 0x4180, 0, IMX8MQ_CLK_I2C2 }, 803 [IMX8MQ_CLK_I2C3_ROOT] = { 0x4190, 0, IMX8MQ_CLK_I2C3 }, 804 [IMX8MQ_CLK_I2C4_ROOT] = { 0x41a0, 0, IMX8MQ_CLK_I2C4 }, 805 [IMX8MQ_CLK_PCIE1_ROOT] = { 0x4250, 0, IMX8MQ_CLK_PCIE1_CTRL }, 806 [IMX8MQ_CLK_PCIE2_ROOT] = { 0x4640, 0, IMX8MQ_CLK_PCIE2_CTRL }, 807 [IMX8MQ_CLK_PWM1_ROOT] = { 0x4280, 0, IMX8MQ_CLK_PWM1 }, 808 [IMX8MQ_CLK_PWM2_ROOT] = { 0x4290, 0, IMX8MQ_CLK_PWM2 }, 809 [IMX8MQ_CLK_PWM3_ROOT] = { 0x42a0, 0, IMX8MQ_CLK_PWM3 }, 810 [IMX8MQ_CLK_PWM4_ROOT] = { 0x42b0, 0, IMX8MQ_CLK_PWM4 }, 811 [IMX8MQ_CLK_UART1_ROOT] = { 0x4490, 0, IMX8MQ_CLK_UART1 }, 812 [IMX8MQ_CLK_UART2_ROOT] = { 0x44a0, 0, IMX8MQ_CLK_UART2 }, 813 [IMX8MQ_CLK_UART3_ROOT] = { 0x44b0, 0, IMX8MQ_CLK_UART3 }, 814 [IMX8MQ_CLK_UART4_ROOT] = { 0x44c0, 0, IMX8MQ_CLK_UART4 }, 815 [IMX8MQ_CLK_USB1_CTRL_ROOT] = { 0x44d0, 0, IMX8MQ_CLK_USB_BUS }, 816 [IMX8MQ_CLK_USB2_CTRL_ROOT] = { 0x44e0, 0, IMX8MQ_CLK_USB_BUS }, 817 [IMX8MQ_CLK_USB1_PHY_ROOT] = { 0x44f0, 0, IMX8MQ_CLK_USB_PHY_REF }, 818 [IMX8MQ_CLK_USB2_PHY_ROOT] = { 0x4500, 0, IMX8MQ_CLK_USB_PHY_REF }, 819 [IMX8MQ_CLK_USDHC1_ROOT] = { 0x4510, 0, IMX8MQ_CLK_USDHC1 }, 820 [IMX8MQ_CLK_USDHC2_ROOT] = { 0x4520, 0, IMX8MQ_CLK_USDHC2 }, 821 [IMX8MQ_CLK_TMU_ROOT] = { 0x4620, 0 }, 822 [IMX8MQ_CLK_OCOTP_ROOT] = { 0x4220, 0, IMX8MQ_CLK_IPG_ROOT }, 823 }; 824 825 const struct imxccm_divider imx8mq_divs[] = { 826 [IMX8MQ_CLK_A53_DIV] = { 0x8000, 0, 0x7, IMX8MQ_CLK_A53_CG }, 827 [IMX8MQ_CLK_ENET_AXI] = { 0x8880, 0, 0x3f }, 828 [IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 0, 0x3f }, 829 [IMX8MQ_CLK_USB_BUS] = { 0x8b80, 0, 0x3f }, 830 [IMX8MQ_CLK_AHB] = { 0x9000, 0, 0x3f }, 831 [IMX8MQ_CLK_PCIE1_CTRL] = { 0xa300, 0, 0x3f }, 832 [IMX8MQ_CLK_PCIE1_PHY] = { 0xa380, 0, 0x3f }, 833 [IMX8MQ_CLK_PCIE1_AUX] = { 0xa400, 0, 0x3f }, 834 [IMX8MQ_CLK_ENET_REF] = { 0xa980, 0, 0x3f }, 835 [IMX8MQ_CLK_ENET_TIMER] = { 0xaa00, 0, 0x3f }, 836 [IMX8MQ_CLK_ENET_PHY_REF] = { 0xaa80, 0, 0x3f }, 837 [IMX8MQ_CLK_USDHC1] = { 0xac00, 0, 0x3f }, 838 [IMX8MQ_CLK_USDHC2] = { 0xac80, 0, 0x3f }, 839 [IMX8MQ_CLK_I2C1] = { 0xad00, 0, 0x3f }, 840 [IMX8MQ_CLK_I2C2] = { 0xad80, 0, 0x3f }, 841 [IMX8MQ_CLK_I2C3] = { 0xae00, 0, 0x3f }, 842 [IMX8MQ_CLK_I2C4] = { 0xae80, 0, 0x3f }, 843 [IMX8MQ_CLK_UART1] = { 0xaf00, 0, 0x3f }, 844 [IMX8MQ_CLK_UART2] = { 0xaf80, 0, 0x3f }, 845 [IMX8MQ_CLK_UART3] = { 0xb000, 0, 0x3f }, 846 [IMX8MQ_CLK_UART4] = { 0xb080, 0, 0x3f }, 847 [IMX8MQ_CLK_USB_CORE_REF] = { 0xb100, 0, 0x3f }, 848 [IMX8MQ_CLK_USB_PHY_REF] = { 0xb180, 0, 0x3f }, 849 [IMX8MQ_CLK_ECSPI1] = { 0xb280, 0, 0x3f }, 850 [IMX8MQ_CLK_ECSPI2] = { 0xb300, 0, 0x3f }, 851 [IMX8MQ_CLK_PWM1] = { 0xb380, 0, 0x3f }, 852 [IMX8MQ_CLK_PWM2] = { 0xb400, 0, 0x3f }, 853 [IMX8MQ_CLK_PWM3] = { 0xb480, 0, 0x3f }, 854 [IMX8MQ_CLK_PWM4] = { 0xb500, 0, 0x3f }, 855 [IMX8MQ_CLK_PCIE2_CTRL] = { 0xc000, 0, 0x3f }, 856 [IMX8MQ_CLK_PCIE2_PHY] = { 0xc080, 0, 0x3f }, 857 [IMX8MQ_CLK_PCIE2_AUX] = { 0xc100, 0, 0x3f }, 858 [IMX8MQ_CLK_ECSPI3] = { 0xc180, 0, 0x3f }, 859 [IMX8MQ_CLK_IPG_ROOT] = { 0x9080, 0, 0x1, IMX8MQ_CLK_AHB }, 860 }; 861 862 const struct imxccm_divider imx8mq_predivs[] = { 863 [IMX8MQ_CLK_ENET_AXI] = { 0x8880, 16, 0x7 }, 864 [IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 16, 0x7 }, 865 [IMX8MQ_CLK_USB_BUS] = { 0x8b80, 16, 0x7 }, 866 [IMX8MQ_CLK_AHB] = { 0x9000, 16, 0x7 }, 867 [IMX8MQ_CLK_PCIE1_CTRL] = { 0xa300, 16, 0x7 }, 868 [IMX8MQ_CLK_PCIE1_PHY] = { 0xa380, 16, 0x7 }, 869 [IMX8MQ_CLK_PCIE1_AUX] = { 0xa400, 16, 0x7 }, 870 [IMX8MQ_CLK_ENET_REF] = { 0xa980, 16, 0x7 }, 871 [IMX8MQ_CLK_ENET_TIMER] = { 0xaa00, 16, 0x7 }, 872 [IMX8MQ_CLK_ENET_PHY_REF] = { 0xaa80, 16, 0x7 }, 873 [IMX8MQ_CLK_USDHC1] = { 0xac00, 16, 0x7 }, 874 [IMX8MQ_CLK_USDHC2] = { 0xac80, 16, 0x7 }, 875 [IMX8MQ_CLK_I2C1] = { 0xad00, 16, 0x7 }, 876 [IMX8MQ_CLK_I2C2] = { 0xad80, 16, 0x7 }, 877 [IMX8MQ_CLK_I2C3] = { 0xae00, 16, 0x7 }, 878 [IMX8MQ_CLK_I2C4] = { 0xae80, 16, 0x7 }, 879 [IMX8MQ_CLK_UART1] = { 0xaf00, 16, 0x7 }, 880 [IMX8MQ_CLK_UART2] = { 0xaf80, 16, 0x7 }, 881 [IMX8MQ_CLK_UART3] = { 0xb000, 16, 0x7 }, 882 [IMX8MQ_CLK_UART4] = { 0xb080, 16, 0x7 }, 883 [IMX8MQ_CLK_USB_CORE_REF] = { 0xb100, 16, 0x7 }, 884 [IMX8MQ_CLK_USB_PHY_REF] = { 0xb180, 16, 0x7 }, 885 [IMX8MQ_CLK_ECSPI1] = { 0xb280, 16, 0x7 }, 886 [IMX8MQ_CLK_ECSPI2] = { 0xb300, 16, 0x7 }, 887 [IMX8MQ_CLK_PWM1] = { 0xb380, 16, 0x7 }, 888 [IMX8MQ_CLK_PWM2] = { 0xb400, 16, 0x7 }, 889 [IMX8MQ_CLK_PWM3] = { 0xb480, 16, 0x7 }, 890 [IMX8MQ_CLK_PWM4] = { 0xb500, 16, 0x7 }, 891 [IMX8MQ_CLK_PCIE2_CTRL] = { 0xc000, 16, 0x7 }, 892 [IMX8MQ_CLK_PCIE2_PHY] = { 0xc080, 16, 0x7 }, 893 [IMX8MQ_CLK_PCIE2_AUX] = { 0xc100, 16, 0x7 }, 894 [IMX8MQ_CLK_ECSPI3] = { 0xc180, 16, 0x7 }, 895 }; 896 897 const struct imxccm_mux imx8mq_muxs[] = { 898 [IMX8MQ_CLK_A53_SRC] = { 0x8000, 24, 0x7 }, 899 [IMX8MQ_CLK_ENET_AXI] = { 0x8880, 24, 0x7 }, 900 [IMX8MQ_CLK_NAND_USDHC_BUS] = { 0x8900, 24, 0x7 }, 901 [IMX8MQ_CLK_USB_BUS] = { 0x8b80, 24, 0x7 }, 902 [IMX8MQ_CLK_AHB] = { 0x9000, 24, 0x7 }, 903 [IMX8MQ_CLK_PCIE1_CTRL] = { 0xa300, 24, 0x7 }, 904 [IMX8MQ_CLK_PCIE1_PHY] = { 0xa380, 24, 0x7 }, 905 [IMX8MQ_CLK_PCIE1_AUX] = { 0xa400, 24, 0x7 }, 906 [IMX8MQ_CLK_ENET_REF] = { 0xa980, 24, 0x7 }, 907 [IMX8MQ_CLK_ENET_TIMER] = { 0xaa00, 24, 0x7 }, 908 [IMX8MQ_CLK_ENET_PHY_REF] = { 0xaa80, 24, 0x7 }, 909 [IMX8MQ_CLK_USDHC1] = { 0xac00, 24, 0x7 }, 910 [IMX8MQ_CLK_USDHC2] = { 0xac80, 24, 0x7 }, 911 [IMX8MQ_CLK_I2C1] = { 0xad00, 24, 0x7 }, 912 [IMX8MQ_CLK_I2C2] = { 0xad80, 24, 0x7 }, 913 [IMX8MQ_CLK_I2C3] = { 0xae00, 24, 0x7 }, 914 [IMX8MQ_CLK_I2C4] = { 0xae80, 24, 0x7 }, 915 [IMX8MQ_CLK_UART1] = { 0xaf00, 24, 0x7 }, 916 [IMX8MQ_CLK_UART2] = { 0xaf80, 24, 0x7 }, 917 [IMX8MQ_CLK_UART3] = { 0xb000, 24, 0x7 }, 918 [IMX8MQ_CLK_UART4] = { 0xb080, 24, 0x7 }, 919 [IMX8MQ_CLK_USB_CORE_REF] = { 0xb100, 24, 0x7 }, 920 [IMX8MQ_CLK_USB_PHY_REF] = { 0xb180, 24, 0x7 }, 921 [IMX8MQ_CLK_ECSPI1] = { 0xb280, 24, 0x7 }, 922 [IMX8MQ_CLK_ECSPI2] = { 0xb300, 24, 0x7 }, 923 [IMX8MQ_CLK_PWM1] = { 0xb380, 24, 0x7 }, 924 [IMX8MQ_CLK_PWM2] = { 0xb400, 24, 0x7 }, 925 [IMX8MQ_CLK_PWM3] = { 0xb480, 24, 0x7 }, 926 [IMX8MQ_CLK_PWM4] = { 0xb500, 24, 0x7 }, 927 [IMX8MQ_CLK_PCIE2_CTRL] = { 0xc000, 24, 0x7 }, 928 [IMX8MQ_CLK_PCIE2_PHY] = { 0xc080, 24, 0x7 }, 929 [IMX8MQ_CLK_PCIE2_AUX] = { 0xc100, 24, 0x7 }, 930 [IMX8MQ_CLK_ECSPI3] = { 0xc180, 24, 0x7 }, 931 }; 932