1 /* $NetBSD: imxusbreg.h,v 1.5 2016/05/17 06:44:46 ryo Exp $ */ 2 /* 3 * Copyright (c) 2009, 2010 Genetec Corporation. All rights reserved. 4 * Written by Hashimoto Kenichi for Genetec Corporation. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY GENETEC CORPORATION ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 17 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 18 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL GENETEC CORPORATION 19 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 */ 27 28 #ifndef _ARM_IMX_IMXUSBREG_H 29 #define _ARM_IMX_IMXUSBREG_H 30 31 #define IMXUSB_ID 0x0000 32 #define IMXUSB_ID_ID __BITS(5,0) 33 #define IMXUSB_ID_REVISION __BITS(23,16) 34 #define IMXUSB_HWGENERAL 0x0004 35 #define IMXUSB_HWHOST 0x0008 36 #define HWHOST_HC __BIT(0) 37 #define HWHOST_NPORT __BITS(3,1) 38 #define IMXUSB_HWDEVICE 0x000c 39 #define HWDEVICE_DC __BIT(0) 40 #define HWDEVICE_DEVEP __BITS(5,1) 41 #define IMXUSB_HWTXBUF 0x0010 42 #define IMXUSB_HWRXBUF 0x0014 43 44 #define IMXUSB_EHCIREGS 0x0100 45 46 #define IMXUSB_ULPIVIEW 0x0170 47 #define ULPI_WU __BIT(31) 48 #define ULPI_RUN __BIT(30) 49 #define ULPI_RW __BIT(29) 50 #define ULPI_SS __BIT(27) 51 #define ULPI_PORT __BITS(26,24) 52 #define ULPI_ADDR __BITS(23,16) 53 #define ULPI_DATRD __BITS(15,8) 54 #define ULPI_DATWR __BITS(7,0) 55 56 #define IMXUSB_OTGSC 0x01A4 57 #define OTGSC_DPIE __BIT(30) 58 #define OTGSC_1MSE __BIT(29) 59 #define OTGSC_BSEIE __BIT(28) 60 #define OTGSC_BSVIE __BIT(27) 61 #define OTGSC_ASVIE __BIT(26) 62 #define OTGSC_AVVIE __BIT(25) 63 #define OTGSC_IDIE __BIT(24) 64 #define OTGSC_DPIS __BIT(22) 65 #define OTGSC_1MSS __BIT(21) 66 #define OTGSC_BSEIS __BIT(20) 67 #define OTGSC_BSVIS __BIT(19) 68 #define OTGSC_ASVIS __BIT(18) 69 #define OTGSC_AVVIS __BIT(17) 70 #define OTGSC_IDIS __BIT(16) 71 #define OTGSC_DPS __BIT(14) 72 #define OTGSC_1MST __BIT(13) 73 #define OTGSC_BSE __BIT(12) 74 #define OTGSC_BSV __BIT(11) 75 #define OTGSC_ASV __BIT(10) 76 #define OTGSC_AVV __BIT( 9) 77 #define OTGSC_ID __BIT( 8) 78 #define OTGSC_IDPU __BIT( 5) 79 #define OTGSC_DP __BIT( 4) 80 #define OTGSC_OT __BIT( 3) 81 #define OTGSC_VC __BIT( 1) 82 #define OTGSC_VD __BIT( 0) 83 #define IMXUSB_USBMODE 0x01A8 84 #define USBMODE_VBPS __BIT(5) /* Vbus power selectt */ 85 #define USBMODE_SDIS __BIT(4) /* Stream disable mode 1=act */ 86 #define USBMODE_SLOM __BIT(3) /* setup lockouts on */ 87 #define USBMODE_ES __BIT(2) /* Endian Select ES=1 */ 88 #define USBMODE_CM __BITS(1,0) /* Controller mode */ 89 #define USBMODE_CM_IDLE __SHIFTIN(0,USBMODE_CM) 90 #define USBMODE_CM_DEVICE __SHIFTIN(2,USBMODE_CM) 91 #define USBMODE_CM_HOST __SHIFTIN(3,USBMODE_CM) 92 93 #define IMXUSB_EHCI_SIZE 0x200 94 95 96 /* extension to PORTSCx register of EHCI. */ 97 #define PORTSC_PTS __BITS(31,30) 98 #define PORTSC_PTS_UTMI __SHIFTIN(0,PORTSC_PTS) 99 #define PORTSC_PTS_PHILIPS __SHIFTIN(1,PORTSC_PTS) /* not in i.MX51*/ 100 #define PORTSC_PTS_ULPI __SHIFTIN(2,PORTSC_PTS) 101 #define PORTSC_PTS_SERIAL __SHIFTIN(3,PORTSC_PTS) 102 #define PORTSC_PTS2 __BIT(25) /* iMX6,7 */ 103 104 #define PORTSC_STS __BIT(29) /* serial transeiver select */ 105 #define PORTSC_PTW __BIT(28) /* parallel transceiver width */ 106 #define PORTSC_PTW_8 0 107 #define PORTSC_PTW_16 PORTSC_PTW 108 #define PORTSC_PSPD __BITS(26,27) /* port speed (RO) */ 109 #define PORTSC_PFSC __BIT(24) /* port force full speed */ 110 #define PORTSC_PHCD __BIT(23) /* PHY low power suspend */ 111 112 #endif /* _ARM_IMX_IMXUSBREG_H */ 113