xref: /netbsd/sys/arch/ews4800mips/include/sbd_tr2a.h (revision ce099b40)
1 /*	$NetBSD: sbd_tr2a.h,v 1.2 2008/04/28 20:23:18 martin Exp $	*/
2 
3 /*-
4  * Copyright (c) 2004 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to The NetBSD Foundation
8  * by UCHIYAMA Yasushi.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 #ifndef _SBD_TR2A_PRIVATE
33 #error "Don't inlucde this file except for TR2A implemetation"
34 #endif /* !_SBD_TR2A_PRIVATE */
35 
36 #ifndef _EWS4800MIPS_SBD_TR2A_H_
37 #define	_EWS4800MIPS_SBD_TR2A_H_
38 /*
39  * EWS4800/360 (TR2A) specific system board definition
40  */
41 /*
42  * [interrupt overview]
43  *
44  *                   +-----+
45  *                   | CPU |
46  *                   +--+--+
47  *                      |
48  *          +----+----+-+--+----+----+
49  *        INT5 INT4 INT3 INT2 INT1 INT0
50  *          |    |    |    |    |    |
51  *        +-+----+----+----+----+----+-+
52  *        |            INTC            |
53  *        | mask:   0xbe000008         |
54  *        | status: 0xbe000004         |
55  *        | clear:  0xbe000000         |       +-------------------+
56  *        +-+----+----+----+----+----+-+       |      APbus        |
57  *          |    |    |    |    +----+---------+Lo                 |
58  *  CLOCK---+    |    +----+---------+---------+Hi                 |
59  * 0xbe4a0008    |         |         |         |                   |
60  * (0x80)      +-+---------+---------+-+       +-------------------+
61  *             |         ASObus        |
62  *             | mask:   0xbe40a00c    |
63  *             | status: 0xbe40a010    |
64  *             | DMA int:0xbe408000    |
65  *             +-+---------+---------+-+
66  *               |         |         |
67  * 0xbe440000 ZS-+         |         |
68  * 0xbe480000 KBMS         |         |
69  *                         |         |
70  * 0xbe500000 SCSI-A-------+         |
71  * 0xbe510000 SCSI-B-------+         |
72  * 0xbe400000 LANCE--------+         |
73  *                                   |
74  *       NMI-------------------------+
75  *
76  * [INTC interrupt mask]  0xbe000008
77  *  0x80000000    INT5
78  *  0x04000000    INT4
79  *  0x00200000    INT3
80  *  0x00010000    INT2
81  *  0x00000800    INT1
82  *  0x00000020    INT0
83  *
84  * [ASObus interrupt mask] 0xbe40a00c
85  *                        TR2A
86  *  0x00800000    INT4    -
87  *  0x00400000    INT4    -
88  *  0x00300010    INT4    ZS
89  *  0x00000040    INT4    KBMS
90  *  0x00000020    INT4    -
91  *  0x00000100    INT2    simd2 A
92  *  0x00000200    INT2    simd2 B
93  *  0x00000001    INT2    limd2
94  *  0x00008000    INT0    NMI
95  *  0x00000008    INT0    -
96  *  0x00000004    INT0    -
97  *  0x00f0837d            0x00300351
98  */
99 
100 /* ROM */
101 #define	TR2A_ROM_FONT_ADDR		0xbfc0ec00
102 #define	TR2A_SCSIROM_ADDR		0xbfc80000
103 #define	TR2A_GAROM_ADDR			0xbfc82000
104 
105 #define	TR2A_ROM_KEYMAP_NORMAL		((uint8_t *)0xbfc39140)
106 #define	TR2A_ROM_KEYMAP_SHIFTED		((uint8_t *)0xbfc38e40)
107 #define	TR2A_ROM_KEYMAP_CONTROL		((uint8_t *)0xbfc38ec0)
108 #define	TR2A_ROM_KEYMAP_CAPSLOCK	((uint8_t *)0xbfc39040)
109 
110 /* System board I/O devices */
111 #define	TR2A_IOBASE_ADDR	0xbe000000
112 #define	TR2A_LANCE_BASE		0xbe400000	/* Ether AM79C90 */
113 #define	TR2A_SIO_BASE		0xbe440000	/* SIO1	85230 */
114 #define	TR2A_KBMS_BASE		0xbe480000	/* SIO0 85230 */
115 #define	TR2A_NVSRAM_BASE	0xbe490000	/* NVSRAM */
116 #define	TR2A_SCSIA_BASE		0xbe500000	/* SCSI-A NCR53C710 */
117 #define	TR2A_SCSIB_BASE		0xbe510000	/* SCSI-B NCR53C710 */
118 #if 0
119 #define	TR2A_FDC_BASE		0xbe420000
120 #define	TR2A_LPT_BASE		0xbe430000
121 #define	TR2A_APBUS_INTC_MASK	0xbe806000
122 #define	TR2A_VMECHK		0xbe000040
123 #define	TR2A_CLK		0xbe000024
124 #endif
125 
126 /* APbus */
127 #define	TR2A_APBUS_ADDR		0xe0000000
128 #define	TR2A_APBUS_SIZE		0x18000000
129 
130 /* NVSRAM */
131 #define	TR2A_NVSRAM_ADDR	0xbe490000
132 #define	NVSRAM_SIGNATURE	0xbe490000
133 #define	NVSRAM_MACHINEID	0xbe490010
134 #define	NVSRAM_ETHERADDR	0xbe491008
135 #define	NVSRAM_TF_PROGRESS	0xbe493010
136 #define	NVSRAM_TF_ERROR		0xbe493028
137 #define	NVSRAM_BOOTDEV		((uint8_t *)0xbe493030)
138 #define	NVSRAM_CONSTYPE		((uint8_t *)0xbe4932a0)
139 #define	NVSRAM_BOOTUNIT		0xbe493414
140 #define	NVSRAM_SBDINIT_0	0xbe493450
141 #define	NVSRAM_SBDINIT_1	0xbe493454
142 #define	NVSRAM_SBDINIT_2	0xbe493458
143 #define	NVSRAM_SBDINIT_3	0xbe49345c
144 
145 /* Frame buffer */
146 #define	TR2A_GAFB_ADDR		0xf0000000
147 #define	TR2A_GAFB_SIZE		0x04000000
148 #define	TR2A_GAREG_ADDR		0xf5f00000
149 #define	TR2A_GAREG_SIZE		0x00001000
150 
151 #define	SOFTRESET_REG		((volatile uint8_t *)0xba000004)
152 #define	SOFTRESET_FLAG		((volatile uint32_t *)0xbe000064)
153 
154 #define	CLOCK_REG		((volatile uint8_t *)0xbe4a0008)
155 #define	POWEROFF_REG		((volatile uint8_t *)0xbe4a0030)
156 #define	LED_TF_REG		((volatile uint8_t *)0xbe4a0040)
157 #define	  LED_TF_ON		1
158 #define	  LED_TF_OFF		0
159 #define	TF_ERROR_CODE		((volatile uint8_t *)0xbe4a0044)
160 #define	BUZZER_REG		((volatile uint8_t *)0xbe4a0050)
161 
162 /* Keyboard/Mouse Z85230 */
163 #define	KBD_STATUS		((volatile uint8_t *)0xbe480000)
164 #define	KBD_DATA		((volatile uint8_t *)0xbe480004)
165 
166 /* RTC	*/
167 #define	RTC_MK48T18_ADDR	((volatile uint8_t *)0xbe493fe0)
168 #define	RTC_MK48T18_NVSRAM_ADDR	0xbe490000
169 
170 /* INTC */
171 #define	INTC_CLEAR_REG		((volatile uint32_t *)0xbe000000)
172 #define	INTC_STATUS_REG		((volatile uint32_t *)0xbe000004)
173 #define	INTC_MASK_REG		((volatile uint32_t *)0xbe000008)
174 #define	INTC_INT5		0x80000000
175 #define	INTC_INT4		0x04000000
176 #define	INTC_INT3		0x00200000
177 #define	INTC_INT2		0x00010000
178 #define	INTC_INT1		0x00000800
179 #define	INTC_INT0		0x00000020
180 
181 /* ASO */
182 #define	ASO_DMAINT_STATUS_REG	((volatile uint32_t *)0xbe408000)
183 #define	ASO_INT_MASK_REG	((volatile uint32_t *)0xbe40a00c)
184 #define	ASO_INT_STATUS_REG	((volatile uint32_t *)0xbe40a010)
185 
186 #define	TR2A_ASO_INTMASK_ALL	0x00f0837d
187 
188 /* Graphic adapter */
189 #include <machine/gareg.h>
190 
191 #endif /* !_EWS4800MIPS_SBD_TR2_H_ */
192