1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2023 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DISPLAY_DEVICE_H__ 7 #define __INTEL_DISPLAY_DEVICE_H__ 8 9 #include <linux/types.h> 10 11 #include "intel_display_conversion.h" 12 #include "intel_display_limits.h" 13 14 struct drm_i915_private; 15 struct drm_printer; 16 17 #define DEV_INFO_DISPLAY_FOR_EACH_FLAG(func) \ 18 /* Keep in alphabetical order */ \ 19 func(cursor_needs_physical); \ 20 func(has_cdclk_crawl); \ 21 func(has_cdclk_squash); \ 22 func(has_ddi); \ 23 func(has_dp_mst); \ 24 func(has_dsb); \ 25 func(has_fpga_dbg); \ 26 func(has_gmch); \ 27 func(has_hotplug); \ 28 func(has_hti); \ 29 func(has_ipc); \ 30 func(has_overlay); \ 31 func(has_psr); \ 32 func(has_psr_hw_tracking); \ 33 func(overlay_needs_physical); \ 34 func(supports_tv); 35 36 #define HAS_4TILE(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14) 37 #define HAS_ASYNC_FLIPS(i915) (DISPLAY_VER(i915) >= 5) 38 #define HAS_CDCLK_CRAWL(i915) (DISPLAY_INFO(i915)->has_cdclk_crawl) 39 #define HAS_CDCLK_SQUASH(i915) (DISPLAY_INFO(i915)->has_cdclk_squash) 40 #define HAS_CUR_FBC(i915) (!HAS_GMCH(i915) && IS_DISPLAY_VER(i915, 7, 13)) 41 #define HAS_D12_PLANE_MINIMIZATION(i915) (IS_ROCKETLAKE(i915) || IS_ALDERLAKE_S(i915)) 42 #define HAS_DDI(i915) (DISPLAY_INFO(i915)->has_ddi) 43 #define HAS_DISPLAY(i915) (DISPLAY_RUNTIME_INFO(i915)->pipe_mask != 0) 44 #define HAS_DMC(i915) (DISPLAY_RUNTIME_INFO(i915)->has_dmc) 45 #define HAS_DOUBLE_BUFFERED_M_N(i915) (DISPLAY_VER(i915) >= 9 || IS_BROADWELL(i915)) 46 #define HAS_DP_MST(i915) (DISPLAY_INFO(i915)->has_dp_mst) 47 #define HAS_DP20(i915) (IS_DG2(i915) || DISPLAY_VER(i915) >= 14) 48 #define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13) 49 #define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb) 50 #define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc) 51 #define HAS_DSC_MST(__i915) (DISPLAY_VER(__i915) >= 12 && HAS_DSC(__i915)) 52 #define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0) 53 #define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg) 54 #define HAS_FW_BLC(i915) (DISPLAY_VER(i915) >= 3) 55 #define HAS_GMBUS_IRQ(i915) (DISPLAY_VER(i915) >= 4) 56 #define HAS_GMBUS_BURST_READ(i915) (DISPLAY_VER(i915) >= 10 || IS_KABYLAKE(i915)) 57 #define HAS_GMCH(i915) (DISPLAY_INFO(i915)->has_gmch) 58 #define HAS_HW_SAGV_WM(i915) (DISPLAY_VER(i915) >= 13 && !IS_DGFX(i915)) 59 #define HAS_IPC(i915) (DISPLAY_INFO(i915)->has_ipc) 60 #define HAS_IPS(i915) (IS_HASWELL_ULT(i915) || IS_BROADWELL(i915)) 61 #define HAS_LRR(i915) (DISPLAY_VER(i915) >= 12) 62 #define HAS_LSPCON(i915) (IS_DISPLAY_VER(i915, 9, 10)) 63 #define HAS_MBUS_JOINING(i915) (IS_ALDERLAKE_P(i915) || DISPLAY_VER(i915) >= 14) 64 #define HAS_MSO(i915) (DISPLAY_VER(i915) >= 12) 65 #define HAS_OVERLAY(i915) (DISPLAY_INFO(i915)->has_overlay) 66 #define HAS_PSR(i915) (DISPLAY_INFO(i915)->has_psr) 67 #define HAS_PSR_HW_TRACKING(i915) (DISPLAY_INFO(i915)->has_psr_hw_tracking) 68 #define HAS_PSR2_SEL_FETCH(i915) (DISPLAY_VER(i915) >= 12) 69 #define HAS_SAGV(i915) (DISPLAY_VER(i915) >= 9 && !IS_LP(i915)) 70 #define HAS_TRANSCODER(i915, trans) ((DISPLAY_RUNTIME_INFO(i915)->cpu_transcoder_mask & \ 71 BIT(trans)) != 0) 72 #define HAS_VRR(i915) (DISPLAY_VER(i915) >= 11) 73 #define HAS_AS_SDP(i915) (DISPLAY_VER(i915) >= 13) 74 #define INTEL_NUM_PIPES(i915) (hweight8(DISPLAY_RUNTIME_INFO(i915)->pipe_mask)) 75 #define I915_HAS_HOTPLUG(i915) (DISPLAY_INFO(i915)->has_hotplug) 76 #define OVERLAY_NEEDS_PHYSICAL(i915) (DISPLAY_INFO(i915)->overlay_needs_physical) 77 #define SUPPORTS_TV(i915) (DISPLAY_INFO(i915)->supports_tv) 78 79 /* Check that device has a display IP version within the specific range. */ 80 #define IS_DISPLAY_IP_RANGE(__i915, from, until) ( \ 81 BUILD_BUG_ON_ZERO((from) < IP_VER(2, 0)) + \ 82 (DISPLAY_VER_FULL(__i915) >= (from) && \ 83 DISPLAY_VER_FULL(__i915) <= (until))) 84 85 /* 86 * Check if a device has a specific IP version as well as a stepping within the 87 * specified range [from, until). The lower bound is inclusive, the upper 88 * bound is exclusive. The most common use-case of this macro is for checking 89 * bounds for workarounds, which usually have a stepping ("from") at which the 90 * hardware issue is first present and another stepping ("until") at which a 91 * hardware fix is present and the software workaround is no longer necessary. 92 * E.g., 93 * 94 * IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_A0, STEP_B2) 95 * IS_DISPLAY_IP_STEP(i915, IP_VER(14, 0), STEP_C0, STEP_FOREVER) 96 * 97 * "STEP_FOREVER" can be passed as "until" for workarounds that have no upper 98 * stepping bound for the specified IP version. 99 */ 100 #define IS_DISPLAY_IP_STEP(__i915, ipver, from, until) \ 101 (IS_DISPLAY_IP_RANGE((__i915), (ipver), (ipver)) && \ 102 IS_DISPLAY_STEP((__i915), (from), (until))) 103 104 #define DISPLAY_INFO(i915) (__to_intel_display(i915)->info.__device_info) 105 #define DISPLAY_RUNTIME_INFO(i915) (&__to_intel_display(i915)->info.__runtime_info) 106 107 #define DISPLAY_VER(i915) (DISPLAY_RUNTIME_INFO(i915)->ip.ver) 108 #define DISPLAY_VER_FULL(i915) IP_VER(DISPLAY_RUNTIME_INFO(i915)->ip.ver, \ 109 DISPLAY_RUNTIME_INFO(i915)->ip.rel) 110 #define IS_DISPLAY_VER(i915, from, until) \ 111 (DISPLAY_VER(i915) >= (from) && DISPLAY_VER(i915) <= (until)) 112 113 struct intel_display_runtime_info { 114 struct { 115 u16 ver; 116 u16 rel; 117 u16 step; 118 } ip; 119 120 u8 pipe_mask; 121 u8 cpu_transcoder_mask; 122 u16 port_mask; 123 124 u8 num_sprites[I915_MAX_PIPES]; 125 u8 num_scalers[I915_MAX_PIPES]; 126 127 u8 fbc_mask; 128 129 bool has_hdcp; 130 bool has_dmc; 131 bool has_dsc; 132 }; 133 134 struct intel_display_device_info { 135 /* Initial runtime info. */ 136 const struct intel_display_runtime_info __runtime_defaults; 137 138 u8 abox_mask; 139 140 struct { 141 u16 size; /* in blocks */ 142 u8 slice_mask; 143 } dbuf; 144 145 #define DEFINE_FLAG(name) u8 name:1 146 DEV_INFO_DISPLAY_FOR_EACH_FLAG(DEFINE_FLAG); 147 #undef DEFINE_FLAG 148 149 /* Global register offset for the display engine */ 150 u32 mmio_offset; 151 152 /* Register offsets for the various display pipes and transcoders */ 153 u32 pipe_offsets[I915_MAX_TRANSCODERS]; 154 u32 trans_offsets[I915_MAX_TRANSCODERS]; 155 u32 cursor_offsets[I915_MAX_PIPES]; 156 157 struct { 158 u32 degamma_lut_size; 159 u32 gamma_lut_size; 160 u32 degamma_lut_tests; 161 u32 gamma_lut_tests; 162 } color; 163 }; 164 165 bool intel_display_device_enabled(struct drm_i915_private *i915); 166 void intel_display_device_probe(struct drm_i915_private *i915); 167 void intel_display_device_remove(struct drm_i915_private *i915); 168 void intel_display_device_info_runtime_init(struct drm_i915_private *i915); 169 170 void intel_display_device_info_print(const struct intel_display_device_info *info, 171 const struct intel_display_runtime_info *runtime, 172 struct drm_printer *p); 173 174 #endif 175