1 /* $OpenBSD: intr.h,v 1.44 2018/01/13 15:18:11 mpi Exp $ */
2
3 /*
4 * Copyright (c) 2002-2004 Michael Shalayeff
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR OR HIS RELATIVES BE LIABLE FOR ANY DIRECT,
20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 * SERVICES; LOSS OF MIND, USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
25 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #ifndef _MACHINE_INTR_H_
30 #define _MACHINE_INTR_H_
31
32 #include <machine/psl.h>
33
34 #define CPU_NINTS 32
35 #define NIPL 17
36
37 #define IPL_NONE 0
38 #define IPL_SOFTCLOCK 1
39 #define IPL_SOFTNET 2
40 #define IPL_BIO 3
41 #define IPL_NET 4
42 #define IPL_SOFTTTY 5
43 #define IPL_TTY 6
44 #define IPL_VM 7
45 #define IPL_AUDIO 8
46 #define IPL_CLOCK 9
47 #define IPL_STATCLOCK 10
48 #define IPL_SCHED 10
49 #define IPL_HIGH 10
50 #define IPL_IPI 11
51 #define IPL_NESTED 12 /* pseudo-level for sub-tables */
52
53 #define IPL_MPFLOOR IPL_AUDIO
54 #define IPL_MPSAFE 0 /* no "mpsafe" interrupts */
55
56 #define IST_NONE 0
57 #define IST_PULSE 1
58 #define IST_EDGE 2
59 #define IST_LEVEL 3
60
61 #ifdef MULTIPROCESSOR
62 #define HPPA_IPI_NOP 0
63 #define HPPA_IPI_HALT 1
64 #define HPPA_IPI_FPU_SAVE 2
65 #define HPPA_IPI_FPU_FLUSH 3
66 #define HPPA_NIPI 4
67 #endif
68
69 #if !defined(_LOCORE) && defined(_KERNEL)
70
71 extern volatile u_long imask[NIPL];
72
73 #ifdef DIAGNOSTIC
74 void splassert_fail(int, int, const char *);
75 extern int splassert_ctl;
76 void splassert_check(int, const char *);
77 #define splassert(__wantipl) do { \
78 if (splassert_ctl > 0) { \
79 splassert_check(__wantipl, __func__); \
80 } \
81 } while (0)
82 #define splsoftassert(__wantipl) splassert(__wantipl)
83 #else
84 #define splassert(__wantipl) do { /* nada */ } while (0)
85 #define splsoftassert(__wantipl) do { /* nada */ } while (0)
86 #endif /* DIAGNOSTIC */
87
88 void cpu_intr_init(void);
89 void cpu_intr(void *);
90
91 void intr_barrier(void *);
92
93 static __inline int
spllower(int ncpl)94 spllower(int ncpl)
95 {
96 register int arg0 asm("r26") = ncpl;
97 register int ret0 asm("r28");
98
99 __asm volatile("break %1, %2"
100 : "=r" (ret0)
101 : "i" (HPPA_BREAK_KERNEL), "i" (HPPA_BREAK_SPLLOWER), "r" (arg0)
102 : "memory");
103
104 return (ret0);
105 }
106
107 static __inline int
splraise(int ncpl)108 splraise(int ncpl)
109 {
110 struct cpu_info *ci = curcpu();
111 int ocpl = ci->ci_cpl;
112
113 if (ocpl < ncpl)
114 ci->ci_cpl = ncpl;
115 __asm volatile ("sync" : : : "memory");
116
117 return (ocpl);
118 }
119
120 static __inline void
splx(int ncpl)121 splx(int ncpl)
122 {
123 (void)spllower(ncpl);
124 }
125
126 static __inline register_t
hppa_intr_disable(void)127 hppa_intr_disable(void)
128 {
129 register_t eiem;
130
131 __asm volatile("mfctl %%cr15, %0": "=r" (eiem));
132 __asm volatile("mtctl %r0, %cr15");
133
134 return eiem;
135 }
136
137 static __inline void
hppa_intr_enable(register_t eiem)138 hppa_intr_enable(register_t eiem)
139 {
140 __asm volatile("mtctl %0, %%cr15":: "r" (eiem));
141 }
142
143 #define splsoftclock() splraise(IPL_SOFTCLOCK)
144 #define splsoftnet() splraise(IPL_SOFTNET)
145 #define splbio() splraise(IPL_BIO)
146 #define splnet() splraise(IPL_NET)
147 #define splsofttty() splraise(IPL_SOFTTTY)
148 #define spltty() splraise(IPL_TTY)
149 #define splvm() splraise(IPL_VM)
150 #define splaudio() splraise(IPL_AUDIO)
151 #define splclock() splraise(IPL_CLOCK)
152 #define splsched() splraise(IPL_SCHED)
153 #define splstatclock() splraise(IPL_STATCLOCK)
154 #define splhigh() splraise(IPL_HIGH)
155 #define splipi() splraise(IPL_IPI)
156 #define spl0() spllower(IPL_NONE)
157
158 #define SOFTINT_MASK ((1 << (IPL_SOFTCLOCK - 1)) | \
159 (1 << (IPL_SOFTNET - 1)) | (1 << (IPL_SOFTTTY - 1)))
160
161 #ifdef MULTIPROCESSOR
162 void hppa_ipi_init(struct cpu_info *);
163 int hppa_ipi_send(struct cpu_info *, u_long);
164 int hppa_ipi_broadcast(u_long);
165 #endif
166
167 #define setsoftast(p) (p->p_md.md_astpending = 1)
168
169 void *softintr_establish(int, void (*)(void *), void *);
170 void softintr_disestablish(void *);
171 void softintr_schedule(void *);
172
173 #ifdef MULTIPROCESSOR
174 void hppa_ipi_init(struct cpu_info *);
175 int hppa_ipi_intr(void *arg);
176 int hppa_ipi_send(struct cpu_info *, u_long);
177 #endif
178
179 #endif /* !_LOCORE && _KERNEL */
180 #endif /* _MACHINE_INTR_H_ */
181