xref: /dragonfly/sys/platform/pc64/icu/icu_vector.s (revision bbf928c6)
1/*
2 * Copyright (c) 2008 The DragonFly Project.  All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in
12 *    the documentation and/or other materials provided with the
13 *    distribution.
14 * 3. Neither the name of The DragonFly Project nor the names of its
15 *    contributors may be used to endorse or promote products derived
16 *    from this software without specific, prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
21 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE
22 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
24 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
26 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
28 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * SUCH DAMAGE.
30 *
31 * from: vector.s, 386BSD 0.1 unknown origin
32 * $FreeBSD: src/sys/i386/isa/icu_vector.s,v 1.14.2.2 2000/07/18 21:12:42 dfr Exp $
33 */
34/*
35 * WARNING!  SMP builds can use the ICU now so this code must be MP safe.
36 */
37
38#include "opt_auto_eoi.h"
39
40#include <machine/asmacros.h>
41#include <machine/lock.h>
42#include <machine/psl.h>
43#include <machine/trap.h>
44#include <machine/segments.h>
45#include <machine_base/icu/icu.h>
46#include <machine_base/icu/icu_ipl.h>
47
48#include <bus/isa/isa.h>
49
50#include "assym.s"
51
52#define	ICU_EOI			0x20	/* XXX - define elsewhere */
53
54#define	IRQ_LBIT(irq_num)	(1 << (irq_num))
55#define	IRQ_BIT(irq_num)	(1 << ((irq_num) % 8))
56#define	IRQ_BYTE(irq_num)	((irq_num) >> 3)
57
58#ifdef AUTO_EOI_1
59#define	ENABLE_ICU1		/* use auto-EOI to reduce i/o */
60#define	OUTB_ICU1
61#else
62#define	ENABLE_ICU1 							\
63	movb	$ICU_EOI,%al ;	/* as soon as possible send EOI ... */ 	\
64	OUTB_ICU1 ;		/* ... to clear in service bit */	\
65
66#define	OUTB_ICU1 							\
67	outb	%al,$IO_ICU1 ;						\
68
69#endif
70
71#ifdef AUTO_EOI_2
72/*
73 * The data sheet says no auto-EOI on slave, but it sometimes works.
74 */
75#define	ENABLE_ICU1_AND_2	ENABLE_ICU1
76#else
77#define	ENABLE_ICU1_AND_2 						\
78	movb	$ICU_EOI,%al ;	/* as above */ 				\
79	outb	%al,$IO_ICU2 ;	/* but do second icu first ... */ 	\
80	OUTB_ICU1 ;	/* ... then first icu (if !AUTO_EOI_1) */	\
81
82#endif
83
84/*
85 * Macro helpers
86 */
87#define ICU_PUSH_FRAME							\
88	PUSH_FRAME_TFRIP ;	/* 15 regs + space for 5 extras */	\
89	movl $0,TF_XFLAGS(%rsp) ;					\
90	movl $0,TF_TRAPNO(%rsp) ;					\
91	movl $0,TF_ADDR(%rsp) ;						\
92	movl $0,TF_FLAGS(%rsp) ;					\
93	movl $0,TF_ERR(%rsp) ;						\
94	cld ;								\
95
96/*
97 * Caller must re-enable the ICU atomically with the masking and
98 * is responsible for ICU_IMASK_LOCK/UNLOCK
99 */
100#define MASK_IRQ(icu, irq_num)						\
101	movb	icu_imen + IRQ_BYTE(irq_num),%al ;			\
102	orb	$IRQ_BIT(irq_num),%al ;					\
103	movb	%al,icu_imen + IRQ_BYTE(irq_num) ;			\
104	outb	%al,$icu+ICU_IMR_OFFSET ;				\
105
106#define UNMASK_IRQ(icu, irq_num)					\
107	cmpl	$0,%eax ;						\
108	jnz	8f ;							\
109	ICU_IMASK_LOCK ;						\
110	movb	icu_imen + IRQ_BYTE(irq_num),%al ;			\
111	andb	$~IRQ_BIT(irq_num),%al ;				\
112	movb	%al,icu_imen + IRQ_BYTE(irq_num) ;			\
113	outb	%al,$icu+ICU_IMR_OFFSET ;				\
114	ICU_IMASK_UNLOCK ;						\
1158: ;									\
116
117/*
118 * Interrupt call handlers run in the following sequence:
119 *
120 *	- Push the trap frame required by doreti.
121 *	- Mask the interrupt and reenable its source.
122 *	- If we cannot take the interrupt set its ipending bit and
123 *	  doreti.
124 *	- If we can take the interrupt clear its ipending bit,
125 *	  call the handler, then unmask the interrupt and doreti.
126 *
127 *	YYY can cache gd base pointer instead of using hidden %fs
128 *	prefixes.
129 */
130
131#define	INTR_HANDLER(irq_num, icu, enable_icus)				\
132	.text ; 							\
133	SUPERALIGN_TEXT ; 						\
134IDTVEC(icu_intr##irq_num) ; 						\
135	ICU_PUSH_FRAME ;						\
136	FAKE_MCOUNT(TF_RIP(%rsp)) ; 					\
137	ICU_IMASK_LOCK ;						\
138	MASK_IRQ(icu, irq_num) ;					\
139	enable_icus ;							\
140	ICU_IMASK_UNLOCK ;						\
141	movq	PCPU(curthread),%rbx ;					\
142	testl	$-1,TD_NEST_COUNT(%rbx) ;				\
143	jne	1f ;							\
144	testl	$-1,TD_CRITCOUNT(%rbx) ;				\
145	je	2f ;							\
1461: ;									\
147	/* set pending bit and return, leave interrupt masked */	\
148	movq	$0,%rdx ;						\
149	orq	$IRQ_LBIT(irq_num),PCPU_E8(ipending,%rdx) ;		\
150	orl	$RQF_INTPEND, PCPU(reqflags) ;				\
151	jmp	5f ;							\
1522: ;									\
153	/* clear pending bit, run handler */				\
154	movq	$0,%rdx ;						\
155	andq	$~IRQ_LBIT(irq_num),PCPU_E8(ipending,%rdx) ;		\
156	pushq	$irq_num ;						\
157	movq	%rsp,%rdi ;		/* rdi = call argument */	\
158	incl	TD_CRITCOUNT(%rbx) ;					\
159	sti ;								\
160	call	ithread_fast_handler ;	/* returns 0 to unmask int */	\
161	decl	TD_CRITCOUNT(%rbx) ;					\
162	addq	$8,%rsp ;		/* intr frame -> trap frame */	\
163	UNMASK_IRQ(icu, irq_num) ;					\
1645: ;									\
165	MEXITCOUNT ;							\
166	jmp	doreti ;						\
167
168MCOUNT_LABEL(bintr)
169	INTR_HANDLER(0, IO_ICU1, ENABLE_ICU1)
170	INTR_HANDLER(1, IO_ICU1, ENABLE_ICU1)
171	INTR_HANDLER(2, IO_ICU1, ENABLE_ICU1)
172	INTR_HANDLER(3, IO_ICU1, ENABLE_ICU1)
173	INTR_HANDLER(4, IO_ICU1, ENABLE_ICU1)
174	INTR_HANDLER(5, IO_ICU1, ENABLE_ICU1)
175	INTR_HANDLER(6, IO_ICU1, ENABLE_ICU1)
176	INTR_HANDLER(7, IO_ICU1, ENABLE_ICU1)
177	INTR_HANDLER(8, IO_ICU2, ENABLE_ICU1_AND_2)
178	INTR_HANDLER(9, IO_ICU2, ENABLE_ICU1_AND_2)
179	INTR_HANDLER(10, IO_ICU2, ENABLE_ICU1_AND_2)
180	INTR_HANDLER(11, IO_ICU2, ENABLE_ICU1_AND_2)
181	INTR_HANDLER(12, IO_ICU2, ENABLE_ICU1_AND_2)
182	INTR_HANDLER(13, IO_ICU2, ENABLE_ICU1_AND_2)
183	INTR_HANDLER(14, IO_ICU2, ENABLE_ICU1_AND_2)
184	INTR_HANDLER(15, IO_ICU2, ENABLE_ICU1_AND_2)
185MCOUNT_LABEL(eintr)
186
187	.data
188
189	.text
190