1 /*========================== begin_copyright_notice ============================ 2 3 Copyright (C) 2017-2021 Intel Corporation 4 5 SPDX-License-Identifier: MIT 6 7 ============================= end_copyright_notice ===========================*/ 8 9 #pragma once 10 #include <stdint.h> 11 12 /// 13 /// ISA Description 14 /// 15 16 #define TYPE_INTEGER ISA_TYPE_UW|ISA_TYPE_W|ISA_TYPE_UB|ISA_TYPE_B|ISA_TYPE_D|ISA_TYPE_UD|ISA_TYPE_Q|ISA_TYPE_UQ 17 #define TYPE_FLOAT ISA_TYPE_DF|ISA_TYPE_F 18 #define TYPE_FLOAT_HF ISA_TYPE_DF|ISA_TYPE_F|ISA_TYPE_HF 19 #define TYPE_FLOAT_ALL ISA_TYPE_DF|ISA_TYPE_F|ISA_TYPE_HF|ISA_TYPE_BF 20 #define TYPE_ANY TYPE_INTEGER | TYPE_FLOAT 21 22 #define SIZEOF_CISA_OPCODE sizeof(unsigned char) 23 #define OPND_DST_GEN 0x100 24 #define OPND_SRC_GEN 0x200 25 #define OPND_DST_INDIR 0x400 26 #define OPND_SRC_INDIR 0x800 27 #define OPND_DST_PRED 0x1000 28 #define OPND_SRC_PRED 0x2000 29 #define OPND_DST_ADDR 0x4000 30 #define OPND_SRC_ADDR 0x8000 31 #define OPND_ADDRESS_OF 0x10000 32 #define OPND_SURFACE 0x20000 33 #define OPND_SAMPLE 0x40000 34 #define OPND_IMM 0x100000 35 #define OPND_PRED 0x200000 36 #define OPND_OTHER 0x400000 37 #define OPND_RAW_SRC 0x800000 38 #define OPND_RAW_DST 0x1000000 39 40 #define OPND_VECTOR_SRC_G_IMM_AO OPND_SRC_GEN | OPND_IMM | OPND_ADDRESS_OF 41 #define OPND_VECTOR_SRC_G_I_IMM_AO OPND_SRC_GEN | OPND_IMM |OPND_SRC_INDIR | OPND_ADDRESS_OF 42 #define OPND_VECTOR_SRC_G_I_IMM OPND_SRC_GEN | OPND_IMM |OPND_SRC_INDIR 43 #define OPND_VECTOR_SRC_G_I_IMM_A_AO OPND_SRC_GEN | OPND_IMM |OPND_SRC_INDIR | OPND_SRC_ADDR | OPND_ADDRESS_OF 44 #define OPND_VECTOR_SRC_G_I_IMM_P_AO OPND_SRC_GEN | OPND_IMM |OPND_SRC_INDIR | OPND_SRC_PRED | OPND_ADDRESS_OF 45 #define OPND_VECTOR_SRC_G_A_AO OPND_SRC_GEN | OPND_SRC_ADDR | OPND_ADDRESS_OF 46 #define OPND_VECTOR_SRC_G_I OPND_SRC_GEN | OPND_SRC_INDIR 47 48 #define OPND_VECTOR_DST_G_I OPND_DST_GEN | OPND_DST_INDIR 49 #define OPND_VECTOR_DST_G_I_A OPND_DST_GEN | OPND_DST_INDIR | OPND_DST_ADDR 50 #define OPND_VECTOR_DST_G_I_P OPND_DST_GEN | OPND_DST_PRED | OPND_DST_INDIR 51 52 #define OPND_VECTOR_SRC OPND_SRC_GEN | OPND_IMM |OPND_SRC_INDIR | OPND_SRC_ADDR | OPND_ADDRESS_OF | OPND_SRC_PRED 53 #define OPND_VECTOR_DST OPND_DST_GEN | OPND_DST_INDIR | OPND_DST_ADDR | OPND_DST_PRED 54 55 #define OPND_SPECIAL OPND_SAMPLE | OPND_SURFACE 56 57 #define SAME_DATA_TYPE 0x1 58 #define SAME_SPECIAL_KIND 0x2 59 60 #define OPND_BLOCK_WIDTH OPND_IMM 61 #define OPND_BLOCK_HEIGHT OPND_IMM 62 #define OPND_PLANE OPND_IMM 63 64 #define OPND_SIMB_INDEX OPND_IMM 65 #define OPND_NUM_OPNDS OPND_IMM 66 #define OPND_KIND OPND_IMM 67 68 typedef enum { 69 SIZE_1 = 1, 70 SIZE_2 = 2, 71 SIZE_4 = 4, 72 SIZE_8 = 8 73 } SpecificSize; 74 75 typedef enum { 76 HORIZON_STRIDE_1 = 1, 77 HORIZON_VERTICAL_STRIDE_0, 78 HORIZON_STRIDE_2, 79 ELEM_NUM_2, 80 ELEM_NUM_4, 81 ELEM_NUM_8_16, 82 ELEM_NUM_96, 83 ELEM_NUM_128, 84 ELEM_NUM_224, 85 ELEM_NUM_GE_2, 86 ELEM_NUM_GE_16, 87 ELEM_NUM_GE_32, 88 ELEM_NUM_GE_128, 89 ELEM_NUM_GE_160, 90 ELEM_NUM_MC32, 91 ELEM_NUM_MC16, 92 SIZE_54, 93 SIZE_128, 94 SIZE_192, 95 SIZE_224, 96 SIZE_228, 97 SIZE_352, 98 SIZE_SIZE, 99 OWORD_SIZE, 100 GE_4, 101 VALUE_0_3, 102 VALUE_1_32, 103 VALUE_1_64, 104 SINGLE_DATA_TYPE, 105 PREDICATE_NONEPRED_OPND, 106 SCALAR_REGION, 107 LABEL_BLOCK_C, 108 LABEL_FUNC_C, 109 SIZE_GE_WIDTH_M_HIEGH, 110 GE_READSIZE, 111 GE_WRITESIZE, 112 SIZE_STREAM_MODE_DEPENDENT_1, 113 SIZE_STREAM_MODE_DEPENDENT_2, 114 SIZE_STREAM_MODE_DEPENDENT_3, 115 SIZE_STREAM_MODE_DEPENDENT_4, 116 LENGHT_LESS_256, 117 GRF_ALIGNED = 0x100, 118 SAT_C = 0x200, 119 SAT_FLOAT_ONLY = 0x400 120 121 //GATHER: UPPER_BITS_IGNORE, 122 // LINENUM: LARGE_THAN_0, 123 //SIZE_BLOCK_HEIGH_WIDTH, 124 //OWORD_LD_UNALIGNED: SIZE_SIZE_OWORD, 125 //Instruction specific features 126 //RIGHT_ALIGNED, 127 //MOVS: SINGLE_SPEC_OPND_TYPE, 128 //FILE NAME: LENGHT_LESS_256, 129 //ALL: WITHIN_SIMD_WIDTH 130 } OpndContraint; 131 132 //Common_ISA_Opnd_Desc_Type 133 enum { 134 OPND_EXECSIZE = 1, 135 OPND_STRING, 136 OPND_LABEL, 137 OPND_ATOMIC_SUBOP, 138 OPND_EMASK_CTRL, 139 OPND_COND_MODE, 140 OPND_CHAN_PATT, 141 OPND_OWORD_SIZE, 142 OPND_IS_MODIFIED, 143 OPND_ELEM_NUM, 144 OPND_ELEM_SIZE, 145 OPND_SIMD_MODE, 146 OPND_CHANNEL_SIMD_MODE, 147 OPND_CMP_SUBOP, 148 OPND_VME_SUBOP, 149 OPND_STREAM_MODE, 150 OPND_SEARCH_CRTL, 151 OPND_MATRIX_MODE, 152 OPND_SUBMATRIX_SHAPE, 153 OPND_SUBPRE_SHAPE, 154 OPND_SPECIAL_KIND, 155 OPND_MEDIA_LD_MODIFIER, 156 OPND_MEDIA_ST_MODIFIER, 157 OPND_RAW, 158 OPND_SUBOPCODE, 159 OP_EXT 160 }; 161 162 typedef enum 163 { 164 ISA_Inst_Mov = 0x0, 165 ISA_Inst_Arith = 0x1, 166 ISA_Inst_Logic = 0x2, 167 ISA_Inst_Compare = 0x3, //CMP 168 ISA_Inst_Address = 0x4, //ADDROF, ADDR_ADD 169 ISA_Inst_Flow = 0x5, 170 ISA_Inst_Data_Port = 0x6, 171 ISA_Inst_Sampler = 0x7, 172 ISA_Inst_Misc = 0x8, // VME, etc. 173 ISA_Inst_SIMD_Flow = 0x9, 174 ISA_Inst_Sync = 0xA, 175 ISA_Inst_SVM = 0xB, 176 ISA_Inst_LSC = 0xC, 177 ISA_Inst_Reserved 178 } ISA_Inst_Type; 179 180 struct ISA_Inst_Info 181 { 182 ISA_Opcode op; 183 ISA_Inst_Type type; 184 const char* str; 185 uint8_t n_srcs; //for send messages, we count the surface as well as all the offsets to be sources 186 uint8_t n_dsts; 187 }; 188 189 #define MAX_OPNDS_PER_INST 24 190 191 typedef struct OpndDesc 192 { 193 unsigned opnd_type; //Common_ISA_Opnd_Desc_Type OR #defines like OPND_VECTOR_SRC_G_IMM_AO 194 unsigned data_type; //VISA_Type, overloaded to supported data types if it's a vector 195 unsigned opnd_constraint; 196 } OpndDesc; 197 198 199 typedef uint8_t ISA_SubOpcode; 200 201 struct ISA_SubInst_Desc 202 { 203 ISA_SubOpcode subOpcode; 204 ISA_Inst_Type type; 205 const char* name; 206 uint16_t opnd_num; 207 OpndDesc opnd_desc[MAX_OPNDS_PER_INST]; 208 }; 209 210 struct VISA_INST_Desc 211 { 212 TARGET_PLATFORM platf; 213 ISA_SubOpcode opcode; 214 ISA_Inst_Type type; 215 const char* name; 216 uint16_t opnd_num; 217 char attr; 218 OpndDesc opnd_desc[MAX_OPNDS_PER_INST]; 219 220 const ISA_SubInst_Desc& getSubInstDesc(uint8_t subOpcode) const; 221 const ISA_SubInst_Desc& getSubInstDescByName(const char *symbol) const; 222 }; 223 224 // looks up a parent opcode and resolves the sub ops of that parent 225 // returns nullptr and sets 'size' to 0 if an op doesn't have a subop. 226 // e.g. ... = getSubInstTable(ISA_SVM, svmSubOps); 227 const ISA_SubInst_Desc *getSubInstTable(uint8_t opcode, int &size); 228 229 enum SVMSubOpcode 230 { 231 SVM_BLOCK_LD = 0x1, 232 SVM_BLOCK_ST = 0x2, 233 SVM_GATHER = 0x3, 234 SVM_SCATTER = 0x4, 235 SVM_ATOMIC = 0x5, 236 SVM_GATHER4SCALED, 237 SVM_SCATTER4SCALED, 238 SVM_LASTOP 239 }; 240 241 struct LscOpInfo { 242 enum OpKind { 243 LOAD, 244 STORE, 245 ATOMIC, 246 OTHER 247 } kind; 248 LSC_OP op; 249 uint32_t encoding; // Desc[5:0] 250 const char *mnemonic; 251 int extraOperands; // e.g. for atomics (0 for inc, 1 for add, 2 for cas) 252 253 // general op category queries 254 // these groups are equivalence classes 255 // (i.e. only one will be true for any given op) isLoadLscOpInfo256 bool isLoad() const {return kind == OpKind::LOAD;} isStoreLscOpInfo257 bool isStore() const {return kind == OpKind::STORE;} isAtomicLscOpInfo258 bool isAtomic() const {return kind == OpKind::ATOMIC;} isOtherLscOpInfo259 bool isOther() const {return kind == OpKind::OTHER;} 260 261 // other queries hasChMaskLscOpInfo262 bool hasChMask() const { 263 return op == LSC_LOAD_QUAD || op == LSC_STORE_QUAD; 264 } isStridedLscOpInfo265 bool isStrided() const { 266 return op == LSC_LOAD_STRIDED || op == LSC_STORE_STRIDED; 267 } isBlock2DLscOpInfo268 bool isBlock2D() const { 269 return op == LSC_LOAD_BLOCK2D || op == LSC_STORE_BLOCK2D; 270 } 271 }; 272 273 LscOpInfo LscOpInfoGet(LSC_OP op); // hard failure 274 bool LscOpInfoFind(LSC_OP op, LscOpInfo &opInfo); // soft failure 275 276 // get cache opts encoding value 277 // isBits17_19: if the value is for desc[19:17] 278 bool LscTryEncodeCacheOpts( 279 const LscOpInfo &opInfo, 280 LSC_CACHE_OPTS cacheOpts, 281 uint32_t &enc, 282 bool isBits17_19); 283 284 extern struct ISA_Inst_Info ISA_Inst_Table[ISA_OPCODE_ENUM_SIZE]; 285 286 extern VISA_INST_Desc CISA_INST_table[ISA_NUM_OPCODE]; 287